semiconductor memory devices

Abstract

A semiconductor memory device includes: a first counting circuit, which is adapted to count a first clock signal that switches continuously in each burst refresh cycle based on a burst refresh command signal and generate a first counting code signal; a cycle guiding circuit, which is adapted to generate a second clock signal that switches once in each burst refresh cycle based on the burst refresh command signal and a precharge signal; a second counting circuit, which is adapted to count the second clock signal and generate a second counting code signal; and a control circuit, which is adapted to generate a latch control signal for latching a target address in each burst refresh cycle based on the first counting code signal and the second counting code signal.

Description

[0001] This patent application is a divisional application of the Chinese invention patent application with application number 201810156970.9 and invention name “Semiconductor Memory Device” filed on February 24, 2018. Technical Field

[0002] Example embodiments relate to a semiconductor design technology, and more particularly, to a semiconductor memory device that performs a refresh operation. Background Art

[0003] The memory cell of a semiconductor memory device is configured by a transistor used as a switch and a capacitor that stores charge (data). Data is divided into a logic high level (logic 1) or a logic low level (logic 0) according to whether there is charge in the capacitor of the memory cell (that is, whether the voltage across the capacitor is high or low). In principle, the storage of data does not consume power because it is implemented in a way that charge accumulates in the capacitor. However, data may be lost because the initial amount of charge stored in the capacitor may be reduced due to leakage current caused by the PN junction of the MOS transistor, etc. In order to prevent this phenomenon, the data in the memory cell should be read before the data is lost, and the data should be recharged to a normal charge amount based on the information read out. The storage of data can only be maintained when such an operation is repeated periodically. This process of recharging the cell charge is called a refresh operation.

[0004] Meanwhile, as the integration density of semiconductor memory devices increases, the intervals between a plurality of word lines included in the semiconductor memory devices decrease. As the intervals between word lines decrease, the coupling effect between adjacent word lines increases.

[0005] Whenever data is input to or output from a memory cell, a word line switches between an activated (active) state and a deactivated (inactive) state. As described above, due to the increased coupling effect between adjacent word lines, the following phenomenon occurs: data in memory cells coupled to word lines adjacent to frequently activated word lines is corrupted. This phenomenon is called row hammering. Due to row hammering, the data in memory cells may be corrupted before the memory cells are refreshed.

[0006] FIG. 1 is a diagram illustrating a portion of a memory cell array included in a semiconductor memory device, for explaining row hammering.

[0007] 1 , word line WLK corresponds to a frequently activated word line with a large number of activations, while word lines WLK-1 and WLK+1 correspond to adjacent word lines disposed adjacent to frequently activated word line WLK. Furthermore, memory cell CELL_K is coupled to frequently activated word line WLK, memory cell CELL_K-1 is coupled to adjacent word line WLK-1, and memory cell CELL_K+1 is coupled to adjacent word line WLK+1. The respective memory cells CELL_K, CELL_K-1, and CELL_K+1 include cell transistors TR_K, TR_K-1, and TR_K+1, and cell capacitors CAP_K, CAP_K-1, and CAP_K+1.

[0008] 1 , when the frequently activated word line WLK is activated or deactivated, due to a coupling phenomenon occurring between the frequently activated word line WLK and the adjacent word lines WLK-1 and WLK+1, the voltages of the adjacent word lines WLK-1 and WLK+1 increase or decrease, and this affects the charge amounts of the cell capacitors CAP_K-1 and CAP_K+1. Therefore, if activation of the frequently activated word line WLK occurs frequently and the frequently activated word line WLK switches between an activated state and a deactivated state, a change in the charge amounts stored in the cell capacitors CAP_K-1 and CAP_K+1 included in the memory cells CELL_K-1 and CELL_K+1 may increase, and the data of the memory cells CELL_K-1 and CELL_K+1 may degrade.

[0009] Furthermore, since electromagnetic waves generated when a word line switches between an activated state and a deactivated state introduce electrons into or discharge electrons from a cell capacitor of a memory cell coupled to an adjacent word line, data may be damaged.

[0010] A method primarily used to combat row hammering (according to row hammering, data degradation of memory cells coupled to word lines WLK-1 and WLK+1 occurs when word line WLK is repeatedly activated at least a predetermined number of times) is to additionally refresh adjacent word lines (e.g., WLK+1 and WLK-1) affected by row hammering in addition to a regular refresh operation (a normal refresh operation). This additional refresh operation on adjacent word lines is called a targeted refresh operation. Summary of the Invention

[0011] Each embodiment of the present invention is directed to a semiconductor memory device capable of effectively preventing row hammering in a burst refresh mode.

[0012] In one embodiment, a semiconductor memory device may include: a first counting circuit adapted to count a first clock signal that switches continuously in each burst refresh cycle based on a burst refresh command signal and generate a first counting code signal; a cycle guiding circuit adapted to generate a second clock signal that switches once in each burst refresh cycle based on the burst refresh command signal and a precharge signal; a second counting circuit adapted to count the second clock signal and generate a second counting code signal; and a control circuit adapted to generate a latch control signal for latching a target address in each burst refresh cycle based on the first counting code signal and the second counting code signal.

[0013] The control circuit may generate a latch control signal when a first count value corresponding to the first count code signal and a second count value corresponding to the second count code signal are identical.

[0014] In response to the burst refresh command signal, the first counting circuit may count the first clock signal during each burst refresh period after being initialized in each burst refresh period.

[0015] The cycle steering circuit may generate a second clock signal that is activated based on the burst refresh command signal and deactivated based on the precharge signal.

[0016] The control circuit may include: a comparison unit adapted to generate a comparison signal corresponding to a result of comparing a first count value corresponding to the first counting code signal and a second count value corresponding to the second counting code signal; a limit unit adapted to generate a limit signal activated within a limit period based on the comparison signal and a burst refresh command signal; and an output unit adapted to output a latch control signal switched within the limit period based on the limit signal and the first clock signal.

[0017] The semiconductor memory device may further include a period conversion circuit adapted to generate the non-periodically switched first clock signal based on the periodically switched third clock signal.

[0018] In one embodiment, a semiconductor memory device may include: a counting circuit adapted to count a first clock signal that switches continuously in each burst refresh cycle based on a burst refresh command signal and generate a counting code signal; a cycle steering circuit adapted to generate a second clock signal that switches once in each burst refresh cycle based on the burst refresh command signal and a precharge signal; a randomizing circuit adapted to generate a random code signal corresponding to a random value in each burst refresh cycle based on the second clock signal; and a control circuit adapted to generate a latch control signal for latching a target address in each burst refresh cycle based on the counting code signal and the random code signal.

[0019] When the count value corresponding to the count code signal and the random value corresponding to the random code signal are identical, the control circuit may generate a latch control signal.

[0020] In response to the burst refresh command signal, the counting circuit may count the first clock signal during each burst refresh period after being initialized in each burst refresh period.

[0021] The cycle steering circuit may generate a second clock signal that is activated based on the burst refresh command signal and deactivated based on the precharge signal.

[0022] The randomization circuit may include: a clock signal generating unit adapted to generate a third clock signal; a random value generating unit adapted to generate a code signal corresponding to a random value at least once in each burst refresh cycle based on the third clock signal; and a latching unit adapted to latch the code signal as a random code signal in each burst refresh cycle based on the second clock signal.

[0023] The control circuit may include: a comparison unit adapted to generate a comparison signal corresponding to a result of comparing a count value corresponding to the count code signal and a random value corresponding to the random code signal; a limit unit adapted to generate a limit signal activated within a limit period based on the comparison signal and a burst refresh command signal; and an output unit adapted to output a latch control signal switched within the limit period based on the limit signal and a first clock signal.

[0024] The semiconductor memory device may further include a period conversion circuit adapted to generate the non-periodically switched first clock signal based on the periodically switched fourth clock signal.

[0025] In one embodiment, a semiconductor memory device may include: a memory area adapted to perform a normal operation based on a normal address signal and to perform a target refresh operation based on a target address signal; a refresh controller adapted to generate a latch control signal in each burst refresh cycle based on a burst refresh command signal, the latch control signal being activated within a limit period different from a previous limit period included in a previous burst refresh cycle; and an address latch adapted to latch a normal address signal input within a different limit period as a target address signal in each burst refresh cycle based on the latch control signal.

[0026] The refresh controller may include: a first counting circuit, which is suitable for counting a first clock signal that switches continuously in each burst refresh cycle based on a burst refresh command signal and generating a first counting code signal; a cycle guiding circuit, which is suitable for generating a second clock signal that switches once in each burst refresh cycle based on the burst refresh command signal and a precharge signal; a second counting circuit, which is suitable for counting the second clock signal and generating a second counting code signal; and a control circuit, which is suitable for generating a latch control signal in each burst refresh cycle based on the first counting code signal and the second counting code signal.

[0027] The control circuit may generate a latch control signal when a first count value corresponding to the first count code signal and a second count value corresponding to the second count code signal are identical.

[0028] In response to the burst refresh command signal, the first counting circuit may count the first clock signal during each burst refresh period after being initialized in each burst refresh period.

[0029] The cycle steering circuit may generate a second clock signal that is activated based on the burst refresh command signal and deactivated based on the precharge signal.

[0030] The control circuit may include: a comparison unit adapted to generate a comparison signal corresponding to a result of comparing a first count value corresponding to the first counting code signal and a second count value corresponding to the second counting code signal; a limit unit adapted to generate a limit signal activated within a limit period based on the comparison signal and a burst refresh command signal; and an output unit adapted to output a latch control signal switched within the limit period based on the limit signal and the first clock signal.

[0031] The refresh controller may further include a period conversion circuit adapted to generate the non-periodically switched first clock signal based on the periodically switched third clock signal.

[0032] The refresh controller may include: a counting circuit adapted to count a first clock signal that switches continuously in each burst refresh cycle based on a burst refresh command signal and generate a counting code signal; a cycle guiding circuit adapted to generate a second clock signal that switches once in each burst refresh cycle based on the burst refresh command signal and a precharge signal; a randomizing circuit adapted to generate a random code signal corresponding to a random value in each burst refresh cycle based on the second clock signal; and a control circuit adapted to generate a latch control signal in each burst refresh cycle based on the counting code signal and the random code signal when the count value corresponding to the counting code signal and the random value corresponding to the random code signal are the same.

[0033] When the count value corresponding to the count code signal and the random value corresponding to the random code signal are identical, the control circuit may generate a latch control signal.

[0034] In response to the burst refresh command signal, the counting circuit may count the first clock signal during each burst refresh period after being initialized in each burst refresh period.

[0035] The cycle steering circuit may generate a second clock signal that is activated based on the burst refresh command signal and deactivated based on the precharge signal.

[0036] The randomization circuit may include: a clock signal generating unit adapted to generate a third clock signal; a random value generating unit adapted to generate a code signal corresponding to a random value at least once in each burst refresh cycle based on the third clock signal; and a latching unit adapted to latch the code signal as a random code signal in each burst refresh cycle based on the second clock signal.

[0037] The control circuit may include: a comparison unit adapted to generate a comparison signal corresponding to a result of comparing a count value corresponding to the count code signal and a random value corresponding to the random code signal; a limit unit adapted to generate a limit signal activated within a limit period based on the comparison signal and a burst refresh command signal; and an output unit adapted to output a latch control signal switched within the limit period based on the limit signal and a first clock signal.

[0038] The refresh controller may include a period conversion circuit adapted to generate the non-periodically switched first clock signal based on the periodically switched fourth clock signal.

[0039] The memory area may perform a target refresh operation in each burst refresh cycle based on the burst refresh command signal and a previous target address signal latched as a target address signal within a previous limit period.

[0040] In an embodiment, by effectively preventing row hammering in the burst refresh mode, operation reliability according to the burst refresh mode may be improved. BRIEF DESCRIPTION OF THE DRAWINGS

[0041] FIG. 1 is a diagram illustrating a portion of a memory cell array for explaining row hammering.

[0042] Figure 2 is a block diagram illustrating a semiconductor memory device according to a first embodiment of the present invention.

[0043] Figure 3 is a diagram illustrating an embodiment of the present invention Figure 2 The block diagram of the refresh controller is shown in .

[0044] Figure 4 is a diagram illustrating another embodiment according to the present invention Figure 2 The block diagram of the refresh controller is shown in .

[0045] Figure 5 It is an icon Figure 3 and Figure 4 The block diagram of the control circuit is shown in .

[0046] Figure 6 The description includes Figure 3 8 is a timing diagram of the operation of the semiconductor memory device shown in FIG.

[0047] Figure 7 The description includes Figure 4 8 is a timing diagram of the operation of the semiconductor memory device shown in FIG.

[0048] Figure 8 is a block diagram illustrating a semiconductor memory device according to a second embodiment of the present invention.

[0049] Figure 9 It is an icon Figure 8 The block diagram of the refresh controller is shown in .

[0050] Figure 10 It is an icon Figure 8 The block diagram of the refresh controller is shown in .

[0051] Figure 11 It is an icon Figure 9 and Figure 10 Block diagram of the randomization circuit shown in .

[0052] Figure 12 It is an icon Figure 9 and Figure 10 The block diagram of the control circuit is shown in .

[0053] Figure 13 The description includes Figure 10 8 is a timing diagram of the operation of the semiconductor memory device shown in FIG. DETAILED DESCRIPTION

[0054] Various embodiments will be described in more detail below with reference to the accompanying drawings. However, the present invention can be implemented in different forms and should not be construed as being limited to the embodiments set forth herein. On the contrary, these embodiments are provided so that this disclosure will be thorough and complete, and these embodiments will fully convey the scope of the present invention to those skilled in the art. Throughout this disclosure, the same reference numerals will always refer to the same parts in each of the figures and embodiments of the present invention.

[0055] Figure 2is a block diagram illustrating a semiconductor memory device according to a first embodiment of the present invention.

[0056] refer to Figure 2 , a semiconductor memory device may include a memory area 100 , a refresh controller 200 , and an address latch 300 .

[0057] The memory area 100 can perform normal operations based on the normal command signal NOR_CMD and the normal address signal NADD, and can perform a targeted refresh operation based on the burst refresh command signal BUR_REF_CMD and the target address signal TADD. Although not shown in the figure, the memory area 100 may include a memory array having a plurality of memory cells arranged in rows and columns, and peripheral circuits for performing normal operations and targeted refresh operations. For example, the peripheral circuits may include a word line driver and a row decoder for controlling the memory array on a row basis.

[0058] The burst refresh command signal BUR_REF_CMD may include a plurality of normal refresh command signals that are input continuously with a minimum time interval therebetween allowing the target refresh operation to be performed. For example, in the 8-burst refresh operation mode, the first to eighth normal refresh command signals may be input continuously in each burst refresh cycle. In the burst refresh operation mode, a plurality of target refresh operations are collectively performed in a specific period of each burst refresh cycle, thereby ensuring that other operations (e.g., normal operations) are performed in the remaining period of the burst refresh cycle without being interfered with by the target refresh operation.

[0059] Normal operations may include a write operation for writing data into a memory array, a read operation for reading data from the memory array, etc. A targeted refresh operation may include an operation of additionally refreshing adjacent word lines in addition to a normal refresh operation to address row hammering, in which data of memory cells coupled to adjacent word lines degrades due to a specific word line being repeatedly accessed and activated at least a predetermined number of times.

[0060] The refresh controller 200 may generate the latch control signal SRLATEN for a limit period different from a previous limit period included in a previous burst refresh period in each burst refresh cycle based on the burst refresh command signal BUR_REF_CMD and the precharge signal PCG.

[0061] The address latch 300 may latch the normal address signal NADD input in different limit periods in each burst refresh period as the target address signal TADD based on the latch control signal SRLATEN.

[0062] Figure 3 is a diagram illustrating an embodiment of the present invention Figure 2 A block diagram of the refresh controller 200 is shown.

[0063] refer to Figure 3 , the refresh controller 200 may include a first counting circuit 210 , a cycle guiding circuit 220 , a second counting circuit 230 and a control circuit 240 .

[0064] The first counting circuit 210 can count the first clock signal OSC that switches continuously in each burst refresh period based on the burst refresh command signal BUR_REF_CMD and generate a first counting code signal OSC_CNT corresponding to the count value thereof (hereinafter referred to as the "first count value"). In response to the burst refresh command signal BUR_REF_CMD, the first counting circuit 210 can count the first clock signal OSC during each burst refresh period after being initialized in each burst refresh period.

[0065] The cycle steering circuit 220 can generate a second clock signal REFCLK that switches once in each burst refresh cycle based on the burst refresh command signal BUR_REF_CMD and the precharge signal PCG. The cycle steering circuit 220 can generate the second clock signal REFCLK, which is activated based on the burst refresh command signal BUR_REF_CMD and deactivated based on the precharge signal PCG. For example, the cycle steering circuit 220 can include an SR latch.

[0066] The second counting circuit 230 may count the second clock signal REFCLK and generate a second counting code signal REFCLK_CNT corresponding to a count value thereof (hereinafter referred to as a “second count value”).

[0067] The control circuit 240 may generate a latch control signal SRLATEN in each burst refresh period based on the first and second counting code signals OSC_CNT and REFCLK_CNT. In each burst refresh period, the control circuit 240 may generate a latch control signal SRLATEN when the first and second counting values ​​are the same.

[0068] Figure 4 is a diagram illustrating another embodiment according to the present invention Figure 2 The block diagram of the refresh controller 200 is shown in FIG. Figure 3 and Figure 4 Throughout the drawings, the same reference numerals are used to refer to the same elements.

[0069] refer to Figure 4The refresh controller 200 may include a first counting circuit 210 , a cycle guiding circuit 220 , a second counting circuit 230 , a control circuit 240 and a cycle converting circuit 250 .

[0070] because Figure 4 The first counting circuit 210, the cycle guiding circuit 220, the second counting circuit 230 and the control circuit 240 shown in FIG. Figure 3 , and thus description thereof will be omitted herein. However, the first counting circuit 210 may generate the first counting code signal PRBS_CNT based on the third clock signal PRBS to be described below, and the control circuit 240 may use the third clock signal PRBS and the first counting code signal PRBS_CNT instead of Figure 3 The latch control signal SRLATEN is generated by using the first clock signal OSC and the first counting code signal OSC_CNT shown in FIG.

[0071] The control circuit 240 may generate the latch control signal SRLATEN when the first count value is identical to the second count value based on the first counting code signal PRBS_CNT and the second counting code signal REFCLK_CNT.

[0072] The period conversion circuit 250 may generate a non-periodically switched third clock signal PRBS based on the periodically switched first clock signal OSC. For example, the period conversion circuit 250 may include a pseudo-random binary sequence (PRBS) circuit.

[0073] Figure 5 It is an icon Figure 3 and Figure 4 The block diagram of the control circuit 240 is shown in FIG. In the following, for the convenience of explanation, the following representative examples will be described. Figure 3 The control circuit 240 shown in FIG.

[0074] refer to Figure 5 , the control circuit 240 may include a comparison unit 241 , a limit unit 243 and an output unit 245 .

[0075] The comparison unit 241 may generate a comparison signal CMP corresponding to a result of comparing the first count value and the second count value based on the first counting code signal OSC_CNT and the second counting code signal REFCLK_CNT.

[0076] The limit unit 243 may generate a limit signal GTED activated within a limit period based on the comparison signal CMP and the burst refresh command signal BUR_REF_CMD. For example, the limit unit 243 may generate a limit signal GTED that is activated based on the burst refresh command signal BUR_REF_CMD and deactivated based on the comparison signal CMP.

[0077] The output unit 245 can generate a latch control signal SRLATEN that switches within a limit period based on the limit signal GTED and the first clock signal OSC. The output unit 245 can generate the latch control signal SRLATEN by gating the first clock signal OSC according to the limit signal GTED. When the limit signal GTED is activated within the limit period, the output unit 245 can output the first clock signal OSC as the latch control signal SRLATEN.

[0078] In the following, reference will be made to Figure 6 and Figure 7 The operation of the semiconductor memory device having the above-described configuration according to the first embodiment will be described.

[0079] Figure 6 The description includes Figure 3 1 is a timing diagram of the operation of the semiconductor memory device of the refresh controller 200 shown in FIG.

[0080] refer to Figure 6 , when the burst refresh command signal BUR_REF_CMD including the first normal refresh command signal to the eighth normal refresh command signal is input in the 8-burst refresh operation mode, the burst refresh period tREFI*8 may include a period corresponding to 8 times the normal refresh period tREFI assigned to each of the first normal refresh command signal to the eighth normal refresh command signal.

[0081] In each burst refresh period tREFI*8, the refresh controller 200 may generate the latch control signal SRLATEN within a limit period different from a previous limit period included in a previous burst refresh period. For example, in each burst refresh period tREFI*8, when the first count value corresponding to the first counting code signal OSC_CNT and the second count value corresponding to the second counting code signal REFCLK_CNT are the same, the refresh controller 200 may generate the latch control signal SRLATEN. That is, in the first burst refresh period tREFI*8, when the limit signal GTED is activated within the first limit period from the time point when the burst refresh command signal BUR_REF_CMD is input to the time point when both the first count value and the second count value become "1", the refresh controller 200 may output the first clock signal OSC as the latch control signal SRLATEN. In addition, in the nth burst refresh period tREFI*8, when the limit signal GTED is activated within the nth limit period from the time point when the burst refresh command signal BUR_REF_CMD is input to the time point when both the first count value and the second count value become "n", the refresh controller 200 can output the first clock signal OSC as the latch control signal SRLATEN.

[0082] The address latch 300 can latch the normal address signal NADD input during different limit periods in each burst refresh period tREFI*8 as the target address signal TADD based on the latch control signal SRLATEN. For example, in the first burst refresh period tREFI*8, the address latch 300 can latch the normal address signal NADD input when the latch control signal SRLATEN switches for the second time (i.e., the last time) during the first limit period as the target address signal TADD. Furthermore, in the nth burst refresh period tREFI*8, the address latch 300 can latch the normal address signal NADD input when the latch control signal SRLATEN switches for the (n+1)th time (i.e., the last time) during the nth limit period as the target address signal TADD.

[0083] For reference, if the latch control signal SRLATEN switches multiple times within each burst refresh period tREFI*8, the address latch 300 may latch the normal address signal NADD input each time the latch control signal SRLATEN switches. As a result, the address latch 300 may latch the normal address signal NADD input when the latch control signal SRLATEN switches last as the final target address signal TADD.

[0084] At the same time, during different defined time periods within each burst refresh period tREFI*8, the address latch 300 can latch the normal address signal NADD input during the last switching period of the latch control signal SRLATEN as the target address signal TADD. This allows for sampling any one of the multiple normal address signals NADD sequentially input during the burst refresh period tREFI*8. In other words, this allows for sampling any one of the normal address signals NADD input during different time periods within each burst refresh period tREFI*8. Here, sampling can mean randomly selecting the most frequently input normal address signal NADD from among the multiple normal address signals NADD. This offers advantages in terms of power and area over a method of counting multiple normal address signals NADD for each individual normal address signal. Furthermore, it allows for sampling and latching the normal address signal NADD input at different sampling points within each burst refresh period tREFI*8 as the target address signal TADD.

[0085] The memory area 100 can perform a target refresh operation based on the burst refresh command signal BUR_REF_CMD and the target address signal TADD. For example, in each burst refresh cycle, when the burst refresh command signal BUR_REF_CMD is input, the memory area 100 can perform a target refresh operation based on the previous target address signal TADD latched within the previous limit period.

[0086] Figure 7 The description includes Figure 4 1 is a timing diagram of the operation of the semiconductor memory device of the refresh controller 200 shown in FIG.

[0087] because Figure 7 and Figure 6 are basically the same, so their description will be omitted in this article. Figure 7 In, compared to Figure 6 , a non-periodic switching third clock signal PRBS may be used instead of the periodically switching first clock signal OSC. For example, the third clock signal PRBS may be non-periodic switching in each predetermined period PRBS 15.

[0088] Figure 8 is a block diagram illustrating a semiconductor memory device according to a second embodiment of the present invention.

[0089] refer to Figure 8 , the semiconductor memory device may include a memory area 1100 , a refresh controller 1200 , and an address latch 1300 .

[0090] Since the memory area 1100 and the address latch 1300 may have substantially the same configuration as the memory area 100 and the address latch 300 shown in the first embodiment, descriptions of the memory area 1100 and the address latch 1300 will be omitted herein. Hereinafter, the refresh controller 1200 will be described in detail.

[0091] Figure 9 It is an icon Figure 8 A block diagram of the refresh controller 1200 is shown in FIG.

[0092] refer to Figure 9 , the refresh controller 1200 may include a counting circuit 1210 , a cycle steering circuit 1220 , a randomizing circuit 1230 , and a control circuit 1240 .

[0093] Since the counting circuit 1210, the cycle guiding circuit 1220 and the control circuit 1240 can be used in conjunction with the first embodiment (see Figure 3 ) have substantially the same configuration, so description thereof will be omitted herein.

[0094] The randomization circuit 1230 may generate a random code signal RDNUM_CNT corresponding to a random value in each burst refresh period based on the second clock signal REFCLK.

[0095] Figure 10 It is an icon Figure 8 A block diagram of the refresh controller 1200 is shown in FIG.

[0096] refer to Figure 10 , compared to Figure 9 , the refresh controller 1200 may further include a cycle conversion circuit 1250. Since the cycle conversion circuit 1250 can be used with the first embodiment (see Figure 4 ) has substantially the same configuration, so a description thereof will be omitted herein.

[0097] Figure 11 It is an icon Figure 9 and Figure 10 A block diagram of the randomization circuit 1230 is shown in FIG.

[0098] refer to Figure 11 The randomization circuit 1230 may include a clock signal generation unit 1231 , a random value generation unit 1233 , and a latch unit 1235 .

[0099] The clock signal generating unit 1231 may generate a fourth clock signal OSC′.

[0100] The random value generation unit 1233 may generate a code signal RDNUM corresponding to a random value at least once in each burst refresh period based on the fourth clock signal OSC′.

[0101] The latch unit 1235 may latch the code signal RDNUM as a random code signal RDNUM_CNT in each burst refresh period based on the second clock signal REFCLK.

[0102] Figure 12 It is an icon Figure 9 and Figure 10 , a block diagram of the control circuit 1240 is shown in FIG.

[0103] refer to Figure 12 , the control circuit 1240 may include a comparing unit 1241 , a limiting unit 1243 and an output unit 1245 .

[0104] Since the comparison unit 1241, the limit unit 1243 and the output unit 1245 can have substantially the same configuration as those of the first embodiment, a detailed description thereof will be omitted herein. However, the comparison unit 1241 can compare the random code signal RDNUM_CNT with the counting code signal OSC_CNT or PRBS_CNT.

[0105] In the following, reference will be made to Figure 13 The operation of the semiconductor memory device having the above-described configuration according to the second embodiment will be described.

[0106] Figure 13 The description includes Figure 10 1 is a timing diagram of the operation of the semiconductor memory device shown in FIG. 1 .

[0107] refer to Figure 13 , when the burst refresh command signal BUR_REF_CMD including the first normal refresh command signal to the eighth normal refresh command signal is input in the 8-burst refresh operation mode, the burst refresh period tREFI*8 may include a period corresponding to 8 times the refresh period tREFI assigned to each of the first normal refresh command signal to the eighth normal refresh command signal.

[0108] In each burst refresh period tREFI*8, the refresh controller 1200 may generate the latch control signal SRLATEN within a limit period different from a previous limit period included in the previous burst refresh period. For example, in each burst refresh period tREFI*8, when the count value corresponding to the count code signal PRBS_CNT and the random value corresponding to the random code signal RDNUM_CNT are the same, the refresh controller 1200 may generate the latch control signal SRLATEN. If the random code signal RDNUM_CNT corresponding to the random value "5" is generated in the first burst refresh period tREFI*8, when the limit signal GTED is activated within the first limit period from the time point when the burst refresh command signal BUR_REF_CMD is input to the time point when the count value corresponding to the count code signal PRBS_CNT becomes the random value "5", the control circuit 1240 may output the third clock signal PRBS as the latch control signal SRLATEN. If a random code signal RDNUM_CNT corresponding to a random value “10” is generated in the second burst refresh period tREFI*8, when the limit signal GTED is activated within the second limit period including the entire period of the second burst refresh period tREFI*8, the control circuit 1240 may output the third clock signal PRBS as the latch control signal SRLATEN.

[0109] The address latch 1300 can latch the normal address signal NADD input in different limit periods in each burst refresh period tREFI*8 as the target address signal TADD based on the latch control signal SRLATEN. For example, in the first burst refresh period tREFI*8, the address latch 1300 can latch the normal address signal NADD input when the latch control signal SRLATEN is last switched during the first limit period as the target address signal TADD.

[0110] The memory area 1100 can perform a target refresh operation based on the burst refresh command signal BUR_REF_CMD and the target address signal TADD. For example, in each burst refresh cycle, when the burst refresh command signal BUR_REF_CMD is input, the memory area 1100 can perform a target refresh operation based on the previous target address signal TADD latched within the previous limit period.

[0111] As apparent from the embodiments of the present disclosure, the following advantage is provided: the target address signal can be latched (ie, sampled) at different time points (ie, different sampling time points) in each burst refresh period.

[0112] Although various embodiments have been described for purposes of illustration, it will be apparent to those skilled in the art that various changes and modifications can be made without departing from the spirit and scope of the invention as defined in the following claims.

Claims

1. A semiconductor memory device comprising: a counting circuit adapted to count the first clock signal continuously switched in each burst refresh period based on the burst refresh command signal and generate a counting code signal; a cycle steering circuit adapted to generate a second clock signal that switches once in each burst refresh cycle based on the burst refresh command signal and the precharge signal; a randomizing circuit adapted to generate a random code signal corresponding to a random value in each burst refresh cycle based on the second clock signal; as well as a control circuit adapted to generate a latch control signal for latching a target address in each burst refresh cycle based on the counting code signal and the random code signal, Wherein, the randomization circuit includes: a clock signal generating unit adapted to generate a third clock signal; a random value generating unit adapted to generate a code signal corresponding to a random value at least once in each burst refresh period based on a third clock signal; and The latch unit is adapted to latch the code signal generated by the random value generating unit into a random code signal in each burst refresh period based on the second clock signal.

2. The semiconductor memory device of claim 1, wherein the control circuit generates the latch control signal when the count value corresponding to the count code signal and the random value corresponding to the random code signal are identical.

3. The semiconductor memory device according to claim 1, wherein The counting circuit counts the first clock signal during each burst refresh period after being initialized in each burst refresh period in response to the burst refresh command signal.

4. The semiconductor memory device according to claim 1, wherein The cycle steering circuit generates a second clock signal that is activated based on the burst refresh command signal and deactivated based on the precharge signal.

5. The semiconductor memory device according to claim 1, wherein The control circuit includes: a comparison unit adapted to generate a comparison signal corresponding to a result of comparing a count value corresponding to the count code signal and a random value corresponding to the random code signal; a limit unit adapted to generate a limit signal activated within a limit period based on the comparison signal and the burst refresh command signal; and The output unit is adapted to output a latch control signal switched within a limit period based on the limit signal and the first clock signal.

6. The semiconductor memory device according to claim 1, further comprising: The period conversion circuit is adapted to generate a non-periodically switched first clock signal based on a periodically switched fourth clock signal.

7. A semiconductor memory device comprising: a counting circuit adapted to count the first clock signal continuously switched in each burst refresh period based on the burst refresh command signal and generate a counting code signal; a cycle steering circuit adapted to generate a second clock signal that switches once in each burst refresh cycle based on the burst refresh command signal and the precharge signal; a randomizing circuit adapted to generate a random code signal corresponding to a random value in each burst refresh cycle based on the second clock signal; as well as a control circuit adapted to generate a latch control signal for latching a target address in each burst refresh cycle based on the counting code signal and the random code signal, Wherein, the control circuit includes: a comparison unit adapted to generate a comparison signal corresponding to a result of comparing a count value corresponding to the count code signal and a random value corresponding to the random code signal; a limit unit adapted to generate a limit signal activated within a limit period based on the comparison signal and the burst refresh command signal; and The output unit is adapted to output a latch control signal switched within a limit period based on the limit signal and the first clock signal.

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