Memory controller and control method thereof

Abstract

A memory controller is used to access multiple NAND memory dies. The memory controller includes an internal memory, an output selection circuit, a control circuit, and a data access circuit. The internal memory is used to store multiple sets of access setting values ​​corresponding to the NAND memory dies. The output selection circuit is coupled to the internal memory and is used to select a set of access setting values ​​for a NAND memory die based on an output selection signal. The control circuit is coupled to the output selection circuit and is used to generate an output selection signal when accessing the NAND memory die. The data access circuit is coupled to the output selection circuit and is used to access the NAND memory die based on the set of access setting values.

Description

Technical Field

[0001] The present invention relates to electronic circuits, and in particular to a memory controller and a control method thereof. Background Art

[0002] Non-volatile memory is widely used in personal computers, telecommunications, consumer electronics, and other fields. Non-volatile memory typically uses NAND (NAND) memory as a storage medium. NAND memory has the characteristics of long response time and large-scale data throughput. With the development of technology, NAND memory has evolved from a two-dimensional structure to a three-dimensional structure, and the number of three-dimensional stacking layers has continued to increase. NAND memory cells have evolved from triple-level cells (TLC) to quad-level cells (QLC) and even multi-level cells (XLC). The capacity of a single NAND memory chip has increased significantly, but the negative impact is that the internal operation has become more complicated and the performance deviation between a large number of NAND memory cells has increased, resulting in reduced performance and increased power consumption of NAND memory. Summary of the Invention

[0003] Embodiments of the present invention relate to a memory controller for accessing multiple NAND memory dies. The memory controller includes an internal memory, an output selection circuit, a control circuit, and a data access circuit. The internal memory is used to store multiple sets of access setting values ​​corresponding to the NAND memory dies. The output selection circuit is coupled to the internal memory and is used to select a set of access setting values ​​corresponding to a NAND memory die based on an output selection signal. The control circuit is coupled to the output selection circuit and is used to generate an output selection signal when accessing the NAND memory die. The data access circuit is coupled to the output selection circuit and is used to access the NAND memory die based on the set of access setting values.

[0004] An embodiment of the present invention relates to a method for controlling a memory controller. The memory controller is coupled to multiple NAND memory dies. The memory controller includes an internal memory, an output selection circuit, a control circuit, and a data access circuit. The output selection circuit is coupled to the internal memory. The control circuit and the data access circuit are coupled to the output selection circuit. The method includes storing multiple sets of access setting values ​​corresponding to the NAND memory dies in the internal memory. When accessing a NAND memory dies, the control circuit generates an output selection signal, the output selection circuit selects a set of access setting values ​​corresponding to the NAND memory dies based on the output selection signal, and the data access circuit accesses the NAND memory dies based on the set of access setting values. BRIEF DESCRIPTION OF THE DRAWINGS

[0005] Figure 1 FIG. 4 is a block diagram of a memory device according to an embodiment of the present invention.

[0006] Figure 2 for Figure 1 A flowchart of a control method for a memory controller in FIG.

[0007] Figure 3 for Figure 1 A flowchart of another control method of a memory controller in FIG.

[0008] Figure 4 for Figure 1 A flowchart of another control method of a memory controller in FIG.

[0009] Figure 5 for Figure 1 A flowchart of another control method of the memory controller in FIG. DETAILED DESCRIPTION

[0010] Figure 1 The following is a block diagram of a memory device 1 according to an embodiment of the present invention. Memory device 1 may be a solid state drive (SSD), an embedded multimedia card (EMMC), or a NAND flash memory device that complies with the Open NAND Flash Interface (ONFI) standard and / or the Toggle Mode standard. Memory device 1 includes a memory controller 10 and NAND memory dies 121-12N, where N is an integer greater than 2 and represents the next digit following the number 12. It should be understood that this is merely an example and does not limit the number of NAND memory dies. Memory controller 10 is coupled to NAND memory dies 121-12N to control data access operations of NAND memory dies 121-12N, including data write operations and data read operations. NAND memory dies 121-12N can communicate with memory controller 10 in a parallel pipeline manner to increase data transfer rates. As the number N of NAND memory dies 121-12N increases, performance variations may exist between the NAND memory dies 121-12N. Furthermore, due to the size limitations of the circuit board, the routing between the NAND memory dies 121-12N and the memory controller 10 may be inconsistent. Therefore, the memory controller 10 may set multiple sets of corresponding access setting values ​​for data access based on the driving capabilities and anti-interference capabilities of the NAND memory dies 121-12N. Before shipment, the memory device 1 may test the routing and performance differences of each NAND memory die and generate a set of corresponding access setting values. During use, the memory device 1 may access data based on the set of corresponding access setting values ​​for each NAND memory die, thereby improving the operating performance of the memory device 1 and reducing the operating power consumption of the memory device 1.

[0011] The memory controller 10 includes a central control unit 100, an input selection circuit 101, a control circuit 102, a first internal memory 103, a second internal memory 104, an output selection circuit 105, a data access circuit 106, and a command transmission circuit 107. The central control unit 100 is coupled to the input selection circuit 101 and the second internal memory 104. The control circuit 102 is coupled to the input selection circuit 101 and the output selection circuit 105. The first internal memory 103 is coupled to the input selection circuit 101 and the output selection circuit 105. The output selection circuit 105 is coupled to the data access circuit 106. The second internal memory 104 is coupled to the command transmission circuit 107. The data access circuit 106 and the command transmission circuit 107 are coupled to the NAND memory dies 121-12N.

[0012] The first internal memory 103 can store multiple sets of access setting values ​​1031 to 103N corresponding to the NAND memory chips 121 to 12N, where N represents the next digit following the number 103. For example, one set of access setting values ​​1031 can correspond to the NAND memory chip 121, another set of access setting values ​​1032 can correspond to the NAND memory chip 122, and so on. The first internal memory 103 can be a non-volatile memory. Each set of access setting values ​​includes the output driver strength (ODS) and the on-die termination (ODT) of the corresponding NAND memory chip. The driving resistance value of the driving force is shown in Table 1:

[0013]

[0014] The data access circuit 106 may include an input / output driver, and the number of file bits of the driving force setting value may be related to the supply voltage of the input / output driver. For example, when the supply voltage of the input / output driver is 1.8V, the driving force setting value may be set to 2.0 times, 1.4 times, 1.0 times, or 0.7 times, respectively providing driving resistance values ​​of 18 ohms, 25 ohms, 35 ohms, and 50 ohms in the data access circuit 106. A smaller driving resistance value may correspond to a larger driving force setting value. The driving force resistance values ​​shown in Table 1 are for example only and are not intended to limit the present invention.

[0015] The terminal resistance setting values ​​corresponding to the terminal resistance can be shown in Table 2:

[0016] Terminal resistance setting value (bit) Terminal resistance value (ohms) 0000001000 150 0000001100 100 0000010000 75 0000011000 50 0000101000 30

[0017] Table 2 shows that the five terminal resistance setting values ​​can provide terminal resistance values ​​of 150 ohms, 100 ohms, 75 ohms, 50 ohms and 30 ohms in the output selection circuit 105 respectively. The smaller the terminal resistance value, the stronger the anti-interference ability of the data access circuit 106 when receiving data. The risk of a resistance value that is too small is that the signal eye diagram may not be able to open, thereby reducing the signal quality. When the transmission quality between the memory controller 10 and the NAND memory grain is good and the noise interference is low, the data access circuit 106 can also turn off the terminal resistance value and directly receive data Ddat from the NAND memory grain. The terminal resistance setting values ​​shown in Table 2 are for example only and are not intended to limit the present invention.

[0018] In one embodiment, the number of NAND memory dies is four (ie, N=4), and the corresponding access setting values ​​1031-1034 of the NAND memory dies 121-124 are shown in Table 3:

[0019]

[0020] Table 3 shows that the data access circuit 106 has a weak data transmission capability and a normal data receiving capability for the NAND memory chip 121. The corresponding access setting value 1031 can be configured as a relatively low driving resistance value (25 ohms) and a medium termination resistance value (100 ohms). The data access circuit 106 has a normal data transmission capability and a normal data receiving capability for the NAND memory chips 122 and 124. The corresponding access setting values ​​1032 and 1034 can be configured as a medium driving resistance value (35 ohms) and a medium termination resistance value (150 ohms). The data access circuit 106 has a normal data transmission capability and a relatively strong data receiving capability for the NAND memory chip 123. The corresponding access setting value 1033 can be configured as a medium driving resistance value (35 ohms) and no termination resistance value (indicated as infinite).

[0021] When accessing NAND memory die 12n, control circuit 102 may generate an output selection signal Sout, where n is a positive integer between 1 and N. Output selection circuit 105 may select a set of access setting values ​​103n for NAND memory die 12n based on output selection signal Sout. Output selection circuit 105 may be implemented as a multiplexer. Control circuit 102 may generate output selection signal Sout using a multiple chip enable (CE) pin approach or a chip enable pin reduction approach. When using multiple chip enable pins, N chip enable signals may correspond to NAND memory die 121-12N. For example, NAND memory die 121-12N may correspond to chip enable signals CE1-CEN, respectively, where N represents the next digit following CE. When accessing NAND memory die 12n, control circuit 102 may use the nth chip enable signal as output selection signal Sout, causing output selection circuit 105 to select the corresponding set of access setting values ​​103n. When using the enable pin reduction method, the control circuit 102 may use a logical unit number (LUN) or a custom memory volume number to generate the output select signal Sout. In some embodiments, the memory controller 10 uses the logical unit number to generate the output select signal Sout, and the N logical unit numbers may correspond to the NAND memory dies 121-12N. For example, the NAND memory dies 121-12N may have logical unit numbers LUN1-LUNN, respectively, where N represents the next digit following LUN. When accessing the NAND memory die 12n, the control circuit 102 may use the logical unit number LUNn of the NAND memory die 12n as the output select signal Sout, so that the output selection circuit 105 selects the set of access settings 103n. In other embodiments, the memory controller 10 uses a custom memory volume number to generate the output select signal Sout, and the N custom memory volume numbers may correspond to the NAND memory dies 121-12N. For example, the user may set the NAND memory chips 121-12N to self-set memory space numbers V1-VN, respectively, after each boot, where N represents the next digit following V. When accessing the NAND memory chip 12n, the control circuit 102 may use the self-set memory space number Vn corresponding to the NAND memory chip 12n as the output selection signal Sout, so that the output selection circuit 105 selects the set of access setting values ​​103n.

[0022] The data access circuit 106 can access the NAND memory die 12n according to the set of access settings 103n. Specifically, the data access circuit 106 can transmit data Ddat to the NAND memory die 12n according to the corresponding driving force (ODS) and receive data Ddat from the NAND memory die 12n according to the corresponding termination resistor.

[0023] When setting the set of access setting values ​​103n, the control circuit 102 can generate an input selection signal Sin, and the central control unit 100 can output a set of updated setting values ​​of the driving force setting value and / or the terminal resistance setting value. The input selection circuit 101 can output the driving force setting value and / or the terminal resistance setting value of the set of access setting values ​​to the first internal memory 103 according to the input selection signal Sin transmitted by the control circuit 102, so as to update the access setting value 103n corresponding to the NAND memory chip 12n. The input selection circuit 101 can be implemented as a multiplexer. The input selection signal Sin can be generated using a multiple chip enable pin method or a chip enable pin reduction method. The multiple chip enable pin method and the chip enable pin reduction method have been explained in the previous paragraph and will not be repeated here.

[0024] The second internal memory 104 can store command channel drive settings 1040 for the NAND memory dies 121-12N. Since commands Dcmd are transmitted at a relatively low speed and require less data drive power, the NAND memory dies 121-12N can share the same command channel drive setting 1040 for data transmission to reduce costs. The second internal memory 104 can be a non-volatile memory. The command transmission circuit 107 can transmit commands Dcmd to the NAND memory die 12n based on the command channel drive setting 1040. The command channel drive setting 1040 can be represented by the drive resistance value shown in Table 1. Although the present embodiment transmits commands Dcmd based on the same command channel drive setting 1040, those skilled in the art can also configure multiple corresponding command channel drive settings for the NAND memory dies 121-12N as needed to enhance transmission performance.

[0025] The memory device 1 sets a set of corresponding access setting values ​​for each NAND memory die, so as to improve the working performance of the memory device 1 and reduce the working power consumption of the memory device 1 .

[0026] Figure 2 This is a flow chart of a control method 200 for the memory controller 10. The control method 200 includes steps S202 to S212, which are used to sequentially test the NAND memory dies 121 to 12N to determine their corresponding driving forces before shipment. Any reasonable technical changes or adjustments to the steps fall within the scope of the present invention. The details of steps S202 to S212 are as follows:

[0027] Step S202: The input selection circuit 101 outputs a set of default access setting values ​​to the first internal memory 103 according to the input selection signal Sin transmitted from the control circuit 102, so as to update a set of access setting values ​​103n corresponding to the NAND memory chip 12n;

[0028] Step S204: the output selection circuit 105 selects the set of access setting values ​​103n according to the output selection signal Sout transmitted from the control circuit 102;

[0029] Step S206: the data access circuit 106 performs a high-speed write operation on the NAND memory die 12n according to the driving force corresponding to the set of access setting values ​​103n;

[0030] Step S208: the data access circuit 106 performs a low-speed read operation on the NAND memory chip 12n according to the terminal resistance corresponding to the set of access setting values ​​103n;

[0031] Step S210: The central control unit 100 determines whether the driving force corresponding to the access setting value 103n is available. If yes, the method 200 ends; if not, the method 200 proceeds to step S212.

[0032] Step S212: the input selection circuit 101 outputs another driving force setting value to the first internal memory 103 according to the input selection signal Sin transmitted from the control circuit 102 to update the driving force corresponding to the set of access setting values ​​103n corresponding to the NAND memory chip 12n; and proceeds to step S204.

[0033] In step S202, the set of preset access setting values ​​may be obtained from past experience, or may be a maximum drive resistance value (e.g., 50 ohms) and a maximum termination resistance value (e.g., 150 ohms). In step S204, the output selection circuit 105 selects the set of access setting values ​​103n corresponding to the NAND memory die 12n. To obtain a preferred drive force corresponding to the NAND memory die 12n, the data access circuit 106 writes the predetermined data to the NAND memory die 12n at a high write speed (step S206), and then reads the data from the NAND memory die 12n at a low read speed (step S208). In some embodiments, the high write speed may be 1600 MHz, and the low read speed may be 50 MHz, but the high write speed and the low read speed are not limited thereto. In step S210, the central control unit 100 compares the read data with the predetermined data. If the read data matches the predetermined data, the central control unit 100 determines that the driving force corresponding to the NAND memory die 12n is available, and the method 200 ends. If the read data does not match the predetermined data, the central control unit 100 determines that the driving force corresponding to the NAND memory die 12n is unavailable. In step S212, because the corresponding driving force is unavailable, the central control unit 100 outputs another terminal resistance setting value to update the terminal resistance corresponding to the set of corresponding access setting values ​​103n. In some embodiments, the other driving force setting value corresponds to another driving resistance value, and the other driving resistance value can be less than the previous driving resistance value of the terminal resistance.

[0034] The memory controller 10 sequentially executes the control method 200 on the NAND memory dies 121-12N to obtain driving forces corresponding to the plurality of access setting values ​​1031-103N. Although the present embodiment terminates the method 200 after obtaining the available driving force, in other embodiments, the memory controller 10 may execute the method 200 on all driving force setting values ​​to determine the availability of all driving resistance values ​​and update the driving force corresponding to the access setting value 103n based on the maximum driving resistance value among all available driving resistance values, thereby accurately transmitting data to the NAND memory die 12n while reducing power consumption.

[0035] Figure 3 This is a flow chart of another control method 300 for the memory controller 10. The control method 300 includes steps S302 to S312, which are used to sequentially test the NAND memory dies 121 to 12N to obtain their corresponding terminal resistances before shipment. Any reasonable technical changes or adjustments to the steps fall within the scope of the present invention. The details of steps S302 to S312 are as follows:

[0036] Step S302: The input selection circuit 101 outputs a set of default access setting values ​​to the first internal memory 103 according to the input selection signal Sin transmitted from the control circuit 102, so as to update a set of access setting values ​​103n corresponding to the NAND memory chip 12n;

[0037] Step S304: the output selection circuit 105 selects the set of access setting values ​​103n according to the output selection signal Sout transmitted from the control circuit 102;

[0038] Step S306: the data access circuit 106 performs a low-speed write operation on the NAND memory chip 12n according to the driving force corresponding to the set of access setting values ​​103n;

[0039] Step S308: the data access circuit 106 performs a high-speed read operation on the NAND memory chip 12n according to the terminal resistance corresponding to the set of access setting values ​​103n;

[0040] Step S310: The central control unit 100 determines whether the terminal resistor corresponding to the access setting value 103n is available. If yes, the method 300 ends; if not, the method 300 proceeds to step S312.

[0041] Step S312: the input selection circuit 101 outputs another terminal resistance setting value to the first internal memory 103 according to the input selection signal Sin sent by the control circuit 102 to update the terminal resistance corresponding to the access setting value 103n of the NAND memory chip 12n; and proceeds to step S304.

[0042] Steps S302 and S304 are the same as steps S202 and S204 and will not be repeated here. To obtain the terminal resistance corresponding to the NAND memory die 12n, the data access circuit 106 writes the predetermined data to the NAND memory die 12n at a low write speed (step S306), and then reads the data from the NAND memory die 12n at a low read speed (step S308). In some embodiments, the low write speed may be 50 MHz and the high read speed may be 1600 MHz, but the high write speed and high read speed are not limited to these. In step S310, the central control unit 100 compares the read data with the predetermined data. If the read data matches the predetermined data, it is determined that the terminal resistance corresponding to the NAND memory die 12n is available, and the method 200 ends. If the read data does not match the predetermined data, it is determined that the terminal resistance corresponding to the NAND memory die 12n is unavailable. In step S312, since the terminal resistor is unavailable, the central control unit 100 outputs another terminal resistor setting value to update the terminal resistor corresponding to the set of access settings 103n. In some embodiments, the other terminal resistor setting value corresponds to another terminal resistance value, and the other terminal resistance value can be smaller than the previous terminal resistance value of the terminal resistor. Steps S304 to S312 are then repeated until it is determined that the terminal resistor is available.

[0043] The memory controller 10 sequentially executes the control method 300 on the NAND memory dies 121-12N to obtain the termination resistances corresponding to the plurality of access setting values ​​1031-103N. Although the present embodiment terminates the method 300 after obtaining the available termination resistances, in other embodiments, the memory controller 10 may execute the method 300 on all termination resistance values ​​to determine the availability of all termination resistance values, and update the termination resistance corresponding to the access setting value 103n based on the maximum termination resistance value among all termination resistance values, thereby accurately reading data from the NAND memory die 12n while reducing power consumption.

[0044] Figure 4 This is a flow chart of another control method 400 for the memory controller 10. The control method 400 includes steps S402 to S410 for accessing the selected NAND memory die 12n. Any reasonable technical changes or step adjustments fall within the scope of the present invention. The details of steps S402 to S410 are as follows:

[0045] Step S402 : The first internal memory 103 stores a plurality of access setting values ​​1031 - 103N corresponding to the NAND memory chips 121 - 12N;

[0046] Step S404: the input selection circuit 101 outputs the updated setting value to the first internal memory 103 according to the input selection signal Sin transmitted from the control circuit 102, so as to update the access setting value 103n corresponding to the NAND memory chip 12n;

[0047] Step S406: When accessing the NAND memory chip 12n, the control circuit 102 generates an output selection signal Sout;

[0048] Step S408: the output selection circuit 105 selects the set of access setting values ​​103n of the NAND memory chip 12n according to the output selection signal Sout;

[0049] Step S410: The data access circuit 106 accesses the NAND memory die 12n according to the set of access setting values ​​103n.

[0050] In step S404, the central control unit 100 outputs the available driving force setting value and / or the available terminal resistance setting value as an update setting value to update the set of access setting values ​​103n. In some embodiments, the available driving force setting value may correspond to the maximum available driving resistance value, and the available terminal resistance setting value may correspond to the maximum available terminal resistance value.

[0051] For example, when the available driving resistance values ​​of the NAND memory die 12n are 25 ohms and 35 ohms, and the available terminal resistance values ​​are 50 ohms and 75 ohms, the central control unit 100 may output an available driving force setting value corresponding to 35 ohms and a terminal resistance setting value corresponding to 75 ohms as the updated setting values. In other embodiments, the available driving force setting value may correspond to any available driving resistance value, and the available terminal resistance setting value may correspond to any available terminal resistance value. The details of steps S402, S406, and S410 have been described in the previous paragraphs and will not be repeated here.

[0052] The control method 400 sets a corresponding set of access setting values ​​to the data access circuit 106 for each NAND memory die to perform data access, thereby improving the operating performance of the memory device 1 and reducing the operating power consumption of the memory device 1 .

[0053] Figure 5 FIG. 5 is a flow chart of another control method 500 for the memory controller 10. The control method 500 includes steps S502 and S504 for transmitting a command Dcmd to the selected NAND memory die 12n. Any reasonable technical changes or step adjustments fall within the scope of the present invention. The details of steps S502 and S504 are as follows:

[0054] Step S502 : The second internal memory 104 stores the command channel driving force setting values ​​1040 of the NAND memory chips 121 ˜ 12N;

[0055] Step S504 : the command transmission circuit 107 transmits the command Dcmd to the NAND memory die 12 n according to the command channel driving force setting value 1040 .

[0056] The details of steps S502 and S504 have been described in the previous paragraphs and will not be repeated here. Since the transmission speed of the command Dcmd is relatively low, the control method 500 can use the same command channel drive setting 1040 to transmit the command Dcmd to the NAND memory dies 121 to 12N, thereby reducing costs without compromising transmission performance.

[0057] The above descriptions are merely preferred embodiments of the present invention. Any equivalent changes and modifications made according to the present invention should fall within the scope of protection of the present invention.

[0058] Description of Reference Numerals

[0059] 1: Memory device

[0060] 10: Memory controller

[0061] 100: Central Control Unit

[0062] 101: Input selection circuit

[0063] 102: Control circuit

[0064] 103: First internal memory

[0065] 1031~103N: Access setting values

[0066] 104: Second internal memory

[0067] 1040: Command channel driver setting value

[0068] 105: Output selection circuit

[0069] 106: Data access circuit

[0070] 107: Command transmission circuit

[0071] 121~12N: NAND memory chips

[0072] Sin: Input selection signal

[0073] Sout: output selection signal

[0074] Ddat: data

[0075] Dcmd: Command

[0076] 200 to 500: Control method

[0077] S202~S212, S302~S312, S402~S410, S502~S504: Steps

Claims

1. A method for controlling a memory controller, wherein the memory controller is coupled to a plurality of NAND memory dies, the memory controller comprising a first internal memory, an output selection circuit, an input selection circuit, a control circuit, a central control unit, and a data access circuit, wherein the output selection circuit is coupled to the first internal memory, and the control circuit and the data access circuit are coupled to the output selection circuit. The method comprises: The input selection circuit outputs a set of preset access setting values ​​to the first internal memory according to an input selection signal transmitted from the control circuit, so as to update a set of access setting values ​​of a NAND memory chip; The output selection circuit selects the set of access setting values ​​according to an output selection signal transmitted from the control circuit; The data access circuit performs a low-speed write operation on the NAND memory die according to the set of access setting values; The data access circuit performs a high-speed read operation on the NAND memory die according to the set of access setting values; and The central control unit determines whether a terminal resistor in the set of access setting values ​​is available based on data obtained by the high-speed read operation.

2. The method according to claim 1, characterized in that The set of access settings includes a driving force and the terminal resistance.

3. The method according to claim 2, characterized in that Determining whether the terminal resistance of the set of access setting values ​​is available includes: If the data obtained by the high-speed read operation matches predetermined data, it is determined that the terminal resistor in the set of access setting values ​​is available.

4. A method for controlling a memory controller, the memory controller being coupled to a plurality of NAND memory dies, the memory controller comprising a first internal memory, an output selection circuit, an input selection circuit, a control circuit, a central control unit, and a data access circuit, the output selection circuit being coupled to the first internal memory, the control circuit and the data access circuit being coupled to the output selection circuit, the method comprising: The input selection circuit outputs a set of preset access setting values ​​to the first internal memory according to an input selection signal transmitted from the control circuit, so as to update a set of access setting values ​​of a NAND memory chip; The output selection circuit selects the set of access setting values ​​according to an output selection signal transmitted from the control circuit; and The data access circuit performs a high-speed write operation on the NAND memory die according to the set of access setting values; The data access circuit performs a low-speed read operation on the NAND memory die according to the set of access setting values; and The central control unit determines whether a driving force in the set of access setting values ​​is available based on data obtained by the low-speed read operation.

5. The method according to claim 4, characterized in that The set of access settings includes the driving force and a terminal resistance.

6. The method according to claim 5, characterized in that Determining whether the set of access settings is available includes: If the data obtained by the low-speed read operation matches predetermined data, it is determined that the driving force in the set of access setting values ​​is available.

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