Polysilicon control gate etching method

Abstract

The present invention discloses a polysilicon control gate etching method, comprising: step 1, forming a first polysilicon layer and a hard mask layer on an underlying structure and performing patterned etching on the hard mask layer; step 2, performing polysilicon opening etching to partially etch the first polysilicon layer in the opening area to form a first opening; polymers will be formed during the polysilicon opening etching, and by increasing the polymers formed during the polysilicon opening etching, a first sidewall formed by the accumulation of polymers will be formed on the side of the first opening after the polysilicon opening etching is completed; step 3, performing polysilicon body etching to etch the first polysilicon layer at the bottom of the first opening to form the side of the polysilicon control gate, the side of the polysilicon control gate surrounds the second opening, and the polysilicon body etching will etch according to the morphology of the first sidewall. The present invention enables the polysilicon control gate to have a vertical side surface and thereby reduces or eliminates the sharp corners at the top of the side surface of the polysilicon control gate.

Description

Technical Field

[0001] The present invention relates to a semiconductor integrated circuit manufacturing method, in particular to a polysilicon control gate (CGPL) etching (ET) method. Background Art

[0002] In the CGPL ET of the flash memory process, the morphology of the CGPL plays an important role in the relevant performance of the product, and the control of the sharp corners of the CGPL top is crucial. In the CGPL ET of the thin gate, due to the non-photoresist (NON-PR) process and the cavity cleaning mode (Clean Mode), the sidewall of the thin gate is not easy to form a sidewall protection (Polymer protection) and the morphology of the concave defect is formed.

[0003] like Figure 1 FIG. 1 is a schematic diagram of a device structure formed by an existing polysilicon control gate etching method; the existing polysilicon control gate etching method includes:

[0004] Step 1: providing an underlying structure 101 , forming a first polysilicon layer 102 on the underlying structure 101 , and forming a hard mask layer 103 on a surface of the first polysilicon layer 102 .

[0005] The hard mask layer 103 is pattern-etched to open the polysilicon opening area.

[0006] Typically, the underlying structure 101 includes:

[0007] Semiconductor substrate;

[0008] A control gate dielectric layer is formed on the semiconductor substrate.

[0009] The polysilicon control gate is applied to flash memory, and the underlying structure 101 further includes:

[0010] A floating gate dielectric layer and a polysilicon floating gate are formed on the surface of the semiconductor substrate.

[0011] The polysilicon control gate is stacked on top of the polysilicon floating gate, and the control gate dielectric layer is located between the polysilicon control gate and the polysilicon floating gate; or, the polysilicon control gate is self-aligned and formed on the side of the polysilicon floating gate.

[0012] The hard mask layer 103 is an oxide layer or a nitride layer.

[0013] The hard mask layer is an oxide layer or a nitride layer.

[0014] The semiconductor substrate includes a silicon substrate.

[0015] The material of the floating gate dielectric layer includes an oxide layer.

[0016] The material of the control gate dielectric layer includes an oxide layer.

[0017] Step 2: Perform polysilicon opening etching (Break Through Etch, BT ET), wherein the polysilicon opening etching etches the hard mask layer 103 in the opening area to form a first opening.

[0018] Step three: performing polysilicon main body etching (MEET), wherein the polysilicon main body etching etches the first polysilicon layer 102 at the bottom of the first opening to form a side surface of a polysilicon control gate, and the side surface of the polysilicon control gate surrounds a second opening.

[0019] The etching of the polysilicon body easily causes the side of the polysilicon control gate to be concave, the bottom width of the second opening will become larger, and a sharp corner is easily formed on the top of the polysilicon control gate, which will have an adverse effect on the performance of products such as flash memory. Moreover, as the thickness of the first polysilicon layer 102 becomes smaller, such as less than During the etching process of the polysilicon body, it is not easy to form a protective sidewall composed of a polymer on the side of the polysilicon control gate, so that a concave defect is inevitably generated.

[0020] Step 4: performing over etching (OE ET), wherein the over etching causes the bottom structure 101 to lose a portion of thickness. Summary of the invention

[0021] The technical problem to be solved by the present invention is to provide a polysilicon control gate etching method, which can eliminate the adverse effect of polysilicon body etching on the side concave of the polysilicon control gate, thereby making the side of the polysilicon control gate vertical and controlling the sharp corners of the polysilicon control gate.

[0022] In order to solve the above technical problems, the polysilicon control gate etching method provided by the present invention comprises:

[0023] Step 1: Provide an underlying structure, form a first polysilicon layer on the underlying structure, form a hard mask layer on the surface of the first polysilicon layer, and perform patterning etching on the hard mask layer to open the polysilicon opening area.

[0024] Step 2: Use the hard mask layer to perform polysilicon opening etching, the polysilicon opening etching removes part of the thickness of the top of the first polysilicon layer in the polysilicon opening area and forms a first opening. A polymer will be formed during the polysilicon opening etching, and by increasing the polymer formed during the polysilicon opening etching, a first side wall formed by the accumulation of the polymer is formed on the side of the first opening after the polysilicon opening etching is completed.

[0025] Step three, perform polysilicon body etching, wherein the polysilicon body etching etches the first polysilicon layer at the bottom of the first opening to form the side of the polysilicon control gate, and the side of the polysilicon control gate surrounds the second opening. The polysilicon body etching will adaptively etch according to the morphology of the first side wall, thereby changing the initial etching direction of the polysilicon body etching and offsetting the effect of the polysilicon body etching process on the side concave of the polysilicon gate, so that the polysilicon control gate has a vertical side and thereby reduces or eliminates the sharp corner of the top side of the polysilicon control gate.

[0026] Further improvements include:

[0027] Step 4: performing over-etching, wherein the over-etching causes the bottom structure to lose a portion of thickness.

[0028] A further improvement is that the underlying structure comprises:

[0029] Semiconductor substrate;

[0030] A control gate dielectric layer is formed on the semiconductor substrate.

[0031] A further improvement is that the underlying structure further comprises:

[0032] A floating gate dielectric layer and a polysilicon floating gate are formed on the surface of the semiconductor substrate.

[0033] A further improvement is that the polysilicon control gate is superimposed on the top of the polysilicon floating gate, and the control gate dielectric layer is located between the polysilicon control gate and the polysilicon floating gate;

[0034] Alternatively, the polysilicon control gate is formed on a side of the polysilicon floating gate in a self-aligned manner.

[0035] A further improvement is that the thickness of the first polysilicon layer is less than

[0036] A further improvement is that the hard mask layer is an oxide layer or a nitride layer.

[0037] A further improvement is that the semiconductor substrate comprises a silicon substrate.

[0038] A further improvement is that the material of the floating gate dielectric layer includes an oxide layer.

[0039] A further improvement is that the material of the control gate dielectric layer includes an oxide layer.

[0040] In view of the technical problem in the prior art that the etching of the polysilicon body easily causes the side of the polysilicon control gate to be concave, the present invention increases the formation of polymers in the polysilicon opening etching and forms a first side wall through the accumulation of polymers, and utilizes the characteristic that the etching of the polysilicon body can adapt to the morphology of the first side wall. The influence of the morphology of the first side wall on the etching of the polysilicon body is used to offset the adverse effect of the polysilicon body etching process on the concave side of the polysilicon gate. Finally, the polysilicon control gate can have vertical sides and thus reduce or eliminate the top sharp angle of the side of the polysilicon control gate, that is, the top sharp angle of the side of the polysilicon control gate can be controlled, thereby improving the performance of products using polysilicon control gates, such as flash memories. BRIEF DESCRIPTION OF THE DRAWINGS

[0041] The present invention is further described in detail below with reference to the accompanying drawings and specific embodiments:

[0042] Figure 1 It is a schematic diagram of a device structure formed by an existing polysilicon control gate etching method;

[0043] Figure 2 is a flow chart of a polysilicon control gate etching method according to an embodiment of the present invention;

[0044] Figure 3A-3C It is a schematic diagram of the device structure in each step of the polysilicon control gate etching method according to an embodiment of the present invention. DETAILED DESCRIPTION

[0045] like Figure 2 As shown in FIG. 1 , it is a flow chart of a polysilicon control gate etching method according to an embodiment of the present invention; FIG. 3A to FIG. 3B , which is a schematic diagram of the device structure in each step of the polysilicon control gate etching method according to an embodiment of the present invention; the polysilicon control gate etching method according to an embodiment of the present invention includes:

[0046] Step 1: Figure 3A As shown, an underlying structure 201 is provided, a first polysilicon layer 202 is formed on the underlying structure 201 , and a hard mask layer 203 is formed on the surface of the first polysilicon layer 202 .

[0047] The hard mask layer 203 is patterned and etched to open the polysilicon opening area. In the patterned etching, a photoresist 301 pattern formed by a photolithography process is required to define the polysilicon opening area, and then the hard mask layer 203 is etched using the photoresist 301 as a mask. After the patterned etching of the hard mask layer 203 is completed, the photoresist 301 will be removed.

[0048] In the embodiment of the present invention, the underlying structure 201 includes:

[0049] Semiconductor substrate;

[0050] A control gate dielectric layer is formed on the semiconductor substrate.

[0051] The polysilicon control gate is applied to flash memory, and the bottom layer structure 201 further includes:

[0052] A floating gate dielectric layer and a polysilicon floating gate are formed on the surface of the semiconductor substrate.

[0053] In some embodiments, the polysilicon control gate is stacked on top of the polysilicon floating gate, and the control gate dielectric layer is located between the polysilicon control gate and the polysilicon floating gate.

[0054] In some embodiments, the polysilicon control gate may be formed on a side of the polysilicon floating gate in a self-aligned manner.

[0055] In some embodiments, the thickness of the first polysilicon layer 202 is less than

[0056] The hard mask layer 203 is an oxide layer or a nitride layer.

[0057] The hard mask layer is an oxide layer or a nitride layer.

[0058] The semiconductor substrate includes a silicon substrate.

[0059] The material of the floating gate dielectric layer includes an oxide layer.

[0060] The material of the control gate dielectric layer includes an oxide layer.

[0061] Step 2: Figure 3B As shown, the hard mask layer 203 is used for polysilicon opening etching, and the polysilicon opening etching removes part of the thickness of the top of the first polysilicon layer 202 in the polysilicon opening area to form a first opening. A polymer will be formed in the polysilicon opening etching, and by increasing the polymer formed in the polysilicon opening etching, a first side wall 204 formed by the accumulation of the polymer is formed on the side of the first opening after the polysilicon opening etching is completed.

[0062] Step 3: Figure 3C As shown, polysilicon body etching is performed, and the polysilicon body etching etches the first polysilicon layer 202 at the bottom of the first opening to form the side of the polysilicon control gate, and the side of the polysilicon control gate surrounds the second opening. The polysilicon body etching will etch according to the morphology of the first sidewall 204, thereby changing the initial etching direction of the polysilicon body etching and offsetting the effect of the polysilicon body etching process on the side concave of the polysilicon gate, so that the polysilicon control gate has a vertical side and thus reduces or eliminates the side top sharp corner of the polysilicon control gate. That is, the first sidewall 204 will reduce the first opening, and the second opening is actually expanded on the opening surrounded by the first sidewall 204, so the size of the second opening after expansion can become the same as the size of the first opening under optimal conditions. In the existing method, the second opening is directly enlarged on the basis of the first opening, which will inevitably cause the defect of the side of the polysilicon control gate being concave. Therefore, the embodiment of the present invention can well solve the defect of the side of the polysilicon control gate being concave.

[0063] In some embodiments, it also includes:

[0064] Step 4: performing over-etching, wherein the over-etching causes the bottom structure 201 to lose a portion of its thickness.

[0065] In view of the technical problem in the prior art that etching of the polysilicon body easily causes the side of the polysilicon control gate to be concave, the embodiment of the present invention increases the formation of polymer in the polysilicon opening etching and forms the first side wall 204 through the accumulation of polymer. The characteristic that the etching of the polysilicon body can adapt to the morphology of the first side wall 204 is utilized. The adverse effect of the polysilicon body etching process on the concave side of the polysilicon gate is offset by the influence of the morphology of the first side wall 204 on the etching of the polysilicon body. Finally, the polysilicon control gate can have a vertical side and thus reduce or eliminate the sharp corner of the top side of the polysilicon control gate, that is, the sharp corner of the top side of the polysilicon control gate can be controlled, thereby improving the performance of products using polysilicon control gates, such as flash memories.

[0066] The present invention has been described in detail above through specific embodiments, but these do not constitute limitations of the present invention. Without departing from the principle of the present invention, those skilled in the art may also make many variations and improvements, which should also be considered as the protection scope of the present invention.

Claims

1. A polysilicon control gate etching method, characterized in that: include: Step 1: providing an underlying structure, forming a first polysilicon layer on the underlying structure, forming a hard mask layer on the surface of the first polysilicon layer, and patterning and etching the hard mask layer to open a polysilicon opening area; Step 2: performing polysilicon opening etching using the hard mask layer, wherein the polysilicon opening etching removes a portion of the thickness of the top of the first polysilicon layer in the polysilicon opening area and forms a first opening, polymers are formed during the polysilicon opening etching, and a first sidewall formed by the accumulation of the polymers is formed on the side of the first opening after the polysilicon opening etching is completed by increasing the polymers formed during the polysilicon opening etching; Step three, perform polysilicon body etching, wherein the polysilicon body etching etches the first polysilicon layer at the bottom of the first opening to form the side of the polysilicon control gate, and the side of the polysilicon control gate surrounds the second opening. The polysilicon body etching will adaptively etch according to the morphology of the first side wall, thereby changing the initial etching direction of the polysilicon body etching and offsetting the effect of the polysilicon body etching process on the side concave of the polysilicon control gate, so that the polysilicon control gate has a vertical side and thereby reduces or eliminates the sharp corner of the top side of the polysilicon control gate.

2. The polysilicon control gate etching method according to claim 1, characterized in that: Also includes: Step 4: performing over-etching, wherein the over-etching causes the bottom structure to lose a portion of thickness.

3. The polysilicon control gate etching method according to claim 2, characterized in that: The underlying structure includes: Semiconductor substrate; A control gate dielectric layer is formed on the semiconductor substrate.

4. The polysilicon control gate etching method according to claim 3, characterized in that: The underlying structure also includes: A floating gate dielectric layer and a polysilicon floating gate are formed on the surface of the semiconductor substrate.

5. The polysilicon control gate etching method according to claim 4, characterized in that: The polysilicon control gate is stacked on top of the polysilicon floating gate, and the control gate dielectric layer is located between the polysilicon control gate and the polysilicon floating gate; Alternatively, the polysilicon control gate is formed on a side of the polysilicon floating gate in a self-aligned manner.

6. The polysilicon control gate etching method according to claim 1, characterized in that: The thickness of the first polysilicon layer is less than 7. The polysilicon control gate etching method according to claim 1, characterized in that: The hard mask layer is an oxide layer or a nitride layer.

8. The polysilicon control gate etching method according to claim 4, characterized in that: The semiconductor substrate includes a silicon substrate.

9. The polysilicon control gate etching method according to claim 8, characterized in that: The material of the floating gate dielectric layer includes an oxide layer.

10. The polysilicon control gate etching method according to claim 8, characterized in that: The material of the control gate dielectric layer includes an oxide layer.

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