Non-planar silicided semiconductor electrical fuses

Abstract

The present invention relates to non-planar silicided semiconductor electrical fuses. An electrical fuse includes a fuse link including a silicided semiconductor layer located above a dielectric layer covering a gate conductor. The silicided semiconductor layer is non-planar and extends orthogonally above the gate conductor. A first terminal is electrically coupled to a first end of the fuse link and a second terminal is electrically coupled to a second end of the fuse link. The fuse link can be formed in the same layer as an intrinsic base and / or extrinsic base of a bipolar transistor. The gate conductor can control a current source to program the electrical fuse. The electrical fuse reduces footprint area and required programming energy compared to conventional electrical fuses.

Description

TECHNICAL FIELD

[0001] The present disclosure relates to integrated circuits, and more particularly to non-planar silicided semiconductor electrical fuses. BACKGROUND

[0002] Different portions of an integrated circuit (IC) can be coupled using electrical fuses (e-fuses). Electrical fuses can be“programmed” to change interconnections within the IC. More specifically, by applying a prescribed current controlled by a transistor, metal migration within a fuse link can be caused. Once there is sufficient metal migration, the fuse link is broken or blown, thereby preventing current from passing through the fuse. One challenge with electrical fuses is that the fuses take up a large footprint in the IC due to the size of the fuse and the associated current source needed to program it. Electrical fuses also include planar fuse links that have a large footprint. Typically, the size of the electrical fuse is limited by the size of the gate conductor within a particular technology node. Thus, one approach to reducing the size of the electrical fuse includes reducing the fuse link size to the minimum gate conductor length allowed by the technology node. SUMMARY

[0003] One aspect of the present disclosure includes an electrical fuse comprising: a fuse link comprising a silicided semiconductor layer positioned above a dielectric layer covering a gate conductor, wherein the silicided semiconductor layer is non-planar; a first terminal electrically coupled to a first end of the fuse link; and a second terminal electrically coupled to a second end of the fuse link.

[0004] One aspect of the present disclosure relates to an integrated circuit (IC) comprising: a bipolar transistor comprising an inner base and an outer base; a complementary metal-oxide-semiconductor (CMOS) transistor; and an electrical fuse comprising: a non-planar fuse link comprising a silicided semiconductor layer positioned above a dielectric layer covering a gate conductor, wherein the silicided semiconductor layer extends orthogonally above the gate conductor; a first terminal electrically coupled to a first end of the non-planar fuse link; and a second terminal electrically coupled to a second end of the non-planar fuse link, wherein the silicided semiconductor layer is a same layer as at least one of the inner base and the outer base of the bipolar transistor.

[0005] Another aspect of the present disclosure is directed to a method comprising: forming a semiconductor layer over a dielectric layer over at least one of an inner base and an outer base of a bipolar transistor and over a gate conductor; patterning the semiconductor layer to extend orthogonally over the gate conductor; forming a fuse chain of an electrical fuse by silicidizing the semiconductor layer over the dielectric layer over the gate conductor, wherein the silicided semiconductor layer is non-planar over the gate conductor; and forming the electrical fuse by forming a first terminal electrically coupled to a first end of the fuse chain and a second terminal electrically coupled to a second end of the fuse chain.

[0006] The above-described and other features of the present disclosure will become more apparent from the following more particular description of embodiments of the present disclosure. BRIEF DESCRIPTION OF DRAWINGS

[0007] Embodiments of the present disclosure will be described in detail with reference to the following drawings, wherein like reference numerals indicate like elements, and wherein:

[0008] Figures 1-2 A cross-sectional view of an electrical fuse formed in accordance with embodiments of the present disclosure is shown.

[0009] Figure 3 An enlarged cross-sectional view of an electrical fuse having a non-planar fuse chain of silicided semiconductor in accordance with embodiments of the present disclosure is shown.

[0010] Figure 4 A plan view of the electrical fuse of Figure 3 is shown.

[0011] Figure 5 A cross-sectional view of an electrical fuse having a non-planar fuse chain of silicided semiconductor in accordance with other embodiments of the present disclosure is shown.

[0012] Figure 6 A plan view of the electrical fuse of Figure 5 is shown.

[0013] Figure 7 A cross-sectional view of an electrical fuse having a non-planar fuse chain of silicided semiconductor in accordance with yet other embodiments of the present disclosure is shown.

[0014] Figure 8 A plan view of the electrical fuse of Figure 7 is shown.

[0015] Figure 9 A plan view of an electrical fuse having a non-planar fuse chain with a turn in accordance with embodiments of the present disclosure is shown.

[0016] Figure 10A plan view of an electrical fuse with a non-planar fuse link with a turn is shown in accordance with further embodiments of the present disclosure.

[0017] Figure 11 A plan view of an electrical fuse with a non-planar fuse link with a turn is shown in accordance with further embodiments of the present disclosure.

[0018] Figure 12 A plan view of an electrical fuse with a non-planar fuse link is shown in accordance with embodiments of the present disclosure.

[0019] Figure 13 A plan view of an electrical fuse with a non-planar fuse link and control transistor is shown in accordance with embodiments of the present disclosure.

[0020] Figure 14 A plan view of an electrical fuse with a non-planar fuse link and control transistor is shown in accordance with further embodiments of the present disclosure.

[0021] Figure 15 A cross-sectional view of an integrated circuit including an electrical fuse with a non-planar fuse link having a silicided semiconductor is shown in accordance with embodiments of the present disclosure.

[0022] It should be noted that the drawings of the present disclosure are not necessarily drawn to scale. The drawings are intended to depict only typical aspects of the disclosure, and therefore should not be considered as limiting the scope of the disclosure. In the drawings, like numbering represents similar elements between the different figures. DETAILED DESCRIPTION

[0023] In the following description, reference is made to the accompanying drawings which form a part hereof, and in which are shown by way of illustration specific exemplary embodiments in which the teachings can be practiced. These embodiments are described in sufficient detail to enable those skilled in the art to practice the teachings, and it is to be understood that other embodiments can be utilized and that changes can be made without departing from the scope of the present teachings. The following description is, therefore, not to be taken in a limiting sense.

[0024] It will be understood that when an element such as a layer, region or substrate is referred to as being "on" or "over" another element, it can be directly on the other element or intervening elements can also be present. In contrast, when an element is referred to as being "directly on" or "directly over" another element, there are no intervening elements present. It will also be understood that when an element is referred to as being "connected" or "coupled" to another element, it can be directly connected or coupled to the other element or intervening elements can be present. In contrast, when an element is referred to as being "directly connected" or "directly coupled" to another element, there are no intervening elements present.

[0025] References in the specification to “one embodiment” or “an embodiment” of the disclosure, or to “the” embodiment, and other variations thereof, mean that a particular feature, structure, characteristic, and so forth being described is included in at least one embodiment of the disclosure. Therefore, the phrase “in one embodiment” or “in an embodiment,” as well as any other variations thereof, are not necessarily referring to the same embodiment. It is appreciated that, for example, in the case of “A / B,” “A and / or B,” and “at least one of A and B,” any of these alternatives can be used with respect to each other. As another example, in the case of “A, B, and / or C” and “at least one of A, B, and C,” these phrases are intended to cover any of the following alternatives: only A, only B, only C, only A and B, only A and C, only B and C, or A and B and C. As will be apparent to those of ordinary skill in the art, this list of alternatives can be expanded to the inclusion of any number of items.

[0026] Embodiments of the present disclosure provide an electrical fuse including a fuse chain including a silicided semiconductor layer positioned above a dielectric layer covering a gate conductor. Thus, the fuse chain is electrically isolated from the gate conductor below it. The silicided semiconductor layer is non-planar and extends orthogonally above the gate conductor. In comparison to a conventional planar electrical fuse, the non-planar fuse chain provides a greater length in a smaller footprint. Further, the length of the fuse chain can be customized based on, for example, the height of the gate conductor and the dielectric layer, the number of gate conductors it passes through, and the number of times it passes through one or more gate conductors. A first terminal is electrically coupled to a first end of the fuse chain and a second terminal is electrically coupled to a second end of the fuse chain. The semiconductor fuse chain can be conveniently formed in the same layer as an intrinsic base and / or extrinsic base of a bipolar transistor during bipolar complementary metal-oxide-semiconductor (BiCMOS) fabrication, thus not requiring additional processing steps to construct. The gate conductor can be part of a transistor that controls a current source used to program the electrical fuse, further reducing the footprint in comparison to a conventional electrical fuse by placing the control transistor at least partially below the fuse chain. The electrical fuse also requires less programming energy in comparison to a conventional electrical fuse.

[0027] Figure 1 and Figure 2An enlarged cross-sectional view showing a method of forming some portions of an IC 102 including an electrical fuse 100 according to an embodiment of the present disclosure is shown. As shown, in one embodiment, the IC 102 includes a bipolar transistor region 110 and a complementary metal-oxide semiconductor (CMOS) transistor region 112. The electrical fuse 100 will be constructed in the CMOS transistor region 112, but can be constructed at the same time as some portions of the bipolar transistor region 110. Alternatively, in the case where the IC 102 does not include a bipolar transistor region 110, the electrical fuse 100 can be constructed only within the CMOS transistor region 112. The substrate 114 on which these regions are constructed can include any now known or later developed semiconductor substrate, such as a bulk substrate or a semiconductor-on-insulator (SOI) substrate.

[0028] At this stage, the bipolar transistor region 110 includes n-type or p-type implant regions 115 to form various portions of a bipolar transistor, such as a collector in this example. As such structures and methods of their formation are well known in the art, no further description is required. The CMOS transistor region 112 can include source / drain regions 118 formed in the substrate 114 in any known manner, such as implanting any appropriate dopant. In one example, a source region 118S for a gate conductor 116 has a drain region 118D separated therefrom by a corresponding channel region (not numbered for clarity, located below the gate conductor 116). Any necessary trench isolation 119 can also be provided and can be formed in any now known or later developed manner, such as etching holes in the substrate 114 prior to forming the gate conductor 116, and filling the holes with a dielectric such as an oxide.

[0029] Etching generally refers to the removal of material from a substrate (or a structure formed on a substrate), and is typically performed using a mask at appropriate locations to selectively remove material from specific areas of the substrate while leaving material in other areas unaffected. There are generally two types of etching: (i) wet etching and (ii) dry etching. Wet etching is performed using a solvent (e.g., acid), allowing the solvent to selectively dissolve a given material (e.g., oxide) while leaving another material (e.g., polycrystalline silicon) relatively intact. This ability to selectively etch a given material is fundamental to many semiconductor manufacturing processes. Wet etching typically isotropically etches homogeneous materials (e.g., oxides), but it can also anisotropically etch single-crystal materials (e.g., silicon wafers). Dry etching can be performed using plasma. Plasma systems can operate in several modes by adjusting plasma parameters. Conventional plasma etching generates neutrally charged high-energy free radicals that react on the wafer surface. Because neutral particles attack the wafer from all angles, the process is isotropic. Ion milling or sputter etching uses high-energy ions of rare gases to bombard the wafer. These high-energy ions approach the wafer from roughly one direction, making the process highly anisotropic. Reactive ion etching (RIE) operates under conditions between sputtering and plasma etching and can be used to create deep, narrow features, such as isolation trenches.

[0030] The CMOS transistor region 112 includes a plurality of gate conductors 116 formed thereon. Figures 1-4 The example shown illustrates two gate conductors 116. As will be described herein, more or fewer gate conductors 116 are also possible. Figures 1-2 In the example shown, gate conductor 116 is located in the active region of CMOS transistor region 112 and thus serves as an active gate. In this case, in a non-limiting example, gate conductor 116 may comprise polysilicon. In another example, gate conductor 116 may comprise a metal gate. Although shown as a single material for clarity, the metal gate may comprise one or more conductive components to provide a gate terminal for the transistor. For example, the metal gate may comprise a high-k dielectric (high-k) layer, a work function metal layer, and a conductor layer (not all shown for clarity). The high-k layer may comprise any high-k material now known or developed hereafter that is commonly used for metal gates, such as, but not limited to, metal oxides such as tantalum oxide (Ta2O5), barium titanium oxide (BaTiO3), hafnium oxide (HfO2), zirconium oxide (ZrO2), aluminum oxide (Al2O3), or hafnium silicate (HfO2). A1 Si A2 O A3 ) or hafnium oxynitride silicate (Hf A1 Si A2 OA3 N A4 ) such as metal silicates, where Al, A2, A3, and A4 represent relative proportions, each greater than or equal to zero and Al + A2 + A3 + A4 = 1 is the total relative molar amount. Depending on whether an NFET device or a PFET device is used, the work function metal layer can include various metals, but can include, for example: aluminum (Al), zinc (Zn), indium (In), copper (Cu), indium copper (InCu), tin (Sn), tantalum (Ta), tantalum nitride (TaN), tantalum carbide (TaC), titanium (Ti), titanium nitride (TiN), titanium carbide (TiC), TiAlC, TiAl, tungsten (W), tungsten nitride (WN), tungsten carbide (WC), polysilicon (poly-Si), and / or combinations thereof. The conductor layer can include any now known or later developed gate conductor, such as copper (Cu). A gate cap (not shown), for example of nitride, can also be formed over the gate region. The gate conductor 116 can also include spacers (not shown) around it, for example of silicon nitride. The gate conductor 116 can be formed over the substrate 114 using any now known or later developed IC fabrication techniques (e.g., material deposition, photolithographic patterning using masks, and etching, etc.). In other embodiments, as will be described, the gate conductor 116 can not be an active gate, and can include materials other than those listed above.

[0031] Figure 1 Also shown is the formation of a semiconductor layer 122 over the gate conductor 116, for the CMOS transistor region 112, and for at least one of the intrinsic and extrinsic base regions of the bipolar transistor region 110 (within dashed box 124), if present. Figure 1A dielectric layer 120 is also shown formed over the gate conductor 116. The semiconductor layer 122 and the dielectric layer 120 can be formed by any appropriate deposition technique. "Deposition" can include any now known or later developed technique for depositing a material suitable for the material to be deposited, including but not limited to, for example: chemical vapor deposition (CVD), low pressure CVD (LPCVD), plasma-enhanced CVD (PECVD), sub-atmospheric CVD (SACVD), and high density plasma CVD (HDPCVD), rapid thermal CVD (RTCVD), ultra-high vacuum CVD (UHVCVD), limited reactant processing CVD (LRPCVD), metalorganic CVD (MOCVD), sputtering deposition, ion beam deposition, e-beam deposition, laser assisted deposition, thermal oxidation, thermal nitridation, spin-on, physical vapor deposition (PVD), atomic layer deposition (ALD), chemical oxidation, molecular beam epitaxy (MBE), plating, evaporation. The semiconductor layer 122 and the dielectric layer 120 can be formed, for example, by ALD. A mask can be used to block deposition of the dielectric layer 120 over the bipolar transistor region 110, or the dielectric layer 120 can be etched away from the region 110. It will be recognized that the processing illustrated for the CMOS transistor region 112 example can be performed without the processing illustrated for the bipolar transistor region 110, i.e., in the absence of bipolar transistors in the IC 102.

[0032] The semiconductor layer 122 can include, for example, silicon (Si) or silicon germanium (SiGe). As described above, the semiconductor layer 122 can be the same layer as used to form the intrinsic base and / or extrinsic base (within the dashed box 124) of the bipolar transistor region 110. In this case, the semiconductor layer 122 can include a doping concentration greater than 5E18 atoms / cm 3 The dopant can be any appropriate element having the polarity type of the base of the bipolar transistor 158 Figure 2 to be formed in the region 110; common donors in silicon (Si): phosphorous (P), arsenic (As), antimony (Sb), common donors in gallium arsenide (GaAs): sulfur (S), selenium (Se), tin (Sn), silicon (Si), and carbon (C). P-type dopants are elements introduced to a semiconductor to create free holes (by "accepting" an electron from a semiconductor atom and simultaneously "releasing" a hole); acceptor atoms must have one less valence electron than the host semiconductor. P-type dopants can include, but are not limited to: boron (B), indium (In), and gallium (Ga).

[0033] The dielectric layer 120 can include any suitable dielectric material, including but not limited to: carbon-doped silicon dioxide material; fluorinated silicate glass (FSG); organic polymer thermoset material; silicon oxycarbide; SiCOH dielectric; fluorine-doped silicon oxide; spin-on glass; silsesquioxane, including hydrogen silsesquioxane (HSQ), methyl silsesquioxane (MSQ), and mixtures or copolymers of HSQ and MSQ; benzocyclobutene (BCB)-based polymer dielectric, and any silicon-containing low-k dielectric. Examples of spin-on low-k films with SiCOH-type composition using silsesquioxane chemistry include HOSP™ (available from Honeywell), JSR 5109 and 5108 (available from Japan Synthetic Rubber), Zirkon™ (available from Shipley Microelectricals' Rohm and Haas division), and porous low-k (ELk) material (available from Applied Materials). Examples of carbon-doped silicon dioxide material or organosilane include Black Diamond™ (available from Applied Materials) and Coral™ (available from Lam Research). An example of HSQ material is FOx™ (available from Dow Corning). Here, for example, the dielectric layer 120 can include high temperature oxide (HTO). It should be noted that the gate conductor 116 is covered by the dielectric layer 120, regardless of form, and is thus generally electrically isolated from structures above it.

[0034] Figure 2 An embodiment is shown in which the semiconductor layer 122 is patterned to extend orthogonally above the gate conductor 116, see also Figure 4 The plan view. This step is shown after a number of intermediate steps for forming the emitter 128 in the bipolar transistor region 110. These intermediate steps can include any now known or later developed technique, and thus will not be described in further detail. As shown, a mask 130 can be formed and patterned to allow the semiconductor layer 122 to be patterned. In the case where a bipolar transistor region 110 is provided, the mask 130 can also be used to pattern some portions of the intrinsic base and / or extrinsic base (within the dashed box 124). Any suitable masking and etching process can be used to pattern the semiconductor layer 122, such as a silicon nitride hard mask and etch. Figure 4 An embodiment is shown of a fuse chain 140 including a semiconductor layer (after silicidation) extending orthogonally above the gate conductor 116. Here, for example, RIE can be used to pattern the semiconductor layer.

[0035] Figure 3A cross-sectional view showing formation of a fuse chain 140 for the electrical fuse 100 by a silicidation semiconductor layer 122 over a dielectric layer 120 over the gate conductor 116 is shown. Figure 4 A schematic plan view of the electrical fuse 100 is shown, where view line 3-3 indicates Figure 3 A cross-sectional view is provided. For clarity, Figure 3 and Figure 4 The bipolar transistor region 110 Figures 1-2 ) is omitted. A silicidation process forms a silicidation semiconductor layer 142 that includes the semiconductor layer 122 composed of silicon (Si) or silicon germanium (SiGe) with a silicide layer 144 on the semiconductor layer 122. Thus, the fuse chain 140 includes the silicidation semiconductor layer 142 having the semiconductor layer 122 and the silicide layer 144. The silicide layer 144 can be formed using any now known or later developed technique, such as performing an in-situ pre-clean, depositing a metal such as titanium, nickel, cobalt, etc., performing an anneal to cause the metal to react with the semiconductor layer 122, and then removing the unreacted metal. While shown as along the entire length of the fuse chain 140, the silicide layer 144 can be along only a portion of the fuse chain 140. Figure 3 It is also shown that the silicidation semiconductor layer 142 (fuse chain 140) is non-planar over the gate conductor 116. That is, because the layer extends over the gate conductor 116, it includes peaks and valleys.

[0036] Figure 3 and Figure 4 It is also shown that the (final) electrical fuse 100 is formed by forming a first terminal 150 electrically coupled to the first end 152 of the fuse chain 140 and a second terminal 154 electrically coupled to the second end 156 of the fuse chain 140. The terminals 150, 154 are on opposite sides of the gate conductor 116. The terminals 150, 154 can be formed using any now known or later developed electrical interconnect formation process. In one non-limiting example, an interlayer dielectric (ILD) 148 Figure 3 ) can be deposited (e.g., using ALD deposition). The ILD 148 can include any of the dielectric materials previously listed herein for the dielectric layer 120. The terminals 150, 154 can be formed by patterning a mask and etching (e.g., using RIE etching) to the terminal openings of the respective ends 152, 156 of the fuse chain 140. As Figure 4As shown, the ends 152, 156 can be patterned during the patterning of the semiconductor layer 122 described herein so as to be enlarged compared to the rest of the fuse chain 140 to provide a landing area for the terminals 150, 154. A conductor can then be formed in the terminal openings. The conductor can include a refractory metal liner (not labeled for clarity) and a terminal metal. The refractory metal liner can include, for example, ruthenium (Ru), tantalum (Ta), titanium (Ti), tungsten (W), iridium (Ir), rhodium (Rh), and platinum (Pt), among others, or mixtures thereof. The terminal metal can include any now known or later developed conductor such as, but not limited to, copper (Cu) or tungsten (W).

[0037] The electrical fuse 100 includes a fuse chain 140 including a silicided semiconductor layer 142 located above a dielectric layer 120 covering a gate conductor 116. The electrical fuse 100 also includes a first terminal 150 electrically coupled to a first end 152 of the fuse chain 140 and a second terminal 154 electrically coupled to a second end 156 of the fuse chain 140. As described above, the silicided semiconductor layer 142 can be in the same layer as at least one of an inner base and an outer base (dashed boxes 124 Figure 2 ) of a bipolar transistor 158. Figure 2 The gate conductor 116 is covered by the dielectric layer 120 and there is no silicide below the dielectric layer 120 below the silicided semiconductor layer 122.

[0038] The fuse chain 140 is configured, i.e., shaped and / or dimensioned, to allow the metal or metal alloy to migrate when an appropriate current is applied through the terminals 150, 154 to break the fuse chain 140, i.e., control programming energy to break or blow the fuse. For example, the fuse chain 140 can be formed to have any desired length W L ( Figure 4 ), for example, during the patterning of the semiconductor layer 122 Figure 2 ).

[0039] The length of the fuse chain 140 can also be controlled during fabrication in a number of ways to produce an electrical fuse 100 with a desired programming energy. Since the silicided semiconductor layer 142 of the fuse chain 140 extends orthogonally above the gate conductor 116, the silicided semiconductor layer 142 and the fuse chain 140 are non-planar and its length can be controlled by controlling the length and / or height of the gate conductor 116 and / or the dielectric layer 120. For example, the height of the gate conductor 116 and the thickness of the dielectric layer 120 can be controlled to tailor the length of the fuse chain 140 above it by a desired amount. Alternatively, the length L g ( Figure 3 ) of the gate conductor 116 can be controlled to change the length of the fuse chain 140.

[0040] The number of gate conductors 116 can also be selected to tailor the length of the fuse chain 140. In Figure 3 and Figure 4 two gate conductors 116 are illustrated. However, any number of gate conductors 116 can be provided. Thus, the fuse chain 140 can include a silicided semiconductor layer 142 over the dielectric layer 120 covering a plurality of gate conductors 116, such that the non-planar fuse chain includes any number of peaks and valleys. One gate conductor 116 or more than two gate conductors 116 can be used. Figure 5 and Figure 6 respectively illustrate a cross-sectional view and a schematic plan view of an electrical fuse 100 having one gate conductor 116 (wherein the view line 5-5 indicates the cross-sectional view line of Figure 5 Here, for example, the length Lg and / or height of the gate conductor 116 and the dielectric layer 120 can be fabricated to control the length of the fuse chain 140. Figure 7 and Figure 8 respectively illustrate a cross-sectional view and a schematic plan view of an electrical fuse 100 having more than two gate conductors 116 (wherein the view line 7-7 indicates the cross-sectional view line of Figure 7 Again, the length Lg and / or height of each gate conductor 116 and / or the dielectric layer 120 can be selected to control the length of the fuse chain 140. Any number of multiple peaks and valleys in the fuse chain 140 can be formed in this manner.

[0041] As shown in Figures 9-11 the length of the fuse chain 140 can also be controlled by providing a fuse chain 140 having at least one lateral turn 160 therein. In this manner, the length of the fuse chain 140 can be selected by the number of times the fuse chain 140 traverses over the gate conductor 116, as well as the additional length provided by the turn 160. Here, the fuse chain 140 typically extends orthogonally over the gate conductor 116 more than once, but can be somewhat non-orthogonal. For example, Figure 9 illustrates a plan view of a fuse chain 140 extending orthogonally over the gate conductor 116 twice, for example having one or two turns 160 therein. Figure 10 and Figure 11 illustrate plan views of two other alternative embodiments including various turns 160 therein. Figure 10 illustrates an electrical fuse 100 including a non-planar fuse chain 140 having a lateral sinusoidal structure, Figure 11 illustrates an electrical fuse 100 including a non-planar fuse chain 140 having a curved central portion. The turns 160 can be any desired number, and / or can take any conceivable shape, to obtain a desired programming energy. As Figure 10 and 11As shown, in certain embodiments, the fuse link 140 can extend over the gate conductor 116 at a non-orthogonal angle. The turn 160 allows the area of the fuse link 140 to be minimized.

[0042] Referring to Figure 7 , Figure 8 and Figure 12 , plan views of alternative embodiments are shown. In certain embodiments, the gate conductors 116 can not function as part of an active device. For example, as shown in Figure 7 , Figure 8 and Figure 12 , the gate conductors 116 can be inactive, meaning that they do not have any source / drain regions and no active device is connected to them. In this case, the gate conductors 116 can include any dummy gate material, such as amorphous silicon or any other suitable dummy gate material, in addition to the materials listed previously herein. In other embodiments, the gate conductors 116 can be resistors 162 (see, for example, Figure 12 ). In this case, the gate conductors 116 can be used to heat the electrical fuse 100 to control the programming energy. When connected to a power source, the gate conductors 116 will generate heat according to the resistance value, which can reduce the programming energy required by the fuse.

[0043] Referring to Figures 13-14 , a schematic plan view of other embodiments of the electrical fuse 100 is shown. The position of the fuse link 140 relative to the gate conductors 116 can also vary to control the programming energy. For example, the position of the fuse link 140 over the gate conductors 116 can be selected to achieve the lowest programming energy. The selected position can not be the center of the gate conductors 116. For example, in Figure 13 , the fuse link 140 is adjacent to an active transistor 168A and not centered over the gate conductors 116. In Figure 4 , Figure 9 and Figure 14 , the fuse link 140 is positioned between active transistors 168B, 168C sharing the gate conductors 116 and is generally centered along the gate conductors 116. In another embodiment, without limitation, the fuse link 140 can be positioned anywhere along the length of the gate conductors 116, for example as shown in Figure 8 .

[0044] Referring to Figures 13-14In certain embodiments, the gate conductor 116 can be part of a control transistor 170 configured to electrically couple a current source 172 to the first terminal 150 to program the electrical fuse 100 with the second terminal 154 electrically coupled to ground. In one embodiment, the gate conductor 116 can be part of a CMOS control transistor 170, and the CMOS transistor can be configured to electrically couple the current source 172 to the non-planar fuse chain 140 to program the electrical fuse 100. In Figures 13-14 In the example shown, the drain region 118D of the control transistor 170 is coupled to the first (cathode) terminal 150 of the electrical fuse 100 via any form of IC interconnect 180, while the second terminal 154 is coupled to the current source 172. The source region 118S of the control transistor 170 is coupled to ground. In this way, when the control transistor 170 is activated, current flows from the current source 172 through the electrical fuse 100 to ground, causing programming of the electrical fuse 100, i.e., breaking the fuse chain 140. The bipolar transistor 158 Figure 2 ) can be similarly arranged as the control transistor 170. In other embodiments, instead of a CMOS transistor in the CMOS region 112, a bipolar transistor 158 Figure 2 ) can be used as a programming source for the electrical fuse 100.

[0045] Figure 15 A cross-sectional view of the IC 102 including the bipolar transistor region 110 and the CMOS transistor region 112 is shown. Here, the IC 102 includes the CMOS transistor 168 and the bipolar transistor 158 with an intrinsic base and / or extrinsic base (dashed box 124). The IC 102 also includes the electrical fuse 100 including the non-planar fuse chain 140 including the silicided semiconductor layer 142 above the dielectric layer 120 covering the gate conductor 116. For example, as shown in Figure 4 、 Figure 6 、 Figure 8 、 Figure 9 and Figures 12-14 The silicided semiconductor layer 142 extends orthogonally above the gate conductor 116. The electrical fuse 100 also includes a first terminal 150 electrically coupled to a first end 152 of the non-planar fuse chain 140, and a second terminal 154 electrically coupled to a second end 156 of the non-planar fuse chain 140. The silicided semiconductor layer 142 is the same layer as at least one of the intrinsic base and extrinsic base (dashed box 124) of the bipolar transistor 158. In this case, the silicided semiconductor layer 142 can include a dopant with a doping concentration that can be greater than 5E18 atoms / cm 3 to accommodate the base of the bipolar transistor 158. The silicided semiconductor layer 142 can include, for example, silicon (Si) or silicon germanium (SiGe). In certain embodiments, for exampleFigures 13-14 The gate conductor 116 is part of a CMOS control transistor 170 configured to electrically couple a current source 172 to the non-planar fuse chain 140 to program the electrical fuse 100. In other embodiments, for example Figure 12 The gate conductor is a resistor 162 that is capable of heating the fuse chain 140 to control the programming energy. In other embodiments, the non-planar fuse chain 140 can include at least one turn 160 as shown in Figures 9-11 The non-planar fuse chain 140 can extend orthogonally over the gate conductor 116 more than once as shown in Figure 9 The non-planar fuse chain 140 (including the silicided semiconductor layer 122 over the dielectric layer 120) can cover multiple gate conductors 116 such that the non-planar fuse chain 140 includes multiple peaks and valleys. Any of the embodiments described herein can be mixed and matched to control the properties of the electrical fuse 100.

[0046] Embodiments of the present disclosure provide an electrical fuse that can reduce the programming energy (e.g., by 25-30%). The electrical fuse also reduces the size of the programming current source 172 compared to conventional planar electrical fuses, which will reduce the footprint of the entire circuit (e.g., by about 10-25%). As described above, the electrical fuse 100 does not require any additional masks to implement, and the minimum size is independent of the gate length. In cases where the gate conductor is used as part of a control transistor, the heat from the transistor can also cause a reduction in the electrical fuse blow current, resulting in further area reduction.

[0047] The above-described process is used in the manufacture of integrated circuit chips. The resulting integrated circuit chips can be distributed by the fabricator in raw chip form (i.e., as a single die), as a bare die packaged in a ceramic, plastic, or glass package, as a bare die mounted on a carrier, or as a part of an integrated circuit chip assembly such as a dual- in-line package, a single- in-line package, or a chip-on-board package with a substrate or board. In any case the chip is then used as a component in an electrical system, such as an electrical system incorporated into a computer system. The computer system can be a desktop computer, a laptop computer, or other type of computer. Alternately, the computer system can be a stand-alone computer system, a client on a network, or a server on a network. In any case, the integrated circuit chip forms at least a part of the system.

[0048] The terminology used herein is for the purpose of describing particular embodiments only and is not intended to be limiting of the disclosure. As used herein, the singular forms "a", "an" and "the" are intended to include the plural forms as well, unless the context clearly indicates otherwise. It will be further understood that the terms "comprises" and / or "comprising," when used in this specification, specify the presence of stated features, integers, steps, operations, elements, and / or components, but do not preclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and / or groups thereof. "Optional" or "optionally" means that the subsequently described event or circumstance can or can not occur, and that the description includes instances where the event occurs and instances where it does not.

[0049] Approximating language can be used to modify any quantitative representation that can possibly vary, depending upon the precision with which it is used and / or it's associated instrument of measurement. For instance, by using the terms "about" and "substantially” it will be understood that the value intended to be approximated will include values that are reasonably close to it, in light of the functional properties of the instrument being used to make the measurement and the error inherent in the measurement itself. Further, it will be understood that the value intended to be approximated will include values that are within + / - 10% of the value, unless otherwise indicated by context or language. Throughout the specification and claims, approximate language will be used to modify any quantitative representation that can possibly vary, depending upon the precision with which it is used and / or it's associated instrument of measurement. Therefore, values modified by one or more of the terms such as "about", "approximately”, and "substantially” are not limited to the precise value specified. In at least some instances, the approximate language can correspond to the precision of the instrument used to measure the value. In this document and throughout the specification and claims, range limitations can be combined and / or interchanged, such ranges are identified and include all the sub-ranges contained therein, unless context or language indicates otherwise. "Approximately” applied to a range of values applies to both values, and unless otherwise indicated by the precision of the instrument used to measure the value, can indicate + / - 10% of the stated value.

[0050] All means or step-plus-function elements in the claims that follow the designation of an element preceded by the phrase "means for” or "step for” are intended to encompass any structure, material, or acts for performing the functions described for that element along with other claimed elements such as in an apparatus or a method. The description of the disclosure has been presented for purposes of illustration and description, but is not intended to be exhaustive or to limit the disclosure to the precise form disclosed. Many modifications and variations will be apparent to those skilled in the art upon reading this disclosure. Embodiments were chosen and described in order to best explain the principles of the disclosure and the practical application, and to enable others skilled in the art to understand various embodiments with various modifications as are suited to the particular use contemplated.

Claims

1. An electrical fuse, comprising: a fuse link comprising a silicided semiconductor layer located above a dielectric layer covering a gate conductor, wherein the silicided semiconductor layer is non-planar; a first terminal electrically coupled to a first end of the fuse link; and a second terminal electrically coupled to a second end of the fuse link.

2. The electrical fuse of claim 1, wherein the silicided semiconductor layer comprises a dopant.

3. The electrical fuse of claim 1, wherein the silicided semiconductor layer comprises one of silicon (Si) and silicon germanium (SiGe).

4. The electrical fuse of claim 1, wherein the gate conductor is part of a transistor configured to electrically couple a current source to the first terminal to program the electrical fuse, the second terminal being electrically coupled to ground.

5. The electrical fuse of claim 1, wherein the gate conductor does not operate as part of an active device.

6. The electrical fuse of claim 1, wherein the gate conductor is a resistor.

7. The electrical fuse of claim 1, wherein the fuse link includes at least one lateral turn therein.

8. The electrical fuse of claim 7, wherein the fuse link extends orthogonally above the gate conductor more than once.

9. The electrical fuse of claim 1, wherein the silicided semiconductor layer is in the same layer as at least one of an inner base and an outer base of a bipolar transistor.

10. The electrical fuse of claim 1, wherein the fuse link comprises the silicided semiconductor layer located above the dielectric layer covering a plurality of gate conductors, such that the fuse link comprises a plurality of peaks and valleys.

11. The electrical fuse of claim 1, wherein the silicided semiconductor layer extends orthogonally above the gate conductor.

12. An integrated circuit (IC), comprising: a bipolar transistor comprising an inner base and an outer base; a complementary metal-oxide-semiconductor (CMOS) transistor; and an electrical fuse comprising: a non-planar fuse link comprising a silicided semiconductor layer located above a dielectric layer covering a gate conductor, wherein the silicided semiconductor layer extends orthogonally above the gate conductor; a first terminal electrically coupled to a first end of the non-planar fuse link; and a second terminal electrically coupled to a second end of the non-planar fuse link, wherein the silicided semiconductor layer is in the same layer as at least one of the inner base and the outer base of the bipolar transistor.

13. The IC of claim 12, wherein the silicided semiconductor layer comprises a dopant.

14. The IC of claim 12, wherein the silicided semiconductor layer comprises one of silicon (Si) and silicon germanium (SiGe).

15. The IC of claim 12, wherein the gate conductor is part of the CMOS transistor, and wherein the CMOS transistor is configured to electrically couple a current source to the non-planar fuse link to program the electrical fuse.

16. The IC of claim 12, wherein the gate conductor is a resistor. ​ 17. The IC of claim 12, wherein the non-planar fuse chain includes at least one lateral turn therein.

18. The IC of claim 17, wherein the non-planar fuse chain extends orthogonally over the gate conductor more than once.

19. The IC of claim 12, wherein the non-planar fuse chain includes the silicided semiconductor layer over the dielectric layer covering a plurality of gate conductors, such that the non-planar fuse chain includes a plurality of peaks and valleys.

20. A method of forming a semiconductor structure, comprising: forming a semiconductor layer over a dielectric layer over a gate conductor for at least one of an intrinsic base and an extrinsic base of a bipolar transistor; patterning the semiconductor layer to extend orthogonally over the gate conductor; forming a fuse chain of an electrical fuse by siliciding the semiconductor layer over the dielectric layer over the gate conductor to form a silicided semiconductor layer, wherein the silicided semiconductor layer is non-planar over the gate conductor, and wherein the silicided semiconductor layer is a same layer as the at least one of the intrinsic base and the extrinsic base of the bipolar transistor; and forming the electrical fuse by forming a first terminal electrically coupled to a first end of the fuse chain and a second terminal electrically coupled to a second end of the fuse chain.

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