Semiconductor device having a well contact diffusion region providing a well potential

Abstract

A semiconductor device having a well contact diffusion region providing a well potential. Disclosed herein is an apparatus comprising: a first diffusion region extending in a first direction; a second diffusion region arranged in the first direction; first metal lines overlapping the first diffusion region; second metal lines each overlapping an associated one of the second diffusion regions; third metal lines overlapping the first and second metal lines; first contact plugs electrically connecting the first metal lines to the first diffusion region; second contact plugs each electrically connecting an associated one of the second metal lines to an associated one of the second diffusion regions; and third contact plugs each electrically connecting the third metal lines to an associated one of the second metal lines.

Description

Technical Field

[0001] This disclosure generally relates to semiconductor devices, and more specifically to a semiconductor device having a well contact diffusion region that provides a well potential. Background Technology

[0002] In a semiconductor device, an n-channel MOS transistor is formed in a p-type well, and a p-channel MOS transistor is formed in an n-type well. A well potential is provided to the well via well contact diffusion regions that are respectively connected to power lines. Since the well contact diffusion regions have a higher resistance than the power lines, it is desirable to arrange the well contact diffusion regions to the power line contact plugs with a shorter spacing. Summary of the Invention

[0003] According to one aspect of this application, an apparatus is provided. The device includes: a well region having a first conductivity type and formed in a semiconductor substrate; a first diffusion region formed in the well region, having the first conductivity type and extending in a first direction; a plurality of second diffusion regions formed in the well region, having a second conductivity type and arranged in the first direction; a first metal line extending in the first direction to overlap with the first diffusion region; a plurality of second metal lines each extending in a second direction to overlap with an associated second diffusion region; a third metal line extending in the first direction to overlap with each of the first metal line and the second metal lines; a plurality of first contact plugs arranged in the first direction, the first contact plugs electrically connecting the first metal line to the first diffusion region; a plurality of second contact plugs each electrically connecting an associated second metal line to an associated second diffusion region; and a plurality of third contact plugs each electrically connecting the third metal line to an associated second metal line.

[0004] According to another aspect of this application, an apparatus is provided. The apparatus includes: a first well region having a first conductivity type and formed in a semiconductor substrate; a first well contact diffusion region having the first conductivity type and formed in the first well region, the first well contact diffusion region extending in a first direction; a plurality of first transistors arranged along the first well contact diffusion region in the first direction, each of the first transistors including a source diffusion region having a second conductivity type opposite to the first conductivity type and formed in the first well region; a first wiring layer including a first power line and a plurality of second power lines, the first power lines extending in the first direction to overlap with the first well contact diffusion region, each of the second power lines extending in a second direction different from the first direction to overlap with the source diffusion region of one of the first transistors associated with it; a second wiring layer; and a second wiring layer. The second wiring layer includes a third power line having a first segment and a plurality of second segments, the first segment extending in a first direction to overlap with the first power line, and each of the plurality of second segments branching from a first edge of the first segment and extending in a second direction to overlap with an associated second power line of the second power line; a plurality of first contact plugs arranged along the first well contact diffusion region and the first power line for electrical connection to each other; a plurality of second contact plugs each electrically connecting the source diffusion region of an associated first transistor of the first transistor to an associated second power line of the second power line; and a plurality of third contact plugs each electrically connecting an associated second power line of the second power line to an associated second segment of the second power line.

[0005] According to another aspect of this application, an apparatus is provided. The apparatus comprises: a diffusion layer including a first diffusion region and a second diffusion region, the first diffusion region being of a first conductivity type and extending in a first direction, and the second diffusion region being of a second conductivity type and disposed separately from the first diffusion region; and a multilayer wiring structure located on the diffusion layer, the multilayer wiring structure including at least a first wiring layer and a second wiring layer on the first wiring layer; wherein the first wiring layer includes a first metal line providing a first voltage to the first diffusion region, the first metal line extending in the first direction and overlapping the first diffusion region; and wherein the second wiring layer includes a second metal line providing a second voltage to the second diffusion region, the second metal line extending in the first direction and overlapping the first metal line. Attached Figure Description

[0006] Figure 1 This is a schematic plan view showing the configuration of the main parts of a semiconductor device according to the present disclosure;

[0007] Figure 2 It is a schematic floor plan, in which when from Figure 1 These components are shown when the diffusion layer and gate electrode are extracted from the planar diagram;

[0008] Figure 3 It is along Figure 2 A schematic cross-sectional view of line A-A shown;

[0009] Figure 4 It is along Figure 1 A schematic cross-sectional view of line B-B shown;

[0010] Figure 5 It is along Figure 1 A schematic cross-sectional view of line C-C shown;

[0011] Figure 6 It is a schematic floor plan, in which when from Figure 1 These layers are shown when the first and second wiring layers are extracted from the plan view;

[0012] Figure 7 It is a schematic floor plan, in which when from Figure 1 When extracting the third wiring layer from the plan view, this layer is shown; and

[0013] Figure 8 This is a schematic perspective view showing the configuration of the main parts of a semiconductor device according to the present disclosure. Detailed Implementation

[0014] Various embodiments of the present invention will now be explained in detail with reference to the accompanying drawings. The following detailed description refers to the accompanying drawings, which illustrate specific aspects and embodiments in which the invention can be practiced. These embodiments are described in sufficient detail to enable those skilled in the art to practice the invention. Other embodiments may be utilized, and structural, logical, and electrical changes may be made without departing from the scope of the invention. The various embodiments disclosed herein are not necessarily mutually exclusive, as some disclosed embodiments may be combined with one or more other disclosed embodiments to form new embodiments.

[0015] The semiconductor device according to this embodiment is a standard cell type semiconductor device, and has, as follows: Figure 1The diagram shows cell regions N1, N2, P1, and P2 extending in the x-direction. Multiple n-channel MOS transistors 10 are arranged in cell regions N1 and N2 along the x-direction, and multiple p-channel MOS transistors 20 are arranged in cell regions P1 and P2 along the x-direction. Cell regions P1 and P2 are arranged to sandwich cell regions N1 and N2 in the y-direction.

[0016] like Figure 2 and 3 As shown, a deep n-well region 4 is formed in a semiconductor substrate 2 made of p-type silicon. A p-well region 6 and an n-well region 8 are formed in the deep n-well region 4. The p-well region 6 is a region with p-conductivity, in which an n-channel MOS transistor 10 is formed. A well potential VPW is provided to the p-well region 6 via a well contact diffusion region 31. The well contact diffusion region 31 includes a p-type diffusion layer with a higher dopant concentration than the p-well region 6. The n-well region 8 is a region with n-conductivity, in which a p-channel MOS transistor 20 is formed. The n-conductivity type is the opposite of the p-conductivity type. A well potential VNW is provided to the n-well region 8 via a well contact diffusion region 33. The well contact diffusion region 33 includes an n-type diffusion layer with a higher dopant concentration than the n-well region 8. A ground potential VSS is provided to the semiconductor substrate 2. The well contact diffusion region 31 is arranged to extend along the x-direction between cell regions N1 and N2. The well potential VPW is provided to the well contact diffusion region 31 via a plurality of contact plugs 32 extending in the x-direction. The well contact diffusion region 33 is arranged in a ring shape along the n-well region 8. The well potential VNW is provided to the well contact diffusion region 32 via a plurality of contact plugs 34 extending in the x or y direction.

[0017] Each of the n-channel MOS transistors 10 includes an n-type source diffusion region 10S and a drain diffusion region 10D, and a gate electrode 10G covering the channel region located between the source diffusion region 10S and the drain diffusion region 10D. Each of the p-channel MOS transistors 20 includes a p-type source diffusion region 20S and a drain diffusion region 20D, and a gate electrode 20G covering the channel region located between the source diffusion region 20S and the drain diffusion region 20D. A dummy gate electrode 10DG is provided between adjacent gate electrodes 10G in the x-direction. A dummy gate electrode 20DG is provided between adjacent gate electrodes 20G in the x-direction.

[0018] like Figure 4 and 5 As shown, wiring layers L1 to L3 are disposed on semiconductor substrate 2. Wiring layer L1 is the bottom layer, wiring layer L2 is the layer above wiring layer L1, and wiring layer L3 is the layer above wiring layer L2. Although there is another wiring layer on wiring layer L3, Figure 4 and 5These layers are omitted. Wiring layers L1 to L3 can be made of metallic materials such as aluminum, copper, or tungsten. Interlayer dielectric film 41 is disposed between semiconductor substrate 2 and wiring layer L1, interlayer dielectric film 42 is disposed between wiring layer L1 and wiring layer L2, and interlayer dielectric film 43 is disposed between wiring layer L2 and wiring layer L3.

[0019] like Figure 6 As shown, wiring patterns 51 to 57 are disposed on wiring layer L1. Wiring pattern 51 extends in the x-direction to overlap with well contact diffusion region 31. Wiring pattern 51 and well contact diffusion region 31 are connected to each other via a plurality of contact plugs 32 configured to penetrate interlayer dielectric film 41. "Connection" may include physical connection and / or electrical connection. Wiring pattern 52 each extends in the y-direction to overlap with one source diffusion region associated with the source diffusion region 10S of the n-channel MOS transistor 10. Wiring pattern 52 is assigned to a plurality of n-channel MOS transistors 10. Thus, the plurality of wiring patterns 52 assigned to the n-channel MOS transistors 10 in cell region N1 are arranged in the x-direction, and the plurality of wiring patterns 52 assigned to the n-channel MOS transistors 10 in cell region N2 are also arranged in the x-direction. Wiring pattern 52 is connected to one of the associated source diffusion regions 10S via contact plugs 35 configured to penetrate interlayer dielectric film 41. Wiring pattern 53 extends in a ring shape to overlap with well contact diffusion region 33. Wiring patterns 53 and well contact diffusion regions 33 are connected to each other via a plurality of contact plugs 34 configured to pass through the interlayer dielectric film 41. Each wiring pattern 54 extends in the y-direction to overlap with one source diffusion region associated with the source diffusion regions 20S of the p-channel MOS transistor 20. Wiring patterns 54 are each assigned to a plurality of p-channel MOS transistors 20. Therefore, the plurality of wiring patterns 54 assigned to the p-channel MOS transistors 20 in cell region P1 are arranged in the x-direction, and the plurality of wiring patterns 54 assigned to the p-channel MOS transistors 20 in cell region P2 are also arranged in the x-direction. Each wiring pattern 54 is connected to one associated source diffusion region in the source diffusion regions 20S via a contact plug 37 configured to pass through the interlayer dielectric film 41.

[0020] Wiring patterns 55 each extend in the y-direction to overlap with one of the associated drain diffusion regions 10D of the n-channel MOS transistor 10. Wiring patterns 55 are each assigned to a plurality of n-channel MOS transistors 10. Therefore, the plurality of wiring patterns 55 assigned to the n-channel MOS transistors 10 in cell region N1 are arranged in the x-direction, and the plurality of wiring patterns 55 assigned to the n-channel MOS transistors 10 in cell region N2 are also arranged in the x-direction. Each wiring pattern 55 is connected to one of the associated drain diffusion regions 10D via a contact plug 36 configured to pass through the interlayer dielectric film 41. Wiring patterns 56 each extend in the y-direction to overlap with one of the associated drain diffusion regions 20D of the p-channel MOS transistor 20. Wiring patterns 56 are each assigned to a plurality of p-channel MOS transistors 20. Therefore, the multiple wiring patterns 56 assigned to the p-channel MOS transistors 20 in cell region P1 are arranged along the x-direction, and the multiple wiring patterns 56 assigned to the p-channel MOS transistors 20 in cell region P2 are also arranged along the x-direction. Each wiring pattern 56 is connected to an associated drain diffusion region in drain diffusion region 20D via a contact plug 38 configured to pass through the interlayer dielectric film 41.

[0021] Each of the wiring patterns 57 is assigned to the gate electrodes 10G and 20G of a pair of transistors (one associated n-channel MOS transistor in n-channel MOS transistor 10 and one associated p-channel MOS transistor in p-channel MOS transistor 20). Wiring patterns 57 are each connected to the associated gate electrode 10G and 20G via contact plugs (not shown). Therefore, the associated gate electrodes 10G and 20G are short-circuited.

[0022] like Figure 6As shown, wiring patterns 61 to 66 are disposed on wiring layer L2. Wiring pattern 61 extends in the x-direction to overlap with the well contact diffusion region 31 and wiring pattern 51. Wiring patterns 61 and 51 are isolated from each other. Wiring pattern 61 has a segment 61A extending in the x-direction and a plurality of segments 61B branching from segment 61A toward the y-direction. Segment 61A overlaps with the well contact diffusion region 31 and wiring pattern 51. Each segment 61B overlaps with one of the associated wiring patterns 52 and is connected to the associated wiring pattern 52 via a contact plug 81 configured to pass through the interlayer dielectric film 42. Wiring pattern 62 extends in the x-direction to overlap with the well contact diffusion region 33 and wiring pattern 53. Wiring patterns 62 and 53 are insulated from each other. Wiring pattern 62 each has a segment 62A extending in the x-direction and a plurality of segments 62B branching from segment 62A toward the y-direction. Segment 62A overlaps with the well contact diffusion region 33 and wiring pattern 53. Each segment 62B overlaps with one of the associated wiring patterns in wiring pattern 54 and is connected to the associated wiring pattern 54 via a contact plug 82 configured to pass through the interlayer dielectric film 42.

[0023] Wiring patterns 63 each extend in the y-direction to overlap with the drain diffusion regions 10D and 20D of a pair of transistors (one associated n-channel MOS transistor in n-channel MOS transistor 10 and one associated p-channel MOS transistor in p-channel MOS transistor 20). Wiring patterns 63 are each connected to associated wiring patterns in wiring patterns 55 and 56 via contact plugs 83 and 84 configured to pass through the interlayer dielectric film 42. Therefore, the drain diffusion region 10D of each n-channel MOS transistor 10 and the drain diffusion region 20D of the associated p-channel MOS transistor in p-channel MOS transistor 20 are short-circuited. Wiring patterns 64 are each configured to overlap with the gate electrodes 10G and 20G of a pair of transistors (one associated n-channel MOS transistor in n-channel MOS transistor 10 and one associated p-channel MOS transistor in p-channel MOS transistor 20). Wiring patterns 64 are each connected to associated wiring pattern in wiring pattern 57 via contact plugs 85 configured to pass through the interlayer dielectric film 42.

[0024] Wiring patterns 65 are respectively disposed at positions overlapping with both ends of wiring pattern 51 along the x-direction. Wiring patterns 65 are connected to wiring pattern 51 via contact plugs 86 configured to pass through interlayer dielectric film 42. Wiring patterns 66 are respectively disposed in wiring pattern 53 at positions not overlapping with wiring pattern 62. Wiring patterns 66 are connected to wiring pattern 53 via contact plugs 87 configured to pass through interlayer dielectric film 42.

[0025] like Figure 7As shown, wiring patterns 71 to 74 are disposed on wiring layer L3. Wiring pattern 71 extends in the x-direction to overlap with segment 61A of the well contact diffusion region 31, wiring pattern 51, and wiring pattern 61. Wiring pattern 71 is connected to wiring pattern 61 via a plurality of contact plugs 91 configured to pass through interlayer dielectric film 43. The contact plugs 91 are arranged in the x-direction. Wiring pattern 72 each extends in the x-direction to overlap with one of the associated segments of the well contact diffusion region 33, wiring pattern 53, and wiring pattern 62. Wiring pattern 72 is connected to one of the associated wiring patterns 62 via contact plugs 92 configured to pass through interlayer dielectric film 43. Wiring pattern 73 is disposed at a position overlapping with wiring pattern 65 and is connected to wiring pattern 65 via contact plugs 93 configured to pass through interlayer dielectric film 43. Wiring pattern 74 is disposed at a position overlapping with wiring pattern 66 and is connected to wiring pattern 66 via contact plugs 94 configured to pass through interlayer dielectric film 43.

[0026] Using this configuration, the well potential VPW supplied to the p-well region 6 is provided to the well contact diffusion region 31 via wiring pattern 73, contact plug 93, wiring pattern 65, contact plug 86, wiring pattern 51, and contact plug 32. Since wiring pattern 51 extends in the x-direction to overlap with the well contact diffusion region 31, and wiring pattern 51 is connected to the well contact diffusion region 31 via contact plug 32, the resistance of the path providing the well potential VPW to the p-well region 6 is reduced. Therefore, as... Figure 8 As shown, the spacing of the path 51A, which provides the well potential VPW to the wiring pattern 51, can be increased. The arrangement spacing of the contact plugs 32 can be shorter than the array spacing of the contact plugs 91. Similarly, because the well contact diffusion region 33 is connected to the wiring pattern 53 via the contact plug 34, the resistance of the path providing the well potential VNW to the n-well region 8 can be reduced.

[0027] Although the invention has been disclosed in the context of certain preferred embodiments and examples, those skilled in the art will understand that the invention extends beyond the specifically disclosed embodiments to other alternative embodiments and / or uses of the invention and their obvious modifications and equivalents. Furthermore, other modifications within the scope of the invention will be apparent to those skilled in the art based on this disclosure. It is also contemplated that various combinations or sub-combinations of specific features and aspects of the embodiments can be made and still fall within the scope of the invention. It should be understood that various features and aspects of the disclosed embodiments can be combined or substituted with each other to form different modes of the disclosed invention. Therefore, it is intended that the scope of at least some of the invention disclosed herein should not be limited to the specific disclosed embodiments described above.

Claims

1. A semiconductor device comprising: a well region having a first conductivity type and formed in a semiconductor substrate; a first diffusion region formed in the well region, the first diffusion region having the first conductivity type and extending in a first direction; a plurality of second diffusion regions formed in the well region, the second diffusion regions having a second conductivity type, the second diffusion regions arranged in the first direction; a first metal line extending in the first direction so as to overlap the first diffusion region; a plurality of second metal lines each extending in a second direction so as to overlap an associated one of the second diffusion regions; a third metal line extending in the first direction so as to overlap each of the first metal line and the second metal lines; a plurality of first contact plugs arranged in the first direction, the first contact plugs electrically connecting the first metal line to the first diffusion region; a plurality of second contact plugs each electrically connecting an associated one of the second metal lines to an associated one of the second diffusion regions; and a plurality of third contact plugs each electrically connecting the third metal line to an associated one of the second metal lines.

2. The semiconductor device of claim 1, wherein the first and second metal lines are provided on a same wiring layer.

3. The semiconductor device of claim 2, wherein the first and second metal lines are provided on a first wiring layer, and wherein the third metal line is provided on a second wiring layer located above the first wiring layer.

4. The semiconductor device of claim 3, wherein the first metal line is isolated from the second and third metal lines.

5. The semiconductor device of claim 4, further comprising: a fourth metal line extending in the first direction so as to overlap the third metal line; and a plurality of fourth contact plugs arranged in the first direction, the fourth contact plugs electrically connecting the fourth metal line to the third metal line.

6. The semiconductor device of claim 5, wherein the fourth metal line is provided on a third wiring layer located above the second wiring layer.

7. The semiconductor device of claim 6, wherein the first diffusion region, the first metal line, the third metal line, and the fourth metal line overlap one another.

8. The semiconductor device of claim 6, wherein a pitch of the first contact plugs is shorter than a pitch of the fourth contact plugs.

9. The semiconductor device of claim 1, wherein a dopant concentration of the first diffusion region is greater than a dopant concentration of the well region.

10. The semiconductor device of claim 1, further comprising a plurality of transistors arranged in the first direction, ​ wherein each of the second diffusion regions is configured as a source diffusion region of an associated one of the transistors.

11. A semiconductor device comprising: a first well region having a first conductivity type and formed in a semiconductor substrate; a first well contact diffusion region having the first conductivity type and formed in the first well region, the first well contact diffusion region extending in a first direction; a plurality of first transistors arranged along the first well contact diffusion region in the first direction, each of the first transistors including a source diffusion region having a second conductivity type opposite the first conductivity type and formed in the first well region; a first wiring layer including a first power line and a plurality of second power lines, the first power line extending in the first direction so as to overlap the first well contact diffusion region, each of the second power lines extending in a second direction different from the first direction so as to overlap the source diffusion region of an associated one of the first transistors; a second wiring layer including a third power line having a first section and a plurality of second sections, the first section extending in the first direction so as to overlap the first power line, the plurality of second sections each branching from a first edge of the first section and extending in the second direction so as to overlap an associated one of the second power lines; a plurality of first contact plugs arranged along the first well contact diffusion region and the first power line so as to be electrically connected to each other; a plurality of second contact plugs each electrically connecting the source diffusion region of an associated one of the first transistors to an associated one of the second power lines; and a plurality of third contact plugs each electrically connecting an associated one of the second power lines to an associated one of the second sections of the third power line.

12. The semiconductor device according to claim 11, further comprising: a third wiring layer including a fourth power line extending in the first direction so as to overlap the first section of the third power line; and a plurality of fourth contact plugs arranged along the first section of the third power line so as to electrically connect the fourth power line to the third power line.

13. The semiconductor device according to claim 12, wherein a pitch of the first contact plugs is shorter than a pitch of the fourth contact plugs.

14. The semiconductor device of claim 12, further comprising a plurality of second transistors arranged in the first direction along the first well contact diffusion region, such that the first well contact diffusion region is arranged between first and second transistors, each of the second transistors including a source diffusion region having the second conductivity type and formed in the first well region, wherein the first wiring layer further includes a plurality of fifth power lines each extending in the second direction so as to overlap the source diffusion region of an associated one of the second transistors, wherein the third power line further has a plurality of third segments each branching from a second edge of the first segment opposite the first edge and extending in the second direction so as to overlap an associated one of the fifth power lines, wherein the semiconductor device further comprises: a plurality of fifth contact plugs each electrically connecting the source diffusion region of an associated one of the second transistors to an associated one of the fifth power lines; and a plurality of sixth contact plugs each electrically connecting an associated one of the fifth power lines to an associated one of the third segments of the third power line.

15. The semiconductor device of claim 12, further comprising: a second well region having the second conductivity type and formed in the semiconductor substrate; a second well contact diffusion region having the second conductivity type and formed in the second well region, the second well contact diffusion region extending in the first direction; and a plurality of second transistors arranged in the first direction along the second well contact diffusion region, each of the second transistors including a source diffusion region having the first conductivity type and formed in the second well region, wherein the first wiring layer further includes a fifth power line extending in the first direction so as to overlap the second well contact diffusion region and a plurality of sixth power lines each extending in the second direction so as to overlap the source diffusion region of an associated one of the second transistors, wherein the second wiring layer further includes a seventh power line having a third segment extending in the first direction so as to overlap the fifth power line and a plurality of fourth segments each branching from the third segment and extending in the second direction so as to overlap an associated one of the sixth power lines, wherein the semiconductor device further comprises: a plurality of fifth contact plugs arranged along the second well contact diffusion region and the fifth power line so as to be electrically connected to each other; and a plurality of sixth contact plugs each electrically connecting an associated one of the sixth power lines to an associated one of the fourth segments of the seventh power line. a plurality of sixth contact plugs each electrically connecting the source diffusion region of an associated one of the second transistors to an associated one of the sixth power lines; and a plurality of seventh contact plugs each electrically connecting an associated one of the sixth power lines to an associated one of the fourth segments of the seventh power lines.

16. The semiconductor device of claim 15, wherein the third wiring layer further comprises an eighth power line that extends in the first direction so as to overlap the third segment of the seventh power line, and wherein, the semiconductor device further includes a plurality of eighth contact plugs arranged along the third segment of the seventh power line so as to electrically connect the eighth power line to the seventh power line.

17. The semiconductor device of claim 16, wherein each of the first transistors further comprises a drain diffusion region having the second conductivity type and formed in the first well region, wherein each of the second transistors further comprises a drain diffusion region having the first conductivity type and formed in the second well region, and wherein the drain diffusion region of each of the first transistors is electrically connected to the drain diffusion region of an associated one of the second transistors.

18. The semiconductor device of claim 17, wherein the second wiring layer further comprises a plurality of ninth lines that extend in the second direction, and wherein the drain diffusion region of each of the first transistors is electrically connected to the drain diffusion region of an associated one of the second transistors via an associated one of the ninth lines.

19. The semiconductor device of claim 18, wherein each of the first transistors further comprises a gate electrode formed over a channel region between source and drain diffusion regions, wherein each of the second transistors further comprises a gate electrode formed over a channel region between source and drain diffusion regions, and wherein the gate electrode of each of the first transistors is electrically connected to the gate electrode of an associated one of the second transistors.

20. A semiconductor device, the semiconductor device comprising: a diffusion layer including a first diffusion region and a second diffusion region, the first diffusion region being of a first conductivity type and elongated in a first direction, the second diffusion region being of a second conductivity type and disposed apart from the first diffusion region; and a multilayer wiring structure on the diffusion layer, the multilayer wiring structure including at least a first wiring layer and a second wiring layer on the first wiring layer; wherein the first wiring layer comprises first metal lines that provide a first voltage to the first diffusion regions, the first metal lines being elongated in the first direction and overlapping the first diffusion regions; and wherein the second wiring layer includes a second metal line, the second metal line providing the second voltage to the second diffusion region, the second metal line being elongated in the first direction and overlapping the first metal line.

21. The semiconductor device according to claim 20, wherein the second metal line includes a first section and a second section, the first section overlapping the first metal line, the second section branching from the first section toward a second direction so as not to overlap the first metal line.

22. The semiconductor device according to claim 21, wherein the first wiring layer further includes a third metal line, one end of the third metal line overlapping and connected to the second diffusion region, and the other end overlapping and connected to the second section of the second metal line.

23. The semiconductor device according to claim 20, wherein the multilayer wiring structure further includes a third wiring layer on the second wiring layer, and wherein the third wiring layer includes a third metal line, the third metal line providing the second voltage to the second metal line, the third metal line being elongated in the first direction and overlapping the second metal line.

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