Semiconductor structure and method for forming the same

Abstract

A semiconductor structure and a method for forming the same include: a substrate; and a plurality of first fin structures located on the substrate, wherein the first fin structure includes a first fin and a second fin arranged in parallel along a first direction, and a third fin and a fourth fin arranged in parallel along a second direction, the third fin connecting one end of the first fin and the second fin, and the fourth fin connecting the other end of the first fin and the second fin. The first fin structure of this structure is relatively large, thereby increasing the surface area of the first source / drain openings formed on both sides of the first fin structure. As the surface area of the first source / drain openings increases, the volume of the first source / drain doped layer formed within the first source / drain openings also increases accordingly, thereby increasing the amount of first source / drain ions doped within the first source / drain doped layer, thereby increasing the current between the first source / drain doped layers and improving the performance of the resulting semiconductor structure.

Description

Technical Field

[0001] The present invention relates to the technical field of semiconductor manufacturing, and in particular to a semiconductor structure and a method for forming the same. Background Art

[0002] As semiconductor device integration increases, the critical dimensions of transistors continue to shrink. This reduction in critical dimensions allows for more transistors to be placed on a chip, thereby improving device performance. However, as device area continues to shrink, problems arise. With the rapid reduction in transistor size, the gate dielectric thickness and operating voltage cannot be adjusted accordingly, making it more difficult to suppress short-channel effects, resulting in increased channel leakage current in transistors.

[0003] As MOS transistors shrink, the gate becomes shorter, shortening the current channel beneath the gate. When the MOS transistor channel shortens to a certain extent, the short channel effect occurs. Theoretically, the channel length is the distance from the source extension to the drain extension. However, the effective channel length varies due to the influence of the junction voids formed by the source and drain electrodes and the substrate. When the channel length is equal to or shorter than the depth of the junction voids, the junction voids significantly cut into the current channel, causing a decrease in the gate threshold voltage. This is the short channel effect.

[0004] To reduce the short-channel effect of semiconductor devices, conventional techniques typically increase the width of the gate structure along the fin extension direction. However, increasing the gate structure's width also creates other issues, resulting in reduced performance of the resulting semiconductor structure. Therefore, the performance of semiconductor structures formed using conventional techniques remains to be improved. Summary of the Invention

[0005] The technical problem solved by the present invention is to provide a semiconductor structure and a method for forming the same, which can effectively improve the performance of the finally formed semiconductor structure.

[0006] To solve the above problems, the present invention provides a semiconductor structure, comprising: a substrate, the substrate comprising a first region; a plurality of first fin structures located on the first region, the first fin structure comprising a first fin and a second fin arranged in parallel along a first direction, and a third fin and a fourth fin arranged in parallel along a second direction, the first direction and the second direction being perpendicular, the third fin connecting one side end portion of the first fin and the second fin, and the fourth fin connecting the other side end portion of the first fin and the second fin; a first gate structure located on the substrate, the first gate structure spanning the first fin and the second fin along the first direction, the third fin and the fourth fin being located on both sides of the first gate structure, respectively; a first source-drain opening within the first fin structure located on both sides of the first gate structure; a first source-drain doping layer located within the first source-drain opening, the first source-drain doping layer having first source-drain ions.

[0007] Optionally, the first fin and the second fin have a first size along the second direction, and the first size ranges from 100 nm to 700 nm.

[0008] Optionally, the third fin and the fourth fin have a second size along the first direction, and the second size ranges from 10 nm to 50 nm.

[0009] Optionally, the first source-drain ions include: N-type ions or P-type ions; the N-type ions include: phosphorus or arsenic; the P-type ions include: boron or indium.

[0010] Optionally, the substrate further includes a second region, and the first region and the second region are arranged in parallel along the first direction.

[0011] Optionally, the method further includes: a plurality of second fin structures located on the second region and arranged in parallel along the first direction.

[0012] Optionally, the method further includes: a second gate structure located on the substrate, the second gate structure spanning the second fin structure, and the second gate structure covering a portion of the sidewall and top surface of the second fin structure.

[0013] Optionally, the first gate structure has a first width dimension, the second gate structure has a second width dimension, the first width dimension is greater than the second width dimension, and directions of the first width dimension and the second width dimension are along the second direction.

[0014] Correspondingly, the present invention also provides a method for forming a semiconductor structure, comprising: providing a substrate, the substrate comprising a first region; forming a plurality of first fin structures on the first region, the first fin structure comprising a first fin and a second fin arranged in parallel along a first direction, and a third fin and a fourth fin arranged in parallel along a second direction, the first direction being perpendicular to the second direction, the third fin connecting one side end portion of the first fin and the second fin, and the fourth fin connecting the other side end portion of the first fin and the second fin; forming a first gate structure on the substrate, the first gate structure spanning the first fin and the second fin along the first direction, the third fin and the fourth fin being located on both sides of the first gate structure respectively; forming a first source-drain opening in the first fin structure on both sides of the first gate structure; forming a first source-drain doping layer in the first source-drain opening, the first source-drain doping layer having first source-drain ions.

[0015] Optionally, the substrate further includes a second region, and the first region and the second region are arranged in parallel along the first direction.

[0016] Optionally, during the process of forming the first fin structure, the method further includes: forming a plurality of second fin structures arranged in parallel along the first direction on the second region.

[0017] Optionally, the method for forming the first fin structure and the second fin structure includes: forming a first core layer on the first region, the first core layer having a plurality of first openings therein, the first openings exposing the top surface of the substrate; forming a second core layer on the second region, the second core layer having a plurality of second openings therein, the second openings exposing the top surface of the substrate, and the second openings penetrating the second core layer along the second direction; forming a fin material layer on the first opening, the second opening, the side walls of the first core layer, the second core layer, and the top surfaces of the first core layer, the second core layer and the substrate; etching back the fin material layer until the first core layer, the second core layer and the top surfaces of the substrate are exposed to form an initial first fin structure and an initial second fin structure; removing the fin material layer located on the side walls of the first core layer to form the first fin structure; removing the fin material layer located on the side walls of the second core layer to form the second fin structure.

[0018] Optionally, the process for forming the fin material layer includes an atomic layer deposition process.

[0019] Optionally, the method for forming the first core layer and the second core layer includes: forming a core material layer on the substrate; forming a patterned layer on the core material layer, the patterned layer exposing a portion of the top surface of the core material layer; etching the core material layer using the patterned layer as a mask until the top surface of the substrate is exposed, thereby forming the first core layer and the second core layer.

[0020] Optionally, a material of the first core layer is different from a material of the first fin structure; a material of the second core layer is different from a material of the second fin structure.

[0021] Optionally, the material of the core material layer includes: silicon or silicon nitride.

[0022] Optionally, after forming the first fin structure and the second fin structure, the method further includes: removing the first core layer and the second core layer.

[0023] Optionally, the first fin and the second fin have a first size along the second direction, and the first size ranges from 100 nm to 700 nm.

[0024] Optionally, the third fin and the fourth fin have a second size along the first direction, and the second size ranges from 10 nm to 50 nm.

[0025] Optionally, the process of forming the first gate structure further includes: forming a second gate structure on the substrate, wherein the second gate structure spans the second fin structure and covers a portion of the sidewall and top surface of the second fin structure.

[0026] Optionally, the first gate structure has a first width dimension, the second gate structure has a second width dimension, the first width dimension is greater than the second width dimension, and directions of the first width dimension and the second width dimension are along the second direction.

[0027] Optionally, before forming the first gate structure, it also includes: forming a first dummy gate structure on the substrate, the first gate structure spanning the first fin and the second fin along the first direction, and the third fin and the fourth fin are respectively located on both sides of the first gate structure.

[0028] Optionally, the method of forming the first source-drain openings in the first fin structure on both sides of the first gate structure includes: etching the first fin structure using the first dummy gate structure as a mask to form the first source-drain openings.

[0029] Optionally, the method for forming the first source-drain doped layer includes: forming a first epitaxial layer in the first source-drain opening using an epitaxial growth process; in-situ doping the first epitaxial layer during the epitaxial growth process, and doping the first source-drain ions into the epitaxial layer to form the first source-drain doped layer.

[0030] Optionally, the first source-drain ions include: N-type ions or P-type ions; the N-type ions include: phosphorus or arsenic; the P-type ions include: boron or indium.

[0031] Compared with the prior art, the technical solution of the present invention has the following advantages:

[0032] In the structure of the technical solution of the present invention, a first fin structure is formed on the first region, and the first fin structure includes a first fin and a second fin arranged in parallel along a first direction, and a third fin and a fourth fin arranged in parallel along a second direction, the first direction and the second direction being perpendicular, the third fin connecting one end of the first fin and the second fin, and the fourth fin connecting the other end of the first fin and the second fin. In this way, the volume of the first fin structure is increased, so that the surface area of the first source and drain opening formed by etching the first fin structure on both sides of the first gate structure is increased. When the surface area of the first source and drain opening is increased, the volume of the first source and drain doping layer formed in the first source and drain opening is also increased accordingly, thereby increasing the first source and drain ions doped in the first source and drain doping layer, thereby increasing the current between the first source and drain doping layers, and improving the performance of the semiconductor structure finally formed.

[0033] In the formation method of the technical solution of the present invention, a first fin structure is formed on the first region, wherein the first fin structure includes a first fin and a second fin arranged in parallel along a first direction, and a third fin and a fourth fin arranged in parallel along a second direction, wherein the first direction is perpendicular to the second direction, the third fin connects one end of the first fin and the second fin, and the fourth fin connects the other end of the first fin and the second fin. In this way, the volume of the first fin structure is increased, so that the surface area of the first source and drain opening formed by etching the first fin structure on both sides of the first gate structure is increased. When the surface area of the first source and drain opening is increased, the volume of the first source and drain doping layer formed in the first source and drain opening is also increased accordingly, thereby increasing the first source and drain ions doped in the first source and drain doping layer, thereby increasing the current between the first source and drain doping layers, and improving the performance of the semiconductor structure finally formed. BRIEF DESCRIPTION OF THE DRAWINGS

[0034] Figure 1 and Figure 2It is a structural diagram of a semiconductor structure;

[0035] Figures 3 to 14 It is a schematic structural diagram of each step of an embodiment of a method for forming a semiconductor structure of the present invention. DETAILED DESCRIPTION

[0036] As described in the background art, the performance of the semiconductor structure formed in the prior art still needs to be improved, which will be described in detail below with reference to the accompanying drawings.

[0037] Please refer to Figure 1 and Figure 2 , Figure 1 It is a top view of the semiconductor structure with the source and drain doping layers omitted. Figure 2 yes Figure 1 In the cross-sectional schematic diagram along line AA, a substrate 100 is provided, wherein the substrate 100 has a plurality of mutually separated fins 101, and the fins extend along a first direction X; an isolation layer 102 is formed on the substrate 100, wherein the isolation layer 102 covers a portion of the sidewall surface of the fin 101, and the top surface of the isolation layer 102 is lower than the top surface of the fin 101; a gate structure 103 is formed on the substrate 100, wherein the gate structure 103 spans the fin 101 and covers a portion of the sidewall and top surface of the fin 101; source and drain openings (not shown) are formed in the fin 101 on both sides of the gate structure 103; a source and drain doping layer 104 is formed in the source and drain openings, wherein the source and drain doping layer 104 has source and drain ions.

[0038] In this embodiment, by increasing the width D1 of the gate structure 103 along the extending direction of the fin 101 , the length of the channel is increased, thereby reducing the influence of the channel effect.

[0039] However, when the width D1 of the gate structure 103 increases, the increased size of the fin 101 along the first direction X also increases, thereby increasing the second width D2 of the fin 101 exposed on both sides of the gate structure 103. When the second width D2 of the exposed fin 101 increases, the size of the subsequently formed source and drain openings along the first direction X also increases. Because the source and drain doped layers 104 are formed by epitaxial growth on the fin 101 exposed on the surface of the source and drain openings, when the size of the source and drain openings along the first direction X is larger, the volume of the source and drain doped layers 104 grown in the second direction Y is smaller. The second direction Y is perpendicular to the first direction X, thereby reducing the overall volume of the source and drain doped layers 104.

[0040] When the overall volume of the source / drain doped layer 104 is small, the amount of the source / drain ions in the source / drain doped layer 104 is also small, and thus the current formed between the source / drain doped layer 104 is also small, which reduces the performance of the final semiconductor structure.

[0041] On this basis, the present invention provides a semiconductor structure and a method for forming the same, wherein a first fin structure is formed on a first region, wherein the first fin structure includes a first fin and a second fin arranged in parallel along a first direction, and a third fin and a fourth fin arranged in parallel along a second direction, wherein the first direction is perpendicular to the second direction, the third fin connects one end of the first fin and the second fin, and the fourth fin connects the other end of the first fin and the second fin. In this way, the volume of the first fin structure is increased, so that the surface area of the first source-drain opening formed by etching the first fin structure on both sides of the first gate structure is increased. When the surface area of the first source-drain opening is increased, the volume of the first source-drain doped layer formed in the first source-drain opening is also increased accordingly, thereby increasing the amount of first source-drain ions doped in the first source-drain doped layer, thereby increasing the current between the first source-drain doped layer, and improving the performance of the semiconductor structure finally formed.

[0042] In order to make the above-mentioned objects, features and advantages of the present invention more obvious and easy to understand, specific embodiments of the present invention are described in detail below with reference to the accompanying drawings.

[0043] Figures 3 to 14 It is a structural schematic diagram of a formation process of a semiconductor structure according to an embodiment of the present invention.

[0044] Please refer to Figure 3 , providing a substrate 200, wherein the substrate 200 includes a first region I.

[0045] In this embodiment, the substrate 200 further includes a second region II, and the first region I and the second region II are arranged in parallel along the first direction X.

[0046] In this embodiment, the material of the substrate 200 is silicon; in other embodiments, the material of the substrate may also be germanium, silicon germanium, silicon carbide, gallium arsenide, or indium gallium.

[0047] After providing the substrate 200, it also includes: forming a plurality of first fin structures on the first region I, the first fin structure including a first fin and a second fin arranged in parallel along a first direction X, and a third fin and a fourth fin arranged in parallel along a second direction, the first direction and the second direction being perpendicular, the third fin connecting one end of the first fin and the second fin, and the fourth fin connecting the other end of the first fin and the second fin; forming a plurality of second fin structures arranged in parallel along the first direction X on the second region II. For the specific formation process of the first fin structure and the second fin structure, please refer to Figures 4 to 6 .

[0048] Please refer to Figure 4 A first core layer 201 is formed on the first region I, and the first core layer 201 has a plurality of first openings 202 therein, and the first openings 202 expose the top surface of the substrate 200; a second core layer 203 is formed on the second region II, and the second core layer 203 has a plurality of second openings 204 therein, and the second openings 204 expose the top surface of the substrate 200, and the second openings 204 penetrate the second core layer 203 along the second direction Y.

[0049] In this embodiment, the method for forming the first core layer 201 and the second core layer 203 includes: forming a core material layer (not shown) on the substrate 200; forming a patterned layer (not shown) on the core material layer, the patterned layer exposing a portion of the top surface of the core material layer; etching the core material layer using the patterned layer as a mask until the top surface of the substrate 200 is exposed, thereby forming the first core layer 201 and the second core layer 203.

[0050] Please refer to Figure 5 After forming the first core layer 201 and the second core layer 203, a fin material layer 205 is formed on the side walls of the first opening 202, the second opening 204, the first core layer 201, the second core layer 203, and the top surfaces of the first core layer 201, the second core layer 203 and the substrate 200.

[0051] In this embodiment, the fin material layer 205 is formed by an atomic layer deposition process. In other embodiments, the fin material layer can also be formed by a chemical vapor deposition process or a physical vapor deposition process.

[0052] The core material layer is made of silicon or silicon nitride. In this embodiment, the core material layer is made of silicon nitride.

[0053] Please refer to Figure 6, back-etching the fin material layer 205 until the top surfaces of the first core layer 201, the second core layer 203 and the substrate 200 are exposed, thereby forming an initial first fin structure and an initial second fin structure; removing the fin material layer 205 located on the sidewall of the first core layer 201 to form the first fin structure 206; removing the fin material layer 205 located on the sidewall of the second core layer 203 to form the second fin structure 207.

[0054] In this embodiment, a first fin structure 206 is formed on the first region I. The first fin structure 206 includes a first fin and a second fin arranged in parallel along a first direction X, and a third fin and a fourth fin (not shown) arranged in parallel along a second direction Y. The third fin connects one end of the first fin and the second fin, and the fourth fin connects the other end of the first fin and the second fin. In this way, the volume of the first fin structure 206 is increased, so that the surface area of the first source and drain opening formed by etching the first fin structure 206 on both sides of the first gate structure is increased. When the surface area of the first source and drain opening is increased, the volume of the first source and drain doping layer formed in the first source and drain opening is also increased accordingly, thereby increasing the first source and drain ions doped in the first source and drain doping layer, thereby increasing the current between the first source and drain doping layers, and improving the performance of the semiconductor structure finally formed.

[0055] In this embodiment, the material of the first fin structure 206 and the second fin structure 207 is silicon; in other embodiments, the material of the first fin structure and the second fin structure may also be germanium, silicon germanium, silicon carbide, gallium arsenide or indium gallium.

[0056] Please refer to Figure 7 After forming the first fin structure 206 and the second fin structure 207 , the first core layer 201 and the second core layer 203 are removed.

[0057] In this embodiment, the material of the first core layer 201 is different from the material of the first fin structure 206; and the material of the second core layer 203 is different from the material of the second fin structure 207. During the removal of the first core layer 201 and the second core layer 203, the etching process has different etch selectivities for different materials, thereby reducing damage to the first fin structure 206 and the second fin structure 207.

[0058] In this embodiment, the first fin and the second fin have a first size L1 along the second direction Y, and the first size L1 ranges from 100 nm to 700 nm.

[0059] In this embodiment, the third fin and the fourth fin have a second size L2 along the first direction X, and the second size L2 ranges from 10 nm to 50 nm.

[0060] Please refer to Figure 8 , an isolation layer 219 is formed on the substrate 200 , wherein the isolation layer 219 covers a portion of the sidewall surface of the first fin structure 206 , and a top surface of the isolation layer 219 is lower than a top surface of the first fin structure 206 .

[0061] In this embodiment, the isolation layer 219 also covers a portion of the sidewalls of the second fin structure 207 , and a top surface of the isolation layer 219 is lower than a top surface of the second fin structure 207 .

[0062] The isolation layer 219 is made of an insulating material, which includes silicon oxide, silicon nitride, or silicon oxynitride. In this embodiment, the isolation layer 219 is made of silicon oxide.

[0063] After forming the isolation layer 219, the method further includes: forming a first gate structure on the substrate 200, wherein the first gate structure spans the first fin and the second fin along the first direction X, and the third fin and the fourth fin are respectively located on both sides of the first gate structure; forming a second gate structure on the substrate 200, wherein the second gate structure spans the second fin structure 207 and covers part of the sidewall and top surface of the second fin structure 207. For the specific formation process, please refer to Figures 9 to 14 .

[0064] Please refer to Figure 9 A first dummy gate structure 208 is formed on the substrate 200 . The first gate structure 208 spans the first fin and the second fin along the first direction X. The third fin and the fourth fin are respectively located on both sides of the first gate structure.

[0065] In this embodiment, the method further includes forming a second dummy gate structure 209 on the substrate 200 , wherein the second dummy gate structure 209 spans the second fin structure 207 and covers a portion of the sidewall and top surface of the second fin structure 207 .

[0066] In this embodiment, the first dummy gate structure 208 includes: a first dummy gate dielectric layer, the first dummy gate dielectric layer covers part of the sidewalls and top surface of the first fin, a first dummy gate layer located on the first dummy gate dielectric layer, and a first sidewall (not marked) located between the first dummy gate dielectric layer and the sidewalls of the first dummy gate layer; the second dummy gate structure 209 includes: a second dummy gate dielectric layer, the second dummy gate dielectric layer covers part of the sidewalls and top surface of the second fin, a second dummy gate layer located on the second dummy gate dielectric layer, and a second sidewall (not marked) located between the second dummy gate dielectric layer and the sidewalls of the second dummy gate layer.

[0067] In this embodiment, the material of the first dummy gate dielectric layer and the second dummy gate dielectric layer is silicon oxide; in other embodiments, the material of the first dummy gate dielectric layer and the second dummy gate dielectric layer may also be silicon oxynitride.

[0068] In this embodiment, the material of the first dummy gate layer and the second dummy gate layer is polysilicon.

[0069] In this embodiment, the first sidewall spacer and the second sidewall spacer are made of silicon nitride.

[0070] In this embodiment, the method for forming the first side wall and the second side wall includes: forming a side wall material layer (not shown) on the side wall surfaces of the first dummy gate dielectric layer, the second dummy gate dielectric layer, the first dummy gate layer and the first dummy gate layer, and the top surfaces of the first dummy gate layer, the second dummy gate layer and the initial isolation layer; and etching back the side wall material layer until the top surfaces of the first dummy gate layer, the second dummy gate layer and the initial isolation layer are exposed to form the first side wall and the second side wall.

[0071] In this embodiment, the process of forming the spacer material layer includes an atomic layer deposition process.

[0072] In this embodiment, the first dummy gate structure 208 and the second dummy gate structure 209 are formed simultaneously. The first dummy gate structure 208 and the second dummy gate structure 209 are formed simultaneously through a global process, which can effectively improve production efficiency.

[0073] Please refer to Figure 10 The first fin structure 206 is etched using the first dummy gate structure 208 as a mask to form a first source / drain opening 210 in the first fin structure 206 .

[0074] In this embodiment, the method further includes: etching the second fin structure 207 using the second dummy gate structure 209 as a mask to form the second source / drain opening 211 in the second fin structure 207 .

[0075] In this embodiment, the process of etching the first fin structure 206 and the second fin structure 207 adopts a wet etching process. Since the wet etching process has the isotropic characteristic, the first source and drain openings 210 and the second source and drain openings 211 formed therein have a "U"-shaped structure.

[0076] Please refer to Figure 11 After forming the first source-drain opening 210 , a first source-drain doping layer 212 is formed in the first source-drain opening 210 , wherein the first source-drain doping layer 212 has first source-drain ions.

[0077] In this embodiment, the method further includes forming a second source-drain doped layer 213 in the second source-drain opening 211 , wherein the second source-drain doped layer 213 has second source-drain ions.

[0078] In this embodiment, the method for forming the first source-drain doped layer 212 includes: forming a first epitaxial layer (not shown) in the first source-drain opening 210 by adopting an epitaxial growth process; in-situ doping the first epitaxial layer during the epitaxial growth process, and doping the first source-drain ions into the first epitaxial layer to form the first source-drain doped layer 212; the method for forming the second source-drain doped layer 213 includes: forming a second epitaxial layer (not shown) in the second source-drain opening 211 by adopting an epitaxial growth process; in-situ doping the second epitaxial layer during the epitaxial growth process, and doping the second source-drain ions into the second epitaxial layer to form the second source-drain doped layer 213.

[0079] The first source-drain ions include N-type ions or P-type ions; the second source-drain ions include N-type ions or P-type ions; the N-type ions include phosphorus or arsenic; the P-type ions include boron or indium.

[0080] In this embodiment, the first source and drain ions are N-type ions; the second source and drain ions are P-type ions.

[0081] Please refer to Figure 12 After forming the first source-drain doped layer 212 , a dielectric layer 214 is formed on the substrate 200 , and the dielectric layer 214 covers the sidewalls of the first dummy gate structure 208 .

[0082] In this embodiment, the dielectric layer 214 also covers the sidewalls of the second dummy gate structure 209 .

[0083] In this embodiment, the material of the dielectric layer 214 is silicon oxide; in other embodiments, the material of the dielectric layer can also be a low-K dielectric material (low-K dielectric material refers to a dielectric material with a relative dielectric constant lower than 3.9) or an ultra-low-K dielectric material (ultra-low-K dielectric material refers to a dielectric material with a relative dielectric constant lower than 2.5).

[0084] Please refer to Figure 13 After forming the dielectric layer 214 , the first dummy gate structure 208 is removed, and a first gate opening 215 is formed in the dielectric layer 214 .

[0085] In this embodiment, the process further includes: removing the second dummy gate structure 209 and forming a second gate opening 216 in the dielectric layer 214 .

[0086] In this embodiment, specifically, the first dummy gate dielectric layer and the first dummy gate layer of the first dummy gate structure 208 are removed; and the second dummy gate dielectric layer and the second dummy gate layer of the second dummy gate structure 209 are removed.

[0087] In this embodiment, the process of removing the first dummy gate structure 208 and the second dummy gate structure 209 is a wet etching process.

[0088] Please refer to Figure 14 After forming the first dummy gate opening 215 , a first gate structure 217 is formed in the first gate opening 215 .

[0089] In this embodiment, the method further includes forming a second gate structure 218 in the second gate opening 216 .

[0090] In this embodiment, the first gate structure 217 includes: a first gate dielectric layer and a first gate layer (not labeled) located on the first gate dielectric layer; the second gate structure 218 includes: a second gate dielectric layer and a second gate layer (not labeled) located on the second gate dielectric layer.

[0091] In this embodiment, the material of the first gate dielectric layer and the second gate dielectric layer includes a high-K dielectric material.

[0092] The material of the first gate layer and the second gate layer includes metal, and the metal includes tungsten, aluminum, copper, titanium, silver, gold, lead or nickel. In this embodiment, the material of the first gate layer and the second gate layer is tungsten.

[0093] In this embodiment, the first gate structure 217 has a first width dimension d1, and the second gate structure 218 has a second width dimension d2. The first width dimension d1 is greater than the second width dimension d2. The directions of the first width dimension d1 and the second width dimension d2 are along the second direction Y.

[0094] In this embodiment, the first width dimension d1 is greater than 50 nm. By setting the first width dimension d1 of the first dummy gate structure 214 to be greater than 50 nm, the length of the channel is increased, thereby reducing the influence of the channel effect.

[0095] Accordingly, an embodiment of the present invention further provides a semiconductor structure, please continue to refer to Figure 14 , comprising: a substrate 200, the substrate 200 including a first region I; a plurality of first fin structures 206 located on the first region I, the first fin structure 206 including a first fin and a second fin arranged in parallel along a first direction X, and a third fin and a fourth fin arranged in parallel along a second direction Y, the first direction X and the second direction Y being perpendicular, the third fin connecting one end of the first fin and the second fin, and the fourth fin connecting the other end of the first fin and the second fin; a first gate structure 217 located on the substrate 200, the first gate structure 217 spanning the first fin and the second fin along the first direction X, the third fin and the fourth fin being located on either side of the first gate structure, respectively; first source and drain openings 210 within the first fin structure 206 located on either side of the first gate structure 217; a first source and drain doping layer 212 located within the first source and drain opening 210, the first source and drain doping layer 212 having first source and drain ions therein.

[0096] A first fin structure 206 is formed on the first region I. The first fin structure 206 includes a first fin and a second fin arranged in parallel along a first direction X, and a third fin and a fourth fin arranged in parallel along a second direction Y. The first direction X is perpendicular to the second direction Y. The third fin connects one end of the first fin and the second fin, and the fourth fin connects the other end of the first fin and the second fin. This increases the volume of the first fin structure 206, thereby increasing the surface area of the first source-drain opening 210 formed by etching the first fin structure 206 on both sides of the first gate structure 27. When the surface area of the first source-drain opening 210 increases, the volume of the first source-drain doped layer 212 formed in the first source-drain opening 210 also increases accordingly, thereby increasing the first source-drain ions doped into the first source-drain doped layer 212, thereby increasing the current between the first source-drain doped layer 212 and improving the performance of the ultimately formed semiconductor structure.

[0097] In this embodiment, the first fin and the second fin have a first size L1 along the second direction Y, and the first size L1 ranges from 100 nm to 700 nm.

[0098] In this embodiment, the third fin and the fourth fin have a second size L2 along the first direction X, and the second size L2 ranges from 10 nm to 50 nm.

[0099] In this embodiment, the first source-drain ions include: N-type ions or P-type ions; the N-type ions include: phosphorus or arsenic; the P-type ions include: boron or indium.

[0100] In this embodiment, the substrate 200 further includes a second region II, and the first region I and the second region II are arranged in parallel along the first direction X.

[0101] In this embodiment, the present invention further includes: a plurality of second fin structures 207 located on the second region II and arranged in parallel along the first direction X.

[0102] In this embodiment, the second gate structure 218 is further included on the substrate 200 . The second gate structure 218 spans the second fin structure 207 and covers a portion of the sidewall and top surface of the second fin structure 207 .

[0103] In this embodiment, the first gate structure 217 has a first width dimension d1, and the second gate structure 218 has a second width dimension d2. The first width dimension d1 is greater than the second width dimension d2. The directions of the first width dimension d1 and the second width dimension d2 are along the second direction Y.

[0104] Although the present invention is disclosed as above, the present invention is not limited thereto. Any person skilled in the art can make various changes and modifications without departing from the spirit and scope of the present invention. Therefore, the scope of protection of the present invention should be based on the scope defined by the claims.

Claims

1. A semiconductor structure, characterized in that include: a substrate comprising a first region; a plurality of first fin structures located on the first region, the first fin structures comprising a first fin and a second fin arranged in parallel along a first direction, and a third fin and a fourth fin arranged in parallel along a second direction, the first direction being perpendicular to the second direction, the third fin connecting one end portion of the first fin and the second fin, and the fourth fin connecting the other end portion of the first fin and the second fin; a first gate structure located on the substrate, the first gate structure spanning the first fin and the second fin along the first direction, the third fin and the fourth fin being located on either side of the first gate structure, respectively; first source and drain openings in the first fin structure located on both sides of the first gate structure; A first source-drain doped layer located in the first source-drain opening, wherein the first source-drain doped layer has first source-drain ions; wherein, The method for forming the first fin structure includes: forming a first core layer on the first region, wherein the first core layer has a plurality of first openings, and the first openings expose the top surface of the substrate; forming a fin material layer on the sidewalls of the first openings and the first core layer, and on the top surface of the first core layer and the substrate; etching back the fin material layer until the first core layer and the top surface of the substrate are exposed to form an initial first fin structure; and removing the fin material layer located on the sidewalls of the first core layer to form the first fin structure.

2. The semiconductor structure according to claim 1, wherein The first fin and the second fin have a first size along the second direction, and the first size ranges from 100 nm to 700 nm.

3. The semiconductor structure according to claim 1, wherein: The third fin and the fourth fin have a second size along the first direction, and the second size ranges from 10 nm to 50 nm.

4. The semiconductor structure according to claim 1, wherein: The first source-drain ions include: N-type ions or P-type ions; the N-type ions include: phosphorus or arsenic; the P-type ions include: boron or indium.

5. The semiconductor structure according to claim 1, wherein The substrate further includes a second region, and the first region and the second region are arranged in parallel along the first direction.

6. The semiconductor structure according to claim 5, wherein: Also includes: A plurality of second fin structures are located on the second region and arranged in parallel along the first direction.

7. The semiconductor structure according to claim 6, wherein: Also includes: A second gate structure is located on the substrate, the second gate structure spans the second fin structure, and the second gate structure covers a portion of the sidewall and a top surface of the second fin structure.

8. The semiconductor structure according to claim 7, wherein: The first gate structure has a first width dimension, and the second gate structure has a second width dimension, the first width dimension is greater than the second width dimension, and directions of the first width dimension and the second width dimension are along the second direction.

9. A method for forming a semiconductor structure, characterized in that: include: providing a substrate, the substrate comprising a first region; forming a plurality of first fin structures on the first region, the first fin structures comprising a first fin and a second fin arranged in parallel along a first direction, and a third fin and a fourth fin arranged in parallel along a second direction, the first direction being perpendicular to the second direction, the third fin connecting one end portion of the first fin and the second fin, and the fourth fin connecting the other end portion of the first fin and the second fin; forming a first gate structure on the substrate, wherein the first gate structure spans the first fin and the second fin along the first direction, and the third fin and the fourth fin are respectively located on both sides of the first gate structure; forming first source and drain openings in the first fin structure on both sides of the first gate structure; A first source-drain doped layer is formed in the first source-drain opening, wherein the first source-drain doped layer contains first source-drain ions; wherein, The method for forming the first fin structure includes: forming a first core layer on the first region, wherein the first core layer has a plurality of first openings, and the first openings expose the top surface of the substrate; forming a fin material layer on the sidewalls of the first openings and the first core layer, and on the top surface of the first core layer and the substrate; etching back the fin material layer until the first core layer and the top surface of the substrate are exposed to form an initial first fin structure; and removing the fin material layer located on the sidewalls of the first core layer to form the first fin structure.

10. The method for forming a semiconductor structure according to claim 9, wherein: The substrate further includes a second region, and the first region and the second region are arranged in parallel along the first direction.

11. The method for forming a semiconductor structure according to claim 10, wherein: The process of forming the first fin structure further includes: forming a plurality of second fin structures arranged in parallel along the first direction on the second region.

12. The method for forming a semiconductor structure according to claim 11, wherein: The method for forming the first fin structure and the second fin structure includes: forming a first core layer on the first area, the first core layer having a plurality of first openings therein, the first openings exposing the top surface of the substrate; forming a second core layer on the second area, the second core layer having a plurality of second openings therein, the second openings exposing the top surface of the substrate, and the second openings penetrating the second core layer along the second direction; forming a fin material layer on the sidewalls of the first opening, the second opening, the first core layer, the second core layer, and the top surfaces of the first core layer, the second core layer and the substrate; etching back the fin material layer until the first core layer, the second core layer and the top surfaces of the substrate are exposed to form an initial first fin structure and an initial second fin structure; removing the fin material layer located on the sidewalls of the first core layer to form the first fin structure; removing the fin material layer located on the sidewalls of the second core layer to form the second fin structure.

13. The method for forming a semiconductor structure according to claim 12, wherein: The process of forming the fin material layer includes an atomic layer deposition process.

14. The method for forming a semiconductor structure according to claim 12, wherein: The method for forming the first core layer and the second core layer includes: forming a core material layer on the substrate; forming a patterned layer on the core material layer, wherein the patterned layer exposes a portion of the top surface of the core material layer; etching the core material layer using the patterned layer as a mask until the top surface of the substrate is exposed, thereby forming the first core layer and the second core layer.

15. The method for forming a semiconductor structure according to claim 12, wherein: A material of the first core layer is different from a material of the first fin structure; a material of the second core layer is different from a material of the second fin structure.

16. The method for forming a semiconductor structure according to claim 14, wherein: The core material layer is made of silicon or silicon nitride.

17. The method for forming a semiconductor structure according to claim 12, wherein: After forming the first fin structure and the second fin structure, the method further includes removing the first core layer and the second core layer.

18. The method for forming a semiconductor structure according to claim 9, wherein: The first fin and the second fin have a first size along the second direction, and the first size ranges from 100 nm to 700 nm.

19. The method for forming a semiconductor structure according to claim 9, wherein: The third fin and the fourth fin have a second size along the first direction, and the second size ranges from 10 nm to 50 nm.

20. The method for forming a semiconductor structure according to claim 11, wherein: The process of forming the first gate structure also includes: forming a second gate structure on the substrate, wherein the second gate structure spans the second fin structure and covers a portion of the sidewall and top surface of the second fin structure.

21. The method for forming a semiconductor structure according to claim 20, wherein: The first gate structure has a first width dimension, and the second gate structure has a second width dimension, the first width dimension is greater than the second width dimension, and directions of the first width dimension and the second width dimension are along the second direction.

22. The method for forming a semiconductor structure according to claim 9, wherein: Before forming the first gate structure, the method further includes: forming a first dummy gate structure on the substrate, wherein the first gate structure spans the first fin and the second fin along the first direction, and the third fin and the fourth fin are respectively located on both sides of the first gate structure.

23. The method for forming a semiconductor structure according to claim 22, wherein: The method for forming first source-drain openings in the first fin structure on both sides of the first gate structure includes: etching the first fin structure using the first dummy gate structure as a mask to form the first source-drain openings.

24. The method for forming a semiconductor structure according to claim 9, wherein: The method for forming the first source-drain doped layer includes: forming a first epitaxial layer in the first source-drain opening using an epitaxial growth process; in-situ doping the first epitaxial layer during the epitaxial growth process, doping the first source-drain ions into the epitaxial layer to form the first source-drain doped layer.

25. The method for forming a semiconductor structure according to claim 9, wherein: The first source-drain ions include: N-type ions or P-type ions; the N-type ions include: phosphorus or arsenic; the P-type ions include: boron or indium.

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