Memory

Abstract

The present invention provides a memory. By making the width dimension of the first bit line located at the edge position in the bit line group larger than that of the second bit lines arranged therein, when preparing the bit line group, not only can the morphology of the first bit line be ensured, but also, under the blocking protection of the first bit line with a larger width, the morphology accuracy of the second bit lines can be improved, which is beneficial to improving the device performance of the formed memory.

Description

[0001] This patent application is a divisional application of an application with the application number 2020100726305, the application date of January 21, 2020, and the invention title of "Memory and Method for Forming the Same". Technical Field

[0002] The present invention relates to the field of semiconductor technology, and particularly to a memory. Background Art

[0003] A memory, such as a Dynamic Random Access Memory (DRAM), generally has a memory cell array, which includes a plurality of memory cells arranged in an array. In addition, the memory also has a plurality of bit lines, each bit line is electrically connected to a corresponding memory cell respectively, and the memory further includes a storage capacitor for storing charges representing stored information, and the memory cell can be electrically connected to the storage capacitor through a node contact portion, so as to realize the storage function of each memory cell.

[0004] Currently, a method for forming a memory generally includes: forming a bit line group, and using the bit line group to define a node contact window, and then a conductive material can be filled in the node contact window to form a node contact portion.

[0005] However, when preparing the bit line group, the graphic morphology of the bit lines at the edge positions is extremely likely to be deformed (for example, the bit lines at the edge positions are easily eroded in large amounts, resulting in the reduction of their morphology), which will not only have an adverse impact on the performance of the bit lines, leading to poor stability of the finally formed semiconductor device, but also cause abnormal morphology of the defined node contact window, and further affect the quality of the finally formed node contact portion. Similarly, when preparing the node contact portion, the node contact portions at the edge positions also have the problem that their graphic morphology is easily deformed. Summary of the Invention

[0006] The purpose of the present invention is to provide a memory to solve the problem that the bit lines and node contact portions at the edge positions of the existing memory are prone to abnormal morphology, thus affecting the performance of the memory.

[0007] To solve the above technical problems, the present invention provides a memory, comprising: a substrate, on which a memory region and a peripheral region are defined, and the peripheral region is located outside the memory region; a bit line group formed in the memory region of the substrate, the bit line group including a plurality of bit lines extending along a predetermined direction, and a bit line arranged at an edge position in the bit line group constitutes a first bit line, and a bit line in the bit line group located on a side of the first bit line away from the peripheral region constitutes a second bit line, and a width dimension of the first bit line is greater than a width dimension of the second bit line; and a plurality of node contact portions, each node contact portion of the plurality of node contact portions is at least partially located on one side of the bit line, and a node contact portion arranged at an edge position in the plurality of node contact portions constitutes a first contact portion, and a node contact portion in the plurality of node contact portions located on a side of the first contact portion away from the peripheral region constitutes a second contact portion, and a bottom of the second contact portion is lower than a bottom of the first contact portion.

[0008] Optionally, the first contact portion includes an insulating contact post formed on the substrate, and a top of the insulating contact post is lower than a top of the second contact portion.

[0009] Optionally, the first contact portion further includes a first electrical conduction layer covering a top surface of the insulating contact post.

[0010] Optionally, a portion of the second contact portion has a material different from that of the first contact portion.

[0011] Optionally, the second contact portion includes a conductive contact layer formed on the substrate and at least partially embedded in the substrate.

[0012] Optionally, the second contact portion further includes a second electrical conduction layer formed above the conductive contact layer.

[0013] Optionally, a bottom of the second contact portion is embedded in the substrate, and a bottom surface of the first contact portion stops at a top surface of the substrate.

[0014] Optionally, the memory further includes: an isolation layer covering a top surface of the bit line. Wherein, a portion of the isolation layer covering the first bit line constitutes a first isolation portion, and the first contact portion also extends laterally onto the first isolation portion, so that a maximum width dimension of the first contact portion is greater than a maximum width dimension of the second contact portion.

[0015] Optionally, an active region array is formed in the memory region, the first contact portion is electrically insulated from an active region below it, and the second contact portion is electrically connected to an active region below it.

[0016] Optionally, a trench isolation structure is formed in the substrate of the peripheral region, and a third contact portion is further disposed on the substrate of the peripheral region, and the third contact portion is formed on the trench isolation structure.

[0017] In the memory provided by the present invention, the width dimension of the first bit line located at the edge position in the bit line group is larger than the width dimension of the second bit line arranged therein, so that the topography of the first bit line located at the edge position can be effectively guaranteed, and under the blocking protection of the first bit line with a larger width, the second bit line arranged therein can be further prevented from being eroded in large quantities, improving the topography accuracy of the second bit line, and further being beneficial to improving the device performance of the formed memory. Description of the Drawings

[0018] Figure 1 FIG. is a layout structure diagram of a bit line group of the memory in Embodiment 1 of the present invention;

[0019] Figure 2a FIG. is a cross-sectional schematic diagram of the memory in Embodiment 1 of the present invention, which forms a bit line group;

[0020] Figure 2b FIG. is a cross-sectional schematic diagram of the memory in Embodiment 1 of the present invention, which forms a node contact portion;

[0021] Figure 2c FIG. is a cross-sectional schematic diagram of the memory in Embodiment 1 of the present invention, which forms a spacer insulating layer;

[0022] Figure 3 FIG. is a flow schematic diagram of a forming method of the memory in Embodiment 1 of the present invention;

[0023] Figures 4a to 4e FIG. is a schematic structural diagram of the memory in Embodiment 1 of the present invention during its preparation process;

[0024] Figure 5 FIG. is a cross-sectional schematic diagram of the memory in Embodiment 2 of the present invention.

[0025] Among them, the reference numerals are as follows:

[0026] 100 - Substrate;

[0027] 100A - Memory region;

[0028] 100B - Peripheral region;

[0029] 110 - First trench isolation structure;

[0030] 120 - Second trench isolation structure;

[0031] 200 - Bit line group;

[0032] 200a - First bit - line conductive layer;

[0033] 200b - Second bit - line conductive layer;

[0034] 200c - Third bit - line conductive layer;

[0035] 200d - Bit - line shielding layer;

[0036] 200e - Isolation sidewall;

[0037] 210 - First bit - line;

[0038] 220 - Second bit - line;

[0039] 310 - First isolation part;

[0040] 320 - Second isolation part;

[0041] 400a - First conductive material layer;

[0042] 400b - Second conductive material layer;

[0043] 410 - First contact part;

[0044] 410a - Insulating contact post;

[0045] 410b - First electrical conduction layer;

[0046] 420 - Second contact part;

[0047] 420a - Conductive contact layer;

[0048] 420b - Second electrical conduction layer;

[0049] 430 - Third contact part;

[0050] 430a - Insulating post;

[0051] 430b - Third electrical conduction layer;

[0052] 440 - Fourth contact part;

[0053] 510 - First contact window;

[0054] 520 - Second contact window;

[0055] 600 - Insulating dielectric layer;

[0056] 710 - First pattern;

[0057] 720 - Second pattern;

[0058] 800 - Separation line;

[0059] AA1 - The first active region;

[0060] AA2 - The second active region. Detailed Description of the Invention

[0061] The following further elaborates on the memory proposed by the present invention in conjunction with the accompanying drawings and specific embodiments. According to the following description, the advantages and features of the present invention will be clearer. It should be noted that the accompanying drawings are all in a very simplified form and use non-precise scales, only for conveniently and clearly assisting in explaining the purpose of the embodiments of the present invention.

[0062] Figure 1 The layout structure of the bit line group is schematically shown for the memory in Embodiment 1 of the present invention. Figure 2a The cross-sectional schematic diagram of the memory in Embodiment 1 of the present invention with a bit line group formed therein. Figure 2b The cross-sectional schematic diagram of the memory in Embodiment 1 of the present invention with a node contact portion formed therein.

[0063] Combined Figure 1 and Figures 2a to 2b As shown, the memory includes: a substrate 100, a bit line group 200 formed on the substrate 100, and a plurality of node contact portions.

[0064] Specifically, a plurality of active regions are formed in the substrate 100. The plurality of active regions are arranged in an array, for example, to form an active region array. Among them, adjacent active regions can be separated from each other by a first trench isolation structure 110, for example. And memory cells are formed on the active regions based on the active regions. Among them, the active regions arranged at the edge positions in the active region array constitute the first active region AA1, and the active regions surrounded by the first active region AA1 in the active region array constitute the second active region AA2.

[0065] It should be noted that due to the limitations of the existing semiconductor manufacturing process, it is easy to cause the active regions arranged at the edge positions in the formed active region array (for example, the first active region AA1) to have lower quality. If memory cells are further fabricated on the low-quality active regions, the device performance of the memory cells formed based on the active regions at the edge positions will be affected, resulting in the need to scrap the memory cells with performance defects. At this time, it will inevitably lead to waste of costs.

[0066] Based on this, in this embodiment, at least the active regions located at the edge positions can be defined as non-functional active regions, and the non-functional active regions are not used to form memory cells. That is, the non-functional active regions include the first active region AA1. And at least part of the second active region AA2 surrounded by the first active region AA1 is defined as a functional active region for forming memory cells.

[0067] Continue to refer to Figure 2a As shown, in this embodiment, a memory region 100A and a peripheral region 100B located outside the memory region 100A are defined on the substrate 100, and the active region array is formed in the memory region 100A. Among them, a trench isolation structure (i.e., the second trench isolation structure 120) is formed in the region where the peripheral region 100B is connected to the memory region 100A, so that the semiconductor devices in the memory region 100A and the semiconductor devices in the peripheral region 100B are isolated from each other. It should be recognized that the first active region AA1 arranged at the edge position in the active region array is correspondingly close to the peripheral region 100B.

[0068] Based on this, it can be considered that the active region closest to the peripheral region 100B in the active region array constitutes the first active region AA1, and the active regions in the active region array located on the side away from the peripheral region 100B of the first active region AA constitute the second active region AA2.

[0069] Continue to refer to Figure 1 and Figure 2a As shown, the bit line group 200 is formed on the substrate 100. The bit line group 200 includes a plurality of bit lines extending along a predetermined direction. And, the bit lines arranged at the edge position in the bit line group 200 constitute the first bit line 210, and the bit lines in the bit line group 200 located on the side away from the peripheral region 100B of the first bit line 210 constitute the second bit line 220. In this embodiment, the first bit line 210 intersects with the first active region AA1 in the active region array, and the second bit line 220 intersects with the second active region AA2 in the active region array.

[0070] Furthermore, the width dimension of the first bit line 210 is greater than the width dimension of the second bit line 220. It should be noted that compared with the circuit layout density of the bit lines in the middle region, the circuit layout density of the bit lines in the edge region (including the first bit line 210) is relatively sparse. Therefore, when performing the patterning process to form the bit line group 200, the first bit line 210 located at the edge position is more likely to be subjected to a larger etching attack compared to the second bit line 220 arranged inside. Based on this, in this embodiment, the width dimension of the first bit line 210 is made greater than the width dimension of the second bit line 220. In this way, even when preparing the bit line group 200, the first bit line 210 is subjected to a larger etching attack, and the morphology of the first bit line 210 can still be guaranteed. And, under the blocking protection of the first bit line 210 with a larger width dimension, the problem of excessive erosion of the second bit line 220 adjacent to the first bit line 210 can also be effectively alleviated.

[0071] In this embodiment, the first bit line 210 intersects with the first active region AA1. As described above, the first active region AA1 is a non-functional active region. Therefore, the first bit line 210 is also used to form a non-functional bit line, for example. Based on this, the adjustment of the width dimension of the first bit line 210 will be more flexible. For example, the width dimension D1 of the first bit line 210 can be made greater than 1 time the width dimension D2 of the second bit line 220 and less than or equal to 2 times the width dimension D2 of the second bit line 220 (i.e., D2 < D1 ≤ 2*D2).

[0072] Continue to refer to Figure 2a As shown, each bit line in the bit line group 200 includes a first bit line conductive layer 200a, a second bit line conductive layer 200b, and a third bit line conductive layer 200c that are stacked in sequence. Among them, the material of the first bit line conductive layer 200a includes doped polysilicon, for example, the material of the second bit line conductive layer 200b includes titanium nitride, and the material of the third bit line conductive layer 200c includes tungsten, for example.

[0073] Furthermore, each bit line in the bit line group 200 may further include a bit line mask layer 200d and an isolation sidewall 200e. Among them, the bit line mask layer 200d is formed above the bit line conductive layers stacked in sequence, and the isolation sidewall 200e covers at least the sidewalls of the bit line conductive layers stacked in sequence and the sidewalls of the bit line mask layer 200d.

[0074] Continue to refer to Figure 2a As shown, adjacent bit lines can further define a node contact window for accommodating a node contact portion. Among them, the bottom of at least a part of the node contact window can further extend into the substrate 100. In a specific embodiment, for example, a plurality of dividing lines (not shown in the figure) are further formed on the substrate 100. The extending direction of the dividing lines and the extending direction of the bit lines are perpendicular to each other, for example, so that the dividing lines and the bit lines intersect to surround the node contact window.

[0075] As described above, adjacent bit lines can further define node contact windows. At this time, multiple node contact windows can be defined based on multiple bit lines in the bit line group 200. The multiple node contact windows are, for example, arranged in an array to form a node contact window array. Among them, the node contact windows arranged at the edge position in the node contact window array constitute the first contact window 510, that is, the first contact window 510 is closer to the peripheral region 100B; and, the node contact windows on the side of the node contact window array away from the peripheral region 100B with respect to the first contact window 510 constitute the second contact window 520 (it can be considered that the node contact windows surrounded by the first contact window 510 in the node contact window array constitute the second contact window 520). In this embodiment, the first contact window 510 is defined by the first bit line 210 and the adjacent second bit line 220, and the second contact window 520 is defined by the adjacent second bit line 220. At this time, the first contact window 510 is correspondingly located on the side of the first bit line 210 close to the second bit line 220.

[0076] In this embodiment, in the node contact window array, the bottom of the second contact window 520 further extends into the substrate 100, so that the bottom of the second contact portion 420 filled in the second contact window 520 is embedded in the substrate 100. And, the bottom of the first contact window 510 stops at the top surface of the substrate 100, and thus does not extend into the substrate 100, so that the bottom surface of the first contact portion 410 filled in the first contact window 510 stops at the top surface of the substrate 100 and is not embedded in the substrate 100.

[0077] Next, referring to Figure 2b As shown, the memory further includes an isolation layer that covers the top surface of the bit lines. In this embodiment, the isolation layer correspondingly covers the bit line shielding layer 200d of the bit lines. As described above, adjacent bit lines are used to define node contact windows. At this time, it can be considered that the height of the node contact windows can be further increased by using the isolation layer above the bit lines. Specifically, the isolation layer includes a first isolation portion 310 and a second isolation portion 320. Among them, the first isolation portion 310 covers the first bit line 210, and the second isolation portion 320 covers the second bit line 220.

[0078] Continuing to refer to Figure 2bAs shown, the node contact portion among the multiple node contact portions fills the node contact window. In this embodiment, the multiple node contact portions can be correspondingly arranged in an array to form a node contact portion array. Further, at least a part of the node contact portion is correspondingly located on the side of the bit line. Among them, in the node contact portion array, the node contact portion filled in the first contact window 510 forms the first contact portion 410, and the node contact portion filled in the second contact window 520 forms the second contact portion 420.

[0079] It can also be understood that correspondingly to the node contact window array, the node contact portions arranged at the edge positions in the node contact portion array form the first contact portion 410, and the node contact portions in the node contact portion array that are located on the side of the first contact portion 410 away from the peripheral region 100B form the second contact portion 420. In this embodiment, a part of the first contact portion 410 is located on the side of the first bit line 210 close to the second bit line 220, so that a part of the first contact portion 410 is located between the first bit line 210 and the adjacent second bit line 220, and the second contact portion 420 is located between the adjacent second bit lines 220.

[0080] Furthermore, the top position of each node contact portion is further higher than the top position of the node contact window. Among them, the top of the first contact portion 410 also extends horizontally onto the first isolation portion 310, so that the maximum width dimension of the first contact portion 410 is greater than the maximum width dimension of the second contact portion 420. In this embodiment, the top of the first contact portion 410 extends towards the direction away from the second bit line 220 onto the first isolation portion 310 to at least partially cover the first isolation portion 310.

[0081] Continue to refer to Figure 2b As shown, in this embodiment, the thickness of the part of the first isolation portion 310 covering the lower part of the first contact portion 410 is greater than the thickness of the second isolation portion 320. That is, the first isolation portion 310 has a part with a thickness greater than that of the second isolation portion 320, and the part of the first isolation portion 310 with a larger thickness is located in the space surrounded by the first bit line 210 and the first contact portion 410. In this embodiment, the part of the first isolation portion 310 covered by the first contact portion 410 is defined as the first part, and the part of the first isolation portion 310 not covered by the first contact portion 410 is defined as the second part.

[0082] Further, the thickness of the second portion of the first isolation portion 310 that is not covered by the first contact portion 410 may be the same as or similar to the thickness of the second isolation portion 320. That is, in this embodiment, the thickness of the first portion of the first isolation portion 310 that is close to the first contact portion 410 and covered by the first contact portion 410 is larger, and the thickness of the second portion of the first isolation portion 310 that is far from the first contact portion 410 and not covered by the first contact portion 410 is smaller, so that the first isolation portion 310 has a stepped structure.

[0083] In this embodiment, the first contact portion 410 may also be defined as a non-functional contact portion. At this time, there may be no electrical transmission between the first contact portion 410 and the active region below it. Specifically, at least part of the first contact portion 410 may be formed on the first active region AA1, and there is no electrical transmission between the at least part of the first contact portion 410 and the first active region AA1. Also, the second contact portion 420 may be defined as a functional contact portion, and the second contact portion 420 is formed on the second active region AA2, so that the bottom of the second contact portion 420 contacts the second active region AA2 and there is electrical transmission between the second contact portion 420 and the second active region AA2.

[0084] Specifically, the first contact portion 410 includes an insulating contact post 410a. The insulating contact post 410a fills the first contact window 510 and is electrically insulated from the mutually contacting active regions. Also, the insulating contact post 410a of the first contact portion 410 is located on the side of the first bit line 210 close to the second bit line 220, so that the insulating contact post 410a is located between the first bit line 210 and the adjacent second bit line 220. Among them, the insulating contact post 410a and the first isolation portion 310 are arranged adjacent to each other, and the top surface of the insulating contact post 410a is flush with the top surface of the first isolation portion 310.

[0085] In this embodiment, the first contact portion 410 further includes a first electrical conduction layer 410b. The first electrical conduction layer 410b covers the top surface of the insulating contact post 410a and extends laterally onto the first isolation portion 310, so that the first electrical conduction layer 410b has a larger width dimension. In this embodiment, the first electrical conduction layer 410b of the first contact portion 410 extends onto the first isolation portion 310 in a direction away from the second bit line 220.

[0086] Continue to refer to Figure 2bAs shown, the second contact portion 420 includes a conductive contact layer 420a. The conductive contact layer 420a fills the second contact window 520 to be electrically connected to the second active region AA2. Among them, the top position of the conductive contact layer 420a is lower than the top position of the bit line, that is, the top position of the conductive contact layer 420a is lower than the top position of the second contact window 520. At this time, the top position of the conductive contact layer 420a in the second contact portion 420 is correspondingly lower than the top position of the insulating contact post 410a in the first contact portion 410.

[0087] Furthermore, the second contact portion 420 further includes a second electrical conduction layer 420b. The second electrical conduction layer 420b fills the second contact window and is formed on the conductive contact portion 420a to be electrically connected to the conductive contact portion 420a. And, the top position of the second electrical conduction layer 420b is also higher than the top position of the second contact window 520, that is, the top surface of the second electrical conduction layer 420b is higher than the top surface of the second isolation portion 320.

[0088] As described above, the first electrical conduction layer 410b also extends laterally onto the first isolation portion 310, so that the first electrical conduction layer 410b has a relatively large width dimension. Correspondingly, the width dimension of the first electrical conduction layer 410b in the first contact portion 410 is greater than the width dimension of the second electrical conduction layer 420b in the second contact portion 420.

[0089] In this embodiment, the top surface of the conductive contact post 420a of the second contact portion 420 is lower than the top surface of the second isolation portion 320, and the top surface of the insulating contact post 410a of the first contact portion 410 is higher than the top surface of the second isolation portion 320; and, the second electrical conduction layer 420b in the second contact portion 420 is formed on the conductive contact layer 420a and extends upward along the height direction, so that the top surface of the second electrical conduction layer 420b in the second contact portion 420 is flush with the top surface of the first electrical conduction layer 410b in the first contact portion 410. Optionally, the first electrical conduction layer 410b and the second electrical conduction layer 420b are made of the same material, for example, both include a first conductive material layer and a second conductive material layer.

[0090] Continue to refer to Figure 2bAs shown, in the first electrical conduction layer 410b, the first conductive material layer and the second conductive material layer are sequentially stacked on the insulating contact post 410a and the first isolation part 310 in an up-and-down manner. In the second electrical conduction layer 420b, the first conductive material layer is formed between the conductive contact layer 420a and the second conductive material layer, and the first conductive material layer surrounds the bottom surface and at least part of the side wall of the second conductive material layer.

[0091] Among them, the first electrical conduction layer 410b in the first contact part 410 and the second electrical conduction layer 420b in the second contact part 420 can be formed simultaneously based on the same electrical conduction material layer by using a patterning process. The forming methods of the first electrical conduction layer 410b and the second electrical conduction layer 420b will be described in detail below.

[0092] It should be noted that when the first electrical conduction layer 410b and the second electrical conduction layer 420b are formed based on the patterning process, for the first electrical conduction layer 410b located at the edge position, for example, it will be subjected to a relatively large etching attack, which may cause the first electrical conduction layer 410b to be easily eroded in large quantities and deformed. Based on this, in this embodiment, the width dimension of the first electrical conduction layer 410b is made larger than the width dimension of the second electrical conduction layer 420b. In this way, even if the first electrical conduction layer 410b is subjected to a relatively large etching attack, the morphology of the first electrical conduction layer 410b can still be guaranteed. Moreover, under the blocking and protection of the first electrical conduction layer 410b with a larger width dimension, the problem that the second electrical conduction layer 420b adjacent to the first electrical conduction layer 410b is overly eroded can also be effectively alleviated.

[0093] Continue to refer to Figure 2b As shown, in this embodiment, the first contact part 410 located at the edge position is at least arranged on one side of the first bit line 210 close to the second bit line 220, and an insulating dielectric layer 600 is also formed on the side of the first bit line 210 far from the second bit line 220. In this embodiment, the isolation layer also extends to cover the insulating dielectric layer 600. It can be considered that the part of the isolation layer extending to cover the insulating dielectric layer 600 constitutes the third isolation part.

[0094] As described above, the top of the second contact part 420 extends upward and is higher than the top surface of the second isolation part 320, and the first contact part 410 is also higher than the second isolation part 320 and also covers the first part of the first isolation part 310, and the side wall of the first part of the first isolation part 310 is connected to the top surface of the second part of the first isolation part 310 to present a stepped structure.

[0095] Based on this, specifically refer to Figure 2cAs shown, in this embodiment, the memory further includes a spacer insulating layer formed on the isolation layer. The material of the spacer insulating layer includes, for example, silicon nitride. Further, the portion of the spacer insulating layer formed on the first isolation portion 310 constitutes a spacer sidewall 910, and the portion of the spacer insulating layer formed on the second isolation portion 320 constitutes a spacer filling portion 920.

[0096] Specifically, the spacer filling portion 920 fills between adjacent second contact portions 420, and also fills between the first contact portion 410 and the second contact portion 420. Also, the spacer sidewall 910 is formed on the top surface of the second part of the first isolation portion 310 and covers the sidewall of the first part of the first isolation portion 310.

[0097] In an alternative solution, the spacer insulating layer does not cover the third isolation portion of the isolation layer, that is, the third isolation portion is exposed from the spacer insulating layer, and the top surface of the third isolation portion is further lower than the top surface of the second part of the first isolation portion. At this time, the top surface of the third isolation portion is correspondingly lower than the top surface of the second isolation portion.

[0098] Specific reference Figure 2c As shown, in this embodiment, the top surface of the insulating contact post 410a is flush with the top surface of the first part of the first isolation portion 310. For example, the top position of the insulating contact post 410a and the top position of the first part of the first isolation portion 310 are both located at the first height position H1; the top surface of the second part of the first isolation portion 310 may be flush with the top surface of the second isolation portion 320. For example, the top position of the second part of the first isolation portion 310 and the top position of the second isolation portion 320 are both located at the second height position H2; and the top surface of the third isolation portion is more sunken relative to the top surfaces of the second isolation portion 320 and the second part of the first isolation portion 320. For example, the top position of the third isolation portion is located at the third height position H3. Among them, the first height position H1 is higher than the second height position H2, and the second height position H2 is higher than the third height position H3.

[0099] Next, in conjunction with the attached Figure 3 and Figures 4a to 4e The method for forming the memory as described above in this embodiment will be described in detail. Among them, Figure 3 is a schematic flow chart of the method for forming the memory in the first embodiment of the present invention, Figures 4a to 4e is a schematic structural diagram of the memory in the first embodiment of the present invention during its preparation process.

[0100] In step S100, specifically refer to Figure 4aAs shown, a substrate 100 is provided. A memory region 100A and a peripheral region 100B are defined on the substrate 100, and the peripheral region 100B is located outside the memory region 100A.

[0101] Specifically, an active region array is formed in the memory region 100A of the substrate 100. As described above, the active region array includes a plurality of active regions arranged in an array, and adjacent active regions can be separated from each other by, for example, a first trench isolation structure 110. Among them, the active regions arranged at the edge positions in the active region array constitute a first active region AA1, and the active regions in the active region array located on the side of the first active region AA1 away from the peripheral region constitute a second active region AA2.

[0102] In this embodiment, the active regions located at the edge positions can be defined as non-functional active regions, and the non-functional active regions are not used to form memory cells. That is, the non-functional active regions include the first active region AA1. And, at least part of the second active region AA2 surrounded by the first active region AA1 is defined as a functional active region for forming memory cells.

[0103] Furthermore, a second trench isolation structure 120 can also be formed in the substrate outside the active region array, so that the active region array in the memory region 100A can be isolated from the devices in the peripheral region 100B.

[0104] In step S200, continue to refer to Figure 4a As shown, a bit line group is formed in the memory region 100A of the substrate 100. The bit line group includes a plurality of bit lines extending along a predetermined direction, and the bit lines arranged at the edge positions in the bit line group constitute a first bit line 210, and the bit lines in the bit line group located on the side of the first bit line 210 away from the peripheral region 100B constitute a second bit line 220, and the width dimension of the first bit line 210 is greater than the width dimension of the second bit line 220.

[0105] Specifically, the method for forming the bit line group includes, for example: first, forming a bit line material layer on the substrate 100; then, patterning the bit line material layer to form the bit line group.

[0106] Among them, when performing a patterning process to form a bit line group, since the first bit line 210 with a relatively large width dimension can be formed at the outermost edge position, even if the first bit line 210 located at the edge position is subject to a relatively large etching attack, the morphology of the formed first bit line 210 can still be ensured; moreover, under the blocking and protection of the first bit line 210 with a relatively large width, the second bit line 220 surrounded by the first bit line 210 can be effectively protected from a relatively large etching attack, ensuring the morphology of the formed second bit line 220. In this way, when using the second bit line 220 to form a functional bit line, the device performance of the corresponding memory cell can be correspondingly ensured.

[0107] Continue to refer to Figure 4b As shown, in this embodiment, the bit line material layer includes three stacked conductive material layers. Based on this, the formed bit lines can include a first bit line conductive layer 200a, a second bit line conductive layer 200b, and a third bit line conductive layer 200c.

[0108] Furthermore, the bit line further includes a bit line mask layer 200d, and the bit line mask layer 200d can be a patterned film layer formed above the three conductive material layers. In an optional solution, for example, the patterned bit line mask layer 200d is used to pattern the conductive material layers below it in sequence.

[0109] In this embodiment, the method for forming each bit line in the bit line group further includes: forming isolation sidewalls 200e on the sidewalls of the first bit line conductive layer 200a, the second bit line conductive layer 200b, the third bit line conductive layer 200c, and the bit line mask layer 200d.

[0110] In step S300, specifically referring to FIG. 4b, an isolation material layer 300 is formed on the bit lines. The isolation material layer 300 and the bit lines below it form a plurality of dividing lines 800, and the node contact window array is defined by using the dividing lines 800. The node contact windows arranged at the edge position in the node contact window array form the first contact windows 510, and the node contact windows located on the side of the first contact windows 510 away from the peripheral region 100B in the node contact window array form the second contact windows 520.

[0111] In a specific embodiment, the isolation material layer 300 and the bit lines below it form a first dividing line, and the first dividing line extends along the extension direction of the bit line, for example, along a first direction. And a second dividing line is further formed on the substrate 100, and the second dividing line extends along a second direction, for example, to intersect with the first dividing line, thereby defining the node contact window array.

[0112] Further, after defining the node contact window array, it further includes etching the bottom of the node contact window to extend the bottom of at least part of the node contact window further into the active region of the substrate. In this embodiment, the bottom of the second node contact window 520 extends into the substrate 100, and the bottom of the first node contact window 510 stops at the top surface of the substrate 100.

[0113] In step S400, specifically referring to Figures 4c to 4d As shown, a electrically conductive material layer is formed (in this embodiment, the electrically conductive material layer includes a first conductive material layer 400a and a second conductive material layer 400b), and the electrically conductive material layer fills at least part of the node contact window and also covers the top surface of the isolation material layer 300. Wherein, the electrically conductive material layer is used to further form the electrically conductive layer in the node contact portion.

[0114] In an alternative solution, before forming the electrically conductive material layer, it further includes: forming a contact layer in the node contact window. That is, in this embodiment, when forming the electrically conductive material layer, the electrically conductive material layer is formed on the contact layer, and the contact layer and the electrically conductive material layer are used to constitute the node contact portion.

[0115] Specifically referring to Figure 4c As shown, the method of forming the contact layer includes: filling a conductive contact layer 420a in at least part of the node contact window. In this embodiment, the conductive contact layer 420a is filled in the second contact window 520 to be electrically connected to the second active region AA2 exposed in the second contact window 520. And, the method of forming the contact layer further includes: filling an insulating contact pillar 410a in the first contact window 510, and the insulating filling pillar 410a is electrically insulated from the active region below it. In this embodiment, at least part of the first active region AA1 is exposed in the first contact window 510. Based on this, at least part of the insulating contact pillar 410a is in contact with and electrically insulated from the first active region AA1.

[0116] It should be noted that the conductive contact layer 420a can be preferentially formed in the second contact window 520, and then the insulating contact pillar 410a is formed in the first contact window 510. Or, the insulating contact pillar 410a can be preferentially formed in the first contact window 510, and then the conductive contact layer 420a is formed in the second contact window 520.

[0117] Further, the top position of the insulating filling column 410a in the first contact window may be the same as the top position of the first contact window, that is, the top surface of the insulating filling column 410a is flush with the top surface of the isolation material layer 300. Also, the top position of the conductive contact layer 420a in the second contact window is lower than the top position of the second contact window 520. In this embodiment, the top surface of the conductive contact layer 420a is further lower than the top surface of the bit line.

[0118] Continuing to refer to Figure 4c and Figure 4d shown, after forming the contact layer, an electrically conductive material layer is formed. In this embodiment, the forming method of the electrically conductive material layer may specifically include the following steps.

[0119] The first step, specifically referring to Figure 4c shown, a first conductive material layer 400a is formed, the first conductive material layer 400a covers the side wall of the second contact window 520 and the top surface of the conductive contact layer 420a, and the first conductive material layer 400a also covers the top surface of the insulating contact column 410a and the top surface of the isolation material layer 300.

[0120] The second step, specifically referring to Figure 4d shown, a second conductive material layer 400b is formed, the second conductive material layer 400b fills the second contact window, and also covers the top surface of the isolation material layer 300 and the insulating contact column 410a. In this embodiment, the second conductive material layer 400b is a planarized film layer.

[0121] In step S500, specifically referring to Figure 4d and Figure 4e described, the electrically conductive material layer is patterned to form a node contact portion array, the node contact portion array includes a second contact portion 420 corresponding to the second contact window and a first contact portion 410 corresponding to the first contact window, and the top of the first contact portion 410 also extends laterally to the isolation material layer directly above the first bit line 210, so that the width dimension of the first contact portion 410 is greater than the width dimension of the second contact portion 420.

[0122] In this embodiment, the electrical conduction material layer is patterned to further form the electrical conduction layer of the node contact portion. Specifically, the electrical conduction material layer is patterned to form the first electrical conduction layer 410b of the first contact portion 410 and the second electrical conduction layer 420b of the second contact portion 420. Among them, the top of the first electrical conduction layer 410b in the first contact portion 410 extends horizontally above the first bit line 210, so that the width dimension of the first electrical conduction layer 410b is greater than the width dimension of the second electrical conduction layer 420b.

[0123] Among them, the method of patterning the electrical conduction material layer specifically includes the following steps.

[0124] Step 1, specifically referring to Figure 4d As shown, a patterned mask layer is formed on the electrical conduction material layer. In this embodiment, the patterned mask layer is formed on the second conductive material layer 400b. Among them, the patterned mask layer is, for example, a patterned photoresist layer.

[0125] Specifically, the patterned mask layer includes a first pattern 710 and a second pattern 720. The first pattern 710 covers above the first contact window and extends horizontally above the first bit line 210 to define the pattern of the first electrical conduction layer in the first contact portion; and the second pattern 720 covers above the second contact window to define the pattern of the second electrical conduction layer in the second contact portion. Among them, the width dimension of the first pattern 710 is greater than the width dimension of the second pattern 720.

[0126] It should be noted that when forming the patterned mask layer, the first pattern 710 located at the edge position will also have the problem of overdevelopment, which will affect the pattern accuracy of the first pattern 710. In this regard, in this embodiment, the width dimension of the first pattern 710 is made greater than the width dimension of the second pattern 720, so as to ensure that the first pattern 710 still meets the size requirements even on the basis of overdevelopment. And under the blocking protection of the first pattern 710 with a larger width dimension, the overdevelopment of the second pattern 720 is avoided, ensuring the pattern accuracy of the second pattern 720.

[0127] Step 2, specifically referring to Figure 4eAs shown, the electrically conductive material layer is etched using the patterned mask layer as a mask, that is, the second conductive material layer 400b and the first conductive material layer 400a are etched in sequence using the patterned mask layer as a mask. In this way, the electrically conductive material layers corresponding to different node contact windows are separated from each other, thereby forming separated electrically conductive layers. Among them, the separated electrically conductive layers specifically include: a first electrically conductive layer 410b for forming the first contact portion 410 and a second electrically conductive layer 420b for forming the second contact portion 420, and the width dimension of the first electrically conductive layer 410b is greater than the width dimension of the second electrically conductive layer 420b.

[0128] Similarly, when etching the electrically conductive material layer, the first electrically conductive layer 410b located at the edge position will be subject to a greater etching attack, which may cause the first electrically conductive layer 410b to be easily eroded and deformed in large quantities. Based on this, in this embodiment, the width dimension of the formed first electrically conductive layer 410b is made greater than the width dimension of the second electrically conductive layer 420b. In this way, even if the first electrically conductive layer 410b is subject to a greater etching attack, the morphology of the first electrically conductive layer 410b can still be ensured. Moreover, under the blocking and protection of the first electrically conductive layer 410b with a larger width dimension, the problem of excessive erosion of the second electrically conductive layer 420b adjacent to the first electrically conductive layer 410b can be effectively alleviated.

[0129] Continue to refer to Figure 4e As shown, in a further solution, after etching the electrically conductive material layer to expose the isolation material layer 300, it further includes: etching the isolation material layer 300 to a predetermined depth to form an isolation layer. By further etching the isolation material layer between adjacent electrically conductive layers, in this way, the conductive material between adjacent electrically conductive layers can be effectively removed to ensure that adjacent electrically conductive layers are isolated from each other.

[0130] In this embodiment, the first contact portion 410 is located between the first bit line 210 and the second bit line 220, and the top of the first contact portion 410 also laterally covers a part of the isolation material layer 300 directly above the first bit line 210. Based on this, when etching the isolation material layer 300, the isolation material layer directly above the first bit line 210 and covered by the first contact portion 410 is not consumed, and the isolation material layer directly above the first bit line 210 and exposed to the first contact portion 410 is partially etched, thereby forming a first isolation portion 310 above the first bit line 210. And, the second contact portion 420 is located between adjacent second bit lines 220, and when etching the isolation material layer, the height of the isolation material layer above the second bit line 220 is reduced, thereby forming a second isolation portion 320 above the second bit line 220.

[0131] Further, after forming the first isolation portion 310 and the second isolation portion 320 with a relatively low height, it further includes forming a spacer insulating layer. The spacer insulating layer is formed on the isolation layer, wherein the portion of the spacer insulating layer formed on the first isolation portion 310 constitutes a spacer sidewall 910, and the portion of the spacer insulating layer formed on the second isolation portion 320 constitutes a spacer filling portion 920.

[0132] In this embodiment, the method for forming the spacer insulating layer, for example, includes: First, depositing an insulating material layer, the insulating material layer filling the gaps between adjacent second contact portions 420 to cover the second isolation portion 320, and the insulating material layer also covering the first isolation portion and the third isolation portion of the isolation layer; then, performing an etch-back process to remove the portion of the insulating material layer that protrudes above the node contact portion and remove the portion of the insulating material layer that covers the third isolation portion to form a spacer sidewall and the spacer filling portion respectively. In addition, after performing the etch-back process on the insulating material layer to expose the third isolation portion, the third isolation portion can be further etched to partially consume the third isolation portion such that the top surface of the third isolation portion is lower than the top surface of the second isolation portion. Embodiment Two

[0133] The difference from Embodiment One is that in this embodiment, a third contact portion and a fourth contact portion are further provided in the peripheral region. Figure 5 It is a cross-sectional schematic diagram of the memory in Embodiment Two of the present invention. As Figure 5 shown, the third contact portion 430 includes an insulating column 430a and a third electrically conductive layer 430b, and the third electrically conductive layer 430b covers the top surface of the insulating column 430a. And, the fourth contact portion 440 only includes an insulating column. Among them, the third contact portion 430 is specifically formed on the second trench isolation structure 120.

[0134] Further, the fourth contact portion 440 and the third contact portion 430 are arranged alternately in sequence, and an isolation material is filled between the insulating column 430a of the third contact portion 430 and the insulating column of the fourth contact portion 440. In this embodiment, a fourth contact portion 440 is spaced between the third contact portion 430 closest to the memory region 100A and the first contact portion 410, so as to prevent the first electrically conductive layer 410b in the first contact portion 410 from being connected to the third electrically conductive layer 430b in the third contact portion 430. Among them, the width dimension of the third electrically conductive layer 430b of the third contact portion 430 can be the same as or similar to the width dimension of the first electrically conductive layer 410b in the first contact portion 410.

[0135] In a more specific embodiment, the third electrical conduction layer 430b of the third contact portion 430 covers the top surface of the insulating pillar 430a and further extends in a direction away from the memory region to cover adjacent isolation materials.

[0136] Continuing to refer to Figure 5 As shown, the top surfaces of the third electrical conduction layer 430b in the third contact portion 430 and the first electrical conduction layer 410b in the first contact portion 410 are flush, and the insulating pillar 430a of the third contact portion 430 protrudes above the insulating pillar of the fourth contact portion 440. In other words, both the insulating pillar and the isolation material covered by the third electrical conduction layer 430b protrude above the insulating pillar and the isolation material not covered by the third electrical conduction layer 430b.

[0137] Furthermore, the memory further includes a spacer portion 910'. The spacer portion 910' is filled between the first contact portion 410 and the third contact portion 430, and is also filled between adjacent third contact portions 430, and the spacer portion 910' covers the fourth contact portion 440 and adjacent isolation materials.

[0138] It should be noted that the insulating pillar 430a of the third contact portion 430, the insulating pillar of the fourth contact portion 440, and the insulating filling pillar 410a of the first contact portion 410 can be prepared simultaneously, and the third electrical conduction layer 430b of the third contact portion 430 and the first electrical conduction layer 410b of the first contact portion 410 can be prepared simultaneously. Specifically, the third electrical conduction layer 430b of the third contact portion 430 and the first electrical conduction layer 410b of the first contact portion 410 can be formed simultaneously by patterning the same conductive material layer.

[0139] In summary, in the memory as described above, the width dimension of the first bit line located at the edge position in the bit line group is greater than the width dimension of the second bit line arranged therein. Thus, when preparing the bit line group, even if the first bit line located at the edge position is easily subject to a large amount of erosion, the morphology of the first bit line can still be ensured. And under the blocking protection of the first bit line with a larger width, the second bit line arranged therein can also be prevented from being subject to a large amount of erosion, improving the morphology accuracy of the second bit line, and further being beneficial to improving the device performance of the formed memory. Similarly, since the width dimension of the first contact portion located at the edge position in the node contact portion array is greater than the width dimension of the second contact portion, the morphology of the first contact portion can be guaranteed correspondingly, and the pattern accuracy of the second contact portion can be improved.

[0140] In a further solution, the active region at the edge position can also be defined as a non-functional active region, and the first bit line at the edge position in the bit line group can be defined as a non-functional bit line. In this way, on the one hand, the width dimension of the first bit line can be adjusted more flexibly; on the other hand, when a functional storage unit is formed based on the active region at the edge position, it can avoid the performance abnormality of the storage unit, which in turn affects the device performance of the formed memory. Similarly, the first contact portion at the edge position in the node contact portion array can be electrically insulated from the active region below it, so that the first contact portion is correspondingly a non-functional contact portion.

[0141] It should be noted that although the present invention has been disclosed above with preferred embodiments, the above embodiments are not intended to limit the present invention. For any person skilled in the art, without departing from the scope of the technical solution of the present invention, many possible changes and modifications can be made to the technical solution of the present invention by using the technical content disclosed above, or modified into equivalent embodiments with equivalent changes. Therefore, all contents that do not depart from the technical solution of the present invention, any simple modification, equivalent change and modification made to the above embodiments according to the technical essence of the present invention still fall within the scope of the protection of the technical solution of the present invention.

[0142] It should also be understood that unless otherwise specified or indicated, the terms "first", "second", "third", etc. in the specification are only used to distinguish the various components, elements, steps, etc. in the specification, rather than to represent the logical relationship or sequential relationship between the various components, elements, steps, etc.

[0143] In addition, it should also be recognized that the terms described herein are only used to describe specific embodiments and are not used to limit the scope of the present invention. It must be noted that the singular forms "a" and "an" used herein and in the appended claims include plural references unless the context clearly indicates the contrary. For example, the reference to "a step" or "a device" means a reference to one or more steps or devices, and may include secondary steps and secondary devices. All conjunctions used should be understood in the broadest sense. And, the word "or" should be understood as having the definition of logical "or", rather than the definition of logical "exclusive or", unless the context clearly indicates the contrary. In addition, the implementation of the methods and / or devices in the embodiments of the present invention may include performing the selected tasks manually, automatically, or in combination.

Claims

1. A memory, characterized in that, Comprising: A substrate, on which a memory region and a peripheral region are defined, and the peripheral region is located outside the memory region; A bit line group formed in the memory region of the substrate, the bit line group includes a plurality of bit lines extending along a predetermined direction, and the bit line arranged at the edge position in the bit line group constitutes a first bit line, and the bit lines in the bit line group located on the side of the first bit line away from the peripheral region constitute a second bit line, and the width dimension of the first bit line is greater than the width dimension of the second bit line; and, A plurality of node contact parts, each node contact part in the plurality of node contact parts is at least partially located on one side of the bit line, and the node contact part arranged at the edge position in the plurality of node contact parts constitutes a first contact part, and the node contact parts in the plurality of node contact parts located on the side of the first contact part away from the peripheral region constitute a second contact part, and the bottom of the second contact part is lower than the bottom of the first contact part; An active region array is formed in the memory region, the first contact part is electrically insulated from the active region below it, and the second contact part is electrically connected to the active region below it.

2. The memory according to claim 1, wherein The first contact part includes an insulating contact pillar, the insulating contact pillar is formed on the substrate, and the top of the insulating contact pillar is lower than the top of the second contact part.

3. The memory according to claim 2, characterized in that, The first contact part further includes a first electrical conduction layer covering the top surface of the insulating contact pillar.

4. The memory according to claim 1, wherein, The second contact part has a portion with a material different from that of the first contact part.

5. The memory according to claim 1, characterized in that, The second contact part includes a conductive contact layer, the conductive contact layer is formed on the substrate and at least partially embedded in the substrate.

6. The memory according to claim 5, wherein The second contact part further includes a second electrical conduction layer formed above the conductive contact layer.

7. The memory according to claim 1, characterized in that, The bottom of the second contact part is embedded in the substrate, and the bottom surface of the first contact part stops at the top surface of the substrate.

8. The memory according to claim 1, characterized in that, Further comprising: An isolation layer covering the top surface of the bit line.

9. The memory according to claim 8, wherein The portion of the isolation layer covering the first bit line constitutes a first isolation part, and the first contact part also extends laterally onto the first isolation part, so that the maximum width dimension of the first contact part is greater than the maximum width dimension of the second contact part.

10. The memory according to claim 1, characterized in that, A trench isolation structure is formed in the substrate of the peripheral region, and a third contact part is further provided on the substrate of the peripheral region, and the third contact part is formed on the trench isolation structure.

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