High-density three-dimensional longitudinal memory

Abstract

High-density three-dimensional longitudinal memory (3D-M V ) includes low-doped segment 3D-M V and non-circular hole type 3D-M V . Low-doped segment 3D-M V does not use lateral space (referring to the radial direction of the storage hole) but uses longitudinal space (referring to the depth direction of the storage hole) to ensure normal read / write operation of the storage element. Non-circular hole type 3D-M V contains a plurality of non-circular storage holes, the cross section of the non-circular storage hole contains at least two pairs of intersecting parallel lines, each pair of parallel lines is formed by DUV lithography single exposure, and the minimum spacing is less than 50 nanometers.

Description

TECHNICAL FIELD

[0001] The present application relates to the field of integrated circuit memory, and more particularly to three-dimensional memory. BACKGROUND

[0002] Three-dimensional longitudinal memory (3D-M V ) contains multiple vertical memory strings, each of which forms multiple vertically stacked memory cells in a vertical memory hole. Since 3D-M V memory cells are distributed in three-dimensional space, while memory cells of traditional memory are distributed in two-dimensional plane, 3D-M V has the advantages of high storage density and low storage cost. 3D-NAND is a large-scale mass-produced 3D-M V . 3D-NAND is a transistor-type 3D-M V , whose memory cell includes a programmable transistor, and the memory hole contains 5 layers of films (including silicon oxide-silicon nitride-silicon oxide-polysilicon-insulator). In order to form these 5 layers of films, the memory hole has a larger diameter, about 80 nanometers (nm).

[0003] Chinese patent application 201811117502.7 (referred to as 5027 application) discloses a diode-type 3D-M V , whose memory cell includes a programmable diode. Since it contains fewer layers of films, its memory hole diameter is smaller than that of 3D-NAND. The 5027 application Figure 1 A (not included in the drawings of the present application) discloses a diode-type 3D-M V contains substrate circuit 0K, horizontal address line 8a-8h, memory hole 2a-2d, programming film 6a-6d, vertical address line 4a-4d and memory cell 1aa-1ha. Substrate circuit 0K is formed in semiconductor substrate 0. Horizontal address line 8a-8h is stacked above substrate circuit 0K, separated by insulating layer 5a-5g in between. Memory hole 2a-2d penetrates horizontal address line 8a-8h and insulating layer 5a-5g. Programming film 6a-6d covers the sidewall of memory hole 2a-2d. Conductive material fills the remaining memory hole 2a-2d to form vertical address line 4a-4d. The intersection of horizontal address line 8a-8h and vertical address line 4a-4d forms multiple memory cells 1aa-1ha. All memory cells 1aa-1ha coupled to the same vertical address line 4a constitute a memory string 1A.

[0004] The 5027 application Figure 1C (not included in the accompanying drawings) is the symbol for memory cell 1. Memory cell 1 is a programmable diode containing a programming film 12 and a diode 14. The resistance of the programming film 12 can be changed by applying an electrical programming signal. Diode 14 has two terminals: a positive terminal (also called an anode) 1+ and a negative terminal (also called a cathode) 1-. Current flows easily from the anode 1+ to the cathode 1-, but not easily in the reverse direction. It has the following generalized characteristic: when the applied voltage is less than the read voltage V... R Or the direction of the applied voltage is opposite to V R Conversely, its resistance is greater than V. R The resistance below (i.e., the reading resistance). In other patents and technical documents, diodes are also referred to as selectors, steering elements, quasi-conductive films, etc. In this specification, these names all have the same meaning.

[0005] Diode 14 is preferably a built-in diode, meaning it naturally forms between the horizontal address line 8a and the vertical address line 4a, without requiring a separate diode film. During programming, part of diode 14 needs to withstand -V. P / 2(V P For programming voltage, see [link / reference] Figure 5C To prevent these diodes 14 from breaking down, the reverse breakdown voltage V of diode 14 is... BD Requires satisfying: V BD >V P / 2. Therefore, diode 14 preferably contains a low-doped region. For example, a PN junction diode may employ a P+ / i / -N+ structure, and a Schottky diode may employ a metal / i / N+ structure. In a specific embodiment, the low-doped region may contain a low-doped N-type (N-type) semiconductor material, an intrinsic (i) semiconductor material, a low-doped P-type (P-type) semiconductor material, or a combination of the above materials.

[0006] Figure 1 (in conjunction with the above 5027 application) Figure 1 E (described in the text) represents the structure of a storage cell 1aa (prior art). The anode 1+ of diode 14 (see application 5027) Figure 1 E) is the horizontal address line 8a, cathode 1- (see application 5027) Figure 1 E) is the vertical address line 4ax. Generally speaking, the anode 1+ (external electrode) contains P+ type semiconductor material (for PN junction diodes) or metal material (for Schottky diodes); the cathode 1- (internal electrode) contains N+ type semiconductor material. Figure 1In the prior art, the storage hole 2a contains a low-doped region 4ay and a high-doped region 4ax in the x direction, and the overall diameter D' of the storage hole 2a is d' + 2r' + 2t', where d' is the diameter of the high-doped region 4ax, r' is the thickness of the low-doped region 4ay, and t' is the thickness of the programming film 6a. In general, the prior art utilizes lateral space (i.e., in the x direction along the radius of the storage hole) to increase the V BD reverse breakdown voltage (V BD ) of the diode in the storage cell. Since the value of r' is between several nanometers and several tens of microns, the storage hole 2a has a large diameter D', which reduces the storage density and increases the storage cost.

[0007] In addition, the conventional 3D-M V uses DUV (deep ultraviolet) lithography to form all the storage holes, and all the storage holes are circular. The minimum diameter of the best circular hole formed by a single exposure of DUV lithography is 54 nanometers, and the minimum pitch (the distance between the centers of the circular holes) is 90 nanometers. Smaller circular holes can be formed by EUV (extreme ultraviolet) lithography. However, EUV lithography is complex and costly. Using only DUV lithography to form circular holes with smaller sizes is of great significance to increasing the storage density of 3D-M V . SUMMARY

[0008] The main purpose of the present application is to increase the storage density of 3D-M V and reduce the storage cost.

[0009] Another purpose of the present application is to reduce the size of the storage hole and simplify the manufacturing process.

[0010] Another purpose of the present application is to increase the reverse breakdown voltage (V BD ) of the diode in the storage cell to ensure the normal read / write operation of the storage cell.

[0011] Another purpose of the present application is to use only DUV lithography to implement a high-density three-dimensional longitudinal memory.

[0012] Another purpose of the present application is to reduce the size / pitch of the storage hole that can be implemented by DUV lithography.

[0013] Another purpose of the present application is to reduce the size / pitch of the hole structure that can be implemented by DUV lithography.

[0014] To achieve these and other purposes, the present application proposes two high-density 3D-M V : a low-doped section 3D-M V and a non-circular hole type 3D-M V . The low-doped section 3D-M V does not utilize lateral space (i.e., in the x direction along the radius of the storage hole) but utilizes longitudinal space (i.e., in the z direction along the depth of the storage hole) to ensure the VBD Each memory hole contains a low-doped segment, which contains only low-doped regions, but not high-doped regions. Specifically, in the low-doped segment, the low-doped semiconductor material completely fills the memory hole in the lateral direction and continuously spans all the horizontal address lines in the longitudinal direction. The overall diameter D of the memory hole is equal to d + 2t, where d is the diameter of the low-doped region 4a and t is the thickness of the programming film 6a. Obviously, D < D', which is beneficial to increasing the storage density of the 3D-M V On the other hand, the low-doped segment is in contact with a hole electrode at a coupling interface. If the doping concentration of the low-doped segment is N1 and the doping concentration of the hole electrode is N2, the coupling interface is located at a position with a doping concentration of sqrt(N1*N2). The shortest distance between the coupling interface and the horizontal address line, i.e., the surface line spacing S, determines the V BD For V P = 5V, V BD > 2.5V, S should be greater than 50 nanometers.

[0015] In addition to the horizontal address lines, the low-doped segment 3D-M V may also contain a horizontal control layer. The horizontal control layer includes a plurality of horizontal control lines. Control transistors are formed at the intersections of the horizontal control lines and the low-doped segment. These control transistors function as switches (such as pass gates) and together form the decoder of the 3D-M V array. Since the horizontal control lines are located between the horizontal address lines and the memory holes, the surface line spacing S is greater than the longitudinal period P of the horizontal lines (such as the horizontal address lines). Since the longitudinal period P is greater than 60 nanometers, this structure also ensures that V BD > V P / 2.

[0016] Correspondingly, the present application proposes a high-density three-dimensional longitudinal memory including a plurality of horizontal address lines (8a-8h) and a plurality of memory holes (2a-2d) penetrating all the horizontal address lines (8a-8h), characterized in that each of the memory holes (2a) contains: a programming film (6a) that completely covers the sidewall of the memory hole (2a); a low-doped segment (4a) containing low-doped semiconductor material that completely fills the memory hole (2a) in the lateral direction and continuously spans all the horizontal address lines (8a-8h) in the longitudinal direction; and a hole electrode (3a or 3a') containing high-doped semiconductor material or metal material and being in contact with the low-doped segment (4a) at a coupling interface (3ai or 3ai'), the shortest distance (S) between the coupling interface (3ai or 3ai') and the horizontal address lines (8a-8h) being greater than 50 nanometers.

[0017] This application also proposes another high-density three-dimensional vertical memory, characterized by comprising: multiple horizontal address lines (8a-8h); multiple memory holes (2a-2d) penetrating all the horizontal address lines (8a-8h); programming films (6a-6d) covering the sidewalls of the memory holes (2a-2d); multiple low-doped segments (4a-4d) located in the memory holes (2a-2d), each of the low-doped segments (4a) containing a low-doped semiconductor material, the low-doped semiconductor material completely filling the corresponding memory hole (2a) in the lateral direction; at least one hole electrode (3z1 or 3z1'), the hole electrode (3z1 or 3z1') containing a highly doped semiconductor material or a metal material, and in At least one coupling interface (3ai or 3ai`...) is in contact with the low-doped segment (4a-4d); at least one horizontal control line (7z1b or 7z1b`) is located between the horizontal address lines (8a-8h) and the via electrode (3z1 or 3z1`); at least one control transistor (9a1 or 9a1`) is located at the intersection of the low-doped segment (4a) and the horizontal control line (7z1b or 7z1b`); the low-doped segment (4a) continuously crosses all the horizontal address lines (8a-8h) and the horizontal control line (7z1b or 7z1b`) in the vertical direction.

[0018] On the other hand, traditional 3D-M V All the memory vias are formed using DUV (deep ultraviolet) lithography, and they are all circular. The smallest circular via diameter that can be formed in a single DUV lithography exposure is 54 nanometers, and the smallest lateral pitch (the distance between the centers of the vias) is 90 nanometers. To further reduce the size of the memory vias, this application proposes a non-circular via 3D-M... V In fact, DUV lithography is not good at forming circles, but it is better at forming parallel lines. The minimum linewidth of parallel lines that can be formed in a single exposure is 38 nanometers, and the minimum lateral pitch is 76 nanometers. Utilizing these characteristics, non-circular aperture 3D-M... V It contains multiple non-circular memory vias. The cross-section of each non-circular memory via (referring to the cross-section along the radius of the memory via) contains two pairs of parallel edges. Each pair of parallel edges is formed by a single exposure using DUV lithography, with a spacing of less than 50 nanometers (up to 38 nanometers). Non-circular via 3D-M V Examples include square hole type 3D-M V Hexagonal 3D-M V Those familiar with this field should know that non-circular hole 3D-M... V It can be applied not only to diode-type 3D-M V It can also be applied to transistor-type 3D-M VOther 3D-M V This technique can also be extended to non-circular hole structures in any integrated circuit.

[0019] Accordingly, the application also proposes a high-density three-dimensional longitudinal memory containing non-circular memory holes (2a), characterized in that the cross section of the non-circular memory holes (2a) contains: a first pair of parallel lines (0a1, 0a2) formed by a single DUV lithography exposure and having a pitch of less than 50 nm; a second pair of parallel lines (0b1, 0b2) formed by a single DUV lithography exposure and having a pitch of less than 50 nm; and the second pair of parallel lines (0b1, 0b2) intersects the first pair of parallel lines (0a1, 0a2).

[0020] The application further proposes a non-circular hole structure (2a) in an integrated circuit, characterized in that its cross section contains: a first pair of parallel lines (0a1, 0a2) formed by a single DUV lithography exposure and having a pitch of less than 50 nm; a second pair of parallel lines (0b1, 0b2) formed by a single DUV lithography exposure and having a pitch of less than 50 nm; and the second pair of parallel lines (0b1, 0b2) intersects the first pair of parallel lines (0a1, 0a2). BRIEF DESCRIPTION OF DRAWINGS

[0021] Figure 1 A diode-type 3D-M V Z-x cross-sectional view of a memory cell, whose memory hole contains a low-doped region and a high-doped region in the lateral direction.

[0022] Figure 2 A low-doped segment 3D-M V Z-x cross-sectional view of a memory cell, whose memory hole contains only a low-doped region in the lateral direction of the low-doped segment.

[0023] Figures 3A-3C A low-doped segment 3D-M V Z-x cross-sectional view of a first type of embodiment (single chip, including the first to third embodiments) of a memory cell, in which the low-doped segment is coupled to the hole electrode at the low end of the memory hole.

[0024] Figures 4A-4C A low-doped segment 3D-M V Z-x cross-sectional view of a second type of embodiment (chip pair, including the fourth to sixth embodiments) of a memory cell, in which the low-doped segment is coupled to the hole electrode at the high end of the memory hole.

[0025] Figure 5A is a z-x sectional view along Figure 5B sectional view along section A-A' of the first embodiment; Figure 5B is an x-y top view of its horizontal address lines 8a; Figure 5C is a 3D-M V array and its circuit diagram.

[0026] Figures 6A-6D are z-x sectional views of four process steps of the first embodiment.

[0027] Figure 7 is a z-x sectional view of the second embodiment.

[0028] Figure 8A is a z-x sectional view of the third embodiment; Figure 8B is a 3D-M V array and its circuit diagram.

[0029] Figures 9A-9B are sectional views of two chip-on-chip embodiments.

[0030] Figure 10 is a z-x sectional view of the fourth embodiment.

[0031] Figure 11 is a z-x sectional view of the fifth embodiment.

[0032] Figure 12A is a z-x sectional view of the sixth embodiment; Figure 12B is a 3D-M V array and its circuit diagram.

[0033] Figure 13 is an x-y top view of a square hole type 3D-M V embodiment.

[0034] Figures 14AA-14BC are two process steps of the Figure 13 embodiment. Therein, Figure 14AA is an x-y top view at the first process step, Figure 14AB is a z-x sectional view along section B-B' of the Figure 14AA embodiment. Figure 14BA is an x-y top view at the second process step, Figure 14BB , Figure 14BC are z-x sectional views along sections C-C' and D-D', respectively, of the Figure 14BA embodiment.

[0035] Figure 15 is an x-y top view of a hexagonal type 3D-M V embodiment.

[0036] Figures 16A-16B isFigure 15 One process step in the embodiment. Figure 16A is an x-y top view of the process step; Figure 16B is Figure 16A is a z-x cross-sectional view of the cross-section E-E' in the embodiment.

[0037] Note that these drawings are only schematic representations of the embodiments, and that for the sake of clarity, the drawings are not to scale. Individual features are not drawn to scale in the interest of clarity and for visualizing purposes only. Identical or corresponding elements are generally designated with the same reference numerals in the various embodiments. "In the substrate" means that the active devices (e.g. transistors) are formed in the substrate (including on the surface of the substrate). Note that the interconnect lines of these active devices can be formed on the substrate. "On the substrate" means that the active devices are formed above the substrate, not in contact with the substrate. " / " means "and" or "or". DETAILED DESCRIPTION

[0038] The present application proposes several high-density 3D longitudinal memory (3D-M V ) architectures: low-doped segment 3D-M V (3D-M Figures 2-12B ) and non-circular hole 3D-M V (3D-M Figures 13-16B ). The low-doped segment 3D-M V architecture does not use lateral space (i.e. along the radius of the memory hole, i.e. x direction) but uses longitudinal space (i.e. along the depth of the memory hole, i.e. z direction) to ensure normal read / write operation of the memory cell (by increasing V BD ).

[0039] Figure 2 represents a low-doped segment 3D-M V memory cell 1aa, which contains a horizontal address line 8a, a memory hole 2a penetrating the horizontal address line 8a, a programming film 6a covering the sidewall of the memory hole 2a, and a low-doped segment 4a formed in the memory hole 2a. Unlike the low-doped segment 3D-M Figure 1 architecture, the memory hole 2a contains only a low-doped region but no high-doped region in the low-doped segment 4a. Specifically, in the low-doped segment 4a, the low-doped semiconductor material completely fills the memory hole 2a in the lateral direction (i.e. along the radius of the memory hole 2a, i.e. x direction) and across the horizontal address line 8a in the longitudinal direction (i.e. along the depth of the memory hole 2a, i.e. z direction). The hole electrode 3a coupled to the low-doped segment 4a is located at least one end (low end or high end, relative to the substrate 0, see Figure 5A and Figure 10 ) of the memory hole 2a. Since the memory hole 2a contains only the low-doped segment 4a and the programming film 6a, its overall diameter D = d + 2t (d is the diameter of the low-doped segment 4a, t is the thickness of the programming film 6a). It is clear that D < D'. This will improve the 3D-MV memory density.

[0040] The programming film 6a can be one-time-programmable (OTP), multi-time-programmable (MTP), or re-programmable. For one-time-programmable memory cells, the programming film 6a contains a layer of anti-fuse film. Examples of anti-fuse materials include silicon oxide, silicon nitride, or a combination thereof. For multi-time-programmable or re-programmable memory cells, the programming film 6a contains a layer of writable film. Examples of writable film materials include resistive random access memory (RRAM), phase change memory (PCM), conductive-bridge RAM, magnetoresistive RAM (MRAM), etc. The thickness of the programming film 6a is between 1 nm and 200 nm.

[0041] The memory cell 1aa can also contain a hole electrode 3a. The horizontal address line 8a, the programming film 6a, the low-doped segment 4a, and the hole electrode 3a form a programmable diode. It can be one of the following A)-D) diodes:

[0042] A) P-N junction diode I - the horizontal address line 8a contains P+ type high-doped semiconductor material, and the hole electrode 3a contains N+ type semiconductor material;

[0043] B) P-N junction diode II - the horizontal address line 8a contains N+ type high-doped semiconductor material, and the hole electrode 3a contains P+ type semiconductor material;

[0044] C) Schottky diode I - the horizontal address line 8a contains metal material, and the hole electrode 3a contains high-doped semiconductor material;

[0045] D) Schottky diode II - the horizontal address line 8a contains high-doped semiconductor material, and the hole electrode 3a contains metal material.

[0046] In the A)-D) diodes, the low-doped segment 4a can contain N- type semiconductor material, intrinsic (i) semiconductor material, P- type semiconductor material, or a combination thereof. To reduce the hole electrode resistance, the hole electrode 3a can also contain a layer of metal material.

[0047] In the memory cell 1aa, the hole electrode 3a is coupled to the low-doped segment 4a at a coupling interface 3ai. If the doping concentration of the low-doped segment 4a is N1 and the doping concentration of the hole electrode 3a is N2, the coupling interface 3ai is located at a doping concentration of sqrt(N1*N2). The shortest distance between the coupling interface 3ai and the horizontal address line 8a-8h, the surface pitch S, determines the reverse breakdown voltage V BD :V BD of the diode. As S increases, V P increases. For V BD = 5V and V > 2.5V, S should be greater than 50 nm.

[0048] This application discloses two types of low-doped 3D-M V Single chip ( Figures 3A-3C , Figures 5A-8B ) and chip pair ( Figures 4A-4C , Figures 9A-12B In a single chip, 3D-M V The array and its peripheral circuitry are integrated into the same chip; in the chip pair, 3D-M V The array and its surrounding circuitry are distributed across two face-to-face bonded chips.

[0049] Figures 3A-3C Displaying the first type of low-doped 3D-M V (Single-chip) memory cell 1aa, its via electrode 3a is located at the lower end of memory via 2a (closest to the direction of the substrate where memory string 1A is located, i.e., the -z direction). Figure 3A In the first embodiment, the hole electrode 3a is located in the storage hole 2a and is laterally surrounded by the programming film 6a. Figure 3B In the second embodiment, the hole electrode 3a is located in the storage hole 2a, and there is no programming film around it. Figure 3C In the third embodiment, the hole electrode is shared by multiple storage holes.

[0050] Figures 4A-4C Displaying Type II low-doped 3D-M V (Chip pair) memory cell 1aa, its aperture electrode 3a' is located at the high end of memory aperture 2a (away from the substrate where memory string 1A is located, i.e., in the +z direction). Figure 4A In the fourth embodiment, the hole electrode 3a' is located in the storage hole 2a and is laterally surrounded by the programming film 6a. Figure 4B In the fifth embodiment, the hole electrode 3a' is located in the storage hole 2a, and there is no programming film around it. Figure 4C In the sixth embodiment, the hole electrode is shared by multiple storage holes.

[0051] Figures 5A-8B The first type of low-doped 3D-M was disclosed. V The overall structure, circuit design, and process steps of the three embodiments (first to third embodiments) in 100 respectively use Figures 3A-3C The storage element 1aa is located within the chip. These embodiments are single-chip structures, containing only one 3D-M. V Chip 10.

[0052] Figure 5A and Figure 5B The overall structure of the first embodiment is disclosed, which uses Figure 3A The storage element 1aa in the memory. For example... Figure 5A As shown, 3D-M VChip 10 includes vertically stacked horizontal address lines 8a-8h, memory vias 2a-2d penetrating the horizontal address lines, programming films 6a-6d covering the sidewalls of the memory vias, and low-doped segments 4a-4d formed in the memory vias 2a-2d. In the z-direction, the thickness of the horizontal address lines 8a-8h is T, and the vertical pitch is P. All memory cells 1aa-1ha along the same memory via 2a form a memory string 1A; all memory cells intersecting with the same set of horizontal address lines 8a-8h form a 3D-M string. V Array 1Z. The via electrodes 3a-3d are located at the lower end of the storage vias 2a-2d, and they contact the low-doped segments 4a-4d at the coupling interface 3ai-3di. The inter-line spacing S satisfies the condition: S > 50 nm. Figure 5B The horizontal address line 8a is plate-shaped and intersects with at least two rows of memory holes 2a-2d, 2e-2h. The horizontal address line 8a can also be strip-shaped and intersect with only one row of memory holes (see [link]). Figure 13 ).

[0053] Figure 5C It is 3D-M V 3D-M in Chip 10 V Circuit diagram of the array. In this embodiment, horizontal address lines 8a-8h are coupled to the anodes of the diodes in memory cells 1aa-1ah, serving as word lines; vertical address lines 4a-4h are coupled to the cathodes of the diodes in memory cells 1aa-1ah, serving as bit lines. During the write process (taking memory cell 1aa as an example), +V is applied to word line 8a. P / 2, add -V to bit line 4a P / 2, with the remaining word lines and bit lines grounded. Thus, the voltage applied to memory cell 1aa is V. P The voltage across the remaining memory cells is -V. P / 2 or 0. During the read process (using the storage cell 1aa-1ah on read word line 8a), the read voltage V R The voltage is applied to word line 8a, and word lines 8b-8h are grounded. Information in storage cells 1aa-1ah is read by monitoring voltage changes on bit lines 4a-4h. In this embodiment, bit lines 4a-4h are coupled to the substrate circuit 0K (including the sense amplifier). Those skilled in the art should understand that 3D-M... V Chip 10 can also use other read / write modes.

[0054] Figures 6A-6DFigure 1 shows the manufacturing process of the first embodiment. The process steps of manufacturing the substrate circuit 0K are well known to the skilled person and will not be described here. After forming the planarized substrate insulating film 5z on the substrate circuit 0K, a plurality of conductor films (highly doped semiconductor material or metal material films...) and interlayer insulating films 5a (silicon oxide, silicon nitride...) are alternately formed, each film having a thickness of 3 nm to 300 nm. The films are etched to form horizontal address lines 8a-8h Figure 6A Although only 8 layers of low-doped films are shown in the figure, in actual manufacturing, tens to hundreds or thousands of horizontal address lines can be formed.

[0055] After that, a plurality of memory holes 2a-2d are etched through all the horizontal address lines 8a-8h Figure 6B Then, programming films 6a-6d are formed on the sidewalls of the memory holes 2a-2d, which can be formed by deposition or growth (such as atomic layer deposition ALD) Figure 6C The above process steps are similar to those of 3D-NAND. They are well known to the skilled person and will not be described here.

[0056] After forming the programming films 6a-6d, the memory holes 2a-2d are filled with highly doped semiconductor material, and then etched back, so that the low end of the memory holes 2a-2d is formed with highly doped semiconductor material to form hole electrodes 3a-3d Figure 6D Finally, the memory holes 2a-2d are filled with low-doped semiconductor material 4a-4d Figure 5A Overall, the low-doped segment 3D-M V Chip 10 has the advantages of simple structure, etc. Since only two materials (low-doped semiconductor material 4a-4d and programming film 6a-6d) need to be filled in the memory holes 2a-2d, its process flow is simpler than that of 3D-NAND.

[0057] Figure 7 The overall structure of the second embodiment is disclosed, which uses the memory cell 1aa in Figure 3B The difference from Figure 5A is that the hole electrode 3a is located in the memory hole 2a, and there is no programming film 6a around it in the lateral direction. In its manufacturing process, the hole electrodes 3a-3d are first formed, and then the programming films 6a-6d are formed.

[0058] Figure 8A and Figure 8A The overall structure and circuit design of the third embodiment are disclosed, which uses the memory cell 1aa in Figure 3C The shared hole electrode 3z1 is in contact with all the low-doped segments 4a-4d in the memory holes 2a-2d Figure 8A For Figure 2A) - C) diodes in FIG. 1A, the shared hole electrode 3z1 contains a highly doped semiconductor material (such as N+or P+) at the coupling interface 3ai, 3bi with the low doped segments 4a-4d; to reduce its resistance, the shared hole electrode 3z1 can contain a layer of metal material underneath the highly doped semiconductor layer. For Figure 2 D) diodes in FIG. 1A, the shared hole electrode 3z1 contains a metal material at the coupling interface 3ai-3bi with the low doped segments 4a-4d.

[0059] In addition to the horizontal address lines 8a-8h, the present embodiment contains horizontal control layers 7z1, 7z2. The horizontal control layer 7z1 includes horizontal control lines 7z1a, 7z1b Figure 8A The control transistors 9a1 are formed at the intersection of the horizontal control line 7z1b and the low doped segments 4a-4d. These control transistors 9a1-9d1, 9a2-9d2 function as switches (such as forming pass gates), which together form the decoder 7Z V of the 3D-MRAM array 1Z. Figure 8B Since the horizontal control lines 7z1a, 7z1b are located between the shared hole electrode 3z1 and the horizontal address lines 8a-8h, the line-to-plane spacing S is greater than the longitudinal period P of the horizontal lines (such as the horizontal address lines 8a-8h). Since the longitudinal period P of the horizontal lines is greater than 60 nanometers, this structure ensures that V BD satisfies: V BD > V P / 2.

[0060] As an example of the decoder 7Z, when the voltage of the horizontal control line 7z1b is a first control voltage, the transistors 9a1, 9d1 are turned on; when the voltage of the horizontal control line 7z1a is a second control voltage, the transistors 9b1, 9c1 are turned off; when the voltage of the horizontal control line 7z2b is the first control voltage, the transistors 9c2, 9d2 are turned on; when the voltage of the horizontal control line 7z2a is the second control voltage, the transistors 9a2, 9b2 are turned off. Under the above control voltage settings, only the signal of the bit line 4d is transmitted through the shared hole electrode 3z1 to the sense amplifier of the substrate circuit 0K.

[0061] It is necessary to distinguish between the horizontal address lines 8a-8h and the horizontal control lines 7z1a-7z1b. Although they are both horizontal lines, the devices formed at their intersections with the low-doped segments 4a-4d are different: 1) The intersection of the horizontal address lines 8a-8h and the low-doped segments 4a-4d forms memory cells 1aa-1ha. Memory cells 1aa-1ha are two-terminal devices. During write operations, the material structure of the thin films 6a-6d changes; 2) The intersection of the horizontal control lines 7z1a-7z1b and the low-doped segments 4a-4d forms transmission gates 9a1-9b1. Transmission gates 9a1-9b1 are three-terminal devices. During write operations, the material structure of the thin films 6a-6d does not change. During read and write operations, the bias voltages of the ports of memory cells 1aa-1ha and transmission gates 9a1-9b1 are different.

[0062] Figures 9A-12B The second type of low-doped 3D-M was disclosed. V The overall structure, circuit design, and process steps of the three embodiments (the fourth to sixth embodiments) in the 100 examples respectively use Figures 4A-4C The storage element 1aa in the memory. For example... Figure 9A and Figure 9B As shown, the second type of low-doped 3D-M V The 100 chip pair structure contains two face-to-face bonded chips 10 and 10'. Chip 10 is a 3D-M... V Chip 10' is a peripheral circuit chip that contains 3D-M V The peripheral circuitry 7Z' of array 1Z. Note that chips 10 and 10' are two different chips located on different semiconductor substrates 0 and 0'.

[0063] Figure 9A and Figure 9B This focuses on various implementation methods for the connection between display chips 10 and 10'. Figure 9A In this embodiment, a first insulating medium 168a is formed on the front surface of the first chip 10, and then a plurality of first channel holes 160za are formed in the first insulating medium 168a. Furthermore, a second insulating medium 168b is also formed on the front surface of the second chip 10', and then a plurality of second channel holes 160zb are formed in the second insulating medium 168b. Next, after flipping the second chip 100b, the first channel holes 160za and the second channel holes 160zb are aligned, and the first and second chips 10 and 10' are bonded together. Accordingly, the first and second chips 10 and 10' are connected to each other 160 through the electrically contacting first and second channel holes 160za and 160zb.

[0064] exist Figure 9BIn an embodiment, the first chip 10 and the second chip 10' are bonded face-to-face. Specifically, the first chip 10 is face-up (+z direction); while the second chip 10' is flipped so that its face is face-down (-z direction). The inter-chip connection 160 is implemented between them through micro-bumps 160x. As a preferred example, Figures 9A-9B In an embodiment, the first chip 10 and the second chip 10' are bonded face-to-face. Specifically, the first chip 10 is face-up (+z direction); while the second chip 10' is flipped so that its face is face-down (-z direction). The inter-chip connection 160 is implemented between them through micro-bumps 160x. As a preferred example,

[0065] Figure 10 The overall structure of the fourth embodiment is disclosed, which uses the memory cell in Figure 4A The hole electrodes 3a'-3d' are located in the memory holes 2a-2d, which are surrounded by the programming films 6a-6d in the lateral direction. Its front-end process is similar to Figures 6A-6B The back-end process is to form the low-doped segments 4a-4d first, then the high end of the low-doped segments 4a-4d can be doped to form the hole electrodes 3a'-3d', or the low-doped segments 4a-4d can be etched back, then filled with high-doped semiconductor material. In this embodiment, the hole electrodes 3a'-3d' are located at the high end of the memory holes 2a-2d (away from the substrate 0, i.e. +z direction), and the hole electrodes 3a'-3d' are coupled with the low-doped segments 4a-4d at the coupling interfaces 3ai'-3di'. The closest distance between the coupling interfaces 3ai'-3di' and the horizontal address line 8h is the line-to-line pitch S. In order to ensure normal read / write operation, S should be greater than 50 nanometers. Note that the second substrate 0' of the second chip 10' is located above the first chip 10 and is flipped, and the second substrate circuit 0K' in the second substrate 0' is coupled with the hole electrodes 3a'-3d', 3D-M V At least part of the peripheral circuit of the array 1Z is located in the second substrate circuit 0K'.

[0066] Figure 11 The overall structure of the fifth embodiment is disclosed, which uses the memory cell in Figure 4B The hole electrodes 3a'-3d' are surrounded by the programming films 6a-6d in the lateral direction. Unlike Figure 10 The difference is that the programming films 6a-6d and the low-doped segments 4a-4d are etched partially first, then high-doped semiconductor material is filled in the memory holes 2a-2d.

[0067] Figure 12A and Figure 12B The overall structure of the sixth embodiment is disclosed, which uses the memory cell in Figure 4Cthe storage hole 2a-2d. The shared hole electrode 3z1` contacts all the low doped segments 4a-4d in the storage hole 2a-2d. This 3D-M V 100 contains multiple horizontal control layers 7z1`, 7z2`. Each horizontal control layer 7z1` contains multiple horizontal control lines 7z1a`, 7z1b`. The control transistors 9b1`, 9a1` are formed at the intersections of the horizontal control lines 7z1a`, 7z1b` and the low doped segments 4a, 4b Figure 12A ). The function of these control transistors 9a1`-9d1`, 9a2`-9d2` is like a switch (e.g. a pass gate), and they are combined together to form the 3D-M V decoder 7Z` of the 3D-M Figures 8A-8B array 1Z, which operates similarly Figure 12B to the decoder 7Z` of the 3D-M

[0068] conventional 3D-M V All the storage holes 2a-2h of the conventional 3D-M Figure 5B are formed by DUV (deep ultraviolet) lithography, and they are all circular V . In fact, DUV lithography is not good at forming circular holes, but it is good at forming parallel lines, and the minimum line width of a parallel line formed by a single exposure of DUV lithography is 38 nm, and the minimum horizontal pitch (the distance between the centers of two adjacent circular holes) is 90 nm. By taking advantage of the above characteristics of DUV lithography, a non-circular hole type 3D-M V contains multiple non-circular storage holes, and the cross section (the section along the radial direction of the storage hole) of each non-circular storage hole contains two pairs of parallel edges, and each pair of parallel edges is formed by a single exposure of DUV lithography, and the distance between the two pairs of parallel edges is less than 50 nm (can reach 38 nm). The non-circular hole type 3D-M V includes square hole type 3D-M V , Figures 13-14BC hexagonal type 3D-M V , Figures 15-16B and so on. Those skilled in the art should understand that the non-circular hole type 3D-M V can also be easily extended to any non-circular hole structure of a semiconductor chip (such as 3D-NAND).

[0069] Figure 13 shows a square hole type 3D-M V . It contains multiple horizontal address lines 08dz, 08da-08dc, etc. These horizontal address lines 08dz, 08da-08dc are in the form of strips, and the line width and the line spacing are both the minimum size of DUV lithography. This embodiment is different from the conventional 3D-M Figure 5B ,Figure 5B The horizontal address lines 8a are plate-shaped with a relatively large linewidth, capable of containing multiple rows of memory holes 2a-2h. In this embodiment, the memory hole 2a is located between two horizontal address lines 08dz and 08da, forming two memory cells with each of the two horizontal address lines 08dz and 08da respectively. Therefore, each memory cell can store two bits of information (2 bits per cell). In this embodiment, the memory hole 2a is square in shape with a size of 38 nanometers, much smaller than the diameter of a circular hole (54 nanometers). Only DUV lithography is used for the square hole type 3D-M. V The storage density is greater than that of the circular aperture 3D-M V .

[0070] Figures 14AA-14AB It is formed Figure 13 3D-M type with Chinese hole V The first process step involves forming horizontal address layers 08a-08d (separated by interlayer insulating layers 05a-05c), followed by first DUV lithography to form a first set of parallel line patterns. These parallel line patterns are then etched to form trenches 02a-02d. Trenches 02a-02d divide the horizontal address layers (such as the top horizontal address layer 08a) into multiple horizontal address lines 08da-08dc. Here, the width and spacing of trenches 02a-02d are the minimum dimensions required for DUV lithography.

[0071] Figures 14BA-14BC It forms a square hole type 3D-M V The second process step involves filling trenches 02a-02d with insulating dielectric 02ax-02dx and planarizing them, then forming an etch-stop layer on top. Following this, a second DUV lithography process is performed to form a second set of parallel line patterns. These parallel line patterns are then etched to form etch-stop bars 09a. The width and spacing of the etch-stop bars 09a are the minimum dimensions for DUV lithography. In this embodiment, the etch-stop bars 09a are at a 90° angle to the horizontal address lines 08da-08dc. Figure 14BA Finally, the trench dielectric 02ax-02dx is etched using the horizontal address lines 08da-08dc and the etch stop bar 09a as etch-stop layers. During this etching step, the trench dielectric 02ax-02dx covered by the horizontal address lines 08da-08dc or the etch stop bar 09a is not etched. Figure 14BB The trench media 02ax-02dx, which are not covered by the horizontal address lines 08da-08dc and the etch stop bar 09a, are etched to form square memory holes 2a-2d. Figure 14BC These square storage holes 2a-2d have the smallest dimensions for DUV lithography, with a lateral period of less than 90 nanometers.

[0072] Besides the square hole type 3D-M V It can also form other non-circular hole type 3D-M V . Figure 15 This represents a hexagonal 3D-M V Its storage hole 2a has six sides, which form three pairs of parallel edges, including the first pair of parallel edges 0a1, 0a2; the second pair of parallel edges 0b1, 0b2; and the third pair of parallel edges 0c1, 0c2. The width and spacing of the three pairs of parallel edges are the minimum dimensions of DUV lithography, only their directions are different.

[0073] Figures 16A-16B It is formed Figure 15 Hexagonal 3D-M V One of the process steps, Figure 16B yes Figure 16A Zx section view of the midsection EE'. (Compared to...) Figures 14AA-14AB Similarly, trenches 02a-02d are first etched to form multiple horizontal address lines 08dz, 08da-08dc. The trenches 02a-02d are then filled with trench dielectric 02ax-02dx and planarized. Next, two layers of etch stop bars are formed on top, including first etch stop bars 18a and 18b and second etch stop bars 28a and 28b. Thus, this embodiment uses three sets of etch stop bars to form a hexagon, including the horizontal address lines 08dz, 08da-08dc; and the first etch stop bars 18a and 18b and the second etch stop bars 28a and 28b. The trench medium 02bx covered by the horizontal address lines 08dz, 08dz-08dc or the etch stop bars 18a, 18b, 28a, 28b is not etched. The trench medium 02bx not covered by the horizontal address lines 08dz, 08dz-08dc and the etch stop bars 18a, 18b, 28a, 28b is etched to form hexagonal memory holes 2a-2c, which have the minimum size for DUV lithography.

[0074] It should be understood that changes to the form and details of this application may be made without departing from the spirit and scope thereof, and such changes do not preclude the application of the spirit of this application. Therefore, this application should not be limited in any way except in accordance with the spirit of the appended claims.

Claims

1. A high-density three-dimensional longitudinal memory comprising a plurality of horizontal address lines (8a-8h) and a plurality of memory holes (2a-2d) penetrating all of said horizontal address lines (8a-8h), characterized in that, Each of the memory holes (2a) contains: a programming film (6a) that completely covers the sidewall of the memory hole (2a), the resistance of the programming film (6a) being changeable by applying an electrical programming signal; a low-doped segment (4a) containing low-doped semiconductor material that completely fills the memory hole (2a) in the lateral direction and continuously spans all the horizontal address lines (8a-8h) in the longitudinal direction; a hole electrode (3a, 3a`, 3z1, or 3z1`) that contacts the low-doped segment (4a) at a coupling interface (3ai or 3ai`), the coupling interface (3ai or 3ai`) having a nearest distance (S) to the horizontal address lines (8a-8h) greater than 50 nanometers; the plurality of horizontal address lines (8a-8h), the low-doped segment (4a), and the hole electrode (3a, 3a`, 3z1, or 3z1`) form a plurality of P-N junction diodes; wherein the plurality of horizontal address lines (8a-8h) contain a first highly-doped semiconductor material, the hole electrode (3a, 3a`, 3z1, or 3z1`) contains a second highly-doped semiconductor material, and the first and second doping types are opposite.

2. A high-density three-dimensional longitudinal memory comprising a plurality of horizontal address lines (8a-8h) and a plurality of memory holes (2a-2d) penetrating all of said horizontal address lines (8a-8h), characterized in that, Each of the memory holes (2a) contains: a programming film (6a) that completely covers the sidewall of the memory hole (2a), the resistance of the programming film (6a) being changeable by applying an electrical programming signal; a low-doped segment (4a) containing low-doped semiconductor material that completely fills the memory hole (2a) in the lateral direction and continuously spans all the horizontal address lines (8a-8h) in the longitudinal direction; a hole electrode (3a, 3a`, 3z1, or 3z1`) that contacts the low-doped segment (4a) at a coupling interface (3ai or 3ai`), the coupling interface (3ai or 3ai`) having a nearest distance (S) to the horizontal address lines (8a-8h) greater than 50 nanometers; the plurality of horizontal address lines (8a-8h), the low-doped segment (4a), and the hole electrode (3a, 3a`, 3z1, or 3z1`) form a plurality of Schottky diodes; wherein the plurality of horizontal address lines (8a-8h) contain a metal material, and the hole electrode (3a, 3a`, 3z1, or 3z1`) contains a highly-doped semiconductor material.

3. A high-density three-dimensional longitudinal memory comprising a plurality of horizontal address lines (8a-8h) and a plurality of memory holes (2a-2d) penetrating all of said horizontal address lines (8a-8h), characterized in that, Each of the memory holes (2a) contains: a programming film (6a) that completely covers the sidewall of the memory hole (2a), the resistance of the programming film (6a) being changeable by applying an electrical programming signal; a low-doped segment (4a) containing a low-doped semiconductor material, which completely fills the storage hole (2a) in the lateral direction and continuously spans all the horizontal address lines (8a-8h) in the longitudinal direction; a hole electrode (3a, 3a`, 3z1, or 3z1`) contacting the low-doped segment (4a) at a coupling interface (3ai or 3ai`), which has a nearest distance (S) to the horizontal address line (8a-8h) greater than 50 nanometers; the plurality of horizontal address lines (8a-8h), the low-doped segment (4a), and the hole electrode (3a, 3a`, 3z1, or 3z1`) form a plurality of Schottky diodes; wherein the plurality of horizontal address lines (8a-8h) contain a highly-doped semiconductor material, and the hole electrode (3a, 3a`, 3z1, or 3z1`) contains a metallic material.

4. The high-density three-dimensional longitudinal memory of any of claims 1-3, further characterized by, containing: at least one horizontal control line (7z1b or 7z1b`) between the horizontal address line (8a-8h) and the hole electrode (3z1 or 3z1`); at least one control transistor (9a1 or 9a1`) at the intersection of the low-doped segment (4a) and the horizontal control line (7z1b or 7z1b`); the low-doped segment (4a) continuously spans all the horizontal address lines (8a-8h) and the horizontal control line (7z1b or 7z1b`) in the longitudinal direction.

5. The three-dimensional longitudinal memory of claim 4, wherein, the nearest distance (S) of the coupling interface (3ai or 3ai`) to the horizontal address line (8a-8h) is greater than the longitudinal period (P) of the horizontal address line (8a).

6. The three-dimensional longitudinal memory of any one of claims 1-3, wherein, the hole electrode (3z1 or 3z1`) contacts all the low-doped segments (4a-4d).

7. The three-dimensional longitudinal memory according to any one of claims 1 to 3, being a single chip (10), characterized in that, containing: a semiconductor substrate (0), the horizontal address line (8a-8h) is located in the single chip (10) and on the semiconductor substrate (0), and the hole electrode (3a) is located between the semiconductor substrate (0) and the horizontal address line (8a-8h).

8. The three-dimensional longitudinal memory according to any one of claims 1-3, being a chip pair (100), characterized in that, further containing: a first chip (10), the horizontal address line (8a-8h) is located in the first chip (10); a second chip (10`), the second chip (10`) contains a second substrate circuit (0K`); the hole electrode (3a) is located between the second substrate circuit (0K`) and the horizontal address line (8a-8h); the first chip (10) and the second chip (10`) are face-to-face bonded.

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