Three-dimensional memory element and method for manufacturing the same

Abstract

The present invention discloses a three-dimensional memory element and a method for manufacturing the three-dimensional memory element. The method comprises providing a precursor structure, wherein the precursor structure comprises a substrate, a multilayer stack, a plurality of vertical channel pillars and a barrier structure. A first slit and a second slit are formed in the multilayer stack and the substrate along a first direction, wherein there is a spacing between the first slit and the second slit, and the second slit cuts the barrier structure. A portion of the second insulating layer is replaced by a conductive layer. A first slit structure and a second slit structure are formed in the first slit and the second slit, wherein the first slit structure and the second slit structure separate the vertical channel pillars in a second direction, and the second direction is different from the first direction.

Description

Technical Field

[0001] The present invention relates to a memory device and a method for manufacturing the same. More specifically, the present invention relates to a three-dimensional memory device and a method for manufacturing the same. Background Art

[0002] A major feature of non-volatile memory devices is that they can preserve the integrity of data status when the memory device loses or removes power. With the increase of various applications and the improvement of functions, the demand for memory devices is also trending towards smaller size and larger storage capacity. In order to meet these needs, designers are currently developing a three-dimensional memory device that includes multiple planes of memory cells.

[0003] However, as the critical dimensions of components are miniaturized to the limit of general memory cell technology, how to obtain higher storage capacity in a smaller component size while taking into account the operational stability of the component has become an important issue facing this technology field. Therefore, an advanced three-dimensional memory component and its manufacturing method are needed to solve the problems faced by the existing technology. Summary of the invention

[0004] One embodiment of the present invention provides a method for manufacturing a three-dimensional memory device. The method includes providing a precursor structure, wherein the precursor structure includes a substrate, a multilayer stack, a plurality of vertical channel pillars, and a barrier structure. A first slit and a second slit are formed in the multilayer stack and the substrate along a first direction, wherein there is a spacing between the first slit and the second slit, and the second slit cuts the barrier structure. A portion of the second insulating layer is replaced with a conductive layer. A first slit structure and a second slit structure are formed in the first slit and the second slit, wherein the first slit structure and the second slit structure separate the vertical channel pillars in a second direction, and the second direction is different from the first direction.

[0005] Another embodiment of the present invention provides a three-dimensional memory element. The three-dimensional memory element includes a substrate, a first multilayer stack, a plurality of vertical channel pillars, a barrier structure, a first slit, and a second slit. The substrate has an array region and a step region, wherein the substrate includes a lower portion and an upper portion. The first multilayer stack is disposed on the substrate, wherein the first multilayer stack includes a plurality of first insulating layers and a plurality of conductive layers arranged alternately. A plurality of vertical channel pillars are disposed in the first multilayer stack and are located in the array region of the substrate. The barrier structure is disposed in the first multilayer stack and is located in the step region of the substrate. The first slit structure and the second slit structure are disposed in the first multilayer stack and the substrate along a first direction, wherein the second slit structure contacts the barrier structure, and the first slit structure and the second slit structure jointly separate the vertical channel pillars in a second direction, wherein the second direction is different from the first direction.

[0006] It is to be understood that both the foregoing general description and the following detailed description are exemplary, and are intended to provide further explanation of the invention as claimed. BRIEF DESCRIPTION OF THE DRAWINGS

[0007] When with Figure 1 The embodiments of the present invention can be best understood from the following detailed description when read together. It should be noted that, in accordance with standard industry practice, various features are not drawn to scale. In fact, the size of each feature may be arbitrarily increased or reduced for clarity of discussion.

[0008] Figure 1 FIG. 4 is a flow chart of a method for manufacturing a three-dimensional memory device according to some embodiments of the present invention.

[0009] FIG. 2A to FIG. 2D 1 shows a stage of manufacturing a three-dimensional memory element according to some embodiments of the present invention. According to some embodiments of the present invention, Figure 2A It is a top view. Figure 2B , Figure 2C and Figure 2D are intercepted along line segment BB′, line segment CC′ and line segment DD′ respectively, corresponding to Figure 2A Cross-sectional view of .

[0010] FIG. 3A to FIG. 3D A stage in the fabrication of a three-dimensional memory device is shown according to some embodiments of the present invention. Figure 3A It is a top view. Figure 3B , Figure 3C and Figure 3D are intercepted along line segment BB′, line segment CC′ and line segment DD′ respectively, corresponding to Figure 3A Cross-sectional view of .

[0011] Figure 4A and Figure 4B According to some embodiments of the present invention, Figure 3A An alternative implementation of .

[0012] FIG. 5A to FIG. 5D 1 shows a stage of manufacturing a three-dimensional memory element according to some embodiments of the present invention. According to some embodiments of the present invention, Figure 5A It is a top view. Figure 5B , Figure 5C and Figure 5D are intercepted along line segment BB′, line segment CC′ and line segment DD′ respectively, corresponding to Figure 5A Cross-sectional view of .

[0013] FIG. 6A to FIG. 6D1 shows a stage of manufacturing a three-dimensional memory element according to some embodiments of the present invention. According to some embodiments of the present invention, Fig. 6A It is a top view. Figure 6B , Figure 6C and Fig.6D are intercepted along line segment BB′, line segment CC′ and line segment DD′ respectively, corresponding to Fig. 6A Cross-sectional view of .

[0014] 7A to 7D 1 shows a stage of manufacturing a three-dimensional memory element according to some embodiments of the present invention. According to some embodiments of the present invention, Fig. 7A It is a top view. Figure 7B , Figure 7C and Fig.7D are intercepted along line segment BB′, line segment CC′ and line segment DD′ respectively, corresponding to Fig. 7A Cross-sectional view of .

[0015] FIG. 8A to FIG. 8D 1 shows a stage of manufacturing a three-dimensional memory element according to some embodiments of the present invention. According to some embodiments of the present invention, Fig. 8A It is a top view. Figure 8B , Figure 8C and Fig.8D are intercepted along line segment BB′, line segment CC′ and line segment DD′ respectively, corresponding to Fig. 8A Cross-sectional view of .

[0016] 9A to 9D 1 shows a stage of manufacturing a three-dimensional memory element according to some embodiments of the present invention. According to some embodiments of the present invention, Fig. 9A It is a top view. Fig. 9B , Fig. 9C and Fig.9D are intercepted along line segment BB′, line segment CC′ and line segment DD′ respectively, corresponding to Fig. 9A Cross-sectional view of .

[0017] FIG. 10A to FIG. 10D 1 shows a stage of manufacturing a three-dimensional memory element according to some embodiments of the present invention. According to some embodiments of the present invention, Fig. 10A It is a top view. Fig. 10B , Fig. 10C and Fig. 10D are intercepted along line segment BB′, line segment CC′ and line segment DD′ respectively, corresponding to Fig. 10A Cross-sectional view of .

[0018] FIG. 11A to FIG. 11D1 shows a stage of manufacturing a three-dimensional memory element according to some embodiments of the present invention. According to some embodiments of the present invention, Fig.11A It is a top view. Fig. 11B , Fig. 11C and Fig.11D are intercepted along line segment BB′, line segment CC′ and line segment DD′ respectively, corresponding to Fig.11A Cross-sectional view of .

[0019]

Explanation of symbols

[0020] 12, 14, 16, 18: Operation

[0021] 100: substrate

[0022] 110: Lower part

[0023] 120, 120': Upper part

[0024] 121, 123, 125: conductive layer

[0025] 122, 124: Insulation layer

[0026] 130, 130': Multilayer stacking

[0027] 131: first insulating layer

[0028] 132: Second insulation layer

[0029] 133: Conductive layer

[0030] 140: Spacer material

[0031] 142: Spacer layer

[0032] 200: Vertical channel column

[0033] 210: Insulation column

[0034] 220: Channel layer

[0035] 230: Conductive plug

[0036] 240, 240': Charge trapping layer

[0037] 300: Barrier structure

[0038] 300a, 300a': Part I

[0039] 300b: Part 2

[0040] 400: Dielectric column

[0041] 500: First slit structure

[0042] 502: first dielectric layer

[0043] 504: first conductive structure

[0044] 510: Second slit structure

[0045] 512: second dielectric layer

[0046] 514: second conductive structure

[0047] AA: Array Area

[0048] AS: Step Area

[0049] A1: First hole

[0050] A2: Second hole

[0051] G1: Cavity

[0052] H140:Thickness

[0053] OP1: First opening

[0054] OP2: Second opening

[0055] P1: Spacing

[0056] R1: Groove

[0057] R2: Region

[0058] S1: First slit

[0059] S2: Second slit

[0060] W133, W300b: Width

[0061] 1000: Front drive structure

[0062] 2000: Three-dimensional memory element DETAILED DESCRIPTION

[0063] In order to make the description of the content of the present invention more detailed and complete, the following is an illustrative description of the embodiments and specific embodiments of the content of the present invention, but this is not the only form of implementing or using the specific embodiments of the content of the present invention. The various embodiments disclosed below can be combined or replaced with each other in a beneficial situation, and other embodiments can also be added to one embodiment without further recording or explanation. In the following description, many specific details will be described in detail so that the reader can fully understand the following embodiments. However, the embodiments of the content of the present invention can be practiced without these specific details.

[0064] Furthermore, spatially relative terms, such as "below", "under", "above", "on", etc., are used to facilitate the description of the relative relationship between one element or feature and another element or feature, as shown in the figure. The true meaning of these spatially relative terms includes other orientations. For example, when the figure is flipped 180 degrees up and down, the relationship between one element and another element may change from "below" or "under" to "above" or "on". In addition, the spatially relative descriptions used in the present invention should also be interpreted in the same way.

[0065] Figure 1 FIG. 1 is a flow chart of a method for manufacturing a three-dimensional memory device according to some embodiments of the present invention. Figure 1 As shown, method 10 includes operation 12, operation 14, operation 16 and operation 18. It should be understood that Figure 1 The method shown is only an example and is not intended to limit the present invention. Figure 1 Additional operations are performed before, during, and / or after the methods shown, and the present disclosure only briefly describes some of the other operations.

[0066] exist FIG. 2A to FIG. 11D In the figure, the figure marked "A" at the end shows a top view of various stages of a method for forming a three-dimensional memory element according to certain embodiments of the present invention, and the figure marked "B" at the end is a top view of the method for forming a three-dimensional memory element according to certain embodiments of the present invention. Figure 2A The section line BB is shown, the section BB' is shown, and the figure marked "C" at the end of the figure is along Figure 2A The section line CC' shown in the figure and the figure marked with "D" at the end of the figure are along Figure 2A The section line DD' is shown.

[0067] Please refer to Figure 1 and Figure 2A-2B .exist Figure 1 In operation 12, a precursor structure 1000 is provided. The precursor structure 1000 includes a substrate 100, a multilayer stack 130, a plurality of vertical channel pillars 200, and a barrier structure 300. The substrate 100 includes an array region AA and a step region AS. Figure 2B As shown, the substrate 100 may include a lower portion 110 and an upper portion 120. In some embodiments, the lower portion 110 of the substrate 100 may be a semiconductor substrate, such as a silicon-containing substrate, but is not limited thereto. The upper portion 120 may include conductive layers 121, 123, 125 and insulating layers 122, 124 arranged alternately along a Z direction, wherein the Z direction is perpendicular to the substrate 100. In some embodiments, the conductive layers 121, 123, 125 may be polycrystalline silicon. In some embodiments, the insulating layers 122, 124 may be oxide layers. In some embodiments, transistors and interconnect structures (not shown) may be further formed in the substrate 100.

[0068] like Figure 2B As shown, the multilayer stack 130 is disposed on the substrate 100. The multilayer stack 130 includes a plurality of first insulating layers 131 and a plurality of second insulating layers 132 arranged alternately. The material of the first insulating layer 131 is different from the material of the second insulating layer 132. In some embodiments, the first insulating layer 131 includes silicon oxide, but is not limited thereto. In some embodiments, the second insulating layer 132 includes silicon nitride, but is not limited thereto.

[0069] like Figure 2A and Figure 2C As shown, the barrier structure 300 is disposed in the first multilayer stack 130 and is located in the stepped area AS of the substrate 100. A plurality of dielectric pillars 400 are disposed in the multilayer stack 130 and in the stepped area AS of the substrate 100. The barrier structure 300 and the dielectric pillars 400 vertically penetrate the multilayer stack 130 and extend to an upper position (e.g., the conductive layer 125) of the upper portion 120 of the substrate 100. Specifically, the barrier structure 300 and the dielectric pillars 400 are in contact with the conductive layer 125 and the insulating layer 124 of the substrate 100. The barrier structure 300 includes a first portion 300a extending along the X direction and a second portion 300b extending along the Y direction. In some embodiments, the width W300b of the barrier structure 300 in the X direction is less than 100 nm.

[0070] In some embodiments, the barrier structure 300 is a closed shape (e.g., a rectangle, a square, etc.) in a top view. In other embodiments, the barrier structure 300 is not a closed shape in a top view. In some embodiments, some dielectric pillars 400 may be surrounded by the barrier structure 300, such as Figure 2A The barrier structure 300 may have inclined side walls, such as Figure 2B and Figure 2C In some embodiments, the dielectric pillars 400 may be arranged in a row along the X direction and the Y direction. In some embodiments, the barrier structure 300 and the dielectric pillars 400 include silicon oxide, but are not limited thereto.

[0071] like Figure 2A and Figure 2DAs shown, the vertical channel column 200 is disposed in the multilayer stack 130 and is located in the array area AA of the substrate 100. Each vertical channel column 200 includes an insulating column 210, a channel layer 220, a conductive plug 230, and a charge trapping layer 240. The insulating column 210 vertically penetrates the multilayer stack 130 and extends into the conductive layer 121 of the substrate 100. In some embodiments, the insulating column 210 includes silicon nitride, silicon oxide, silicon oxynitride, high-k material, or any combination thereof. The channel layer 220 surrounds the insulating column 210. In some embodiments, the channel layer 220 includes polysilicon. The conductive plug 230 is disposed on the insulating column 210 and the channel layer 220. In some embodiments, the conductive plug 230 includes a conductive material. In some examples, the material of the conductive plug 230 is the same as that of the channel layer 220. The charge trapping layer 240 is disposed between the channel layer 220 and the multilayer stack 130. The charge trap layer 240 may be formed of a composite layer including a silicon oxide layer, a silicon nitride layer, and a silicon oxide layer (ie, an ONO structure).

[0072] Please refer to Figure 1 and Figure 3A-3D .exist Figure 1 In operation 14, first slits S1 and second slits S2 are formed in the multilayer stack 130 and the substrate 100. The first slits S1 and the second slits S2 extend in the X direction, respectively, and are parallel to each other. Figure 3A As shown, the first slit S1 passes through the array area AA and the step area AS. The second slit S2 contacts the barrier structure 300. In some embodiments, the second slit S2 passes through the barrier structure 300 and intersects with the second portion 300b of the barrier structure 300. In other words, in a top view, the second slit S2 overlaps the barrier structure 300. Therefore, the second slit S2 cuts the second portion 300b of the barrier structure 300 into two parts. In some examples, the vertical channel column 200 can be divided into two parts by the first slit S1 and the second slit S2 in the Y direction. In some examples, the dielectric column 400 can be divided into two or more parts by the first slit S1, the second slit S2 and the barrier structure 300 in the Y direction.

[0073] In some embodiments, Figure 3D As shown, the first slit S1 and the second slit S2 are formed by removing a portion of the multilayer stack 130 and the conductive layer 125 to form two grooves extending along the Z direction and penetrating the multilayer stack 130. Figure 3BAs shown, the first slit S1 is recessed from the top surface of the multilayer stack 130 to expose the sidewalls of the conductive layer 125 of the substrate 100. However, the second slit S2 is recessed from the top surface of the barrier structure 300 (the second portion 300b) to expose the sidewalls of the insulating layers 122, 124 and the sidewalls of the conductive layer 123 of the substrate 100. The top surface of the multilayer stack 130 and the top surface of the barrier structure 300 are substantially coplanar. In some embodiments, the first slit S1 and the second slit S2 have inclined sidewalls, respectively. Figure 3B and Figure 3C As shown, the second slit S2 further extends into the conductive layer 123 (located below the conductive layer 125) of the substrate 100, so as to form a gap in the region R2 (shown in FIG. 1 ) where the second slit S2 contacts the barrier structure 300. Figure 3A Specifically, a portion of the second slit S2 overlaps with the barrier structure 300 (the second portion 300 b ) in the region R2 . Figure 3A As previously described, the barrier structure 300 vertically penetrates the multilayer stack 130 and extends into the conductive layer 125 of the substrate 100. During the formation of the second slit S2 in the region R2, the groove R1 of the second slit S2 may further extend into the conductive layer 123 (or the conductive layer 121), as shown in FIG. Figure 3B and Figure 3C At region R2, the bottom surface of the second slit S2 may be below the bottom surface of the first slit S1, as shown in FIG. Figure 3B shown.

[0074] Please refer to Figure 4A-4B . Figure 4A and Figure 4B According to some embodiments of the present invention, Figure 3A An alternative implementation of . Figure 4A and Figure 3A The difference between the structures shown is that Figure 4A The second slit S2 shown does not pass through the second portion 300b of the barrier structure 300. Therefore, the second slit S2 does not cut through the barrier structure 300. In other embodiments, such as Figure 4B As shown, the first portion 300a' of the barrier structure 300 includes a plurality of segments spaced apart from each other. The first portion 300a' of the barrier structure 300 may be randomly cut or may be cut into uniform segments. In this embodiment, the second slit S2 may pass through the second portion 300b of the barrier structure 300, such as Figure 3A Alternatively, the second slit S2 may not pass through the second portion 300b of the barrier structure 300, as shown in FIG. Figure 4B It should be understood that Figure 4B The arrangement of the segments shown is merely an example and is not limiting.

[0075] Please refer to Figure 5A-5D A spacer material 140 is formed in the first slit S1 and the second slit S2. For clarity, Figure 5A The spacer material 140 located on the top surface of the multilayer stack 130 is not shown. In some embodiments, the spacer material 140 is formed on the sidewalls and bottom of the first slit S1 and the second slit S2 by a suitable deposition method. In some embodiments, the spacer material 140 includes silicon nitride, but is not limited thereto. Figure 5B and 5C As shown, the spacer material 140 is filled in the groove R1 in the region R2. The spacer material 140 has a thickness H140. In some embodiments, the ratio of the thickness H140 to the width W300b of the barrier structure 300 (ie, the width of the groove R1) is greater than 0.5.

[0076] Please refer to Figure 6A-6D A portion of the spacer material 140 is removed to form a spacer layer 142 that exposes the conductive layer 123 of the substrate 100. In some embodiments, as Fig.6D As shown, the spacer material 140 at the bottom of the first slit S1 and the second slit S2 is removed to form the first hole A1 and the second hole A2 exposing the sidewalls of the insulating layer 124 and the sidewalls of the conductive layer 123. In the process of forming the first hole A1 and the second hole A2, a portion of the insulating layer 124 and the conductive layer 123 is further removed. Figure 6B and Figure 6C As shown, when the spacer material 140 on the insulating layer 124 is removed, the spacer layer 142 in the groove R1 in the region R2 is retained. As previously described, the thickness H140 of the spacer material 140 is less than the width W300b of the barrier structure 300 (i.e., the width of the groove R1). The groove R1 is completely filled with the spacer material 140. During the removal of a portion of the spacer material 140, the spacer layer 142 in the region R2 ( Figure 3A As shown) a spacer layer 142.

[0077] Please refer to Figure 7A-7D A portion of the substrate 100 is removed to form the cavity G1. In some embodiments, a portion of the conductive layer 123 of the substrate 100 is removed through the first Al and the second hole A2 (eg, Fig.6D As shown in Figure 7C As shown in FIG. 1 , the conductive layer 123 is recessed from the second slit S2 to form a cavity G1 between the insulating layers 122 and 124. The cavity G1 connected to the second slit S2 has a depth D1 in the X direction. Figure 7C There is a spacing P1 between the first slit S1 and the second slit S2, as shown in FIG. Figure 7B In some embodiments, the ratio of the depth D1 to the pitch P1 is 0.5-1.

[0078] Please refer to Figure 8A-8D The charge trapping layer 240 exposed by the cavity G1 is removed. In some embodiments, the exposed charge trapping layer 240 is removed through the first slit S1 and the second slit S2 to expose the channel layer 220, such as Fig.8D During the removal of the exposed charge trapping layer 240, the spacer layer 142 is thinned and a portion of the insulating layers 122 and 124 are also removed. Figure 8C As shown, the spacer layer 142 still remains in the groove R1.

[0079] Please refer to Figure 9A-9D The cavity G1 is filled with the same material as the substrate 100. In some embodiments, the same conductive material as the conductive layer 123 (i.e., polysilicon) is backfilled into the cavity G1 to form an upper portion 120' of the substrate 100. The conductive material contacts the channel layer 220 of the vertical channel pillar 200. A portion of the conductive material in the first slit S1 and the second slit S2 may be further removed to form a first opening OP1 and a second opening OP2 that expose the sidewalls of the spacer layer 142 in the first slit S1 and the second slit S2, respectively.

[0080] Please refer to Figure 1 and Figures 10A-10D .exist Figure 1 In operation 16, a portion of the second insulating layer 132 is replaced by a plurality of conductive layers 133. In some embodiments, the conductive layer 133 includes a metal (e.g., titanium (Ti), tungsten (W), aluminum (Al), copper (Cu), gold (Au), silver (Ag) or alloys thereof), a metal oxide or other suitable conductive material. Figure 9A-9D In some embodiments, replacing the second insulating layer 132 with the conductive layer 133 includes removing the second insulating layer 132 exposed by the first slit S1 and the second slit S2 to form a plurality of lateral openings (not shown) between the first insulating layer 131. Then, a conductive material is formed in the lateral openings by a suitable deposition method. Then, the conductive material filled in the lateral openings is recessed to form the conductive layer 133. Fig. 10B As shown, each conductive layer 133 is recessed from the sidewall of the first insulating layer 131. Fig. 10C As shown, a portion of the second insulating layer 132 surrounded by the blocking structure 300 is retained and is not replaced by the conductive layer 133. The conductive layer 133 has a width W133 in the X direction. In some embodiments, the width W133 is substantially equal to the pitch P1 (shown in FIG. 1 ). Figure 7B ) is 0.5-0.7. In some embodiments, all second insulating layers 132 in array area AA are replaced by conductive layers 133, such as Fig. 10B and Fig. 10DAs shown. The barrier structure 300 and the dielectric pillar 400 passing through the multilayer stack 130 can support the first insulating layer 131 in the Z direction so that the first insulating layer 131 will not be deformed or collapsed when the second insulating layer 132 is removed. After replacing a portion of the second insulating layer 132 with a plurality of conductive layers 133, a multilayer stack 130' is formed. The multilayer stack 130' includes a plurality of first insulating layers 131 and a plurality of conductive layers 133 arranged alternately. The multilayer stack 130' is located in the array area AA and a portion of the step area AS.

[0081] Please refer to Figure 1 and Figures 11A-11D .exist Figure 1 In operation 18, a first slit structure 500 and a second slit structure 510 are formed in the first slit S1 and the second slit S2. The first slit structure 500 and the second slit structure 510 collectively separate the vertical channel pillars 200 in the Y direction. The first slit structure 500 and the second slit structure 510 may include a dielectric layer and a conductive structure, respectively.

[0082] like Fig. 11B As shown, the first dielectric layer 502 is formed on the sidewalls of the conductive layer 133 in the first slit S1 and the sidewalls of the first insulating layer 131. The first conductive structure 504 is surrounded by the first dielectric layer 502 and is in contact with the upper portion 120' of the substrate 100. The second dielectric layer 512 is formed on the sidewalls of the conductive layer 133 in the second slit S2 and the sidewalls of the first insulating layer 131. The second conductive structure 514 is surrounded by the second dielectric layer 512 and is in contact with the upper portion 120' of the substrate 100. The first dielectric layer 502 and the second dielectric layer 512 separate the conductive layer 133 from the first conductive structure 504 and the second conductive structure 514, respectively. In some embodiments, the first dielectric layer 502 and the second dielectric layer 512 include dielectric materials, including but not limited to silicon oxide, silicon nitride, silicon oxynitride, or a combination thereof. In some embodiments, the first conductive structure 504 and the second conductive structure 514 include conductive materials including but not limited to tungsten (W), cobalt (Co), copper (Cu), aluminum (Al), polysilicon, doped silicon, or combinations thereof.

[0083] In this way, a three-dimensional memory element 2000 is formed. The three-dimensional memory element 2000 includes a substrate 100, a multilayer stack 130', a plurality of vertical channel pillars 200, a barrier structure 300, a first slit structure 500, and a second slit structure 510. The substrate 100 includes an array region AA and a step region AS. The multilayer stack 130' is disposed on the substrate 100 and includes a plurality of first insulating layers 131 and a plurality of conductive layers 133 arranged alternately. Another multilayer stack 130 is disposed in the step region AS and is surrounded by the barrier structure 300. Fig. 11CAs shown, the multilayer stack 130 is disposed on the substrate 100. The multilayer stack 130 includes a plurality of first insulating layers 131 and a plurality of second insulating layers 132 arranged alternately. The second insulating layers 132 are connected to the conductive layers 133.

[0084] The vertical channel pillars 200 are disposed in the multilayer stack 130' and are located in the array area AA of the substrate 100. Each vertical channel pillar 200 includes an insulating pillar 210, a channel layer 220, a conductive plug 230, and a charge trapping layer 240. The insulating pillar 210 vertically penetrates the multilayer stack 130' and extends into the upper portion 120' of the substrate 100. The channel layer 220 surrounds the insulating pillar 210. The conductive plug 230 is disposed on the insulating pillar 210 and the channel layer 220. The charge trapping layer 240 is disposed between the channel layer 220 and the multilayer stack 130', wherein the charge trapping layer 240 has an opening exposing a portion of the sidewall of the channel layer 220 in the upper portion 120' of the substrate 100 located in the array area AA.

[0085] The barrier structure 300 is disposed in the multilayer stack 130' and is located in the step area AS of the substrate 100. The barrier structure 300 includes a first portion 300a extending in the X direction and a second portion 300b extending in the Y direction and connected to the first portion 300a. The first slit structure 500 and the second slit structure 510 are disposed in the multilayer stack 130' along the X direction. The second slit structure 510 contacts the second portion 300b of the barrier structure 300. The first slit structure 500 and the second slit structure 510 jointly separate the vertical channel pillars 200 in the Y direction. Specifically, the first slit structure 500, the second slit structure 510 and the barrier structure 300 extending in the X direction can divide the three-dimensional memory element 2000 into a plurality of portions. The first slit structure 500 and the second slit structure 510 can serve as source contacts.

[0086] The three-dimensional memory device 2000 further includes a plurality of dielectric pillars 400 disposed in the stepped region AS of the multilayer stack 130' and the substrate 100. Fig.11A As shown, a portion of the dielectric pillar 400 is surrounded by the barrier structure 300. In some embodiments, the three-dimensional memory device 2000 further includes a plurality of contacts disposed in the stepped region AS. The contacts may penetrate the multilayer stack 130 and be electrically connected to the transistor and / or interconnect structure disposed in the substrate 100. In some embodiments, the contacts are surrounded by the barrier structure 300.

[0087] As described above, according to an embodiment of the present invention, a three-dimensional memory element and a method for manufacturing the same are provided. The three-dimensional memory element includes a substrate, a multilayer stack disposed on the substrate, a plurality of vertical channel pillars disposed in the multilayer stack, a barrier structure, a first slit structure, and a second slit structure. The first slit structure and the second slit structure extend in a first direction, respectively, and the second slit structure contacts the barrier structure. The barrier structure surrounds an area in the step region. The multilayer stack includes a plurality of conductive layers and a plurality of first insulating layers alternately stacked. The multilayer stack also includes a plurality of first insulating layers and a plurality of second insulating layers alternately stacked in an area surrounded by the barrier structure, and each second insulating layer connects each conductive layer.

[0088] In the manufacture of the three-dimensional memory element, the second insulating layer is replaced by the conductive layer. Since the barrier structure can prevent the second insulating layer from being etched, the second insulating layer surrounded by the barrier structure may not be replaced. The first slit structure, the second slit structure and the barrier structure can divide the three-dimensional memory element into a plurality of parts and together separate the vertical channel columns in a second direction, and the second direction is different from the first direction. When performing the replacement process, the barrier structure can further support the multilayer stack to prevent the collapse or deformation of the multilayer stack.

[0089] So far, the embodiments of the present disclosure have been described in detail with reference to the accompanying drawings.

[0090] The specific embodiments described above further illustrate the objectives, technical solutions and beneficial effects of the present invention in detail. It should be understood that the above description is only a specific embodiment of the present invention and is not intended to limit the present invention. Any modifications, equivalent substitutions, improvements, etc. made within the spirit and principles of the present invention should be included in the protection scope of the present invention.

Claims

1. A method for manufacturing a three-dimensional memory element, wherein: include: A precursor structure is provided, wherein the precursor structure comprises: A substrate having an array region and a step region; A multilayer stack is disposed on the substrate, wherein the multilayer stack includes a plurality of first insulating layers and a plurality of second insulating layers arranged alternately; a plurality of vertical channel pillars disposed in the multilayer stack and located in the array region of the substrate; and a barrier structure disposed in the multilayer stack and located in the step region of the substrate, the barrier structure vertically penetrating the multilayer stack and extending into the substrate; Forming a first slit and a second slit in the multilayer stack and the substrate along a first direction, wherein there is a spacing between the first slit and the second slit in a second direction, and the second slit cuts the barrier structure; replacing a portion of the second insulating layers with a plurality of conductive layers, wherein a portion of the second insulating layers surrounded by the barrier structure is retained without being replaced by the conductive layer; and A first slot structure and a second slot structure are formed in the first slot and the second slot, wherein the first slot structure and the second slot structure separate the vertical channel pillars in the second direction, and the second direction is different from the first direction.

2. The method according to claim 1, wherein: The second slit further vertically extends to the substrate to form a groove, and a bottom surface of the groove is located below a bottom surface of the first slit.

3. The method according to claim 2, wherein: The method further includes forming a spacer layer in the first slit and the second slit, wherein the spacer layer has a first hole and a second hole to expose the substrate.

4. The method according to claim 3, wherein: The spacer layer has a thickness, the groove has a width, and a ratio of the thickness to the width is greater than 0.

5.

5. The method according to claim 1, wherein: Replacing a portion of the second insulating layers with the conductive layers includes replacing the second insulating layers in the array region of the substrate.

6. A three-dimensional memory element, wherein: include: A substrate having an array region and a step region, wherein the substrate includes a lower portion and an upper portion; a first multilayer stack disposed on the substrate, wherein the first multilayer stack comprises a plurality of first insulating layers and a plurality of conductive layers arranged alternately; a plurality of vertical channel pillars disposed in the first multilayer stack and located in the array region of the substrate; a barrier structure disposed in the first multilayer stack and located in the stepped region of the substrate, the barrier structure vertically penetrating the first multilayer stack and extending into the upper portion of the substrate; as well as A first slit structure and a second slit structure are disposed in the first multilayer stack and the substrate along a first direction, wherein the second slit structure contacts the barrier structure, and the first slit structure and the second slit structure jointly separate the vertical channel pillars in a second direction, wherein the second direction is different from the first direction; The first multi-layer stack further includes a plurality of the first insulating layers and a plurality of second insulating layers alternately stacked in a region surrounded by the barrier structure, and each of the second insulating layers is connected to each of the conductive layers.

7. The three-dimensional memory element according to claim 6, wherein: The blocking structure includes a first portion extending along the first direction, and a second portion extending along the second direction and contacting the second slit structure.

8. The three-dimensional memory element according to claim 7, wherein: The first portion of the barrier structure has a plurality of segments spaced apart from one another.

9. The three-dimensional memory element according to claim 6, wherein: A plurality of dielectric pillars are also included and are disposed in the first multi-layer stack and the stepped region of the substrate.

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