Methods of forming microelectronic devices and related microelectronic devices, memory devices, and electronic systems

Abstract

The present application relates to methods for forming microelectronic devices, and related microelectronic devices, memory devices, and electronic systems. A microelectronic device includes pillar structures (including semiconductor material), contact structures in physical contact with upper portions of the pillar structures, and electrically conductive structures over and in physical contact with the contact structures. Each of the electrically conductive structures includes a lower portion having a first horizontal width, an upper portion vertically overlying the lower portion and having a second horizontal width greater than the first horizontal width, and an additional portion vertically interposed between the lower portion and the upper portion and having an arcuate horizontal boundary defining an additional horizontal width that varies from the first horizontal width proximate the lower portion to a relatively greater horizontal width proximate the upper portion. Memory devices, electronic systems, and methods of forming microelectronic devices are also described.

Description

[0001] Priority Statement

[0002] This application claims the benefit of U.S. Patent Application No. 16 / 952,939, filed November 19, 2020, entitled “METHODS OF FORMING MICROELECTRONIC DEVICES, AND RELATED MICROELECTRONIC DEVICES, MEMORY DEVICES AND ELECTRONIC SYSTEMS”. Technical Field

[0003] In various embodiments, this disclosure generally relates to the field of microelectronic device design and fabrication. More specifically, this disclosure relates to methods of forming microelectronic devices, and to related microelectronic devices, memory devices, and electronic systems. Background Technology

[0004] Microelectronic device designers typically aim to increase the level or density of features within a microelectronic device by reducing the size of individual features and by decreasing the spacing between adjacent features. Furthermore, microelectronic device designers often seek designs that are not only compact but also offer performance advantages and simplified architectures.

[0005] An example of a microelectronic device is a memory device. Memory devices are generally provided as internal integrated circuits in computers or other electronic devices. Many types of memory devices exist, including, but not limited to, non-volatile memory devices (e.g., NAND flash memory devices). One way to increase memory density in non-volatile memory devices is to use a vertical memory array (also known as a “three-dimensional (3D) memory array”) architecture. A conventional vertical memory array comprises strings of memory cells that extend vertically through openings in one or more layers (e.g., a stacked structure) containing conductive and insulating structural layers. Each string of memory cells may contain at least one selection device coupled thereto. Compared to structures with a conventional planar (e.g., two-dimensional) arrangement of transistors, such a configuration allows for the placement of a greater number of switching devices (e.g., transistors) within a unit die area (i.e., the length and width of the consumed active surface) by building an array upwards (e.g., vertically) on the die.

[0006] Reducing the size and spacing of memory device features places increasing demands on the methods used to form these features. For example, as feature spacing decreases to accommodate increasing feature density, 3D NAND flash memory device manufacturers face the significant challenge of reducing the area of ​​vertical memory arrays. Reducing the spacing between closely packed conductive structures (e.g., conductive plug structures, conductive contact structures) that couple digital line structures to memory cell strings can, for example, lead to undesirable electrical coupling (e.g., capacitive coupling) effects, which can result in a loss of programming time (tPROG) margin in high-speed memory applications. Summary of the Invention

[0007] In some embodiments, a microelectronic device includes a pillar structure (including a semiconductor material), a contact structure physically in contact with the upper portion of the pillar structure, and a conductive structure above and physically in contact with the contact structure. Each of the conductive structures includes a lower portion having a first horizontal width, an upper portion perpendicularly covering the lower portion and having a second horizontal width greater than the first horizontal width, and an additional portion perpendicularly inserted between the lower portion and the upper portion and having an arcuate horizontal boundary, the arcuate horizontal boundary defining an additional horizontal width that varies from the first horizontal width near the lower portion to a relatively larger horizontal width near the upper portion.

[0008] In an additional embodiment, a method of forming a microelectronic device includes forming a contact structure that physically contacts the upper part of a pillar structure, the pillar structure comprising a semiconductor material. A dielectric material is formed over the contact structure. The dielectric material includes a first dielectric material over the contact structure, a second dielectric material over the first dielectric material, and a third dielectric material over the second dielectric material. The dielectric material is patterned to form holes extending into the contact structure. Each of the holes includes a first width within a vertical boundary of the first dielectric material, a second width greater than the first width within a vertical boundary of the third dielectric material, and a plurality of widths within a vertical boundary of the second dielectric material. The plurality of widths increase from the first width near the first dielectric material to a relatively large width near the third dielectric material. A conductive structure is formed within the hole. The conductive structure substantially fills the hole and is in physical contact with the contact structure.

[0009] In another embodiment, a memory device includes a stacked structure, at least one source structure, a cell pillar structure, a cell contact structure, a conductive plug structure, and a digital line structure. The stacked structure includes a vertically alternating sequence of insulating and conductive structures. The at least one source structure is located below the stacked structure. The cell pillar structure extends vertically through the stacked structure and is coupled to the at least one source structure. The cell contact structure is coupled to the cell pillar structure. The conductive plug structure covers and is coupled to the cell contact structure. Each of the conductive plug structures includes a first portion having a first horizontal boundary extending substantially perpendicular to the upper surface of the cell contact structure, a second portion covering the first portion and having a second horizontal boundary exhibiting a rounded concave shape, and a third portion covering the second portion and having a third horizontal boundary extending substantially perpendicular to the upper surface of the cell contact structure. The digital line structure covers and is coupled to the conductive plug structure.

[0010] In another embodiment, an electronic system includes an input device, an output device, a processor device operatively coupled to the input device and the output device, and a memory device operatively coupled to the processor device. The memory device includes at least one microelectronic device structure comprising a vertically extending string of memory cells coupled to an access line structure and at least one source structure, a conductive structure covering and coupled to the vertically extending string of memory cells, and a digital line structure covering and coupled to the conductive structure. Each of the conductive structures includes a lower portion having a first width, an upper portion having a second width greater than the first width, and an intermediate portion between the lower portion and the upper portion having a horizontal boundary that presents a concave arcuate shape defining an additional width that varies from the first width near the lower portion to a relatively larger width near the upper portion. Attached Figure Description

[0011] Figures 1A to 1I This is a partial cross-sectional view illustrating a method of forming a microelectronic device according to an embodiment of the present disclosure.

[0012] Figure 2 This is a simplified partial cross-sectional perspective view of a microelectronic device according to an embodiment of the present disclosure.

[0013] Figure 3 This is a schematic block diagram illustrating an electronic system according to an embodiment of the present disclosure. Detailed Implementation

[0014] The following description provides specific details, such as material composition, shape, and size, to provide a comprehensive description of embodiments of this disclosure. However, those skilled in the art will understand that embodiments of this disclosure can be implemented without these specific details. In fact, embodiments of this disclosure can be implemented in conjunction with conventional microelectronic device manufacturing techniques used in industry. Furthermore, the description provided below does not form a complete process flow for manufacturing microelectronic devices (e.g., memory devices). The structures described below do not form a complete microelectronic device. Only those process actions and structures necessary for understanding embodiments of this disclosure are described in detail below. Additional actions to form a complete microelectronic device from the structures can be performed using conventional manufacturing techniques.

[0015] The accompanying drawings shown herein are for illustrative purposes only and are not intended to be actual views of any particular material, component, structure, device, or system. Variations in the shapes depicted in the drawings are expected as a result of, for example, manufacturing techniques and / or tolerances. Therefore, the embodiments described herein should not be construed as limited to the specific shapes or areas shown, but rather include, for example, shape deviations due to manufacturing processes. For example, areas shown or described as box-shaped may have rough and / or non-linear characteristics, while areas shown or described as circular may contain some rough and / or linear characteristics. Furthermore, acute angles shown may be rounded, and vice versa. Therefore, the areas shown in the drawings are schematic in nature, and their shapes are not intended to show the precise shapes of the areas and do not limit the scope of the claims. The drawings are not necessarily drawn to scale. Additionally, elements common to each other in the drawings may retain the same numerical designations.

[0016] As used herein, the term "substrate" means and includes the base material or structure on which additional material is formed. A substrate can be a semiconductor substrate, a base semiconductor layer on a support structure, a metal electrode, or a semiconductor substrate on which one or more layers, structures, or regions are formed. A substrate can be a conventional silicon substrate or other bulk substrate that includes layers of semiconductor material. As used herein, the term "bulk substrate" means and includes not only silicon wafers, but also silicon-on-insulator (SOI) substrates, such as silicon-on-sapphire (SOS) and silicon-on-glass ("SOG") substrates, silicon epitaxial layers on a base semiconductor substrate, and other semiconductor or optoelectronic materials such as silicon-germanium, germanium, gallium arsenide, gallium nitride, and indium phosphide. Substrates can be doped or undoped. As a non-limiting example, the substrate may include at least one of silicon, silicon dioxide, silicon having a natural oxide, silicon nitride, silicon carbonitride, glass, semiconductor, metal oxide, metal, titanium nitride, titanium carbonitride, tantalum, tantalum nitride, tantalum carbonitride, niobium, niobium nitride, niobium carbonitride, molybdenum, molybdenum nitride, molybdenum carbonitride, tungsten, tungsten nitride, tungsten carbonitride, copper, cobalt, nickel, iron, aluminum, and noble metals.

[0017] As used herein, the term "memory device" means and includes microelectronic devices that present memory functions, but is not necessarily limited to memory functions. In other words, and only as a non-limiting example, the term "memory device" includes not only conventional memory (e.g., conventional volatile memory such as conventional dynamic random access memory (DRAM); conventional non-volatile memory such as conventional NAND memory), but also application-specific integrated circuits (ASICs) (e.g., system-on-a-chip (SoC)), microelectronic devices that combine logic and memory, and graphics processing units (GPUs) incorporating memory.

[0018] As used herein, the term “configured” refers to the size, shape, material composition, orientation, and arrangement of one or more of at least one structure and at least one device to facilitate operation of one or more of the structure and device in a predetermined manner.

[0019] As used herein, the terms “vertical,” “longitudinal,” “horizontal,” and “lateral” refer to the principal plane of the structure and are not necessarily defined by the Earth’s gravitational field. A “horizontal” or “lateral” direction is a direction substantially parallel to the principal plane of the structure, while a “vertical” or “longitudinal” direction is a direction substantially perpendicular to the principal plane of the structure. The principal plane of the structure is defined by a surface of the structure that has a relatively large area compared to the other surfaces of the structure. Referring to the accompanying drawings, a “horizontal” or “lateral” direction may be perpendicular to the indicated “Z” axis and may be parallel to the indicated “X” axis and / or parallel to the indicated “Y” axis; and a “vertical” or “longitudinal” direction may be parallel to the indicated “Z” axis, perpendicular to the indicated “X” axis, and perpendicular to the indicated “Y” axis.

[0020] As used herein, features described as “adjacent” to each other (e.g., regions, structures, devices) refer to and include the features that are closest to each other among the disclosed identities (or identities). Additional features (e.g., additional regions, additional structures, additional devices) that do not match the disclosed identities (or identities) of the “adjacent” features may be positioned between the “adjacent” features. In other words, “adjacent” features may be positioned directly adjacent to each other such that no other features intervene between the “adjacent” features; or “adjacent” features may be positioned indirectly adjacent to each other such that at least one feature having an identity different from that associated with at least one “adjacent” feature is located between the “adjacent” features. Thus, features described as “vertically adjacent” to each other refer to and include features of the disclosed identities (or identities) that are closest to each other in the vertical direction (e.g., closest in the vertical direction). Furthermore, features described as “horizontally adjacent” to each other refer to and include features of the disclosed identities (or identities) that are closest to each other in the horizontal direction (e.g., closest in the horizontal direction).

[0021] As used herein, spatially relative terms such as “below,” “under,” “below,” “bottom,” “above,” “above,” “top,” “front,” “back,” “left,” “right,” etc., are used to facilitate the description of the relationship of an element or feature to other elements or features shown in the figures. Unless otherwise stated, spatially relative terms are intended to cover different orientations of material other than those depicted in the figures. For example, if the material in the figures is inverted, an element described as “below,” “under,” “below,” or “bottom” of other elements or features would be oriented as “above” or “top” of other elements or features. Thus, the term “below” can cover both above and below orientations, depending on the context in which the term is used, as will be apparent to those skilled in the art. Material may be oriented in other ways (e.g., rotated 90 degrees, inverted, flipped), and the spatially relative descriptors used herein are interpreted accordingly.

[0022] As used herein, unless the context clearly indicates otherwise, the singular forms “a, an” and “the” are intended to also include the plural forms.

[0023] As used in this article, "and / or" includes any and all combinations of one or more of the associated listed items.

[0024] As used herein, the phrase “coupled to” refers to structures that are operatively connected to each other, such as by direct ohmic connection or by indirect connection (e.g., via another structure) electrical connection.

[0025] As used herein, the term "substantially" with respect to a given parameter, property, or condition means and includes, to the extent that a person skilled in the art will understand, that the given parameter, property, or condition satisfies a certain degree of variation, such as within acceptable tolerances. As an example, depending on the specific parameter, property, or condition being substantially satisfied, the parameter, property, or condition may satisfy at least 90.0%, at least 95.0%, at least 99.0%, at least 99.9%, or even 100.0%.

[0026] As used herein, the term "about" or "approximately" with respect to a particular parameter includes the value and the degree of deviation from that value, which will be understood by one of ordinary skill in the art to be within acceptable tolerances for that particular parameter. For example, "about" or "approximately" with respect to a value may include additional values ​​within the range of 90.0% to 110.0% of the value, such as within the range of 95.0% to 105.0%, 97.5% to 102.5%, 99.0% to 101.0%, 99.5% to 100.5%, or 99.9% to 100.1%.

[0027] As used herein, “conductive material” means and includes conductive materials such as metals (e.g., tungsten (W), titanium (Ti), molybdenum (Mo), niobium (Nb), vanadium (V), hafnium (Hf), tantalum (Ta), chromium (Cr), zirconium (Zr), iron (Fe), ruthenium (Ru), osmium (Os), cobalt (Co), rhodium (Rh), iridium (Ir), nickel (Ni), palladium (Pa), platinum (Pt), copper (Cu), silver (Ag), gold (Au), aluminum (Al)) and alloys (e.g., Co-based alloys, Fe-based alloys). The term "conductive structure" refers to and includes one or more of the following: gold, Ni-based alloys, Fe, Ni-based alloys, Co, Ni-based alloys, Fe, Co-based alloys, Co, Ni, Fe-based alloys, Al-based alloys, Cu-based alloys, magnesium (Mg)-based alloys, Ti-based alloys, steel, low-carbon steel, and stainless steel; conductive materials containing metals (e.g., conductive metal nitrides, conductive metal silicides, conductive metal carbides, and conductive metal oxides); and conductive doped semiconductor materials (e.g., conductive doped polycrystalline silicon, conductive doped germanium (Ge), and conductive doped silicon-germanium (SiGe)). Furthermore, "conductive structure" means and includes structures formed from and containing conductive materials.

[0028] As used herein, “insulating material” means and includes electrically insulating materials, such as one or more of the following: at least one dielectric oxide material (e.g., silicon oxide (SiO2)). x Phosphorus silicate glass, borosilicate glass, borosilicate-phosphorus silicate glass, fluorosilicate glass, alumina (AlO) x ), Hafnium oxide (HfO) x ), niobium oxide (NbO) x Titanium oxide (TiO) x Zirconium oxide (ZrO) x ), tantalum oxide (TaO) x ) and magnesium oxide (MgO) x One or more of the following), at least one dielectric nitride material (e.g., silicon nitride (SiN) y()), at least one dielectric oxide nitride material (e.g., silicon oxynitride (SiO2) x N y and at least one dielectric carbon oxynitride material (e.g., silicon carbon oxynitride (SiO2)). x C z N y This text contains one or more of the formulas “x”, “y”, and “z” (e.g., SiO2). x AlO x HfO x NbO x TiO x SiN y SiO x N y SiO x C z N y An insulating material is defined as having, for each atom of another element (e.g., Si, Al, Hf, Nb, Ti), an average ratio of “x” atoms of one element, “y” atoms of another element, and “z” atoms of an additional element (if any). Because these formulas represent relative atomic ratios rather than strict chemical structures, insulating materials can include one or more stoichiometric compounds and / or one or more non-stoichiometric compounds, and the values ​​of “x,” “y,” and “z” (if any) can be integers or non-integers. As used herein, the term “non-stoichiometric compound” means and includes chemical compounds composed of elements that cannot be expressed by a ratio of well-defined natural numbers and violate the law of definite proportions. Additionally, “insulating structure” means and includes structures formed by and containing insulating materials.

[0029] As used herein, the term "homogeneous" means that the relative amounts of elements contained in a feature (e.g., material, structure) do not vary across different parts of the feature (e.g., different horizontal parts, different vertical parts). Conversely, as used herein, the term "heterogeneous" means that the relative amounts of elements contained in a feature (e.g., material, structure) vary across different parts of the feature. If a feature is heterogeneous, the amounts of one or more elements contained in the feature may vary gradually (e.g., abruptly) or may vary continuously across different parts of the feature (e.g., gradually, such as linearly, parabolically). For example, the feature may be formed by and contain a stack of at least two different materials.

[0030] Unless the context otherwise indicates, the materials described herein can be formed by any suitable technique, including but not limited to spin coating, blanket coating, chemical vapor deposition (CVD), plasma-enhanced CVD (PECVD), atomic layer deposition (ALD), plasma-enhanced ALD (PEALD), physical vapor deposition (PVD) (e.g., sputtering), or epitaxial growth. Depending on the specific material to be formed, a person skilled in the art may choose the technique for depositing or growing the material. Furthermore, unless the context otherwise indicates, the removal of the materials described herein can be achieved by any suitable technique, including but not limited to etching (e.g., dry etching, wet etching, vapor phase etching), ion milling, planarization (e.g., chemical mechanical planarization (CMP)), or other known methods.

[0031] Figures 1A to 1I This is a simplified partial cross-sectional view illustrating an embodiment of a method for forming a microelectronic device (e.g., a memory device, such as a 3D NAND flash memory device). Compared to conventional configurations, the microelectronic device formed by the method of this disclosure may include a configuration that reduces capacitive coupling between conductive structures (e.g., conductive contact structures, conductive plug structures). Compared to conventional microelectronic devices formed by conventional methods, the microelectronic device formed by the method of this disclosure may have reduced wire (e.g., digital line, bit line) capacitance. From the description provided below, it will be apparent to those skilled in the art that the methods and structures described herein can be used in a variety of devices and electronic systems.

[0032] refer to Figure 1A The microelectronic device structure 100 may be formed to include: a unit pillar structure 102; pillar contact structures 104 on, above, and / or inside the unit pillar structure 102 (e.g., in the Z direction); a first dielectric material 106 surrounding the unit pillar structure 102 and the pillar contact structures 104; a second dielectric material 108 on or above the first dielectric material 106; a third dielectric material 110 on or above the second dielectric material 108; a first masking material 112 on or above the third dielectric material 110; and a second masking material 114 on or above the first masking material 112. As described in further detail below, the unit pillar structure 102 may extend vertically (e.g., in the Z direction) through a stacked structure located vertically below the first dielectric material 106, wherein the stacked structure includes a vertically alternating sequence of conductive structures (e.g., access line structures, word line structures) and insulating structures disposed in layers, each layer comprising at least one conductive structure and at least one insulating structure.

[0033] The cell pillar structure 102 may be formed and comprised of a plurality of materials that facilitate the formation of vertically extending (e.g., in the Z direction) memory cell strings. As a non-limiting example, each of the cell pillar structures 102 may be formed to comprise a charge-blocking material, a charge-trapping material, a tunneling dielectric material, a channel material, and a dielectric filler material. The dielectric filler material may be horizontally surrounded outward by the channel material; the channel material may be horizontally surrounded outward by the tunneling dielectric material; the tunneling dielectric material may be horizontally surrounded outward by the charge-trapping material; and the charge-trapping material may be horizontally surrounded outward by the charge-blocking material. For example, the charge-blocking material may be formed and comprised of a first dielectric oxide material, such as SiO₂. x One or more of SiO2 (e.g., SiO2) and AlOx (e.g., Al2O3). For example, the charge trapping material may be formed of and contain a dielectric nitride material, such as SiN. y (For example, Si3N4). For instance, the tunneling dielectric material may be formed from and contain a second oxide dielectric material, such as SiO2. x (e.g., SiO2). For example, the channel material may be formed of and contain a semiconductor material, such as one or more silicon (e.g., polycrystalline silicon), germanium, silicon-germanium, and oxide semiconductor materials (e.g., zinc tin oxide (ZnO2)). x Sn y O, commonly known as "ZTO"), indium zinc oxide (In x Zn y O, commonly known as "IZO"), zinc oxide (Zn) x O), Indium gallium zinc oxide (In x Ga y Zn z O, commonly known as "IGZO"), indium gallium silicon oxide (In) x Ga y Si z O, commonly known as "IGSO"), indium tungsten oxide (In) x W y O, commonly known as "IWO"), indium oxide (In) x O), tin oxide (Sn) x O), titanium dioxide (Ti) x O), zinc oxide nitride (Zn) x ON z ), magnesium zinc oxide (Mg x Zn y O), Zirconia indium zinc (Zr) x In y Zn z O), hafnium indium zinc oxide (Hf) x In y Zn zO), tin indium zinc oxide (Sn) x In y Zn z O), aluminum tin indium zinc (Al) x Sn y In z Zn a O), silicon indium zinc (Si) x In y Zn z O), aluminum zinc tin oxide (Al) x Zn y Sn z O), gallium zinc tin oxide (Ga) x Zn y Sn z O), Zirconia zinc tin (Zr) x Zn y Sn z (O) and one or more other similar materials). For example, the dielectric filling material may be formed from one or more of dielectric oxide materials, dielectric nitride materials and air, and may contain one or more of dielectric oxide materials, dielectric nitride materials and air.

[0034] See below for reference Figure 2 In further detail, the intersection of the unit pillar structure 102 with the conductive structure of the stacked structure located vertically below the first dielectric material 106 defines a vertically extending string of memory cells coupled in series with each other within the stacked structure. In some embodiments, the memory cells formed at the intersection of the conductive structure within each layer of the stacked structure and the unit pillar structure 102 include so-called "MONOS" (metal-oxide-nitride-oxide-semiconductor) memory cells. In additional embodiments, the memory cells include so-called "TANOS" (tantalum nitride-alumina-nitride-oxide-semiconductor) memory cells or so-called "BETANOS" (band / barrier engineered TANOS) memory cells, each of which is a subset of MONOS memory cells. In another embodiment, the memory cells include so-called "floating gate" memory cells, which include a floating gate (e.g., a metal floating gate) as a charge storage structure. The floating gate may be horizontally positioned between the central structure of the unit pillar structure 102 and the conductive structures of different layers of the stacked structure.

[0035] The column contact structure 104 can contact (e.g., physical contact, electrical contact) the channel material of the unit column structure 102. For example... Figure 1AAs shown, in some embodiments, the column contact structure 104 extends at least partially (e.g., substantially) vertically into the unit column structure 102. For a single column contact structure 104, at least a portion may be positioned within the vertical boundary of the single unit column structure 102 and may be horizontally surrounded and contacted (e.g., physically or electrically) by the channel material at the inner horizontal boundary (e.g., inner sidewall) of the channel material of the unit column structure 102. In some embodiments, the highest vertical boundary (e.g., uppermost surface) of the column contact structure 104 is substantially coplanar with the highest vertical boundary (e.g., uppermost surface) of the unit column structure 102. In additional embodiments, one or more of the highest vertical boundaries of the column contact structures 104 deviate from (e.g., vertically overlap) the highest vertical boundary of the unit column structure 102. For example, for a single column contact structure 104, its vertical upper portion may be vertically positioned above the highest vertical boundary of the unit column structure 102 it contacts. For example, the upper vertical portion of a single column contact structure 104 may extend horizontally beyond the horizontal boundary of the lower vertical portion of a single unit column structure 102 within the vertical boundary of the column contact structure 104, and may contact (e.g., physical contact, electrical contact) the channel material at the highest vertical boundary of the channel material of the single unit column structure 102.

[0036] The pillar contact structure 104 may be formed of and contain a conductive material. As a non-limiting example, each pillar contact structure 104 may be formed of one or more of at least one conductive doped semiconductor material, at least one metal, at least one alloy, and at least one metal-containing conductive material (e.g., conductive metal nitride, conductive metal silicide, conductive metal carbide, conductive metal oxide), and contain one or more of the aforementioned materials. In some embodiments, each pillar contact structure 104 is formed of and contains polysilicon doped with one or more conductivity-enhancing dopants (e.g., one or more N-type dopants, one or more P-type dopants). Each pillar contact structure 104 may be substantially homogeneous, or one or more pillar contact structures 104 may be heterogeneous.

[0037] Still referencing Figure 1AA first dielectric material 106 may be formed to cover and surround portions of the unit pillar structure 102 and the pillar contact structure 104. The highest vertical boundary (e.g., the uppermost surface) of the first dielectric material 106 may vertically cover the highest vertical boundary (e.g., the uppermost surface) of the unit pillar structure 102 and the pillar contact structure 104. The first dielectric material 106 may substantially surround and physically contact the upper portion of the outer surface (e.g., the outer wall) of the unit pillar structure 102, and may also substantially cover and physically contact the upper surface of the pillar contact structure 104. The first dielectric material 106 may also substantially cover and physically contact the upper surface of the unit pillar structure 102, which is substantially coplanar with the upper surface of the pillar contact structure 104. The lower vertical boundary (e.g., the lower surface) of the first dielectric material 106 may be non-planar, and the upper vertical boundary (e.g., the upper surface) may be substantially planar.

[0038] The first dielectric material 106 may be formed of and comprise at least one insulating material. As a non-limiting example, the first dielectric material 106 may be formed of at least one dielectric oxide material (e.g., SiO₂). x Phosphorosilicate glass, borosilicate glass, borosilicate-phosphorosilicate glass, fluorosilicate glass, AlO x HfO x NbO x TiO x ZrO x TaO x and MgO x One or more of the following), at least one dielectric nitride material (e.g., SiN). y ), and at least one dielectric oxide nitride material (e.g., SiO2). x N y ), and at least one dielectric carbon oxide material (e.g., SiO2). x C y ), and at least one hydrogenated dielectric carbon oxide material (e.g., SiC) x O y H z and at least one dielectric carbonitride material (e.g., SiO2) x C z N y One or more of the above materials are formed and comprise one or more of the aforementioned materials. In some embodiments, the first dielectric material 106 is formed of and comprises at least one dielectric oxide material, such as SiO2. x (For example, SiO2). The first dielectric material 106 can be substantially homogeneous, or the first dielectric material 106 can be heterogeneous.

[0039] The second dielectric material 108 may be formed of and contain at least one additional insulating material, which may be selectively removed relative to the first dielectric material 106 (as described in further detail below). The material composition of the second dielectric material 108 differs from that of the first dielectric material 106. The second dielectric material 108 may be selectively etched relative to the first dielectric material 106 during common (e.g., collective, mutual) exposure to a first etchant; and the first dielectric material 106 may be selectively etched relative to the second dielectric material 108 during common exposure to a different second etchant. As used herein, a material is “selectively etchable” relative to another material if its etch rate is at least about five times (5X) (e.g., about ten times (10X), about twenty times (20X), or about forty times (40X)) the etch rate of another material. As a non-limiting example, the second dielectric material 108 may be formed of at least one dielectric oxide material (e.g., SiO2) depending on the material composition of the first dielectric material 106. x Phosphorosilicate glass, borosilicate glass, borosilicate-phosphorosilicate glass, fluorosilicate glass, AlO x HfO x NbO x TiO x ZrO x TaO x and MgO x (at least one or more of) at least one dielectric nitride material (e.g., SiN) y ), and at least one dielectric oxide nitride material (e.g., SiO2). x N y ), and at least one dielectric carbon oxide material (e.g., SiO2). x C y ), and at least one hydrogenated dielectric carbon oxide material (e.g., SiC) x O y H z and at least one dielectric carbonitride material (e.g., SiO2) x C z N y It is formed of one or more of the above materials and comprises one or more of the above materials. In some embodiments, such as in which the first dielectric material 106 is composed of a dielectric oxide material (e.g., SiO2). x In embodiments where the dielectric oxide material is formed and includes the dielectric oxide material (e.g., SiO2), the second dielectric material 108 is formed of a dielectric nitride material (e.g., SiN). y The dielectric nitride material 108 is formed and contains a dielectric nitride material, such as Si3N4. The second dielectric material 108 may be substantially homogeneous or heterogeneous.

[0040] The third dielectric material 110 may be formed of and contain at least one additional insulating material, which may be selectively removed relative to the second dielectric material 108 (as described in further detail below). The material composition of the third dielectric material 110 differs from that of the second dielectric material 108. The third dielectric material 110 may be selectively etched relative to the second dielectric material 108 during co-exposure (e.g., co-existing, co-existing) to the first etchant; and the second dielectric material 108 may be selectively etched relative to the third dielectric material 110 during co-exposure to a different second etchant. The material composition of the third dielectric material 110 may be substantially the same as that of the first dielectric material 106, or the material composition of the third dielectric material 110 may differ from that of the first dielectric material 106. As a non-limiting example, depending on the material composition of the second dielectric material 108, the third dielectric material 110 may be formed of at least one dielectric oxide material (e.g., SiO2). x Phosphorosilicate glass, borosilicate glass, borosilicate-phosphorosilicate glass, fluorosilicate glass, AlO x HfO x NbO x TiO x ZrO x TaO x and MgO x (at least one or more of) at least one dielectric nitride material (e.g., SiN) y ), and at least one dielectric oxide nitride material (e.g., SiO2). x N y ), and at least one dielectric carbon oxide material (e.g., SiO2). x C y ), and at least one hydrogenated dielectric carbon oxide material (e.g., SiC) x O y H z and at least one dielectric carbonitride material (e.g., SiO2) x C z N y It is formed of one or more of the above materials and comprises one or more of the above materials. In some embodiments, such as where the second dielectric material 108 is composed of a dielectric nitride material (e.g., SiN), y In embodiments where the dielectric nitride material is formed and includes the dielectric nitride material (e.g., Si3N4), the third dielectric material 110 is formed and includes the dielectric oxide material (e.g., SiO2). x (e.g., SiO2). The third dielectric material 110 can be substantially homogeneous, or the third dielectric material 110 can be heterogeneous.

[0041] As described in further detail below, the first masking material 112 may be formed of and contain at least one material (e.g., at least one hard mask material) suitable for use as an etching mask to pattern portions of the third dielectric material 110, the second dielectric material 108, and the first dielectric material 106 to form holes (e.g., openings, vias) that extend vertically into the pillar contact structure 104 and have a desired geometry (e.g., shape, size). As a non-limiting example, the first masking material 112 may be formed of and contain one or more hard mask materials that have etch selectivity relative to the materials of the third dielectric material 110, the second dielectric material 108, and the first dielectric material 106. In some embodiments, the first masking material 112 is formed from one or more of amorphous carbon and doped amorphous carbon (e.g., boron-doped amorphous carbon, such as boron-doped amorphous carbon comprising at least 1 wt% boron and at least 20 wt% carbon, such as boron between about 1 wt% and about 40 wt%, and carbon between about 99 wt% and about 60 wt%) and contains the aforementioned materials. The first masking material 112 may be substantially homogeneous, or the first masking material 112 may be heterogeneous.

[0042] As described in further detail below, the second masking material 114 may be formed of and comprise at least one material (e.g., at least one photoresist material) suitable for use as an etching mask to pattern portions of the first masking material 112. As a non-limiting example, the second masking material 114 may be formed of and comprise at least one photoresist material, such as a positive or negative photoresist material. If the second masking material 114 comprises a positive photoresist material, the second masking material 114 may be formulated such that areas exposed to at least a minimum threshold dose of electromagnetic radiation and optionally baked after exposure become at least partially soluble in a suitable developer (e.g., a positive developer). The exposed areas of the second masking material 114 (e.g., areas exposed to a minimum threshold dose of electromagnetic radiation) may be at least partially (e.g., substantially) removed by the developer, while unexposed areas (e.g., areas not exposed to a minimum threshold dose of electromagnetic radiation) may remain substantially intact (e.g., substantially unremoved). Alternatively, if the second masking material 114 comprises a negative photoresist material, the second masking material 114 may be formulated such that regions of it not exposed to at least a minimum threshold dose of electromagnetic radiation are at least partially soluble in a suitable developer (e.g., a negative developer). The unexposed regions of the second masking material 114 may be at least partially (e.g., substantially) removed by the developer, while the exposed regions may remain substantially intact (e.g., substantially unremoved). As described in further detail below, the properties (e.g., characteristics) of the second masking material 114 may be selected relative to the material composition of the first masking material 112 to facilitate the desired patterning of the first masking material 112. Suitable photoresist materials (e.g., positive photoresist materials, negative photoresist materials) are known in the art and therefore will not be described in detail herein. The second masking material 114 may, for example, be compatible with wavelength systems of 13.7 nm, 157 nm, 193 nm, 248 nm, or 365 nm; have a 193 nm wavelength immersion system; and / or have an electron beam lithography system. The second masking material 114 can be substantially homogeneous, or the second masking material 114 can be heterogeneous.

[0043] Next reference Figure 1B Second shielding material 114 ( Figure 1A The first masking material 112 may be subjected to at least one patterning and material removal process to form a first opening 116 (e.g., a hole, a through hole) extending vertically through the first masking material 112. Figure 1BAs shown, a first opening 116 extends vertically (e.g., in the Z direction) from the highest vertical boundary (e.g., the uppermost surface) of the first masking material 112 through the first masking material 112 to its lowest vertical boundary (e.g., the lowermost surface). The first opening 116 extends vertically to portions of a third dielectric material 110 located beneath the first masking material 112 and exposes these portions. The exposed portions of the third dielectric material 110 define the lowest vertical boundary (e.g., bottom surface, base) of the first opening 116. Figure 1B As shown, after the first opening 116 is formed in the first masking material 112, the second masking material 114 can be substantially removed. Figure 1A The remaining portion (if any) is used to expose the upper surface of the first masking material 112.

[0044] The geometry (e.g., shape, size), horizontal position (e.g., in the X and Y directions), and horizontal spacing of each of the first openings 116 formed in the first masking material 112 depend at least in part on the geometry, horizontal position, and horizontal spacing of the pillar contact structure 104 and the unit pillar structure 102. The first openings 116 may be formed to be at least partially horizontally aligned (e.g., in the X and Y directions) with the pillar contact structure 104 and the unit pillar structure 102. Additionally, the first openings 116 may be formed such that their horizontal dimensions (e.g., in the X and Y directions) are less than or equal to the corresponding horizontal dimensions of the unit pillar structure 102 (e.g., less than or equal to the corresponding horizontal dimensions of the pillar contact structure 104). Figure 1B As shown, in some embodiments, the horizontal center of the first opening 116 is formed to be substantially horizontally aligned with the horizontal center of the column contact structure 104. Additionally, as also... Figure 1B As shown, in some embodiments, the width W1 (e.g., diameter) of each of the first openings 116 is formed to be smaller than the width of the column contact structure 104 which is at least partially (e.g., substantially) horizontally aligned with it.

[0045] In some embodiments, the first openings 116 are formed to present substantially the same geometry as each other (e.g., substantially the same shape and substantially the same size). For example, each of the first openings 116 may be formed to present a substantially circular horizontal cross-sectional shape and may have a width W1 (e.g., diameter) substantially the same as that of the first openings 116. In other embodiments, one or more of the first openings 116 are formed to present a different geometry than one or more other first openings 116 (e.g., a different shape, such as a non-circular horizontal cross-sectional shape; and / or a different size, such as a smaller or larger width). For example, one or more of the first openings 116 may be formed to present a width different from (e.g., greater than or less than) the width W1.

[0046] The second masking material 114 can be patterned (e.g., by photolithographic patterning through selective exposure and development). Figure 1A The first opening 116 is formed in the first masking material 112, and then the second masking material 114 is removed by at least one first material removal process (e.g., at least one first etching process, such as at least one first anisotropic etching process). Figure 1A The resulting pattern is transferred to the first masking material 112. Afterwards, the second masking material 114 can be removed. Figure 1A The remainder (if any).

[0047] Next reference Figure 1C The third dielectric material 110 can be removed from the first opening 116 ( Figure 1B The portion within the horizontal boundary of ) extends the first opening 116 ( Figure 1B The vertical depth of ) and forms a second opening 118. For example Figure 1C As shown, the second opening 118 may have the same characteristics as the first opening 116. Figure 1B The second opening 118 may be formed to extend vertically to and expose a portion of the second dielectric material 108 located below the third dielectric material 110, having substantially the same horizontal dimensions (e.g., substantially the same width W1 in both the X and Y directions) and extending vertically (in the Z direction) completely through the third dielectric material 110. The exposed portion of the second dielectric material 108 may define the lowest vertical boundary (e.g., bottom surface, base) of the second opening 118. Figure 1C As shown, in some embodiments, the second opening 118 is formed to extend vertically into the second dielectric material 108 such that the lower vertical boundary of the second opening 118 lies within the vertical boundary of the second dielectric material 108 (e.g., between the lowest and highest vertical boundaries). In additional embodiments, the second opening 118 is formed to terminate vertically at the highest vertical boundary (e.g., the uppermost surface) of the second dielectric material 108 such that the lower vertical boundary of the second opening 118 is substantially coplanar with the highest vertical boundary of the second dielectric material 108.

[0048] The second opening 118 can be processed by employing at least one second material removal process. Figure 1BThe microelectronic device structure 100 is formed by the processing stage depicted in the diagram. For example, the second material removal process may include at least one anisotropic etching process (e.g., anisotropic dry etching processes such as reactive ion etching (RIE), deep RIE, plasma etching, reactive ion beam etching, chemically assisted ion beam etching; and anisotropic wet etching processes) employing at least one etchant that is more selective for the third dielectric material 110 than the first masking material 112 and the second dielectric material 108. The second material removal process may remove the third dielectric material 110 from the first opening 116 ( Figure 1B The portion within the horizontal boundary of the first masking material 112 is essentially not removed from the previous reference. Figure 1B The portion remaining after the described processing stage. The second dielectric material 108 can serve as the so-called "etch-stop" material for the second material removal process.

[0049] Next reference Figure 1D The additional portion of the third dielectric material 110 can be removed to horizontally expand (e.g., horizontally widen) the second opening 118. Figure 1C And form a third opening 120. (For example...) Figure 1D As shown, the third opening 120 may present a second opening 118 within the vertical boundary (e.g., in the Z direction) of the first masking material 112. Figure 1C The horizontal dimensions are substantially the same (e.g., in the X and Y directions) and may present a second opening 118 within the vertical boundary of the third dielectric material 110. Figure 1C Larger (e.g., larger, wider) horizontal dimensions. For example, such as Figure 1D As shown, the third opening 120 may have a second opening 118 within the vertical boundary of the first masking material 112. Figure 1C The second opening 118 has a substantially the same width W1, and may each have an additional width W2 greater than the width W1 within the vertical boundary of the third dielectric material 110. The third opening 120 may be included in an undercut region 120A extending horizontally below the first masking material 112. The undercut region 120A may extend horizontally outward beyond the second opening 118. Figure 1C The width W1 extends to an additional width W2 that defines the horizontal dimension of the third opening 120 within the third dielectric material 110. The lower vertical boundary of the undercut region 120A of the third opening 120 may be defined by the upper vertical boundary (e.g., upper surface) of the second dielectric material 108, and the upper vertical boundary of the undercut region 120A of the third opening 120 may be defined by the lower vertical boundary (e.g., lower surface) of the first masking material 112.

[0050] The third opening 120 can be processed by employing at least one third material removal process. Figure 1CThe microelectronic device structure 100 is formed according to the processing stages depicted herein. For example, the third material removal process may include an isotropic etching process employing at least one etchant that is more selective for the third dielectric material 110 than the first masking material 112 and the second dielectric material 108. In some embodiments, such as where the third dielectric material 110 comprises a dielectric oxide material (e.g., SiO2), x In embodiments such as SiO2, the etchant includes hydrofluoric acid (HF). A third material removal process can remove the third dielectric material 110 from the second opening 118 ( Figure 1C The portion outside the horizontal boundary of the first masking material 112 and the second dielectric material 108 are essentially not removed from the previous reference. Figure 1C The part remaining after the described processing stage.

[0051] Next reference Figure 1E The second dielectric material 108 can be removed from the first opening 116. Figure 1B The portion within the horizontal boundary of the third opening 120 () extends to the third opening. Figure 1D The fourth opening 122 is formed by extending vertically (in the Z direction) completely through the second dielectric material 108. The fourth opening 122 may expose a portion of the first dielectric material 106 located beneath the second dielectric material 108. The exposed portion of the first dielectric material 106 may define the lowest vertical boundary (e.g., bottom surface, base) of the fourth opening 122. Figure 1E As shown, in some embodiments, the fourth opening 122 is formed to extend vertically into the first dielectric material 106 such that the lowest vertical boundary of the fourth opening 122 lies within the vertical boundary of the first dielectric material 106 (e.g., between the lowest and highest vertical boundaries). In additional embodiments, the fourth opening 122 is formed to terminate vertically at the highest vertical boundary of the first dielectric material 106 (e.g., the uppermost surface), such that the lower vertical boundary of the fourth opening 122 is substantially coplanar with the highest vertical boundary of the first dielectric material 106.

[0052] like Figure 1E As shown, the fourth opening 122 may present a third opening 120 within the vertical boundary (e.g., in the Z direction) of the first masking material 112 and the third dielectric material 110. Figure 1D The fourth opening 122 may have substantially the same horizontal dimensions (e.g., in the X and Y directions) as the first opening 116 within the vertical boundary of the second dielectric material 108. Figure 1BThe lower vertical portion of the fourth opening 122 within the vertical boundary of the second dielectric material 108 may have a horizontal dimension substantially the same as the upper vertical portion of the fourth opening 122 within the vertical boundary of the first masking material 112, and may have a smaller (e.g., narrower) horizontal dimension than the centrally located portion of the fourth opening 122 within the vertical boundary of the third dielectric material 110. For example, as Figure 1E As shown, the fourth opening 122 can present the width W1 within the vertical boundaries of the first masking material 112 and the second dielectric material 108, and can present an additional width W2 that is greater than the width W1 within the vertical boundaries of the third dielectric material 110.

[0053] The fourth opening 122 can be processed by employing at least one fourth material removal process. Figure 1D The microelectronic device structure 100 is formed by the processing stage depicted in the diagram. For example, the fourth material removal process may include an anisotropic etching process (e.g., anisotropic dry etching process, anisotropic wet etching process) that employs at least one etchant that is more selective for the second dielectric material 108 than each of the first masking material 112, the third dielectric material 110, and the first dielectric material 106. The fourth material removal process may remove the second dielectric material 108 from the first opening 116 ( Figure 1B The portion within the horizontal boundary of the first masking material 112 and the third dielectric material 110 is essentially not removed from the previously referenced portion. Figure 1D The remaining portion after the described processing stage. The first dielectric material 106 can serve as the so-called "etch-stop" material for the fourth material removal process.

[0054] Next reference Figure 1F The first dielectric material 106 can be removed from the first opening 116 ( Figure 1B The portion within the horizontal boundary of ) extends to the fourth opening 122 ( Figure 1E The fifth opening 124 is formed by extending vertically (in the Z direction) through a portion of the first dielectric material 106 of the vertical cover unit pillar structure 102. The fifth opening 124 may extend vertically to and expose a portion of the pillar contact structure 104. The exposed portion of the pillar contact structure 104 may at least partially (e.g., substantially) define the lowest vertical boundary (e.g., bottom surface, base) of the fifth opening 124. Figure 1FAs shown, in some embodiments, the fifth opening 124 is formed to terminate vertically at the highest vertical boundary (e.g., the uppermost surface) of the column contact structure 104, such that the lower vertical boundary of the fifth opening 124 is substantially coplanar with the highest vertical boundary of the column contact structure 104. In an additional embodiment, the fifth opening 124 is formed to extend vertically into the column contact structure 104, such that the lowest vertical boundary of the fifth opening 124 is within the vertical boundary of the column contact structure 104 (e.g., between the lowest and highest vertical boundaries).

[0055] like Figure 1E As shown, the fifth opening 124 can be presented in the same way as the fourth opening 120 ( Figure 1E The first masking material 112 and the third dielectric material 110 have substantially the same horizontal dimensions (e.g., in the X and Y directions) within their vertical boundaries (e.g., in the Z direction) and can be presented with the same dimensions as the first opening 116. Figure 1B The fifth opening 124 has substantially the same horizontal dimension within the vertical boundary of the first dielectric material 106. Additionally, within the vertical boundary of the second dielectric material 108, the fifth opening 124 may present a lower vertical region that is similar in size to the fourth opening 120. Figure 1E The horizontal dimensions within the vertical boundary of the second dielectric material 108 are substantially the same; and the vertical upper region presents a dimension greater than that of the fourth opening 120. Figure 1E The portion within the vertical boundary of the second dielectric material 108 has a larger (e.g., wider) horizontal dimension. The horizontal dimension of the upper vertical region can increase within the second dielectric material 108 in the vertical upward direction from a horizontal dimension substantially the same as the horizontal dimension of the portion of the fifth opening 124 within the vertical boundary of the first dielectric material 106 (e.g., width W1) to a relatively larger horizontal dimension that is closer to or even substantially the same as the horizontal dimension of other portions of the fifth opening 124 within the vertical boundary of the third dielectric material 110 (e.g., additional width W2). For example, as... Figure 1F As shown, the fourth opening 122 may have a width W1 within the vertical boundaries of the first masking material 112 and the first dielectric material 106, may have an additional width W2 greater than the width W1 within the vertical boundary of the third dielectric material 110, and may have different widths within the vertical boundary of the second dielectric material 108, increasing from the width W1 to the additional width W2 in the upward vertical direction (e.g., the positive Z direction).

[0056] like Figure 1FAs shown, within the vertical boundaries of the first masking material 112, the third dielectric material 110, and the first dielectric material 106, the fifth opening 124 may be formed to present a horizontal boundary oriented substantially perpendicular (e.g., orthogonal to) the upper vertical boundaries (e.g., upper surfaces) of the pillar contact structure 104 and the unit pillar structure 102. In other words, within the vertical boundaries of the first masking material 112, the third dielectric material 110, and the first dielectric material 106, the horizontal boundary of the fifth opening 124 may be oriented parallel to the horizontal boundaries (e.g., side surfaces, sidewalls) of the pillar contact structure 104 and the unit pillar structure 102. As used herein, the term "parallel" means substantially parallel. Additionally, within the vertical boundary of the second dielectric material 108, the fifth opening 124 may be formed to present a horizontal boundary that is at least partially not oriented perpendicular to the upper vertical boundaries of the pillar contact structure 104 and the unit pillar structure 102. For example, as... Figure 1F As depicted, within the vertical boundary of the second dielectric material 108, the fifth opening 124 may present an arcuate (e.g., rounded, circular, curved) horizontal boundary within one or more (e.g., all) vertically oriented (e.g., vertically extending) planes (such as the ZX plane (e.g., a plane defined by the Z and X directions) and / or the ZY plane (e.g., a plane defined by the Z and Y directions)). As described in further detail below, the arcuate profile of the fifth opening 124 within the vertical boundary of the second dielectric material 108 may be defined by an arcuate edge 126 (e.g., a rounded edge, a circular edge, a curved edge) of the second dielectric material 108, formed by a process (e.g., a material removal process) for forming the fifth opening 124.

[0057] The fifth opening 124 can be processed by employing at least one fifth material removal process. Figure 1E The microelectronic device structure 100 is formed by the processing stages depicted in the diagram. For example, the fifth material removal process may include an anisotropic etching process (e.g., anisotropic dry etching process, anisotropic wet etching process) employing at least one etchant that is more selective for the first dielectric material 106 than the second dielectric material 108 and the pillar contact structure 104. The pillar contact structure 104 may serve as a so-called "etch stop" structure for the fifth material removal process. Compared to the second dielectric material 108 at the fourth opening 122 ( Figure 1E For the exposed portion within the first dielectric material 106, the fifth material removal process can remove that portion at a relatively faster rate. However, removing (e.g., etching) a portion of the second dielectric material 108 during the fifth material removal process creates an arcuate edge 126 on the remaining portion of the second dielectric material 108, which provides a fifth opening 124 with an arcuate profile within the vertical boundary of the second dielectric material 108. Figure 1FAs shown, the fifth material removal process can also remove the upper vertical portion of the first masking material 112, so that the vertical thickness (e.g., vertical height) of the residue (e.g., the remaining portion) of the first masking material 112 after the fifth material removal process is smaller than the vertical thickness of the first masking material 112 before the fifth material removal process.

[0058] Next reference Figure 1G It can remove any residue (if any) of the first masking material 112, and can be used in the fifth opening 124 ( Figure 1F The remaining portion of the interior and exterior forms (e.g., non-conformally deposited) plugging material 128. The plugging material 128 can substantially fill the fifth opening 124. Figure 1F The remaining portion of the plug material 128 may present a substantially planar upper vertical boundary (e.g., upper surface) and a non-planar lower vertical boundary, which is at least partially formed by the surfaces (e.g., upper surface, side surface) of the third dielectric material 110, the second dielectric material 108, the first dielectric material 106, and the pillar contact structure 104 at the fifth opening 124. Figure 1F The boundary and external shape of the ) are defined.

[0059] The plug material 128 may be formed of and contain a conductive material. As a non-limiting example, the plug material 128 may be formed of one or more of at least one metal, at least one alloy, and at least one metal-containing conductive material (e.g., conductive metal nitride, conductive metal silicide, conductive metal carbide, conductive metal oxide), and may contain one or more of the aforementioned materials. The material composition of the plug material 128 may be substantially the same as the material composition of the pillar contact structure 104, or the material composition of the plug material 128 may be different from the material composition of the pillar contact structure 104. In some embodiments, the plug material 128 is formed of and contains W. The plug material 128 may be substantially homogeneous, or the plug material 128 may be heterogeneous.

[0060] The plug material 128 can be formed using conventional processes (e.g., conventional deposition processes) and conventional processing equipment, which are not described in detail herein. For example, the plug material 128 can be formed on or above the exposed portion of the microelectronic device structure 100 using one or more conventional non-conformal deposition processes (such as one or more of conventional non-conformal PVD and conventional non-conformal CVD processes).

[0061] Next reference Figure 1H Plug material 128 ( Figure 1GThe portion of the third dielectric material 110 covering its uppermost vertical boundary (e.g., uppermost surface) can be substantially removed to form the plug structure 130. The removal process can expose (e.g., reveal) the third dielectric material 110. The uppermost vertical boundary (e.g., uppermost surface) of the plug structure 130 can be formed to be substantially coplanar with the highest vertical boundary of the third dielectric material 110.

[0062] like Figure 1H As shown, each of the plug structures 130 may respectively include a first portion 130A (e.g., lower portion) perpendicularly adjacent to one of the pillar contact structures 104 and within the vertical boundary of the first dielectric material 106, a second portion 130B (e.g., middle portion) within the vertical boundary of the second dielectric material 108, and a third portion 130C (e.g., upper portion) within the vertical boundary of the third dielectric material 110. The second portion 130B may be perpendicularly inserted between the first portion 130A and the third portion 130C, and may be integral and continuous with the first portion 130A and the third portion 130C. As described in further detail below, the geometry (e.g., shape, size) of the plug structure 130 may correspond to (e.g., may be substantially the same as) the fifth opening 124 within the vertical boundaries of the first dielectric material 106, the second dielectric material 108, and the third dielectric material 110. Figure 1F The geometric configuration of ).

[0063] The first portion 130A and the third portion 130C of the plug structure 130 may have horizontal boundaries (e.g., side surfaces, sidewalls) oriented substantially perpendicular (e.g., orthogonal to) the upper vertical boundaries (e.g., upper surfaces) of the post contact structure 104 and the unit post structure 102. For each plug structure 130, the horizontal boundaries of its first portion 130A and third portion 130C may be oriented parallel to each other and parallel to the horizontal boundaries of the post contact structure 104 and the unit post structure 102 operatively associated with the plug structure 130. Additionally, the second portion 130B of each of the plug structures 130 may have a horizontal boundary at least partially oriented not perpendicular to the upper vertical boundaries of the post contact structure 104 and the unit post structure 102. For each plug structure 130, the horizontal boundary of its second portion 130B may be at least partially oriented not parallel to the horizontal boundaries of the first portion 130A and the third portion 130C of the plug structure 130, and not parallel to the horizontal boundaries of the pillar contact structure 104 and the unit pillar structure 102 operatively associated with the plug structure 130. For example, the second portion 130B of each of the plug structures 130 may present an arcuate horizontal boundary 131 (e.g., an arcuate side surface, an arcuate sidewall) having a rounded (e.g., circular, curved, arcuate) concave cross-sectional shape in one or more (e.g., all) vertical orientation planes (such as the ZY plane and / or the ZX plane). The rounded concave shape of the arcuate horizontal boundary 131 of the second portion 130B of the plug structure 130 in one or more vertical orientation planes may be complementary (e.g., mirror image) to the rounded convex shape of the arcuate edge 126 of the second dielectric material 108 in one or more vertical orientation planes.

[0064] Each of the plug structures 130 has a first portion 130A that has a substantially uniform (e.g., substantially constant, substantially immutable) horizontal dimension (e.g., width W1) over its entire vertical dimension (e.g., vertical height). The horizontal dimension of the first portion 130A may be smaller than the horizontal dimension of the unit post structure 102 operatively associated with the plug structure 130 (e.g., smaller than or equal to the horizontal dimension of the post contact structure 104 operatively associated with the plug structure 130). Additionally, each of the plug structures 130 has a third portion 130C that has a substantially uniform (e.g., substantially constant, substantially immutable) horizontal dimension (e.g., additional width W2) over its entire vertical dimension (e.g., vertical height). The horizontal dimension of the third portion 130C is larger than the horizontal dimension of the first portion 130A of the plug structure 130. Furthermore, each of the plug structures 130 has a second portion 130B that has a variable (e.g., substantially non-constant, substantially inconsistent) horizontal dimension over its entire vertical dimension (e.g., vertical height). The horizontal dimensions of the second portion 130B at different vertical positions therein can be defined at least in part by the arcuate horizontal boundary 131 of the second portion 130B. The horizontal dimension (e.g., width) of the second portion 130B can increase in a direction away from the first portion 130A and toward the third portion 130C (e.g., the positive Z direction). As a non-limiting example, for a single plug structure 130, its first portion 130A can present a width W1 over its entire vertical height; its third portion 130C can present an additional width W2 over its entire vertical height that is greater than the width W1; and its second portion 130B can present a different width over its entire vertical height (from a relatively small width (e.g., width W1) near the first portion 130A of the plug structure 130 to a relatively large width (e.g., additional width W2) near the third portion 130C of the plug structure 130).

[0065] Compared to capacitive coupling between conventional plug structures with conventional geometries, the plug structure 130 is formed with a reference... Figure 1IThe described geometry enables a reduction in capacitive coupling between horizontally adjacent plug structures 130 of the microelectronic device structure 100. For example, compared to conventional geometries that simply present a gradually narrowing horizontal cross-sectional area between a relatively high portion and a relatively low portion of the plug structure, the geometry of the first portion 130A, the second portion 130B (including its arcuate horizontal boundary 131), and the third portion 130C of each of the plug structures 130 of this disclosure reduces capacitive coupling between horizontally adjacent plug structures 130. Therefore, compared to conventional microelectronic devices containing plug structures with conventional geometries, the geometry of the plug structures 130 of this disclosure enhances the performance (e.g., reduces capacitive coupling) of the microelectronic device (e.g., a memory device, such as a 3D NAND flash memory device) containing the plug structures 130.

[0066] The plug structure 130 can be processed by employing at least one sixth material removal process. Figure 1G The microelectronic device structure 100 is formed by the processing stages depicted herein. For example, the sixth material removal process may include a grinding and planarization process, such as a CMP process. The sixth material removal process can remove the plug material 128 ( Figure 1G The portion of the third dielectric material 110 that is vertically covered by the highest vertical boundary (e.g., the uppermost surface) is essentially not removed from the plug material 128. Figure 1G The additional portion of the third dielectric material 110 located vertically below its uppermost vertical boundary. In some embodiments, the sixth material removal process (e.g., a CMP process) terminates upon reaching the highest vertical boundary of the third dielectric material 110. In an additional embodiment, the sixth material removal process may also remove a portion of the third dielectric material 110 and the plug material 128. Figure 1G The corresponding portion of the third dielectric material 110 (e.g., the portion at the same vertical height as the removed portion of the third dielectric material 110), but the remaining portion of the third dielectric material 110 and the upper vertical boundary of the plug structure 130 are formed to be substantially coplanar with each other.

[0067] Next reference Figure 1I A fourth dielectric material 132 may be formed on or above the third dielectric material 110 and the plug structure 130, and then an additional contact structure 134 (e.g., a digital line contact structure, a bit line contact structure) may be formed to extend vertically through the fourth dielectric material 132 and contact (e.g., a physical contact, an electrical contact) the plug structure 130. Figure 1I As shown, in some embodiments, the additional contact structure 134 is formed to physically contact (e.g., sit on) the upper surface of the plug structure 130.

[0068] The fourth dielectric material 132 may be formed of and comprise at least one insulating material. The material composition of the fourth dielectric material 132 may be substantially the same as that of the third dielectric material 110, or the material composition of the fourth dielectric material 132 may differ from that of the third dielectric material 110. As a non-limiting example, the fourth dielectric material 132 may be made of at least one dielectric oxide material (e.g., SiO2). x Phosphorosilicate glass, borosilicate glass, borosilicate-phosphorosilicate glass, fluorosilicate glass, AlO x HfO x NbO x TiO x ZrO x TaO x and MgO x One or more of the following), at least one dielectric nitride material (e.g., SiN). y ), and at least one dielectric oxide nitride material (e.g., SiO2). x N y ), and at least one dielectric carbon oxide material (e.g., SiO2). x C y ), and at least one hydrogenated dielectric carbon oxide material (e.g., SiC) x O y H z and at least one dielectric carbonitride material (e.g., SiO2) x C z N y One or more of the above materials are formed and comprise one or more of the above materials. In some embodiments, the fourth dielectric material 132 is formed of a dielectric oxide material and comprises the dielectric oxide material (e.g., SiO2). x (e.g., SiO2). The fourth dielectric material 132 can be substantially homogeneous, or the fourth dielectric material 132 can be heterogeneous.

[0069] Additional contact structure 134 can be used to couple plug structure 130 (and thus post contact structure 104 and unit post structure 102) to conductive structure (e.g., conductive wiring structure, conductive line structure) to be subsequently formed on or above microelectronic device structure 100. See below for reference. Figure 2 As described in further detail, as a non-limiting example, the additional contact structure 134 can couple the plug structure 130 to the digital line structure (e.g., bit line structure, data line structure) of the microelectronic device (e.g., memory device, such as a 3D NAND flash memory device) that includes the microelectronic device structure 100.

[0070] The geometry (e.g., shape, size) and horizontal position (e.g., in the X and Y directions) of each of the additional contact structures 134 depend at least in part on the geometry and horizontal position of the plug structure 130. Figure 1I As shown, each additional contact structure 134 may be configured such that its horizontal dimension (e.g., in the X and Y directions) is less than or equal to the corresponding horizontal dimension of the highest vertical boundary (e.g., the uppermost surface) of the individual plug structure 130 with which it contacts (e.g., physical contact, electrical contact). In some embodiments, the horizontal area of ​​the lowest vertical boundary of each additional contact structure 134 is less than the horizontal area of ​​the highest vertical boundary of the plug structure 130 with which it physically contacts. The horizontal area of ​​the lowest vertical boundary of each additional contact structure 134 may be less than, equal to, or greater than the horizontal area of ​​the highest vertical boundary of the additional contact structure 134. In some embodiments, the horizontal area of ​​the lowest vertical boundary of each additional contact structure 134 is less than the horizontal area of ​​the highest vertical boundary of the additional contact structure 134, such that the additional contact structure 134 presents a tapered cross-sectional profile in one or more vertical planes (e.g., the ZY plane, the ZX plane). Additionally, each additional contact structure 134 may be configured to have a desired horizontal cross-sectional shape (e.g., in the XY plane). In some embodiments, each additional contact structure 134 is configured to present a substantially circular horizontal cross-sectional shape. Furthermore, each of the additional contact structures 134 can be configured to have a desired horizontal position relative to the plug structure 130 it contacts. For example... Figure 1I As shown, in some embodiments, each additional contact structure 134 is formed such that its horizontal center is offset (e.g., misaligned) from the horizontal center of the plug structure 130 it contacts. In other embodiments, at least one (e.g., each) of the additional contact structures 134 is formed such that its horizontal center is substantially aligned with the horizontal center of the plug structure 130 it contacts.

[0071] The additional contact structure 134 may be formed of and contain a conductive material. As a non-limiting example, the additional contact structure 134 may be formed of one or more of at least one metal, at least one alloy, and at least one metal-containing conductive material (e.g., conductive metal nitride, conductive metal silicide, conductive metal carbide, conductive metal oxide), and may contain one or more of the aforementioned materials. The material composition of the additional contact structure 134 may be substantially the same as the material composition of one or more (e.g., each) of the plug structure 130 and the pillar contact structure 104, or the material composition of the plug material 128 may be different from the material composition of one or more (e.g., each) of the plug structure 130 and the pillar contact structure 104. In some embodiments, the additional contact structure 134 is formed of and contains W. The additional contact structures 134 may be substantially homogeneous or heterogeneous.

[0072] Therefore, according to embodiments of this disclosure, a microelectronic device includes a pillar structure (including a semiconductor material), a contact structure physically in contact with the upper portion of the pillar structure, and a conductive structure above and physically in contact with the contact structure. Each of the conductive structures includes a lower portion having a first horizontal width, an upper portion vertically covering the lower portion and having a second horizontal width greater than the first horizontal width, and an additional portion vertically inserted between the lower portion and the upper portion and having an arcuate horizontal boundary, the arcuate horizontal boundary defining an additional horizontal width that varies from the first horizontal width near the lower portion to a relatively larger horizontal width near the upper portion.

[0073] Furthermore, according to embodiments of this disclosure, a method of forming a microelectronic device includes forming a contact structure that physically contacts the upper part of a pillar structure, the pillar structure comprising a semiconductor material. A dielectric material is formed above the contact structure. The dielectric material includes a first dielectric material above the contact structure, a second dielectric material above the first dielectric material, and a third dielectric material above the second dielectric material. The dielectric material is patterned to form holes extending into the contact structure. Each of the holes includes a first width within a vertical boundary of the first dielectric material, a second width greater than the first width within a vertical boundary of the third dielectric material, and a plurality of widths within a vertical boundary of the second dielectric material. The plurality of widths increase from the first width near the first dielectric material to a relatively large width near the third dielectric material. A conductive structure is formed within the hole. The conductive structure substantially fills the hole and is in physical contact with the contact structure.

[0074] The microelectronic device structure disclosed herein (e.g., in previous references) Figure 1I The microelectronic device structure 100 described at or after the processing stage may be included in the microelectronic device of this disclosure. For example, Figure 2 A partial cross-sectional perspective view of a portion of a microelectronic device 201 (e.g., a memory device, such as a 3D NAND flash memory device) including a microelectronic device structure 200 is shown. The microelectronic device structure 200 may be related to the microelectronic device structure 200 described in the previous references. Figure 1I The microelectronic device structure 100 described at or after the processing stage is substantially similar. For clarity and ease of understanding of the accompanying drawings and associated description, some features of the microelectronic device structure 100 previously described herein (e.g., structure, materials) are not repeated. Figure 2 As shown in the previous reference. However, it should be understood that, in the previous reference Figure 1I Any feature of the microelectronic device structure 100 at or after the described processing stage (which has been referenced herein) Figures 1A to 1I (One or more of the terms described herein) may be included in the references herein. Figure 2The microelectronic device structure 200 of the microelectronic device 201 described herein.

[0075] like Figure 2 As shown, in addition to the features of microelectronic device structure 200 with respect to microelectronic device structure 100 previously described herein, microelectronic device 201 may also include a stacked structure 202 comprising a vertically alternating (e.g., in the Z direction) sequence of conductive structures 204 and insulating structures 206 arranged in layers 208, each layer comprising at least one conductive structure 204 perpendicularly adjacent to at least one insulating structure 206. (Refer to previous references) Figure 1A The described unit column structure 102 is substantially similar to a unit column structure 210 that extends vertically through the stacked structure 202. The intersection of the unit column structure 210 and the conductive structure 204 of the stacked structure 202 forms a memory cell string 212 extending vertically through the stacked structure 202. The conductive structure 204 may serve as a local access line structure (e.g., a local word line structure) of the memory cell string 212. Additionally, the microelectronic device 201 may also include one or more step structures 214 having steps 216 defined by the edges (e.g., horizontal ends in the X direction) of the layers 208 of the stacked structure 202. The steps 216 of the step structure 214 may serve as contact areas of the conductive structure 204 of the stacked structure 202.

[0076] The microelectronic device 201 may further include at least one source structure 218, an access line wiring structure 220, a first select gate 222 (e.g., an upper select gate, a drain select gate (SGD)), a select line wiring structure 224, one or more second select gates 226 (e.g., a lower select gate, a source select gate (SGS)), a digital line structure 228, an access line contact structure 230, and a select line contact structure 232. The digital line structure 228 can be referenced in the previous section. Figure 1I The additional contact structure 134, plug structure 130, and pillar contact structure 104, which are substantially similar to those described, are coupled to the unit pillar structure 210. For example, the digit line structure 228 may vertically cover and physically contact the additional contact structure (e.g., additional contact structure 134). Figure 1I Additional contact structures can vertically cover and physically contact the plug structure (e.g., plug structure 130). Figure 1I The plug structure can vertically cover and physically contact the column contact structure (e.g., column contact structure 104); and the column contact structure can physically contact the unit column structure 210 (e.g., corresponding to unit column structure 102). Figure 1IAdditionally, access line contact structure 230 and select line contact structure 232 may couple additional features of microelectronic device 201 to each other as presented (e.g., select line wiring structure 224 is coupled to first select gate 222, and access line wiring structure 220 is coupled to conductive structure 204 of layer 208 of stacked structure 202).

[0077] The microelectronic device 201 may also include a foundation structure 234 vertically positioned below the cell pillar structure 210 (and thus below the memory cell string 212). The foundation structure 234 may include at least one control logic region containing control logic means configured to control various operations of other features of the microelectronic device 201 (e.g., the memory cell string 212). As a non-limiting example, the control logic region of the foundation structure 234 may also include one or more (e.g., each) of the following: a charge pump (e.g., V0). CCP Charge pump, V NEGWL Charge pumps, DVC2 charge pumps), delay-locked loop (DLL) circuits (e.g., ring oscillators), V dd Regulators, drivers (e.g., serial drivers), page buffers, decoders (e.g., local layer decoders, column decoders, row decoders), sense amplifiers (e.g., equalization (EQ) amplifiers, isolation (ISO) amplifiers, NMOS sense amplifiers (NSA), PMOS sense amplifiers (PSA)), repair circuitry (e.g., column repair circuitry, row repair circuitry), I / O devices (e.g., local I / O devices), memory test devices, MUX, error checking and correction (ECC) devices, self-refresh / loss equalization devices, and other chip / layer control circuitry. The control logic region of infrastructure 234 may be coupled to source structure 218, access line routing structure 220, select line routing structure 224, and digital line structure 228. In some embodiments, the control logic region of infrastructure 234 includes CMOS (complementary metal-oxide-semiconductor) circuitry. In such embodiments, the control logic region of infrastructure 234 may be characterized as having an "array-under-CMOS" ("CuA") configuration.

[0078] Therefore, according to embodiments of this disclosure, a memory device includes a stacked structure, at least one source structure, a cell pillar structure, a cell contact structure, a conductive plug structure, and a digital line structure. The stacked structure includes a vertically alternating sequence of insulating and conductive structures. The at least one source structure is located below the stacked structure. The cell pillar structure extends vertically through the stacked structure and is coupled to the at least one source structure. The cell contact structure is coupled to the cell pillar structure. The conductive plug structure covers and is coupled to the cell contact structure. Each of the conductive plug structures includes a first portion having a first horizontal boundary extending substantially perpendicular to the upper surface of the cell contact structure, a second portion covering the first portion and having a second horizontal boundary exhibiting a rounded concave shape, and a third portion covering the second portion and having a third horizontal boundary extending substantially perpendicular to the upper surface of the cell contact structure. The digital line structure covers and is coupled to the conductive plug structure.

[0079] Microelectronic device structures according to embodiments of the present disclosure (e.g., in previous references) Figure 1I The microelectronic device structure 100 described at or after the processing stage and the microelectronic device (e.g., microelectronic device 201) Figure 2 This can be used in embodiments of the electronic systems disclosed herein. For example, Figure 3 This is a block diagram of an illustrative electronic system 300 according to embodiments of the present disclosure. Electronic system 300 may include, for example, a computer or computer hardware component, a server or other network hardware component, a cellular phone, a digital camera, a personal digital assistant (PDA), a portable media (e.g., music) player, a Wi-Fi or cellular-enabled tablet computer, such as... or Tablet computers, e-book readers, navigation devices, etc. Electronic system 300 includes at least one memory device 302. For example, memory device 302 may include the microelectronic device architecture previously described herein (e.g., microelectronic device architecture 100). Figure 1I )) and microelectronic devices (e.g., microelectronic device 201 ( Figure 2 One or more of the following. The electronic system 300 may also include at least one electronic signal processor device 304 (generally referred to as a “microprocessor”). The electronic signal processor device 304 may (optionally) include the microelectronic device architecture previously described herein (e.g., microelectronic device architecture 100). Figure 1I )) and microelectronic devices (e.g., microelectronic device 201 ( Figure 2 One or more of the following. Although memory device 302 and electronic signal processor device 304 are in Figure 3The electronic system 300 is depicted as two (2) separate devices, but in additional embodiments, a single (e.g., only one) memory / processor device having the functions of memory device 302 and electronic signal processor device 304 is included in the electronic system 300. In such embodiments, the memory / processor device may comprise the microelectronic device architecture previously described herein (e.g., microelectronic device architecture 100). Figure 1I )) and microelectronic devices (e.g., microelectronic device 201 ( Figure 2 The electronic system 300 may include one or more of the following: Input devices 306, such as a mouse or other pointing device, keyboard, touchpad, button, or control panel, for inputting information to the electronic system 300 by a user. The electronic system 300 may also include one or more output devices 308, such as a monitor, display, printer, audio output jack, speaker, etc., for outputting information to the user (e.g., visual or audio output). In some embodiments, the input devices 306 and output devices 308 may include a single touchscreen device that can be used to input information to the electronic system 300 and output visual information to the user. The input devices 306 and output devices 308 may be electrically connected to one or more of the memory device 302 and the electronic signal processor device 304.

[0080] Therefore, according to embodiments of this disclosure, an electronic system includes an input device, an output device, a processor device operatively coupled to the input and output devices, and a memory device operatively coupled to the processor device. The memory device includes at least one microelectronic device structure comprising a vertically extending string of memory cells coupled to an access line structure and at least one source structure, a conductive structure covering and coupled to the vertically extending string of memory cells, and a digital line structure covering and coupled to the conductive structure. Each of the conductive structures includes a lower portion having a first width, an upper portion having a second width greater than the first width, and an intermediate portion between the lower and upper portions having a horizontal boundary that presents a concave arcuate shape defining an additional width that varies from the first width near the lower portion to a relatively larger width near the upper portion.

[0081] Compared to conventional structures, devices, and methods, the structures and devices of this disclosure advantageously facilitate one or more of the following: improved microelectronic device performance, reduced costs (e.g., manufacturing costs, material costs), increased component miniaturization, and increased package density. For example, compared to conventional methods and structures, the methods and structures of this disclosure can reduce undesirable capacitive coupling between horizontally adjacent conductive structures (e.g., horizontally adjacent plug structures coupling digital line structures to vertically extended memory cell strings) while maintaining or even reducing feature sizes. The structures and devices of this disclosure also improve scalability, efficiency, and simplicity compared to conventional structures and devices.

[0082] The following describes additional non-limiting example embodiments of this disclosure.

[0083] Example 1: A microelectronic device comprising: a pillar structure (including a semiconductor material), a contact structure physically in contact with the upper part of the pillar structure, and a conductive structure above and physically in contact with the contact structure, each of the conductive structures comprising: a lower part having a first horizontal width, an upper part vertically covering the lower part and having a second horizontal width greater than the first horizontal width, and an additional part vertically inserted between the lower part and the upper part and having an arcuate horizontal boundary, the arcuate horizontal boundary defining an additional horizontal width that varies from the first horizontal width near the lower part to a relatively larger horizontal width near the upper part.

[0084] Example 2: The microelectronic device according to Example 1 further includes: a first dielectric material that substantially horizontally surrounds the lower portion of each conductive structure along its entire vertical height; a second dielectric material that covers the first dielectric material and substantially horizontally surrounds the additional portion of each conductive structure along its entire vertical height; and a third dielectric material that covers the second dielectric material and substantially horizontally surrounds the upper portion of each conductive structure along its entire vertical height.

[0085] Example 3: The microelectronic device according to Example 2, wherein the first dielectric material and the third dielectric material each comprise a dielectric oxide material; and the second dielectric material comprises a dielectric nitride material.

[0086] Example 4: In the microelectronic device according to Example 2, the arcuate horizontal boundary of each additional part of the conductive structure is rounded concave; and the second dielectric material has an arcuate edge opposite to the arcuate horizontal boundary of each additional part of the conductive structure, the arcuate edge of the second dielectric material being rounded convex.

[0087] Example 5: A microelectronic device according to any one of Examples 1 to 4, wherein the horizontal center of the conductive structure is substantially aligned with the horizontal center of the contact structure in physical contact with it.

[0088] Example 6: A microelectronic device according to any one of Examples 1 to 5, wherein the lower portion of at least one conductive structure is substantially confined within the horizontal boundary of at least one contact structure in physical contact with it.

[0089] Example 7: The microelectronic device according to Example 6, wherein the upper part of at least one conductive structure extends horizontally beyond the horizontal boundary of at least one contact structure.

[0090] Example 8: The microelectronic device according to any one of Examples 1 to 7 further includes an additional contact structure above and in physical contact with the conductive structure.

[0091] Example 9: The microelectronic device according to Example 8, wherein the horizontal center of the additional contact structure is offset from the horizontal center of the conductive structure in physical contact with it.

[0092] Example 10: The microelectronic device according to Example 8, wherein at least one additional contact structure is substantially confined within the horizontal boundary of the upper portion of at least one conductive structure in physical contact with it.

[0093] Example 11: A method of forming a microelectronic device, the method comprising: forming a contact structure in physical contact with the upper part of a pillar structure comprising a semiconductor material; forming a dielectric material above the contact structure, the dielectric material comprising: a first dielectric material above the contact structure, a second dielectric material above the first dielectric material, and a third dielectric material above the second dielectric material; patterning the dielectric material to form holes extending into the contact structure, each hole comprising: a first width within a vertical boundary of the first dielectric material, a second width greater than the first width within a vertical boundary of the third dielectric material, and a plurality of widths within a vertical boundary of the second dielectric material, the plurality of widths increasing from the first width near the first dielectric material to a relatively large width near the third dielectric material; and forming a conductive structure within the hole, the conductive structure substantially filling the hole and physically contacting the contact structure.

[0094] Example 12: The method according to Example 11 further includes forming an additional contact structure that is in physical contact with the conductive structure, the width of the additional contact structure being less than the second width and the horizontal center of the additional contact structure being offset from the horizontal center of the conductive structure in physical contact with it.

[0095] Example 13: The method according to one of the embodiments of Examples 11 and 12, wherein patterning the dielectric material includes: forming a hard mask material over the third dielectric material; patterning the hard mask material to form an opening extending vertically therethrough, the horizontal center of the opening being substantially aligned with the horizontal center of the contact structure and each having a first width; removing a portion of the third dielectric material after patterning the hard mask material to form an additional opening from the opening, the additional opening having a first width within the vertical boundary of the hard mask material and a second width within the vertical boundary of the third dielectric material; and removing a portion of the second dielectric material and a portion of the first dielectric material after removing a portion of the third dielectric material to form a hole.

[0096] Example 14: According to the method of Example 13, removing a portion of the third dielectric material includes: removing a first portion of the third dielectric material to form an initial additional opening extending vertically through the hard mask material and the third dielectric material, the initial additional opening having a first width within the vertical boundary of the hard mask material and within the vertical boundary of the third dielectric material; and removing a second portion of the third dielectric material horizontally adjacent to the initial additional opening to form an additional opening from the initial additional opening.

[0097] Example 15: According to the method of Example 13, removing portions of the second dielectric material and the first dielectric material includes: removing a first region of the second dielectric material after removing portions of the third dielectric material to form an additional opening from the additional opening, the additional opening having a first width vertically within the vertical boundary of the hard mask material, a second width vertically within the vertical boundary of the third dielectric material, and a first width vertically within the vertical boundary of the second dielectric material; and removing a second region of the second dielectric material and portions of the first dielectric material after removing the first region of the second dielectric material to form a hole from the additional opening.

[0098] Example 16: The method according to any of Examples 11 to 15, wherein the relatively large width of each of the holes within the vertical boundary of the second dielectric material is substantially equal to the second width.

[0099] Example 17: The method according to any of Examples 11 to 16, wherein patterning the dielectric material to form a hole includes forming the hole to have a horizontal boundary, the horizontal boundary being rounded concave within the vertical boundary of the second dielectric material.

[0100] Example 18: The method according to Example 17 further includes: a portion of the horizontal boundary of the hole formed within the vertical boundary of the first dielectric material, extending substantially perpendicular to the upper surface of the contact structure; and an additional portion of the horizontal boundary of the hole formed within the vertical boundary of the third dielectric material, extending substantially perpendicular to the upper surface of the contact structure.

[0101] Example 19: The method according to any one of Examples 11 to 18 further includes: forming the first dielectric material to include silicon dioxide; forming the second dielectric material to include silicon nitride; and forming the third dielectric material to include additional silicon dioxide.

[0102] Example 20: The method according to any one of Examples 11 to 19, wherein forming a conductive structure in the hole includes: forming a conductive material inside and outside the hole, the conductive material substantially filling the hole; and removing a portion of the conductive material covering the upper vertical boundary of the third dielectric material to form the conductive structure.

[0103] Example 21: A memory device comprising: a stacked structure including a vertically alternating sequence of insulating and conductive structures; at least one source structure located below the stacked structure; a cell pillar structure extending vertically through the stacked structure and coupled to the at least one source structure; a cell contact structure coupled to the cell pillar structure; and conductive plug structures covering and coupled to the cell contact structures, each of the conductive plug structures comprising: a first portion having a first horizontal boundary extending substantially perpendicular to the upper surface of the cell contact structure; a second portion covering the first portion and having a second horizontal boundary exhibiting a rounded concave shape; and a third portion covering the second portion and having a third horizontal boundary extending substantially perpendicular to the upper surface of the cell contact structure; and a digital line structure covering and coupled to the conductive plug structures.

[0104] Example 22: The memory device according to Example 21 further includes: a dielectric oxide material covering the stacked structure and horizontally adjacent to a first horizontal boundary of a first portion of each of the conductive plug structures; a dielectric nitride material on the dielectric oxide material and horizontally adjacent to a second horizontal boundary of a second portion of each of the conductive plug structures; and an additional dielectric oxide material located on the dielectric nitride material and horizontally adjacent to a third horizontal boundary of a third portion of each of the conductive plug structures.

[0105] Example 23: The memory device according to one of the embodiments of Examples 21 and 22 further includes a base structure that is vertically located below the stacked structure and includes control logic circuitry that is coupled to at least one source structure, a digital line structure, and a conductive structure of the stacked structure.

[0106] Example 24: An electronic system comprising: an input device; an output device; a processor device operatively coupled to the input device and the output device; and a memory device operatively coupled to the processor device and including at least one microelectronic device structure comprising: a vertically extending string of memory cells coupled to an access line structure and at least one source structure; a conductive structure covering and coupled to the vertically extending string of memory cells, each of the conductive structures comprising: a lower portion having a first width, an upper portion having a second width greater than the first width, and an intermediate portion between the lower portion and the upper portion having a horizontal boundary, the horizontal boundary presenting a concave arcuate shape defining an additional width that varies from the first width near the lower portion to a relatively larger width near the upper portion; and a digital line structure covering and coupled to the conductive structure.

[0107] Example 25: The electronic system according to Example 24, wherein the memory device includes a 3D NAND flash memory device.

[0108] While this disclosure may have various modifications and alternatives, specific embodiments have been shown by way of example in the accompanying drawings and will be described in detail. However, this disclosure is not limited to the particular forms disclosed. Rather, this disclosure is intended to cover all modifications, equivalents, and alternatives falling within the scope of the appended claims and their legal equivalents.

Claims

1. A microelectronic device, the microelectronic device comprising: Pillar structures, which include semiconductor materials; A contact structure that is in physical contact with the upper part of the column structure; as well as A conductive structure, which is above and in physical contact with the contact structure, each of the conductive structures comprising: The lower part has a first horizontal width; The upper part, which vertically covers the lower part and has a second horizontal width greater than the first horizontal width; and An additional portion, which is vertically inserted between the lower portion and the upper portion and has an arcuate horizontal boundary, the arcuate horizontal boundary defining an additional horizontal width that gradually increases from a first horizontal width near the lower portion to a relatively larger horizontal width near the upper portion, the additional portion including arcuate sidewalls and presenting a rounded concave cross-sectional shape in one or more vertical oriented planes.

2. The microelectronic device according to claim 1, further comprising: A first dielectric material, which substantially horizontally surrounds the lower portion along the entire vertical height of the lower portion of each of the conductive structures; A second dielectric material, which covers the first dielectric material and substantially horizontally surrounds the additional portion along the entire vertical height of each of the conductive structures; and A third dielectric material covers the second dielectric material and surrounds the upper portion substantially horizontally along the entire vertical height of the upper portion of each of the conductive structures.

3. The microelectronic device according to claim 2, wherein: The first dielectric material and the third dielectric material each comprise a dielectric oxide material; and The second dielectric material includes a dielectric nitride material.

4. The microelectronic device according to claim 2, wherein: The arc-shaped horizontal boundary of the additional portion of each of the conductive structures presents a rounded concave shape; and The second dielectric material has an arcuate edge opposite to the arcuate horizontal boundary of the additional portion of each of the conductive structures, and the arcuate edge of the second dielectric material is rounded and convex.

5. The microelectronic device of claim 1, wherein the horizontal center of the conductive structure is substantially aligned with the horizontal center of the contact structure in physical contact therewith.

6. The microelectronic device of claim 1, wherein the lower portion of at least one of the conductive structures is substantially confined within the horizontal boundary of at least one of the contact structures in physical contact therewith.

7. The microelectronic device of claim 6, wherein the upper portion of at least one of the conductive structures extends horizontally beyond the horizontal boundary of at least one of the contact structures.

8. The microelectronic device of claim 1 further includes an additional contact structure above and in physical contact with the conductive structure.

9. The microelectronic device of claim 8, wherein the horizontal center of the additional contact structure is offset from the horizontal center of the conductive structure in physical contact with it.

10. The microelectronic device of claim 8, wherein at least one of the additional contact structures is substantially confined within the horizontal boundary of the upper portion of at least one of the conductive structures in physical contact therewith.

11. A method of forming a microelectronic device, the method comprising: A contact structure that forms physical contact with the upper part of a pillar structure including semiconductor material; A dielectric material is formed above the contact structure, the dielectric material comprising: A first dielectric material is disposed above the contact structure; A second dielectric material, which is positioned above the first dielectric material; and A third dielectric material is located above the second dielectric material; The dielectric material is patterned to form holes extending into the contact structure, each of the holes comprising: The upper section, which lies within the vertical boundary of the first dielectric material, has a first width; The lower section, within the vertical boundary of the third dielectric material, has a second width greater than the first width; and An intermediate section, located within the vertical boundary of the second dielectric material, comprising arcuate sidewalls and exhibiting a rounded concave cross-sectional shape in one or more vertical orientation planes, the intermediate section comprising a plurality of widths gradually increasing from a first width approaching the first dielectric material to a relatively larger width approaching the third dielectric material; and A conductive structure is formed within the hole, the conductive structure substantially filling the hole and physically contacting the contact structure.

12. The method of claim 11, further comprising forming an additional contact structure in physical contact with the conductive structure, the width of the additional contact structure being less than the second width and the horizontal center of the additional contact structure being offset from the horizontal center of the conductive structure in physical contact with it.

13. The method of claim 11, wherein patterning the dielectric material comprises: A hard mask material is formed on top of the third dielectric material; The hard mask material is patterned to form openings that extend vertically through it, the horizontal center of the openings being substantially aligned with the horizontal center of the contact structure, and the openings each exhibiting the first width; After patterning the hard mask material, a portion of the third dielectric material is removed to form an additional opening from the opening, the additional opening having the first width within the vertical boundary of the hard mask material and the second width within the vertical boundary of the third dielectric material; as well as After removing a portion of the third dielectric material, portions of the second dielectric material and the first dielectric material are removed to form the hole.

14. The method of claim 13, wherein removing the portion of the third dielectric material comprises: A first portion of the third dielectric material is removed to form an initial additional opening extending vertically through the hard mask material and the third dielectric material, the initial additional opening having a first width within the vertical boundary of the hard mask material and within the vertical boundary of the third dielectric material; as well as Remove the second portion of the third dielectric material that is horizontally adjacent to the initial additional opening to form the additional opening from the initial additional opening.

15. The method of claim 13, wherein removing the portions of the second dielectric material and the first dielectric material comprises: After removing a portion of the third dielectric material, a first region of the second dielectric material is removed to form a further opening from the additional opening. This further opening vertically extends the first width within the vertical boundary of the hard mask material, vertically extends the second width within the vertical boundary of the third dielectric material, and vertically extends the first width within the vertical boundary of the second dielectric material; and After removing the first region of the second dielectric material, a second region of the second dielectric material and a portion of the first dielectric material are removed to form the hole from the additional opening.

16. The method of claim 11, wherein the relatively large width of each of the holes within the vertical boundary of the second dielectric material is substantially equal to the second width.

17. The method of claim 11, wherein patterning the dielectric material to form a hole includes forming the hole to have a horizontal boundary, the intermediate section of the hole including arcuate sidewalls and presenting a curved concave cross-sectional shape in one or more vertical orientation planes.

18. The method of claim 17, further comprising: The portion of the horizontal boundary of the hole formed within the vertical boundary of the first dielectric material extends substantially perpendicular to the upper surface of the contact structure. as well as An additional portion of the horizontal boundary of the hole is formed within the vertical boundary of the third dielectric material, extending substantially perpendicular to the upper surface of the contact structure.

19. The method of claim 11, further comprising: The first dielectric material is formed to include silicon dioxide; The second dielectric material is formed to include silicon nitride; and The third dielectric material is formed to include additional silicon dioxide.

20. The method of claim 11, wherein forming a conductive structure within the hole comprises: A conductive material is formed inside and outside the hole, and the conductive material substantially fills the hole. as well as The portion of the conductive material covering the upper vertical boundary of the third dielectric material is removed to form the conductive structure.

21. A memory device, the memory device comprising: A stacked structure comprising a vertically alternating sequence of insulating and conductive structures; At least one source structure is located below the stacked structure; A unit column structure that extends vertically through the stacked structure and is coupled to the at least one source structure; The unit contact structure is coupled to the unit column structure; A conductive plug structure covering and coupled to the unit contact structure, each of the conductive plug structures comprising: The first part has a first horizontal boundary extending substantially perpendicular to the upper surface of the unit contact structure, the first horizontal boundary defining a first width; The second portion, which covers the first portion and has a second horizontal boundary defining a second width, includes arcuate sidewalls and presents a rounded concave cross-sectional shape in one or more vertically oriented planes; and The third portion covers the second portion and has a third horizontal boundary extending substantially perpendicular to the upper surface of the unit contact structure, the third horizontal boundary defining a third width greater than the first width of the first portion, wherein the second width comprises a plurality of widths that gradually increase from the first width near the first portion to the third width near the third portion; and A digital line structure that covers and couples to the conductive plug structure.

22. The memory device of claim 21, further comprising: A dielectric oxide material that covers the stacked structure and is horizontally adjacent to the first horizontal boundary of the first portion of each of the conductive plug structures; A dielectric nitride material, situated on the dielectric oxide material and horizontally adjacent to the second horizontal boundary of the second portion of each of the conductive plug structures; and An additional dielectric oxide material is located on the dielectric nitride material and is horizontally adjacent to the third horizontal boundary of the third portion of each of the conductive plug structures.

23. The memory device of claim 21, further comprising a base structure that vertically covers the stacked structure and includes control logic circuitry coupled to the at least one source structure, the digital line structure, and the conductive structure of the stacked structure.

24. An electronic system, the electronic system comprising: Input device; Output device; A processor device operatively coupled to the input device and the output device; as well as A memory device operatively coupled to the processor device and including at least one microelectronic device structure, the microelectronic device structure comprising: A vertically extending string of memory cells coupled to an access line structure and at least one source structure; A conductive structure that covers and couples to the vertically extending string of memory cells, each of the conductive structures comprising: The lower part has a first width; The upper part has a second width greater than the first width; and A middle portion, situated between the lower and upper portions and having a horizontal boundary, the middle portion including arcuate sidewalls and exhibiting a rounded concave cross-sectional shape in one or more vertically oriented planes, the middle portion having an additional width that gradually increases from a first width near the lower portion to a relatively larger width near the upper portion; and A digital line structure that covers and couples to the conductive structure.

25. The electronic system of claim 24, wherein the memory device comprises a 3D NAND flash memory device.

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