Integrated circuits and their fabrication methods

Abstract

An integrated circuit includes a first type of active region structure, a second type of active region structure, and a plurality of gate conductors located on a substrate. The integrated circuit also includes a back-side horizontal conductor in a back-side first conductive layer beneath the substrate, a back-side vertical conductor in a back-side second conductive layer beneath the back-side first conductive layer, and pin connections for circuit cells. The pin connections are directly connected between the back-side horizontal conductor and the back-side vertical conductor. The back-side horizontal conductor extends across the vertical boundary of the circuit cell. Embodiments of the invention also relate to a method of forming the integrated circuit.

Description

Technical Field

[0001] Embodiments of the present invention relate to integrated circuits and methods for forming the same. Background Technology

[0002] The recent trend towards miniaturization of integrated circuits (ICs) has resulted in smaller devices that consume less power but deliver more functionality at higher speeds. Miniaturization processes have also led to more stringent design and manufacturing specifications and reliability challenges. Various electronic design automation (EDA) tools generate, optimize, and verify standard cell layout designs for integrated circuits while ensuring compliance with standard cell layout design and manufacturing specifications. Summary of the Invention

[0003] Embodiments of the present invention provide an integrated circuit, comprising: a first type of active region structure and a second type of active region structure, located on a substrate and extending in a first direction; a front-side first layer of conductive lines, located in a first interconnect layer above the substrate; a plurality of gate conductors, located below the first interconnect layer and extending in a second direction, wherein two adjacent gate conductors are separated by a spacing distance equal to the contact polycrystalline pitch (“CPP”); and a circuit unit having a first vertical boundary and a second vertical boundary extending in the second direction perpendicular to the first direction, wherein each of the first vertical boundary and the second vertical boundary crosses at least one boundary space. The circuit cell includes: a region, wherein the distance between the first vertical boundary and the second vertical boundary along the first direction is less than or equal to three of the contact polycrystalline pitches; a back-side horizontal conductor located in a back-side first conductive layer beneath the substrate and extending in the first direction, wherein the back-side horizontal conductor extends across the first vertical boundary of the circuit cell; a back-side vertical conductor located in a back-side second conductive layer beneath the back-side first conductive layer and extending in the second direction, wherein the back-side vertical conductor is aligned with the first vertical boundary; and a pin connector for the circuit cell, directly connected between the back-side horizontal conductor and the back-side vertical conductor.

[0004] According to another embodiment of the present invention, an integrated circuit is provided, comprising: a first type of active region structure and a second type of active region structure, located on a substrate and extending in a first direction; a front-side first layer of conductive lines, located in a first interconnect layer above the substrate; a plurality of gate conductors, located below the first interconnect layer and extending in a second direction, wherein two adjacent gate conductors are separated by a spacing distance equal to the contact polycrystalline pitch (“CPP”); and circuit units having a first vertical boundary and a second vertical boundary extending in the second direction perpendicular to the first direction, wherein each of the first vertical boundary and the second vertical boundary spans at least one boundary isolation region. A back-side horizontal conductor, located in a back-side first conductive layer below the substrate and extending in the first direction; a back-side vertical conductor, located in a back-side second conductive layer below the back-side first conductive layer and extending in the second direction; a pin connector for the circuit unit, directly connecting the back-side horizontal conductor and the back-side vertical conductor at the overlapping area between the back-side horizontal conductor and the back-side vertical conductor; and wherein the back-side vertical conductor has a first portion covering the overlapping area and a second portion located outside the overlapping area, and wherein a first width of the first portion along the first direction is greater than a second width of the second portion along the first direction.

[0005] According to another embodiment of the present invention, a method for forming an integrated circuit is provided, comprising: fabricating a first type of active region structure and a second type of active region structure extending in a first direction on a substrate; fabricating a plurality of gate conductors extending in a second direction perpendicular to the first direction, wherein each of the gate conductors intersects with the first type of active region structure and / or the second type of active region structure above the substrate, and wherein two adjacent gate conductors are separated by a spacing distance equal to the contact polycrystalline pitch (CPP); and fabricating a back-side horizontal conductor extending in the first direction in a back-side first conductive layer below the substrate; Manufacture a pin connector connected to the back-side horizontal conductor; manufacture a back-side vertical conductor extending in the second direction in a back-side second conductive layer below the back-side first conductive layer, wherein the back-side vertical conductor is aligned with the first vertical boundary of the circuit unit, and wherein the pin connector is directly connected between the back-side horizontal conductor and the back-side vertical conductor at the overlapping area between the back-side horizontal conductor and the back-side vertical conductor; and wherein manufacturing the back-side horizontal conductor includes manufacturing the back-side horizontal conductor as an extension conductor extending across the first vertical boundary of the circuit unit, the extension distance being less than one of the contact polycrystalline pitches. Attached Figure Description

[0006] The various aspects of the invention will be best understood from the following detailed description when read in conjunction with the accompanying drawings. It should be noted that, in accordance with standard industrial practice, the components are not drawn to scale. In fact, for clarity of discussion, the dimensions of the components may be arbitrarily increased or decreased.

[0007] Figures 1A to 1B It is a layout diagram of NOR gate circuits according to some embodiments.

[0008] Figure 1C It is based on some embodiments by Figures 1A to 1B The layout diagram in the diagram specifies the equivalent circuit of the circuit or non-circuit.

[0009] Figures 2A to 2E It is based on some embodiments by Figures 1A to 1B The layout diagram in the diagram is a cross-sectional view of the circuit or a non-circuit.

[0010] Figures 3A to 3C It is based on some embodiments by Figures 1A to 1B The layout diagram in the diagram is a cross-sectional view of the circuit or a non-circuit.

[0011] Figures 4A to 4E It is a layout diagram of NOR gate circuits according to some embodiments.

[0012] Figures 5A to 5B This is a layout diagram of NAND gate circuits according to some embodiments.

[0013] Figures 6A to 6B This is a layout diagram of an inverter circuit according to some embodiments.

[0014] Figures 7A to 7B This is a layout diagram of an inverter circuit according to some embodiments.

[0015] Figure 8 This is a flowchart illustrating the process of designing integrated circuits according to some embodiments.

[0016] Figures 9A to 9C This is a layout diagram of the units according to some embodiments.

[0017] Figure 10 This is a flowchart of a method for manufacturing an integrated circuit according to some embodiments.

[0018] Figure 11 This is a block diagram of an electronic design automation (EDA) system according to some embodiments.

[0019] Figure 12 This is a block diagram of an integrated circuit (IC) manufacturing system and its associated IC manufacturing process according to some embodiments. Detailed Implementation

[0020] The following disclosure provides numerous different embodiments or instances for implementing various features of the provided subject matter. Specific examples of components and arrangements are described below to simplify the invention. Of course, these are merely examples and not intended to be limiting. For example, in the following description, forming a first component above or on a second component can include embodiments where the first and second components are in direct contact, and can also include embodiments where an additional component can be formed between the first and second components, such that the first and second components are not in direct contact. Furthermore, reference numerals and / or letters may be repeated in various examples. This repetition is for simplicity and clarity and does not in itself indicate a relationship between the individual embodiments and / or configurations discussed.

[0021] Furthermore, for ease of description, spatial relative terms such as “below,” “under,” “lower,” “above,” and “upper” may be used herein to describe the relationship between one element or component and another, as shown in the figures. In addition to the orientations shown in the figures, spatial relative terms are intended to include different orientations of the device during use or operation. The device may be positioned in other ways (rotated 90 degrees or in other orientations), and the spatial relative descriptors used herein may be interpreted accordingly.

[0022] In some embodiments, the integrated circuit includes a gate conductor and a terminal conductor located on the front side of a substrate. The integrated circuit also includes a back-side horizontal conductor in a first back-side conductive layer and a back-side vertical conductor in a second back-side conductive layer located on the back side of the substrate. The back-side vertical conductor of interest is aligned with a first vertical boundary of the circuit cell and is connected to the back-side horizontal conductor of interest via a pin connector. In some embodiments, the back-side horizontal conductor of interest is an extended conductor extending across the first vertical boundary of the circuit cell. In some embodiments, the back-side vertical conductor of interest is a partially two-dimensional conductor having a first portion of a first width and a second portion of a second width different from the first width. In some embodiments, the extended conductor and / or partially two-dimensional conductor provide greater flexibility for the positioning of the pin connector without generating design rule violations.

[0023] Figures 1A to 1B This is a layout diagram of NOR gate circuit 100 according to some embodiments. Figures 1A to 1BThe layout diagram includes a layout pattern for specifying p-type active region structures 80p and n-type active region structures 80n extending in the X direction, gate conductors (152 and 158) extending in the Y direction, terminal conductors (132p, 132n, 135p, 135n and 138) extending in the Y direction, and dummy gate conductors (151 and 159) extending in the Y direction. The NOR gate circuit 100 is located in a cell defined by cell boundary 110, and the cell width along the X direction is defined by two vertical cell boundaries 111 and 119 extending in the Y direction. Figure 1A The layout diagram also includes layout patterns for specifying the power rails (40 and 20) extending in the X direction, the front first layer conductors (122, 124 and 126) extending in the X direction, and the various through-hole connectors. Figure 1B The layout diagram also includes layout patterns for specifying the back-side horizontal guides (181, 182, 184, and 186) extending in the X direction, the back-side vertical guides (172, 175, and 178) extending in the Y direction, and the various through-hole connectors. In the XY coordinate system, the X and Y directions are perpendicular to each other.

[0024] In the Figures 1A to 1B In the NOR gate 100 specified in the layout diagram, two adjacent gate conductors (such as gate conductors 152 and 158) are separated by a spacing equal to the contact polycrystalline pitch (CPP). In the NOR gate 100, the distance between the vertical cell boundary 111 and the vertical cell boundary 119 along the X direction is three CPPs.

[0025] Figure 1C It is based on some embodiments by Figures 1A to 1B The layout diagram specifies the equivalent circuit of the NOR gate 100. Figures 2A to 2E and Figures 3A to 3C It is based on some embodiments by Figures 1A to 1B The layout diagram specifies the cross-sectional view of the NOR gate circuit 100.

[0026] In the Figures 1A to 1B The layout diagram specifies the NOR gate 100 and such Figure 1CAs shown in the equivalent circuit diagram, gate conductor 152 intersects with p-type active region structure 80p in the channel region of p-type transistor pA1, and with n-type active region structure 80n in the channel region of n-type transistor nA1. Gate conductor 158 intersects with p-type active region structure 80p in the channel region of p-type transistor pA2, and with n-type active region structure 80n in the channel region of n-type transistor nA2. Terminal conductors 132p and 135p intersect with p-type active region structure 80p in the respective source / drain regions of p-type transistors pA2 and pA1. Terminal conductors 132n and 135n intersect with n-type active region structure 80n in the respective source / drain regions of n-type transistors nA2 and nA1. Terminal conductor 138 intersects the p-type active region structure 80p and the n-type active region structure 80n respectively at the drain region of the p-type transistor pA1 and the drain region of the n-type transistor nA1. Non-limiting examples of p-type transistors (pA1 and pA2) and n-type transistors (nA1 and nA2) include FinFETs, nanosheet transistors, and nanowire transistors. Figures 1A to 1B The layout pattern of the pseudo gate conductors 151 and 159 in the NOR gate 100 specifies that the active regions (such as source regions, drain regions, and channel regions) in the NOR gate 100 are isolated from the active regions in adjacent cells.

[0027] In the Figures 1A to 1B The layout diagram specifies the NOR gate 100 and such Figure 1C As shown in the equivalent circuit diagram, the front-side first layer conductors (122, 124, and 126) and power rails (40 and 20) are located in a first interconnect layer above the substrate. In some embodiments, the first interconnect layer is a first metal layer MO above a top insulating layer fabricated in a front-end process (FEOL) process. In the NOR gate 100, terminal conductor 132p is conductively connected to power rail 40 via via connector 1VDdd, and power rail 40 is configured to provide a first power supply voltage VDD. Terminal conductor 135n is conductively connected to power rail 20 via via connector 1VDss, and power rail 20 is configured to provide a second power supply voltage VSS. Front-side first layer conductor 126 is conductively connected to terminal conductor 132n via via connector 1VD1 and conductively connected to terminal conductor 138 via via connector 1VD2.

[0028] In the NOR gate 100, terminal conductor 138 ( Figure 1A The middle section is also electrically connected to the back-side horizontal conductor 182 via a through-hole connector 1BVD1 passing through the substrate. Figure 1B (in the middle). In addition, gate conductor 152 ( Figure 1A (middle) is electrically connected to the back side horizontal wire 184 via through-hole connector 1BVG1. Figure 1B (middle), and gate conductor 158 ( Figure 1A (in) conductively connected to the back-side horizontal conductor 186 via through-hole connector 1BVG2 (in) Figure 1B middle).

[0029] In the NOR gate 100, the back-side horizontal conductor 182 is electrically connected to the back-side vertical conductor 178 via a through-hole connector 1BV0A. The back-side horizontal conductor 184 is electrically connected to the back-side vertical conductor 172 via a through-hole connector 1BV0B. The back-side horizontal conductor 186 is electrically connected to the back-side vertical conductor 175 via a through-hole connector 1BV0C.

[0030] In the NOR gate 100, back-side horizontal conductors 181, 182, 184, and 186 are located in a back-side first conductive layer beneath the substrate. Back-side vertical conductors 172, 175, and 178 are located in a back-side second conductive layer beneath the back-side first conductive layer. In some embodiments, the back-side first conductive layer is a first back-side metal layer BM0 fabricated on the back side of the substrate, and the back-side second conductive layer is a second back-side metal layer BM1 fabricated on the back side of the substrate. The first back-side metal layer BM0 is sandwiched between the substrate and the second back-side metal layer BM1. Each of the via connectors 1BV0A, 1BV0B, and 1BV0C is a via connector BV0 that passes through an interlayer dielectric (ILD) material separating the second back-side metal layer BM1 and the first back-side metal layer BM0.

[0031] In the NOR gate 100, the back-side vertical conductor 172, the through-hole connector 1BV0B, and the back-side horizontal conductor 184 are electrically connected together to carry the input signal "A1" of the NOR gate 100. The back-side vertical conductor 175, the through-hole connector 1BV0C, and the back-side horizontal conductor 186 are electrically connected together to carry the input signal "A2" of the NOR gate 100. The back-side vertical conductor 178, the through-hole connector 1BV0A, and the back-side horizontal conductor 182 are electrically connected together to carry the output signal "ZN" of the NOR gate 100.

[0032] In the NOR gate circuit 100, the through-hole connector 1BV0A (e.g.) Figure 1C (As shown) serves as a pin connector extending in the Z direction, used to connect the back-side vertical wire 178 to the back-side horizontal wire 182 to carry the output signal "ZN" of the NOR gate 100. In some embodiments, such as Figure 1B As shown, when the back-side horizontal conductor 182 extends across the vertical cell boundary 119, it provides greater flexibility for the positioning of the pin connector (i.e., the through-hole connector 1BV0A) without creating design rule violations. Figure 1BIn this embodiment, the back-side horizontal conductor 182 extends across the vertical cell boundary 119 by a distance "Δ" in the X direction. In some embodiments, the back-side horizontal conductor 182 extends across the vertical cell boundary 119 by a distance "Δ" less than one CPP but greater than one-eighth of a CPP. In some embodiments, the back-side horizontal conductor 182 extends across the vertical cell boundary 119 by a distance "Δ" less than one CPP but greater than one-quarter of a CPP. In some embodiments, the back-side horizontal conductor 182 extends across the vertical cell boundary 119 by a distance "Δ" less than one CPP but greater than half of a CPP. In some embodiments, the distance "Δ" is chosen to be large enough to mitigate design rule violations associated with pin connector connections between the back-side vertical conductor 178 and the back-side horizontal conductor 182. In some embodiments, the distance "Δ" is chosen to be less than one CPP such that the horizontal gap distance from the vertical cell boundary 119 to the vertical cell boundary of the adjacent cell is reduced to a minimum to mitigate design rule violations associated with pin connector connections.

[0033] exist Figure 1B In this design, the back-side vertical conductor 178 has a width "W" extending in the X direction. In some embodiments, the width "W" is chosen to reduce the IR drop in the back-side vertical conductor 178. In some embodiments, the width "W" of the back-side vertical conductor 178 is greater than half of the CPP. In some embodiments, the width "W" of the back-side vertical conductor 178 is greater than three-quarters of the CPP. Generally, the larger the width "W", the smaller the IR drop in the back-side vertical conductor 178. However, the spacing requirements between adjacent back-side vertical conductors limit the maximum value of the width "W" if the number of tracks for back-side vertical conductors in the cell is fixed. Reducing the number of tracks may increase the maximum value of the width "W", but at the same time reduce the routing flexibility of the cell design. In some embodiments, a trade-off between routing flexibility and IR drop requirements determines the maximum value of the width "W".

[0034] Figure 2A According to some embodiments, in the cutting plane A-A', by Figures 1A to 1B The layout diagram specifies a cross-sectional view of the NOR gate 100. For example... Figure 2AAs shown, a p-type active region structure 80p is located on substrate 50. Each of terminal conductors 132p, 135p, and 138 intersects the p-type active region structure 80p. Each of gate conductors 152 and 158 also intersects the p-type active region structure 80p. In some embodiments, the active regions (such as source regions, channel regions, or drain regions) in the p-type active region structure 80p are isolated from the active regions in adjacent cells by boundary isolation regions 151i below dummy gate conductor 151 and boundary isolation regions 159i below dummy gate conductor 159. A front-side first layer conductor 122 is located on insulating layer 52, which covers the gate conductors (152 and 158) and terminal conductors (132p, 135p, and 138). Backside vertical conductors 172, 175, and 178 are located on backside interlayer dielectric 56, which is located on backside interlayer dielectric 54 on the backside of substrate 50.

[0035] Figure 2B According to some embodiments, in the cutting plane B-B', by Figures 1A to 1B The layout diagram specifies a cross-sectional view of the NOR gate 100. For example... Figure 2B As shown, an n-type active region structure 80n is located on substrate 50. Each of terminal conductors 132n, 135n, and 138 intersects the n-type active region structure 80n. Each of gate conductors 152 and 158 also intersects the n-type active region structure 80n. In some embodiments, active regions (such as source regions, channel regions, or drain regions) in the n-type active region structure 80n are isolated from active regions in adjacent cells by boundary isolation regions 151i below dummy gate conductor 151 and boundary isolation regions 159i below dummy gate conductor 159. A front-side first layer conductor 126 is located on insulating layer 52, which covers the gate conductors (152 and 158) and terminal conductors (132n, 135n, and 138). Backside vertical conductors 172, 175, and 178 are located on backside interlayer dielectric 56, which is located on backside interlayer dielectric 54 on the backside of substrate 50.

[0036] Figure 2C According to some embodiments, in the cutting plane C-C', by Figures 1A to 1B The layout diagram specifies a cross-sectional view of the NOR gate 100. For example... Figure 2CAs shown, insulating layer 52 covers gate conductors (152 and 158), terminal conductors (132p, 135p and 138), and dummy gate conductors (151 and 159). Back-side horizontal conductors 181 and 182 are located on the back side of substrate 50. A portion of back-side interlayer dielectric 54 separates back-side horizontal conductors 181 and 182. Back-side vertical conductors 172, 175, and 178 are located on back-side interlayer dielectric 56, which covers back-side interlayer dielectric 54 and back-side horizontal conductors 181 and 182. Through-hole connector 1BVD1 passes through substrate 50 and electrically connects terminal conductor 138 to back-side horizontal conductor 182. Through-hole connector 1BV0A passes through back-side interlayer dielectric 56 and electrically connects back-side horizontal conductor 182 to back-side vertical conductor 178.

[0037] Figure 2D According to some embodiments, in the cutting plane D-D', by Figures 1A to 1B The layout diagram specifies a cross-sectional view of the NOR gate 100. For example... Figure 2D As shown, insulating layer 52 covers gate conductors (152 and 158), terminal conductors 138, and dummy gate conductors (151 and 159). A back-side horizontal conductor 184 is located on the back side of substrate 50. Back-side vertical conductors 172, 175, and 178 are located on back-side interlayer dielectric 56, which covers back-side interlayer dielectric 54 and back-side horizontal conductor 184. Through-hole connector 1BVG1 passes through substrate 50 and electrically connects gate conductor 152 to back-side horizontal conductor 184. Through-hole connector 1BV0B passes through back-side interlayer dielectric 56 and electrically connects back-side horizontal conductor 184 to back-side vertical conductor 172.

[0038] Figure 2E According to some embodiments, in the cutting plane E-E', by Figures 1A to 1B The layout diagram specifies a cross-sectional view of the NOR gate 100. For example... Figure 2E As shown, insulating layer 52 covers gate conductors (152 and 158), terminal conductors (132n, 135n and 138), and dummy gate conductors (151 and 159). A back-side horizontal conductor 186 is located on the back side of substrate 50. Back-side vertical conductors 172, 175, and 178 are located on back-side interlayer dielectric 56, which covers back-side interlayer dielectric 54 and back-side horizontal conductor 186. Through-hole connector 1BVG2 passes through substrate 50 and electrically connects gate conductor 158 to back-side horizontal conductor 186. Through-hole connector 1BV0C passes through back-side interlayer dielectric 56 and electrically connects back-side horizontal conductor 186 to back-side vertical conductor 175.

[0039] Figure 3A According to some embodiments, in the cutting plane P-P', by Figures 1A to 1B The layout diagram specifies a cross-sectional view of the NOR gate 100. For example... Figure 3A As shown, terminal conductor 132n intersects with n-type active region structure 80n on substrate 50, and terminal conductor 132p intersects with p-type active region structure 80p on substrate 50. Insulating layer 52 covers terminal conductors 132n and 132p. Power rails (40 and 20) and front-side first layer conductors 122 and 126 are located in a first connection layer above insulating layer 52. Through-hole connector 1VDDd passes through insulating layer 52 and electrically connects terminal conductor 132p to power rail 40. Back-side horizontal conductors 181, 184, and 186 are located on the back side of substrate 50. Back-side interlayer dielectric 54 and back-side horizontal conductors 181, 184, and 186 are covered by back-side interlayer dielectric 56. Back-side vertical conductor 172 is located above back-side interlayer dielectric 56. The through-hole connector 1BV0B passes through the back-side interlayer dielectric 56 and electrically connects the back-side horizontal conductor 184 to the back-side vertical conductor 172.

[0040] Figure 3B According to some embodiments, in the cutting plane Q-Q', by Figures 1A to 1B The layout diagram specifies a cross-sectional view of the NOR gate 100. For example... Figure 3B As shown, terminal conductor 135n intersects with n-type active region structure 80n on substrate 50, and terminal conductor 135p intersects with p-type active region structure 80p on substrate 50. Insulating layer 52 covers terminal conductors 135n and 135p. Power rails (20 and 40) and front-side first layer conductors 122, 124, and 126 are located in a first connection layer above insulating layer 52. Through-hole connector 1VDss passes through insulating layer 52 and electrically connects terminal conductor 135n to power rail 20. Back-side horizontal conductors 184 and 186 are located on the back side of substrate 50. Back-side interlayer dielectric 54 and back-side horizontal conductors 184 and 186 are covered by back-side interlayer dielectric 56. Back-side vertical conductor 175 is located above back-side interlayer dielectric 56. The through-hole connector 1BV0C passes through the back-side interlayer dielectric 56 and electrically connects the back-side horizontal conductor 186 to the back-side vertical conductor 175.

[0041] Figure 3C According to some embodiments, in the cutting plane R-R', by Figures 1A to 1B The layout diagram specifies a cross-sectional view of the NOR gate 100. For example... Figure 3CAs shown, terminal conductor 138 intersects with n-type active region structure 80n and p-type active region structure 80p on substrate 50. Insulating layer 52 covers terminal conductor 138. Power rails (20 and 40) and front first layer conductors 124 and 126 are located in the first connection layer above insulating layer 52. Back side horizontal conductors 182, 184, and 186 are located on the back side of substrate 50. Through-hole connector 1BVD1 passes through substrate 50 and electrically connects terminal conductor 138 to back side horizontal conductor 182. Back side interlayer dielectric 54 and back side horizontal conductors 182, 184, and 186 are covered by back side interlayer dielectric 56. Back side vertical conductor 178 is located on back side interlayer dielectric layer 56. Through-hole connector 1BV0A passes through back side interlayer dielectric layer 56 and electrically connects back side horizontal conductor 182 to back side vertical conductor 178.

[0042] In the Figures 1A to 1B In the NOR gate 100 specified in the layout diagram, the back-side vertical conductor 178 has a uniform width "W" on the back side of the substrate 50. In some alternative embodiments, at least one back-side vertical conductor includes a first portion having a first width and a second portion having a second width, and the first width of the first portion is greater than the second width of the second portion. As an example, in the layout diagram of the NOR gate 100, the back-side vertical conductor 178 has a uniform width "W" on the back side of the substrate 50. Figures 4A to 4B In the NOR gate circuit specified in the layout diagram (described in more detail below), the first portion of the back-side vertical conductor 178 has a first width "Wa", and the second portion of the back-side vertical conductor 178 has a second width "Wb", wherein the first width "Wa" is greater than the second width "Wb".

[0043] Figures 4A to 4E This is a layout diagram of a NOR gate circuit 400 according to some embodiments. Figures 4A to 4E Each of the layout diagrams includes a layout pattern for specifying the back-side horizontal conductors (181, 182, 184, and 186) and the back-side vertical conductors (172, 175, and 178). The layout of the components in the NOR gate 400 on the back side of the substrate (e.g., Figures 4A to 4E The arrangement of components in the NOR gate 100 on the back side of the substrate (as shown) and the NOR gate 100 on the back side of the substrate (as shown) Figure 1B The arrangement of components in the NOR gate 400 on the front side of the substrate is different from that in the NOR gate 100 on the front side of the substrate (as shown). Figure 1A (As shown). Therefore, for NOR gate 400, refer only to Figures 4A to 4E The layout diagram describes the arrangement of components on the back side of the substrate in detail, and no longer refers to the front layout diagram to describe the arrangement of components on the front side.

[0044] like Figures 4A to 4EThe NOR gate circuit 400, as specified in the layout diagram, includes back-side horizontal conductors 181, 182, 184, and 186 in a back-side first conductive layer beneath the substrate. The NOR gate circuit 400 also includes back-side vertical conductors 172, 175, and 178 in a back-side second conductive layer beneath the back-side first conductive layer. Gate conductor 152 is conductively connected to back-side horizontal conductor 184 via via connector 1BVG1, and back-side horizontal conductor 184 is conductively connected to back-side vertical conductor 172 via via connector 1BV0B. Gate conductor 158 is conductively connected to back-side horizontal conductor 186 via via connector 1BVG2, and back-side horizontal conductor 186 is conductively connected to back-side vertical conductor 175 via via connector 1BV0C. Terminal conductor 138 (in...) Figure 1A The middle section is electrically connected to the back side horizontal conductor 182 through the through-hole connector 1BVD1, and the back side horizontal conductor 182 is electrically connected to the back side vertical conductor 178 through the through-hole connector 1BV0A.

[0045] As by Figures 4A to 4E As specified in the layout diagram, in the NOR gate 400, the back-side vertical conductor 178 includes a first portion 178A and a second portion 178B. The first portion 178A covers the overlapping area between the back-side horizontal conductor 182 and the back-side vertical conductor 178, while the second portion 178B is located outside the overlapping area. The first portion 178A has a first width "Wa", and the second portion has a second width "Wb". The first width "Wa" is greater than the second width "Wb". In some embodiments, the first width "Wa" is larger than the second width "Wb" by more than one-eighth of a CPP. In some embodiments, the first width "Wa" is larger than the second width "Wb" by more than one-quarter of a CPP. In some embodiments, the first width "Wa" is large enough to allow the positioning of the pin connector 1BV0A without generating design rule violations. In some embodiments, the flexibility in positioning pin connectors for circuit cells with a cell width less than or equal to three CPPs improves the layout area coverage in integrated circuit design.

[0046] In some embodiments, such as in Figure 4AIn the NOR gate 400, the back-side horizontal conductor 182 extends across the vertical cell boundary 119 by a distance “Δ” in the X direction. In some embodiments, the back-side horizontal conductor 182 extends across the vertical cell boundary 119 by a distance “Δ” less than one CPP but greater than one-eighth of a CPP. In some embodiments, the back-side horizontal conductor 182 extends across the vertical cell boundary 119 by a distance “Δ” less than one CPP but greater than one-quarter of a CPP. In some embodiments, the back-side horizontal conductor 182 extends across the vertical cell boundary 119 by a distance “Δ” less than one CPP but greater than half of a CPP. In some embodiments, the distance “Δ” is chosen to be large enough to mitigate design rule violations associated with pin connector connections between the back-side vertical conductor 178 and the back-side horizontal conductor 182. In some embodiments, the distance “Δ” is chosen to be less than one CPP such that the horizontal gap distance from the vertical cell boundary 119 to the vertical cell boundary of the adjacent cell is reduced to a minimum distance to mitigate design rule violations associated with pin connector connections.

[0047] In some embodiments, such as in Figure 4B In the NOR gate 400, the back-side horizontal conductor 182 extends across the vertical cell boundary 119. In some embodiments, such as in Figure 4C In the NOR gate 400, a first portion 178A of the back-side vertical conductor 178 extends across the vertical cell boundary 119, while a second portion 178B of the back-side vertical conductor 178 does not extend across the vertical cell boundary 119. In some embodiments, such as in Figure 4D In the NOR gate circuit 400, the first portion 178A and the second portion 178B of the back-side vertical conductor 178 both extend across the vertical cell boundary 119.

[0048] In some embodiments, such as in Figure 4E In the NOR gate 400, although the back-side vertical conductor 178 does not extend across the vertical cell boundary 119, the first width "Wa" of the first portion 178A is increased to provide greater flexibility in positioning the pin connector (i.e., the through-hole connector 1BV0A) on the back-side horizontal conductor 182. Furthermore, the back-side vertical conductor 175 (adjacent to the back-side vertical conductor 178) is also modified to avoid design rule violations.

[0049] Figures 5A to 5B This is a layout diagram of a NAND gate circuit 500 according to some embodiments. Figures 5A to 5BThe layout diagram includes layout patterns for specifying p-type active region structures 80p and n-type active region structures 80n, gate conductors (552 and 558), terminal conductors (532p, 532n, 535p, 535n and 538), and dummy gate conductors (151 and 159). NAND gates 500 are located in cells defined by cell boundaries 110, and the cell width is defined by two vertical cell boundaries 111 and 119. Figure 5A The layout diagram also includes layout patterns for specifying the power rails (40 and 20), the front first layer conductors (522, 524 and 526), ​​and the various through-hole connectors. Figure 5B The layout diagram also includes layout patterns for specifying the back side horizontal conductors (581, 582, 584 and 586), the back side vertical conductors (572, 575 and 578), and the various through-hole connectors.

[0050] In the Figures 5A to 5B In the NAND gate circuit 500 specified in the layout diagram, gate conductor 552 intersects with p-type active region structure 80p at the channel region of p-type transistor pA1 and with n-type active region structure 80n at the channel region of n-type transistor nA1. Gate conductor 558 intersects with p-type active region structure 80p at the channel region of p-type transistor pA2 and with n-type active region structure 80n at the channel region of n-type transistor nA2. Terminal conductors 532p and 535p intersect with p-type active region structure 80p at their respective source / drain regions of p-type transistors pA2 and pA1. Terminal conductors 532n and 535n intersect with n-type active region structure 80n at their respective source / drain regions of n-type transistors nA2 and nA1. Terminal conductor 538 intersects with p-type active region structure 80p and n-type active region structure 80n respectively at the drain region of p-type transistor pA1 and at the drain region of n-type transistor nA1.

[0051] In the Figures 5A to 5B In the NAND gate 500 specified in the layout diagram, the front first layer conductors (522, 524, and 526) and power rails (40 and 20) are located in a first interconnect layer above the substrate. In the NAND gate 500, terminal conductor 535p is conductively connected to power rail 40 via via connector 5VDDd, and power rail 40 is configured to provide a first power supply voltage VDD. Terminal conductor 532n is conductively connected to power rail 20 via via connector 5VDss, and power rail 20 is configured to provide a second power supply voltage VSS. Front first layer conductor 522 is conductively connected to terminal conductor 532p via via connector 5VD1, and conductively connected to terminal conductor 538 via via connector 5VD2.

[0052] In the NAND gate 500, terminal conductor 538 ( Figure 5A (in the middle) is also electrically connected to the back-side horizontal conductor 582 via a through-hole connector 5BVD1 passing through the substrate. Figure 5B (Middle). In addition, gate conductor 552 ( Figure 5A (middle) is electrically connected to the back side horizontal conductor 584 via through-hole connector 5BVG1. Figure 5B (in the middle), and the gate conductor 558 ( Figure 5A (in) conductively connected to the back-side horizontal conductor 586 via through-hole connector 5BVG2 (in) Figure 5B middle).

[0053] In the NAND gate 500, the back-side horizontal conductor 582 is electrically connected to the back-side vertical conductor 578 via a via connector 5BV0A. The back-side horizontal conductor 584 is electrically connected to the back-side vertical conductor 572 via a via connector 5BV0B. The back-side horizontal conductor 586 is electrically connected to the back-side vertical conductor 575 via a via connector 5BV0C. In the NAND gate 500, the back-side horizontal conductors 581, 582, 584, and 586 are located in the back-side first conductive layer beneath the substrate. The back-side vertical conductors 572, 575, and 578 are located in the back-side first conductive layer and the back-side second conductive layer beneath the substrate 50.

[0054] In the NAND gate 500, the back-side vertical conductor 572, the through-hole connector 5BV0B, and the back-side horizontal conductor 584 are electrically connected together to carry the input signal "A1" of the NAND gate 500. The back-side vertical conductor 575, the through-hole connector 5BV0C, and the back-side horizontal conductor 586 are electrically connected together to carry the input signal "A2" of the NAND gate 500. The back-side vertical conductor 578, the through-hole connector 5BV0A, and the back-side horizontal conductor 582 are electrically connected together to carry the output signal "ZN" of the NAND gate 500.

[0055] In the NAND gate 500, the through-hole connector 1BV0A serves as a pin connector extending in the Z direction, connecting the back-side vertical conductor 578 to the back-side horizontal conductor 582 to carry the output signal "ZN" of the NAND gate 500. In some embodiments, the positioning of the pin connector (i.e., the through-hole connector 1BV0A) is more flexible without violating design rules when the back-side horizontal conductor 582 extends across the vertical cell boundary 119. Figure 5BIn this configuration, the back-side horizontal conductor 582 extends a distance "Δ" across the vertical cell boundary 119 along the X direction. In some embodiments, the back-side horizontal conductor 582 extends a distance "Δ" across the vertical cell boundary 119 that is less than one CPP. In some embodiments, the back-side horizontal conductor 582 extends a distance "Δ" across the vertical cell boundary 119 that is more than one-eighth, one-quarter, or one-half of a CPP. In some embodiments, the distance "Δ" is chosen to be large enough to mitigate design rule violations associated with pin connector connections between the back-side vertical conductor 578 and the back-side horizontal conductor 582. In some embodiments, the distance "Δ" is chosen to be less than one CPP such that the horizontal gap distance from the vertical cell boundary 119 to the vertical cell boundary of the adjacent cell is reduced to a minimum distance to mitigate design rule violations associated with pin connector connections.

[0056] Figures 6A to 6B This is a layout diagram of an inverter circuit 600 according to some embodiments. Figures 6A to 6B The layout diagram includes layout patterns for specifying the p-type active region structure 80p and the n-type active region structure 80n, gate conductors (652 and 658), terminal conductors (632, 635p, 635n and 638), and dummy gate conductors (151 and 159). The inverter circuit 600 is located in a cell defined by cell boundary 110, and the cell width is defined by two vertical cell boundaries 111 and 119. Figure 6A The layout diagram also includes layout patterns for specifying the power rails (40 and 20), the front first layer conductors (622, 624 and 626), and the various through-hole connectors. Figure 6B The layout diagram also includes layout patterns for specifying the back side horizontal conductors (681, 682, 684 and 686), the back side vertical conductors (672, 675 and 678), and the various through-hole connectors.

[0057] In the Figures 6A to 6BIn the inverter circuit 600 specified in the layout diagram, gate conductor 652 intersects with p-type active region structure 80p at the channel region of p-type transistor pA1 and with n-type active region structure 80n at the channel region of n-type transistor nA1. Gate conductor 658 intersects with p-type active region structure 80p at the channel region of p-type transistor pA2 and with n-type active region structure 80n at the channel region of n-type transistor nA2. Terminal conductor 635p intersects with p-type active region structure 80p at the source regions of p-type transistors pA2 and pA1. Terminal conductor 635n intersects with n-type active region structure 80n at the source regions of n-type transistors nA2 and nA1. Terminal conductor 632 intersects with the p-type active region structure 80p and the n-type active region structure 80n respectively at the drain regions of p-type transistor pA1 and n-type transistor nA1. Terminal conductor 638 intersects with the p-type active region structure 80p and the n-type active region structure 80n respectively at the drain regions of p-type transistor pA2 and n-type transistor nA2.

[0058] In the Figures 6A to 6B In the inverter circuit 600 specified in the layout diagram, the front first layer conductors (622, 624, and 626) and power rails (40 and 20) are located in a first interconnect layer above the substrate. In the inverter circuit 600, terminal conductor 635p is electrically connected to power rail 40 via via connector 6VDDd, and power rail 40 is configured to provide a first power supply voltage VDD. Terminal conductor 635n is electrically connected to power rail 20 via via connector 6VDss, and power rail 20 is configured to provide a second power supply voltage VSS. Front first layer conductor 626 is electrically connected to terminal conductor 632 via via connector 6VD1 and to terminal conductor 638 via via connector 6VD2.

[0059] In inverter circuit 600, terminal conductor 638 ( Figure 6A The middle section is also electrically connected to the back-side horizontal wire 682 via a through-hole connector 6BVD1 passing through the substrate. Figure 6B (Middle). In addition, the back-side horizontal conductor 684 ( Figure 6B (in the middle) is electrically connected to the gate conductor 652 through the through-hole connector 6BVG1, and electrically connected to the gate conductor 658 through the through-hole connector 6BVG2.

[0060] In inverter circuit 600, back-side horizontal conductor 682 is electrically connected to back-side vertical conductor 678 via through-hole connector 6BV0A. Back-side horizontal conductor 684 is electrically connected to back-side vertical conductor 672 via through-hole connector 6BV0B. In inverter circuit 600, back-side horizontal conductors 681, 682, 684, and 686 are located in a back-side first conductive layer beneath the substrate. Back-side vertical conductors 672, 675, and 678 are located in a back-side second conductive layer beneath the back-side first conductive layer. In inverter circuit 600, back-side vertical conductor 672 serves as the input node "IN" of inverter circuit 600. Back-side vertical conductor 678 serves as the output node "ZN" of inverter circuit 600.

[0061] In inverter circuit 600, through-hole connector 6BV0A serves as a pin connector extending in the Z direction, connecting back-side vertical conductor 678 to back-side horizontal conductor 682 to carry the output signal "ZN" of inverter circuit 600. In some embodiments, the positioning of the pin connector (i.e., through-hole connector 6BV0A) is provided without violating design rules when the back-side horizontal conductor 682 extends across vertical cell boundary 119. Figure 6B In this embodiment, the back-side horizontal conductor 682 extends across the vertical cell boundary 119 by a distance "Δ" in the X direction. In some embodiments, the back-side horizontal conductor 682 extends across the vertical cell boundary 119 by a distance "Δ" less than one CPP. In some embodiments, the back-side horizontal conductor 682 extends across the vertical cell boundary 119 by a distance "Δ" greater than one-eighth, one-quarter, or one-half of a CPP. In some embodiments, the distance "Δ" is chosen to be large enough to mitigate design rule violations associated with pin connector connections between the back-side vertical conductor 678 and the back-side horizontal conductor 682. In some embodiments, the distance "Δ" is chosen to be less than one CPP such that the horizontal gap distance from the vertical cell boundary 119 to the vertical cell boundary of the adjacent cell is reduced to a minimum distance to mitigate design rule violations associated with pin connector connections.

[0062] Figures 7A to 7B This is a layout diagram of an inverter circuit 700 according to some embodiments. Figures 7A to 7B The layout diagram includes layout patterns for specifying the p-type active region structure 80p and the n-type active region structure 80n, the gate conductor 758, the terminal conductors (735p, 735n and 738), and the dummy gate conductors (151 and 159). The inverter circuit 700 is located in a cell defined by cell boundary 110, and the cell width is defined by two vertical cell boundaries 111 and 119. Figure 7AThe layout diagram also includes layout patterns for specifying the power rails (40 and 20), the front first layer conductors (722, 724 and 726), and the various through-hole connectors. Figure 7B The layout diagram also includes layout patterns for specifying the back side horizontal conductors (782, 784 and 786), the back side vertical conductors (775 and 778) and the various through-hole connectors.

[0063] In the Figures 7A to 7B In the inverter circuit 700 specified in the layout diagram, the gate conductor 758 intersects with the p-type active region structure 80p at the channel region of the p-type transistor Tp and with the n-type active region structure 80n at the channel region of the n-type transistor Tn. The terminal conductor 735p intersects with the p-type active region structure 80p at the source region of the p-type transistor Tp. The terminal conductor 735n intersects with the n-type active region structure 80n at the source region of the n-type transistor Tn. The terminal conductor 738 intersects with the p-type active region structure 80p and the n-type active region structure 80n respectively at the drain regions of the p-type transistor Tp and the n-type transistor Tn.

[0064] In the Figures 7A to 7B In the inverter circuit 700 specified in the layout diagram, the front-side first layer conductors (722, 724, and 726) and power rails (40 and 20) are located in a first interconnect layer above the substrate. In the inverter circuit 700, terminal conductor 735p is electrically connected to power rail 40 via via connector 7VDDd, and power rail 40 is configured to provide a first power supply voltage VDD. Terminal conductor 735n is electrically connected to power rail 20 via via connector 7VDss, and power rail 20 is configured to provide a second power supply voltage VSS.

[0065] In inverter circuit 700, terminal conductor 738 ( Figure 7A The middle section is also electrically connected to the back-side horizontal conductor 782 via a through-hole connector 7BVD1 passing through the substrate. Figure 7B (in the middle). In addition, the gate conductor 758 is electrically connected to the back-side horizontal conductor 784 through the through-hole connector 7BVG1.

[0066] In inverter circuit 700, back-side horizontal conductor 782 is electrically connected to back-side vertical conductor 778 via through-hole connector 7BV0A. Back-side horizontal conductor 784 is electrically connected to back-side vertical conductor 775 via through-hole connector 7BV0B. In inverter circuit 700, back-side horizontal conductors 782, 784, and 786 are located in a back-side first conductive layer beneath the substrate. Back-side vertical conductors 772, 775, and 778 are located in a back-side second conductive layer beneath the back-side first conductive layer. In inverter circuit 700, back-side vertical conductor 775 serves as the input node "IN" of inverter circuit 700. Back-side vertical conductor 778 serves as the output node "ZN" of inverter circuit 700.

[0067] In inverter circuit 700, via connector 7BV0A serves as a pin connector extending in the Z direction to connect back-side vertical conductor 778 to back-side horizontal conductor 782 to carry the output signal "ZN" of inverter circuit 700. In some embodiments, the placement of the pin connector (i.e., via connector 7BV0A) provides greater flexibility without generating design rule violations when the back-side horizontal conductor 782 extends across vertical cell boundary 119. In some embodiments, the flexibility in positioning pin connectors for circuit cells with cell widths less than or equal to two CPPs improves layout area coverage in integrated circuit design. Figure 7B In this embodiment, the back-side horizontal conductor 782 extends across the vertical cell boundary 119 by a distance "Δ" in the X direction. In some embodiments, the back-side horizontal conductor 782 extends across the vertical cell boundary 119 by a distance "Δ" less than one CPP. In some embodiments, the back-side horizontal conductor 782 extends across the vertical cell boundary 119 by a distance "Δ" greater than one-eighth, one-quarter, or one-half of a CPP. In some embodiments, the distance "Δ" is chosen to be large enough to mitigate design rule violations associated with pin connector connections between the back-side vertical conductor 778 and the back-side horizontal conductor 782. In some embodiments, the distance "Δ" is chosen to be less than one CPP such that the horizontal gap distance from the vertical cell boundary 119 to the vertical cell boundary of the adjacent cell is reduced to a minimum distance to mitigate design rule violations associated with pin connector connections.

[0068] Figure 8 This is a flowchart illustrating the process 800 of designing an integrated circuit according to some embodiments. As an example, see [reference]. Figures 9A to 9C Explanation of the layout diagram Figure 8 The process is 800. Figures 9A to 9C This is a layout diagram of unit 900 according to some embodiments. For example... Figures 9A to 9CAs shown, unit 900 includes back-side horizontal conductors (981, 982, 984, and 986) in a first back-side metal layer BM0 and back-side vertical conductors (972, 975, and 978) in a second back-side metal layer BM1. A through-hole connector 1BV0A (used as a pin connector) connects the back-side vertical conductor 978 to the back-side horizontal conductor 982.

[0069] exist Figure 8 In this process, process 800 begins with the first part 805 of the design flow. The first part 805 includes design operations prior to the placement and routing of back-side traces. Example operations in the first part 805 of the design flow include placement planning, partitioning, power planning, and placement and routing of various components on the front side of the substrate. After completing the first part 805 of the design flow, process 800 proceeds to operation 810, performing automatic placement and routing (APR) on various back-side traces. Then, after operation 810, process 800 proceeds to operation 820, performing a design rule check (DRC) on the back-side trace placement design. Design rules are geometric constraints imposed on the placement design to ensure that the corresponding circuits based on the placement design can operate reliably and can be manufactured at an acceptable yield. The design rule check ensures that the placement design does not violate design rules. If the back-side trace placement design passes the design rule check, process 800 proceeds to the remainder 895 of the design flow. On the other hand, if the back-side trace placement design fails the design rule check, process 800 proceeds to operation 832. One example of a DRC failure is when the spacing between the two back-side conductors becomes too small. Another example of a DRC failure is when the pin connector is positioned too close to the edge of the back-side conductor.

[0070] In operation 832, the layout region near cell 900 is analyzed (cell 900 was found to have at least one design rule violation at operation 820) to determine whether the position of cell 900 can be moved. If the position of cell 900 can be moved, process 800 proceeds to operation 838 to fix the design rule violation, and the position of cell 900 is moved from its original position to an optional position in the modified layout design. For example, in... Figure 9A In the modified layout design shown, cell 900 is moved from its original position 902 to an optional position 908. On the other hand, in operation 832, if the position of cell 900 cannot be moved, process 800 proceeds to operation 834.

[0071] In operation 834, the layout region near cell 900 (where cell 900 was found to have at least one design rule violation in operation 820) is analyzed to determine whether the back-side horizontal trace used to support pin access can be extended. If the back-side horizontal trace can be extended, process 800 proceeds to operation 838 to correct the design rule violation and redesign the back-side horizontal trace as an extended trace that extends across the vertical cell boundary in the modified layout design. For example, in... Figure 9B In the modified layout design shown, the back-side horizontal conductor 982 (as an extended conductor) extends a distance “Δ” across the vertical cell boundary 119. On the other hand, in operation 834, if the back-side horizontal conductor used to support pin access cannot be extended, process 800 proceeds to operation 836.

[0072] In operation 836, the back-side vertical conductors used for accessing circuit nodes via pin connectors are redesigned as local two-dimensional conductors in a modified layout design, and process 800 proceeds to operation 838. The local two three-dimensional conductors have a first portion with a first width and a second portion with a second width different from the first width. For example, in... Figure 9C In the modified layout design shown, the back-side vertical guide 978 has a first portion 978A and a second portion 978B. The first portion 978A has a first width "Wa", and the second portion 978B has a second width "Wb" that is smaller than the first width "Wa". Furthermore, in... Figure 9C In the modified layout design shown, the back-side vertical conductor 975 is also modified. In some embodiments, the back-side vertical conductor 975 is modified to avoid design rule violations caused by the increased first width "Wa" of the first portion 978A. In some alternative embodiments, the back-side vertical conductor 975 is not modified, and the first portion 978A is designed to have an increased first width "Wa". In operation 836, when the back-side vertical conductor used to access the circuit node (such as...) Figure 9C When redesigning 978) as a local 2D traverse, the local 2D traverse may lead to design rule violations and may require modification of adjacent back-side vertical traverses (such as...). Figure 9C (975) to mitigate design rule violations. For example, when the back-side vertical guide 978 is changed... Figure 9C When using local two-dimensional wires, Figure 9C The back side vertical conductor 975 from Figure 9C The vertical conductor on the back side of the middle is shortened to 975. Figure 8 In the example flowchart, due to the possibility of modifying the adjacent back side vertical conductor, operation 836 is located in the process flow after operations 832 and 934.

[0073] exist Figure 8In the process, after completing operation 838 in process 800, process 800 returns to operation 810 and performs automatic placement and routing (APR) on various back-side traces. Then, process 800 proceeds to operation 820 and re-checks the modified layout design for design rule violations. The iterations including operations 838, 810, and 820 are repeated until the layout design passes the design rule check. Then, process 800 proceeds to the remainder of the design flow, 895. Example operations in the remainder of the design flow, 895, include clock tree synthesis, RC extraction, timing analysis, signal integrity analysis, verification, etc.

[0074] Figure 10 This is a flowchart of a method 1000 for manufacturing an integrated circuit according to some embodiments. Figure 10 The order of operations described in method 1000 is for illustrative purposes only; the operations of method 1000 can be performed in a different order than described in the previous section. Figure 10 The execution order described herein. It should be understood that it can be... Figure 10 Additional operations are performed before, during, and / or after the method described in the document 1000, and some other processes may be described only briefly in this document.

[0075] In operation 1010 of method 1000, a first type of active region structure and a second type of active region structure are manufactured. In some embodiments, the first type of active region structure is a p-type active region structure, and the second type of active region structure is an n-type active region structure. In some embodiments, the first type of active region structure is an n-type active region structure, and the second type of active region structure is a p-type active region structure. Figures 2A to 2E and Figures 3A to 3C In the example embodiment shown, a p-type active region structure 80p and an n-type active region structure 80n are fabricated on top of the substrate 50. Examples of active region structures fabricated in operation 1010 include fin structures, nanosheet structures, and nanowire structures.

[0076] In operations 1022 and 1024 of method 1000, a gate conductor and a terminal conductor are manufactured. Each of the gate conductor and the terminal conductor intersects with a first type of active region structure and / or a second type of active region structure on the substrate. Figures 2A to 2E and Figures 3A to 3CIn the illustrated example embodiment, the gate conductors manufactured in operation 1022 include gate conductors 152 and 158 intersecting with p-type active region structure 80p and n-type active region structure 80n. In the illustrated example embodiment, the terminal conductors manufactured in operation 1022 include terminal conductors 132p, 135p, and 138 intersecting with p-type active region structure 80p, and terminal conductors 132n, 135n, and 138 intersecting with n-type active region structure 80n. After operations 1022 and 1024, the process flow proceeds to operation 1030.

[0077] In operation 1030 of method 1000, the first layer of wires on the front side is manufactured. Figures 2A to 2E and Figures 3A to 3C In the example embodiment shown, after the top insulating layer is manufactured in the front-end process (FEOL) process, front-side first layer conductors 122, 124 and 126 in the first interconnect layer (such as the first metal layer M0) located above the top insulating layer are manufactured in operation 1030.

[0078] Following operations 1010, 1022, 1024, and 1030, the wafer containing the substrate is flipped in operation 1040. The process flow then proceeds to 1050. In operation 1050 of method 1000, through-hole connectors are fabricated through the substrate. One example of a through-hole connector fabricated in operation 1050 is a through-hole connector for connecting a gate conductor on the front side of the substrate to a wire on the back side of the substrate. Another example of a through-hole connector fabricated in operation 1050 is a through-hole connector for connecting a terminal conductor on the front side of the substrate to a wire on the back side of the substrate. Figures 2A to 2E and Figures 3A to 3C In the example embodiment shown, through-hole connectors 1BVG1, 1BVG2, and 1BVD1 are fabricated through the substrate 50 in operation 1050. After operation 1050, the process flow proceeds to operation 1060.

[0079] In operation 1060 of method 1000, a back-side horizontal conductor is fabricated on the back side of the substrate. In some embodiments, one of the back-side horizontal conductors is fabricated as a conductor extending less than one CPP across the vertical boundary of a circuit cell. Figures 2A to 2E and Figures 3A to 3C In the example embodiment shown, back-side horizontal conductors 181, 182, 184, and 186 are fabricated in a back-side first conductive layer (such as a first back-side metal layer BMO) on the back side of substrate 50. In the example embodiment, back-side horizontal conductor 182 extends across vertical cell boundary 119 by a distance “Δ” less than one CPP. After operation 1060, the process flow proceeds to operation 1070.

[0080] In operation 1070 of method 1000, a through-hole connector is manufactured. An example of a through-hole connector manufactured in operation 1070 is a through-hole connector for connecting a back-side horizontal conductor and a back-side vertical conductor. Figures 2A to 2E and Figures 3A to 3C In the example embodiment shown, through-hole connectors 1BV0A, 1BV0B, and 1BV0C are manufactured through the back-side interlayer dielectric 56 in operation 1070. After operation 1070, the process proceeds to operation 1080.

[0081] In operation 1080 of method 1000, a back-side vertical conductor is manufactured. In some embodiments, one of the back-side vertical conductors is aligned with the vertical boundary of the circuit cell and directly connected to one of the back-side horizontal conductors via a pin connector. In some embodiments, the back-side vertical conductor aligned with the vertical boundary of the circuit cell is a partial two-dimensional conductor having a first portion of a first width and a second portion of a second width different from the first width. Figures 2A to 2E and Figures 3A to 3C In the example embodiment shown, back-side vertical conductors 172, 175, and 178 are fabricated in a back-side first conductive layer (such as in a first back-side metal layer BMO). In the example embodiment, back-side vertical conductor 178 is aligned with the vertical cell boundary 119. Back-side vertical conductor 178 is electrically connected to back-side horizontal conductor 182 via a through-hole connector 1BV0A (used as a pin connector). Figures 4A to 4E In the example embodiment shown, the back-side vertical conductor 178 includes a first portion 178A having a first width “Wa” and a second portion 178B having a second width “Wb”.

[0082] In such Figures 2A to 2E and Figures 3A to 3C In the example embodiment shown, the gear ratio between the back-side vertical conductor (in the second back-side metal layer BM1) and the contact polycrystalline pitch (CPP) of the gate conductor is 1:1 (i.e., 1:1). In some alternative embodiments, the gear ratio between the back-side vertical conductor (in the second back-side metal layer BM1) and the CPP of the gate conductor is 2:3 (i.e., 2:3). In still other alternative embodiments, the gear ratio between the back-side vertical conductor (in the second back-side metal layer BM1) and the CPP of the gate conductor is 1:2 (i.e., 1:2). Other choices of gear ratios are also within the scope of this invention.

[0083] Figure 11 This is a block diagram of an electronic design automation (EDA) system 1100 according to some embodiments.

[0084] In some embodiments, EDA system 1100 includes an APR system. According to some embodiments, for example, EDA system 1100 can be used to implement a layout diagram of a design representing a circuit arrangement according to one or more embodiments described herein.

[0085] In some embodiments, the EDA system 1100 is a general-purpose computing device including a hardware processor 1102 and a non-transitory computer-readable storage medium 1104. The storage medium 1104 is encoded with (i.e., stores) computer program code 1106 (i.e., a set of executable instructions). According to one or more embodiments, execution of the instructions 1106 by the hardware processor 1102 represents (at least partially) an EDA tool that implements some or all of the methods described herein (hereinafter, the process and / or methods).

[0086] Processor 1102 is electrically coupled to computer-readable storage medium 1104 via bus 1108. Processor 1102 is also electrically coupled to I / O interface 1110 via bus 1108. Network interface 1112 is also electrically connected to processor 1102 via bus 1108. Network interface 1112 is connected to network 1114, enabling processor 1102 and computer-readable storage medium 1104 to be connected to external components via network 1114. Processor 1102 is configured to execute computer program code 1106 encoded in computer-readable storage medium 1104, so that system 1100 can be used to perform some or all of the process and / or method. In one or more embodiments, processor 1102 is a central processing unit (CPU), a multiprocessor, a distributed processing system, an application-specific integrated circuit (ASIC), and / or a suitable processing unit.

[0087] In one or more embodiments, the computer-readable storage medium 1104 is an electronic, magnetic, optical, electromagnetic, infrared, and / or semiconductor system (or apparatus or device). For example, the computer-readable storage medium 1104 includes semiconductor or solid-state memory, magnetic tape, removable computer disk, random access memory (RAM), read-only memory (ROM), hard disk, and / or optical disk. In some embodiments using optical disk, the computer-readable storage medium 1104 includes a compact disc-read-only memory (CD-ROM), a compact disc-read / write (CD-R / W), and / or a digital video disc (DVD).

[0088] In one or more embodiments, storage medium 1104 stores computer program code 1106 configured to enable system 1100 (where such execution representation is (at least partially) an EDA tool) to perform part or all of the process and / or method. In one or more embodiments, storage medium 1104 also stores information facilitating part or all of the execution of the process and / or method. In one or more embodiments, storage medium 1104 stores a library 1107 of standard cells including such standard cells as disclosed herein. In one or more embodiments, storage medium 1104 stores one or more layout diagrams 1109 corresponding to one or more layouts disclosed herein.

[0089] EDA system 1100 includes I / O interface 1110. I / O interface 1110 is coupled to external circuitry. In one or more embodiments, I / O interface 1110 includes a keyboard, keypad, mouse, trackball, trackpad, touchscreen, and / or cursor arrow keys for transmitting information and commands to processor 1102.

[0090] EDA system 1100 also includes a network interface 1112 coupled to processor 1102. Network interface 1112 allows system 1100 to communicate with network 1114, to which one or more other computer systems are connected. Network interface 1112 includes a wireless network interface, such as Bluetooth, Wi-Fi, WiMAX, GPRS, WCDMA, etc.; or a wired network interface, such as Ethernet, USB, or IEEE-1364. In one or more embodiments, some or all of the process and / or method are implemented in two or more systems 1100.

[0091] System 1100 is configured to receive information via I / O interface 1110. The information received via I / O interface 1110 includes one or more of the following: instructions, data, design rules, libraries of standard cells, and / or other parameters for processing by processor 1102. The information is transmitted to processor 1102 via bus 1108. EDA system 1100 is configured to receive UI-related information via I / O interface 1110. This information is stored as a user interface (UI) 1142 on computer-readable medium 1104.

[0092] In some embodiments, part or all of the process and / or method is implemented as a standalone software application executed by a processor. In some embodiments, part or all of the process and / or method is implemented as a software application as part of an additional software application. In some embodiments, part or all of the process and / or method is implemented as a plug-in to a software application. In some embodiments, at least one of the process and / or method is implemented as a software application as part of an EDA tool. In some embodiments, part or all of the process and / or method is implemented as a software application used by EDA system 1100. In some embodiments, a software application such as those available from CADENCE DESIGN SYSTEMS is used. Use tools or other suitable layout generation tools to generate layout diagrams that include standard cells.

[0093] In some embodiments, the process is implemented as a function of a program stored in a non-transitory computer-readable recording medium. Examples of non-transitory computer-readable recording media include, but are not limited to, external / removable and / or internal / built-in storage or storage units, such as one or more optical discs (e.g., DVDs), magnetic disks (e.g., hard disks), semiconductor memories (e.g., ROM, RAM, memory cards, etc.).

[0094] Figure 12 This is a block diagram of an integrated circuit (IC) manufacturing system 1200 and its associated IC manufacturing process according to some embodiments. In some embodiments, based on a layout diagram, at least one of (A) one or more semiconductor masks or (B) at least one component of a layer of a semiconductor integrated circuit is manufactured using the manufacturing system 1200.

[0095] exist Figure 12 In this IC manufacturing system 1200, entities such as design studio 1220, mask room 1230, and IC vendor / manufacturer (“fab”) 1250 interact with each other in the design, development, and manufacturing cycle and / or in services related to the manufacture of IC devices 1260. The entities in system 1200 are connected via a communication network. In some embodiments, the communication network is a single network. In some embodiments, the communication network is a variety of different networks, such as an intranet and the Internet. The communication network includes wired and / or wireless communication channels. Each entity interacts with one or more other entities and provides services to and / or receives services from one or more other entities. In some embodiments, two or more of design studio 1220, mask room 1230, and IC manufacturer 1250 are owned by a single, larger company. In some embodiments, two or more of design studio 1220, mask room 1230, and IC manufacturer 1250 coexist in a shared facility and use shared resources.

[0096] Design studio (or design team) 1220 generates IC design layout 1222. IC design layout 1222 includes various geometric patterns designed for IC device 1260. These geometric patterns correspond to patterns of metal, oxide, or semiconductor layers that constitute various components of the IC device 1260 to be manufactured. The layers combine to form various IC components. For example, portions of IC design layout 1222 include various IC components such as active regions, gate electrodes, source and drain electrodes, metal lines or vias for interlayer interconnects, and openings for forming bonding pads, which will be formed in a semiconductor substrate (such as a silicon wafer) and various material layers disposed on the semiconductor substrate. Design studio 1220 performs appropriate design steps to form IC design layout 1222. These design steps include one or more of logic design, physical design, or placement and routing. IC design layout 1222 is presented in one or more data files containing geometric pattern information. For example, IC design layout 1222 may be represented in GDSII or DFII file format.

[0097] Mask chamber 1230 includes data preparation 1232 and mask fabrication 1244. Mask chamber 1230 uses an IC design layout 1222 to fabricate one or more masks 1245 for fabricating various layers of an IC device 1260 according to the IC design layout 1222. Mask chamber 1230 performs mask data preparation 1232, in which the IC design layout 1222 is converted into a representative data file (“RDF”). Mask data preparation 1232 provides the RDF to mask fabrication 1244. Mask fabrication 1244 includes a mask writer. The mask writer converts the RDF into an image on a substrate, such as a mask (intermediate mask) 1245 or a semiconductor wafer 1253. The IC design layout 1222 is manipulated by mask data preparation 1232 to conform to the specific characteristics of the mask writer and / or the requirements of the IC manufacturer 1250. Figure 12 In this diagram, mask data preparation 1232 and mask manufacturing 1244 are shown as separate elements. In some embodiments, mask data preparation 1232 and mask manufacturing 1244 may be collectively referred to as mask data preparation.

[0098] In some embodiments, mask data preparation 1232 includes optical proximity correction (OPC), which uses lithographic enhancement techniques to compensate for image errors, such as those that may be caused by diffraction, interference, or other process effects. OPC adjusts the IC design layout (Figure 1222). In some embodiments, mask data preparation 1232 includes further resolution enhancement techniques (RET), such as off-axis illumination, sub-resolution aids, phase-shift masks, other suitable techniques, or combinations thereof. In some embodiments, inverse lithography (ILT) is also used, where ILT treats OPC as an inverse imaging problem.

[0099] In some embodiments, mask data preparation 1232 includes a mask rule checker (MRC). The MRC checks the IC design layout 1222, which has undergone processes in the OPC, using a set of mask creation rules. These mask creation rules include certain geometric and / or connectivity constraints to ensure sufficient margin to address variability in semiconductor manufacturing processes, etc. In some embodiments, the MRC modifies the IC design layout 1222 to compensate for constraints during mask fabrication 1244. This can undo some modifications implemented by the OPC to satisfy the mask creation rules.

[0100] In some embodiments, mask data preparation 1232 includes lithography process inspection (LPC), an LPC simulation performed by IC manufacturer 1250 to manufacture IC device 1260. The LPC simulates this process based on IC design layout 1222 to create a simulated manufactured device, such as IC device 1260. Process parameters in the LPC simulation may include parameters related to various processes in the IC manufacturing cycle, parameters related to the tools used to manufacture the IC, and / or other aspects of the manufacturing process. The LPC considers various factors, such as spatial image contrast, depth of focus (“DOF”), mask error enhancement factor (“MEEF”), other suitable factors, or combinations thereof. In some embodiments, after creating the simulated manufactured device via LPC, if the simulated device is not close enough in shape to meet design rules, OPC and / or MRC are repeated to further refine the IC design layout 1222.

[0101] It should be understood that, for clarity, the above description of mask data preparation 1232 has been simplified. In some embodiments, data preparation 1232 includes additional features such as logic operations (LOPs) to modify the IC design layout 1222 according to manufacturing rules. Furthermore, the processes applied to the IC design layout 1222 during data preparation 1232 can be performed in various different sequences.

[0102] After mask data preparation 1232 and during mask fabrication 1244, a mask 1245 or a group of masks 1245 is fabricated based on a modified IC design layout 1222. In some embodiments, mask fabrication 1244 includes performing one or more photolithographic exposures based on the IC design layout 1222. In some embodiments, a pattern is formed on the mask (photomask or intermediate mask) 1245 using a mechanism of electron beams (e-beams) or multiple electron beams based on the modified IC design layout 1222. The mask 1245 can be formed using various techniques. In some embodiments, a binary technique is used to form the mask 1245. In some embodiments, the mask pattern includes opaque regions and transparent regions. Radiation beams (such as ultraviolet (UV) beams) used to expose image-sensitive material layers (e.g., photoresist) already coated on the wafer are blocked by the opaque regions and propagate through the transparent regions. In one example, a binary mask version of mask 1245 includes a transparent substrate (e.g., fused silica) and an opaque material (e.g., chromium) coated on the opaque regions of the binary mask. In another example, mask 1245 is formed using a phase-shifting technique. In a phase-shifting mask (PSM) version of mask 1245, various components in the pattern formed on the phase-shifting mask are configured to have appropriate phase differences to improve resolution and imaging quality. In various examples, the phase-shifting mask can be attenuated PSM or alternating PSM. The mask generated by mask fabrication 1244 is used in various processes. For example, such a mask is used in ion implantation processes to form various doped regions in semiconductor wafer 1253, in etching processes to form various etched regions in semiconductor wafer 1253, and / or in other suitable processes.

[0103] IC manufacturer 1250 is an IC manufacturing business that includes one or more manufacturing facilities for manufacturing various different IC products. In some embodiments, IC manufacturer 1250 is a semiconductor foundry. For example, there may be a manufacturing facility for front-end manufacturing of multiple IC products (front-end process (FEOL) manufacturing), a second manufacturing facility for providing back-end manufacturing for interconnects and packaging of IC products (back-end process (BEOL) manufacturing), and a third manufacturing facility for providing other services for the foundry business.

[0104] IC manufacturing plant 1250 includes manufacturing tooling 1252 configured to perform various manufacturing operations on semiconductor wafer 1253, such that IC device 1260 is manufactured according to a mask (e.g., mask 1245). In various embodiments, manufacturing tooling 1252 includes a wafer stepper, ion implanter, photoresist coater, processing chamber (e.g., CVD chamber or LPCVD furnace), CMP system, plasma etching system, wafer cleaning system, or other manufacturing equipment capable of performing one or more suitable manufacturing processes as discussed herein.

[0105] IC manufacturer 1250 uses a mask (or multiple masks) 1245 manufactured by mask chamber 1230 to manufacture IC device 1260. Therefore, IC manufacturer 1250 uses IC design layout 1222 at least indirectly to manufacture IC device 1260. In some embodiments, semiconductor wafer 1253 is manufactured by IC manufacturer 1250 using mask (or multiple masks) 1245 to form IC device 1260. In some embodiments, IC manufacturing includes performing one or more photolithographic exposures at least indirectly based on IC design layout 1222. Semiconductor wafer 1253 includes a silicon substrate or other suitable substrate on which a material layer is formed. Semiconductor wafer 1253 also includes one or more of various doped regions, dielectric components, multilevel interconnects, etc. (formed in subsequent manufacturing steps).

[0106] Regarding integrated circuit (IC) manufacturing systems (e.g., Figure 12 Details of the system 1200 and its associated IC manufacturing process can be found, for example, in U.S. Patent No. 9,256,709, granted February 9, 2016; U.S. Pre-Grant Publication No. 20150278429, published October 1, 2015; U.S. Pre-Grant Publication No. 20140040838, published February 6, 2014; and U.S. Patent No. 7,260,442, granted August 21, 2007, the entire contents of which are incorporated herein by reference.

[0107] For example, in U.S. Patent No. 9,256,709, an IC design layout is generated in a design room (or design team). The IC design layout includes various geometric patterns designed for an IC device. These geometric patterns correspond to patterns of metal, oxide, or semiconductor layers that constitute various components of the IC device to be manufactured. The various layers combine to form various IC functions. For example, portions of the IC design layout include various IC components such as active regions, gate electrodes, source and drain electrodes, metal lines or vias for interlayer interconnects, and openings for forming pads in the semiconductor. These openings will be formed on a semiconductor substrate (e.g., a silicon wafer) and various material layers disposed on the semiconductor substrate. The design room performs appropriate design processes to form the IC design layout. These design processes may include logic design, physical design, and / or placement and routing. The IC design layout is presented in one or more data files containing geometric pattern information. A mask room uses the IC design layout to fabricate one or more masks, which are used to fabricate the various layers of the IC device according to the IC design layout. The mask room performs mask data preparation, in which the IC design layout is converted into a form that can be physically written by a mask writer. The design layout prepared by mask data preparation is modified to conform to a specific mask manufacturer and / or mask vendor before fabrication. In this embodiment, mask data preparation and mask fabrication are illustrated as separate elements; however, they can be collectively referred to as mask data preparation. Mask data preparation typically includes optical proximity correction (OPC), which uses lithographic enhancement techniques to compensate for image errors, such as those that may be caused by diffraction, interference, or other processing effects. Mask data preparation may include other resolution enhancement techniques (RET), such as off-axis illumination, sub-resolution auxiliary features, phase-shift masks, other suitable techniques, or combinations thereof. Mask data preparation 132 also includes a mask rule checker (MRC), which uses a set of mask creation rules to check the IC design layout that has already been processed in the OPC. These mask creation rules may include some geometric and connectivity constraints to ensure sufficient margin.

[0108] For example, in U.S. Prelicense Publication No. 20150278429, in one embodiment, the IC manufacturing system may employ maskless lithography techniques, such as electron beam lithography or optical maskless lithography. In such a system, mask fabrication is bypassed, and the IC design layout is modified through data preparation suitable for wafer processing using a specific maskless lithography technique. The data preparation modifies the design layout to suit subsequent operations in the IC manufacturing system. The result of the data preparation is represented by one or more data files, such as files in GDSII or DFII file formats. The one or more data files include information on geometric patterns, such as polygons representing primary design patterns and / or auxiliary components. In this embodiment, the one or more data files also include auxiliary data generated by the data preparation. The auxiliary data will be used to enhance various operations of the IC manufacturing system, such as mask fabrication performed in the mask chamber and wafer exposure performed by the IC manufacturer.

[0109] For example, in U.S. Prelicity License No. 20140040838, an IC design layout is presented in one or more data files containing geometric pattern information. In one example, the IC design layout is represented in the “GDS” format known in the art. In alternative embodiments, the IC design layout may be transferred between components in an IC manufacturing system in alternative file formats such as DFII, CIF, OASIS, or any other suitable file type. IC design layout 300 includes various geometric patterns representing components of an integrated circuit. For example, the IC design layout may include primary IC components such as active regions, gate electrodes, source and drain electrodes, metal lines, interlayer interconnect vias, and openings for forming pads in the semiconductor, the openings being formed on a semiconductor substrate (e.g., a silicon wafer) and various material layers disposed on the semiconductor substrate. The IC design layout may also include auxiliary components, such as those for imaging effects, processing enhancement and / or mask recognition information.

[0110] For example, in U.S. Patent No. 7,260,442, a mask manufacturing system includes: a processing tool for processing a mask; a metrology tool connected to the processing tool for inspecting the mask and obtaining inspection results; and a controller coupled to the processing tool and the metrology tool for generating a manufacturing model of the processing tool and calibrating the manufacturing model based on equipment data, material data, and the mask inspection results. The mask manufacturing system may include at least one processing tool, a metrology tool, a controller, a database, and a manufacturing execution system. The processing tool may be an exposure tool, a developer, an etcher, or a photoresist stripper. The metrology tool performs post-etch or post-stripping inspections and obtains post-etch or post-stripping inspection results, respectively. The controller provides operation-to-operation control for the processing tool, including feedforward and feedback control. The controller receives post-etch or post-stripping inspection results from the metrology tool and retrieves device and material data from the database. The controller, connected to the manufacturing execution system, generates a manufacturing model of the processing tool and calibrates the manufacturing model based on equipment data, material data, and the mask inspection results.

[0111] One aspect of the present invention relates to an integrated circuit. The integrated circuit includes: a first type of active region structure and a second type of active region structure extending in a first direction on a substrate; a front-side first layer of conductors in a first interconnect layer above the substrate; and a plurality of gate conductors extending in a second direction below the first interconnect layer. Two adjacent gate conductors are separated by a spacing distance equal to the contact polypropylene pitch (“CPP”). The integrated circuit also includes circuit cells having a first vertical boundary and a second vertical boundary extending in a second direction perpendicular to the first direction. Each of the first and second vertical boundaries spans at least one boundary isolation region, and the distance between the first and second vertical boundaries along the first direction is less than or equal to three CPPs. The integrated circuit also includes a back-side horizontal conductor extending in the first direction in a back-side first conductive layer below the substrate, a back-side vertical conductor extending in the second direction in a back-side second conductive layer below the back-side first conductive layer, and pin connections for the circuit cells directly connecting the back-side horizontal conductor and the back-side vertical conductor. The back-side horizontal conductor extends across the first vertical boundary of the circuit cell. The back-side vertical conductor is aligned with the first vertical boundary.

[0112] In the aforementioned integrated circuit, the distance by which the back-side horizontal conductor extends across the first vertical boundary of the circuit cell is less than one contact polycrystalline pitch but greater than one-eighth of the contact polycrystalline pitch.

[0113] In the aforementioned integrated circuit, the distance by which the back-side horizontal conductor extends across the first vertical boundary of the circuit cell is less than one contact polycrystalline pitch but greater than one-quarter of the contact polycrystalline pitch.

[0114] In the aforementioned integrated circuit, the distance by which the back-side horizontal conductor extends across the first vertical boundary of the circuit cell is less than one contact polycrystalline pitch but greater than half of the contact polycrystalline pitch.

[0115] In the aforementioned integrated circuit, the width of the back-side vertical conductor along the first direction is greater than three-quarters of the contact polycrystalline pitch.

[0116] In the aforementioned integrated circuit, the width of the back-side vertical conductor along the first direction is greater than half of the contact polycrystalline pitch.

[0117] In the aforementioned integrated circuit, the distance between the first vertical boundary and the second vertical boundary along the first direction is less than or equal to two contact polycrystalline pitches.

[0118] Another aspect of the invention relates to an integrated circuit. The integrated circuit includes a first type of active region structure and a second type of active region structure extending in a first direction on a substrate, a front-side first layer conductor in a first interconnect layer above the substrate, and a plurality of gate conductors extending in a second direction below the first interconnect layer. Two adjacent gate conductors are separated by a spacing distance equal to the contact polypropylene pitch (“CPP”). The integrated circuit also includes circuit cells having a first vertical boundary and a second vertical boundary extending in a second direction perpendicular to the first direction. Each of the first and second vertical boundaries spans at least one boundary isolation region. The integrated circuit also includes a back-side horizontal conductor extending in the first direction in a back-side first conductive layer below the substrate, a back-side vertical conductor extending in the second direction in a back-side second conductive layer below the back-side first conductive layer, and a pin connector for the circuit cell directly connected between the back-side horizontal conductor and the back-side vertical conductor at an overlap region between the back-side horizontal conductor and the back-side vertical conductor. The back-side vertical conductor has a first portion covering the overlap region and a second portion located outside the overlap region. A first width along the first direction is greater than a second width along the second direction.

[0119] In the aforementioned integrated circuit, the first width is larger than the second width by more than one-eighth of the contact polycrystalline pitch.

[0120] In the aforementioned integrated circuit, the first width is greater than the second width by more than a quarter of the contact polycrystalline pitch.

[0121] In the aforementioned integrated circuit, the distance between the first vertical boundary and the second vertical boundary along the first direction is less than or equal to three contact polycrystalline pitches.

[0122] In the aforementioned integrated circuit, the distance between the first vertical boundary and the second vertical boundary along the first direction is less than or equal to two contact polycrystalline pitches.

[0123] In the aforementioned integrated circuit, the distance by which the back-side horizontal conductor extends across the first vertical boundary of the circuit cell is less than one contact polycrystalline pitch but greater than one-eighth of the contact polycrystalline pitch.

[0124] In the aforementioned integrated circuit, the distance by which the back-side horizontal conductor extends across the first vertical boundary of the circuit cell is less than one contact polycrystalline pitch but greater than one-quarter of the contact polycrystalline pitch.

[0125] Another aspect of the invention relates to a method. The method includes fabricating a first type of active region structure and a second type of active region structure extending in a first direction on a substrate, and fabricating a plurality of gate conductors extending in a second direction perpendicular to the first direction. Each gate conductor intersects with the first type of active region structure and / or the second type of active region structure above the substrate. Two adjacent gate conductors are separated by a spacing distance equal to the contact polycrystalline pitch (CPP). The method also includes fabricating a back-side horizontal conductor extending in the first direction in a back-side first conductive layer beneath the substrate, fabricating pin connections connected to the back-side horizontal conductor, and fabricating a back-side vertical conductor extending in the second direction in a back-side second conductive layer beneath the back-side first conductive layer, the back-side vertical conductor being aligned with a first vertical boundary of a circuit cell. The pin connections are directly connected between the back-side horizontal conductor and the back-side vertical conductor at an overlap region between them. In this method, fabricating the back-side horizontal conductor includes fabricating it as an extension conductor extending across the first vertical boundary of the circuit cell by a distance less than one CPP.

[0126] In the above method, the method further includes: manufacturing a back-side vertical conductor to form a first portion covering the overlapping area and a second portion located outside the overlapping area, wherein a first width of the first portion along a first direction is greater than a second width of the second portion along the first direction.

[0127] In the above method, the method further includes: fabricating a front-side first layer of wires in a first interconnect layer above the substrate and above the plurality of gate conductors.

[0128] In the above method, manufacturing the back-side horizontal conductor includes:

[0129] The back-side horizontal conductor is fabricated as an extension conductor that extends across the first vertical boundary of the circuit cell, with the extension distance being less than one contact polycrystalline pitch but greater than one-eighth of the contact polycrystalline pitch.

[0130] In the above method, manufacturing the back-side horizontal conductor includes: manufacturing the back-side horizontal conductor as an extension conductor extending across the first vertical boundary of the circuit cell, the extension distance being less than one contact polycrystalline pitch but greater than one-quarter of the contact polycrystalline pitch.

[0131] In the above method, manufacturing the back-side vertical conductor includes: manufacturing the back-side vertical conductor as a conductor with a uniform width, the width being greater than half of the contact polycrystalline spacing.

[0132] Those skilled in the art will readily recognize that one or more of the disclosed embodiments achieve one or more of the advantages described above. Having read the foregoing specification, those skilled in the art will be able to influence various variations, equivalent substitutions, and various other embodiments as broadly disclosed herein. Therefore, the protection granted herein is intended to be limited only to the definitions contained in the appended claims and their equivalents.

Claims

1. An integrated circuit, comprising: a first type of active area structure and a second type of active area structure on a substrate and extending in a first direction; a front side first layer of conductive lines in a first connection layer above the substrate; a plurality of gate conductors below the first connection layer and extending in a second direction, and wherein two adjacent gate conductors are separated by a pitch distance, the pitch distance being equal to a contact poly pitch; a circuit cell having a first vertical boundary and a second vertical boundary extending in the second direction perpendicular to the first direction, wherein each of the first vertical boundary and the second vertical boundary spans at least one boundary isolation region, and wherein a distance between the first vertical boundary and the second vertical boundary along the first direction is less than or equal to three contact poly pitches; a back side horizontal conductor in a back side first conductive layer below the substrate and extending in the first direction, wherein the back side horizontal conductor extends across the first vertical boundary of the circuit cell; a back side vertical conductor in a back side second conductive layer below the back side first conductive layer and extending in the second direction, wherein the back side vertical conductor is aligned with the first vertical boundary, wherein a front side and a back side of the substrate are opposite in a third direction, the third direction being perpendicular to the first direction and the second direction; and a pin connection for the circuit cell directly connected between the back side horizontal conductor and the back side vertical conductor.

2. The integrated circuit of claim 1, wherein, The distance that the back side horizontal conductor extends across the first vertical boundary of the circuit cell is less than one contact poly pitch but greater than one eighth of the contact poly pitch.

3. The integrated circuit of claim 1, wherein, The distance that the back side horizontal conductor extends across the first vertical boundary of the circuit cell is less than one contact poly pitch but greater than one fourth of the contact poly pitch.

4. The integrated circuit of claim 1, wherein, The distance that the back side horizontal conductor extends across the first vertical boundary of the circuit cell is less than one contact poly pitch but greater than one half of the contact poly pitch.

5. The integrated circuit of claim 1, wherein, A width of the back side vertical conductor along the first direction is greater than three fourths of the contact poly pitch.

6. The integrated circuit of claim 1, wherein, A width of the back side vertical conductor along the first direction is greater than one half of the contact poly pitch.

7. The integrated circuit of claim 1, wherein, The distance between the first vertical boundary and the second vertical boundary along the first direction is less than or equal to two contact poly pitches.

8. An integrated circuit, comprising: a first type of active area structure and a second type of active area structure on a substrate and extending in a first direction; a front side first layer of conductive lines in a first connection layer above the substrate; a plurality of gate conductors below the first connection layer and extending in a second direction, and wherein two adjacent gate conductors are separated by a pitch distance, the pitch distance being equal to a contact poly pitch, a circuit cell having a first vertical boundary and a second vertical boundary extending in a second direction perpendicular to the first direction, wherein each of the first vertical boundary and the second vertical boundary spans at least one boundary isolation region; a backside horizontal wire in a backside first conductive layer below the substrate and extending in the first direction; a backside vertical wire in a backside second conductive layer below the backside first conductive layer and extending in the second direction, wherein a front side and a backside of the substrate oppose in a third direction perpendicular to the first direction and the second direction; a pin connection for the circuit cell directly connected between the backside horizontal wire and the backside vertical wire at an overlap region between the backside horizontal wire and the backside vertical wire; and wherein the backside vertical wire has a first portion covering the overlap region and a second portion outside the overlap region, and wherein a first width of the first portion along the first direction is greater than a second width of the second portion along the first direction.

9. The integrated circuit of claim 8, wherein, the first width is greater than the second width by an amount more than one-eighth of the contact poly pitch.

10. The integrated circuit of claim 8, wherein, the first width is greater than the second width by an amount more than one-fourth of the contact poly pitch.

11. The integrated circuit of claim 8, wherein, the first vertical boundary and the second vertical boundary are separated along the first direction by a distance less than or equal to three contact poly pitches.

12. The integrated circuit of claim 8, wherein, the first vertical boundary and the second vertical boundary are separated along the first direction by a distance less than or equal to two contact poly pitches.

13. The integrated circuit of claim 8, wherein, the backside horizontal wire extends across the first vertical boundary of the circuit cell by a distance less than one contact poly pitch but greater than one-eighth of the contact poly pitch.

14. The integrated circuit of claim 8, wherein, the backside horizontal wire extends across the first vertical boundary of the circuit cell by a distance less than one contact poly pitch but greater than one-fourth of the contact poly pitch.

15. A method of forming an integrated circuit, comprising: fabricating, on a substrate, first-type active region structures and second-type active region structures extending in a first direction; fabricating a plurality of gate conductors extending in a second direction perpendicular to the first direction, wherein each of the gate conductors intersects the first-type active region structures and / or the second-type active region structures above the substrate, and wherein two adjacent gate conductors are separated by a pitch distance equal to a contact poly pitch; fabricating a backside horizontal wire extending in the first direction in a backside first conductive layer below the substrate; fabricating a pin connection connected to the backside horizontal wire; fabricating backside vertical wires extending in the second direction in a backside second conductive layer under the backside first conductive layer, wherein the backside vertical wires are aligned with the first vertical boundaries of the circuit cells, and wherein the pin connections are directly connected between the backside horizontal wires and the backside vertical wires at overlapping areas between the backside horizontal wires and the backside vertical wires, wherein a front side and a back side of the substrate are opposite in a third direction, the third direction being perpendicular to the first direction and the second direction; and wherein fabricating the backside horizontal wires includes fabricating the backside horizontal wires as extended wires extending across the first vertical boundaries of the circuit cells by a distance that is less than one of the contact poly pitch.

16. The method of claim 15, further comprising: fabricating the backside vertical wires to form a first portion covering the overlapping areas and a second portion located outside the overlapping areas, and wherein a first width of the first portion along the first direction is greater than a second width of the second portion along the first direction.

17. The method of claim 15, further comprising: fabricating front side first layer wires in a first connection layer over the substrate and over the plurality of gate conductors.

18. The method of claim 15, wherein, fabricating the backside horizontal wires includes: fabricating the backside horizontal wires as extended wires extending across the first vertical boundaries of the circuit cells by a distance that is less than one of the contact poly pitch but greater than one eighth of the contact poly pitch.

19. The method of claim 15, wherein, fabricating the backside horizontal wires includes: fabricating the backside horizontal wires as extended wires extending across the first vertical boundaries of the circuit cells by a distance that is less than one of the contact poly pitch but greater than one fourth of the contact poly pitch.

20. The method of claim 15, wherein, fabricating the backside vertical wires includes: fabricating the backside vertical wires as wires having a uniform width that is greater than half of the contact poly pitch.

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