Array substrate and display panel

Abstract

An embodiment of the present application provides an array substrate and a display panel; the array substrate includes a substrate, an active layer having a plurality of patterned active portions, and a first inter-insulating layer having a plurality of patterned covering portions, wherein a covering portion corresponds to at least one active portion, wherein, in the top view direction of the array substrate, the orthographic projection of the active portion on the substrate is located within the orthographic projection of the corresponding covering portion on the substrate; the array substrate is formed by patterning the first inter-insulating layer arranged corresponding to the active layer in the array substrate to form a plurality of patterned covering portions, and in the top view direction of the array substrate, the orthographic projection of the active portion on the substrate is located within the orthographic projection of the corresponding covering portion on the substrate, so that the first inter-insulating layer forms a separated island structure on the substrate while covering the area of ​​the active layer, thereby avoiding the insulating layer design of forming a continuous structure in the area covering the active layer, and improving the bending resistance of the array substrate.

Description

Technical Field

[0001] The present application relates to the field of display, and in particular to an array substrate and a display panel. Background Art

[0002] Thin film transistors are widely used in display backplane technology. Thin film transistors with top-gate structures can greatly improve the parasitic capacitance problem caused by the overlap of the source, drain and gate in the vertical direction. In the current traditional thin film transistor structure with top-gate structure, there is a continuous inorganic inter-insulating layer between the source, drain and gate, and the thickness is relatively thick (about 500 nanometers). When the traditional top-gate thin film transistor is used to prepare a flexible display panel, the inter-insulating layer in the flexible display panel generates too much stress when it is bent. Excessive stress will cause the inter-insulating layer to break, resulting in the problem of metal wire disconnection in the source and drain layer, affecting the yield of the product.

[0003] Therefore, an array substrate and a display panel are urgently needed to solve the above technical problems. Summary of the invention

[0004] The embodiments of the present application provide an array substrate and a display panel, which can improve the technical problem that during the bending process of the current display panel, the functional film layer in the thin film transistor is easily broken due to the bending stress, resulting in the disconnection of the metal wires in the source and drain layer.

[0005] The embodiment of the present application provides an array substrate, comprising: a substrate, an active layer disposed on the substrate, and a first interlayer insulating layer disposed on the active layer, wherein the active layer further comprises a plurality of patterned active portions, and the first interlayer insulating layer comprises a plurality of patterned covering portions, wherein one of the covering portions corresponds to at least one of the active portions;

[0006] Wherein, in the top view direction of the array substrate, the orthographic projection of the active portion on the substrate is located within the orthographic projection of the corresponding covering portion on the substrate.

[0007] Optionally, in some embodiments of the present application, the array substrate further comprises a second insulating layer disposed on the substrate and partially covering each of the covering portions;

[0008] The bending strength of the material of the second insulating layer is greater than the bending strength of the first insulating layer.

[0009] Optionally, in some embodiments of the present application, the material of the first insulating layer is at least one of silicon nitride, silicon oxide and silicon oxynitride, and the material of the second insulating layer is at least one of acrylic resin, polycarbonate and polystyrene.

[0010] Optionally, in some embodiments of the present application, the array substrate further comprises a first electrode layer disposed on the second inter-insulating layer and in contact with a portion of the covering portion, and a source-drain pattern disposed on the first electrode layer, wherein the source-drain pattern comprises a source electrode and a drain electrode;

[0011] Among them, the array substrate is provided with a first via hole and a second via hole, both of which penetrate the covering part and the first electrode layer; the source is connected to the active part through the first via hole, and the drain is connected to the active part through the second via hole.

[0012] Optionally, in some embodiments of the present application, in the top view direction of the array substrate, the orthographic projection of the source and drain pattern on the substrate is located within the orthographic projection of the corresponding covering portion on the substrate.

[0013] Optionally, in some embodiments of the present application, in the top view direction of the array substrate, the orthographic projection of the first electrode layer on the substrate is located within the orthographic projection of the source and drain pattern on the substrate.

[0014] Optionally, in some embodiments of the present application, the array substrate further includes a gate insulating layer and a gate, the gate insulating layer is disposed on the substrate and completely covers the active layer, and the gate is disposed on the gate insulating layer and corresponds to the active layer;

[0015] The covering portion is disposed on the gate insulating layer and covers the gate, and the second interlayer insulating layer is disposed on the gate insulating layer and covers a portion of the first interlayer insulating layer.

[0016] Optionally, in some embodiments of the present application, in the top view direction of the array substrate, the orthographic projection of the covering portion on the substrate is located within the orthographic projection of the corresponding second inter-insulating layer on the substrate;

[0017] Wherein, the thickness of the first insulating layer is smaller than the thickness of the second insulating layer.

[0018] Optionally, in some embodiments of the present application, the array substrate further includes a buffer layer, the buffer layer is disposed between the substrate and the gate insulating layer, and the active portion is disposed on the buffer layer;

[0019] Wherein, the material of the buffer layer is the same as that of the first insulating layer.

[0020] Correspondingly, an embodiment of the present application further provides a display panel, comprising an array substrate and a plurality of light-emitting devices disposed on the array substrate, wherein the array substrate comprises a substrate, an active layer disposed on the substrate, and a first interlayer insulating layer disposed on the active layer, wherein the active layer further comprises a plurality of patterned active portions, and the first interlayer insulating layer comprises a plurality of patterned covering portions, wherein one of the covering portions corresponds to at least one of the active portions;

[0021] Wherein, in the top view direction of the array substrate, the orthographic projection of the active portion on the substrate is located within the orthographic projection of the corresponding covering portion on the substrate.

[0022] The embodiment of the present application provides an array substrate and a display panel; the array substrate comprises: a substrate, an active layer arranged on the substrate, and a first inter-insulating layer arranged on the active layer, the active layer further comprising a plurality of patterned active parts, the first inter-insulating layer comprising a plurality of patterned covering parts, one of the covering parts corresponding to at least one of the active parts, wherein in the top view direction of the array substrate, the orthographic projection of the active part on the substrate is located within the orthographic projection of the corresponding covering part on the substrate; the array substrate is formed by patterning the first inter-insulating layer arranged corresponding to the active layer in the array substrate to form a plurality of patterned covering parts, and in the top view direction of the array substrate, the orthographic projection of the active part on the substrate is located within the orthographic projection of the corresponding covering part on the substrate, so that the first inter-insulating layer forms a separated island structure on the substrate while covering the area of ​​the active layer, avoiding the design of an insulating layer with a continuous structure formed in the area covering the active layer, thereby reducing the stress acting on the active layer and other metal film layers when the array substrate is bent, improving the bending resistance of the array substrate, and further improving the product yield of the display panel. BRIEF DESCRIPTION OF THE DRAWINGS

[0023] In order to more clearly illustrate the technical solutions in the embodiments of the present application, the drawings required for use in the description of the embodiments will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present application. For those skilled in the art, other drawings can be obtained based on these drawings without paying any creative work.

[0024] Figure 1 A schematic diagram of a first cross-sectional structure of an array substrate provided in an embodiment of the present application;

[0025] Figure 2 A schematic diagram of a second cross-sectional structure of an array substrate provided in an embodiment of the present application;

[0026] Figure 3It is a schematic diagram of the process of manufacturing the array substrate provided by the present application;

[0027] Figure 4A-4F This is the specific process of the method for manufacturing the array substrate provided in this application. DETAILED DESCRIPTION

[0028] The following will be combined with the drawings in the embodiments of the present application to clearly and completely describe the technical solutions in the embodiments of the present application. Obviously, the described embodiments are only part of the embodiments of the present application, not all of the embodiments. Based on the embodiments in the present application, all other embodiments obtained by those skilled in the art without creative work are within the scope of protection of the present application. In addition, it should be understood that the specific implementation methods described herein are only used to illustrate and explain the present application, and are not used to limit the present application. In the present application, unless otherwise stated, the directional words used, such as "upper" and "lower", generally refer to the upper and lower parts of the device in actual use or working state, specifically the drawing direction in the accompanying drawings; and "inside" and "outside" refer to the outline of the device.

[0029] The embodiments of the present application are directed to the technical problem that during the bending process of the current display panel, the functional film layer in the thin film transistor is easily broken due to the bending stress, which causes the metal wires in the source and drain pattern to be disconnected. The embodiments of the present application can improve the above technical problem.

[0030] The technical solution of the present application is now described in conjunction with specific embodiments.

[0031] See also Figure 1 to Figure 2 The embodiment of the present application provides an array substrate 100, the array substrate 100 includes a substrate 101, an active layer 103 disposed on the substrate 101, and a first interlayer insulating layer 106 disposed on the active layer 103, the active layer 103 further includes a plurality of patterned active portions 1031, the first interlayer insulating layer 106 includes a plurality of patterned covering portions, and one of the covering portions corresponds to at least one of the active portions 1031;

[0032] In the top view direction of the array substrate 100 , the orthographic projection of the active portion 1031 on the substrate 101 is located within the orthographic projection of the corresponding covering portion on the substrate 101 .

[0033] The array substrate 100 provided in the embodiment of the present application is formed with a plurality of patterned covering portions after patterning the first inter-insulating layer 106 corresponding to the active layer 103 in the array substrate 100, and in the top view direction of the array substrate 100, the orthographic projection of the active portion 1031 on the substrate 101 is located within the orthographic projection of the corresponding covering portion on the substrate 101, so that the first inter-insulating layer 106 forms a separated island structure on the substrate 101 while covering the area of ​​the active layer 103, thereby avoiding the design of an insulating layer that forms a continuous structure in the area covering the active layer 103, thereby reducing the stress acting on the active layer 103 and other metal film layers when the array substrate 100 is bent, improving the bending resistance of the array substrate 100, and further improving the product yield of the display panel.

[0034] The technical solution of the present application is now described in conjunction with specific embodiments.

[0035] Embodiment 1

[0036] like Figure 1 , which is a schematic diagram of a first cross-sectional structure of an array substrate 100 provided in an embodiment of the present application; wherein the array substrate 100 includes a substrate 101, an active layer 103 disposed on the substrate 101, and a first interlayer insulating layer 106 disposed on the active layer 103, the active layer 103 further includes a plurality of patterned active portions 1031, the first interlayer insulating layer 106 includes a plurality of patterned covering portions, and one of the covering portions corresponds to one of the active portions 1031;

[0037] In the top view direction of the array substrate 100 , the orthographic projection of the active portion 1031 on the substrate 101 is located within the orthographic projection of the corresponding covering portion on the substrate 101 .

[0038] In the embodiment of the present application, the array substrate 100 includes a plurality of thin film transistors. In each of the thin film transistors, the array substrate 100 also includes: a buffer layer 102 disposed on the substrate 101, the active portion 1031 disposed on the buffer layer 102, a gate insulating layer 104 disposed on the buffer layer 102 and covering the active portion 1031, a gate 105 disposed on the gate insulating layer 104 and corresponding to the active portion 1031, the first interlayer insulating layer 106 disposed on the gate insulating layer 104 and completely covering the gate 105, and the second interlayer insulating layer 107 disposed on the gate insulating layer 104.

[0039] Furthermore, the substrate 101 may be a polyimide film, and the substrate 101 may be composed of one or more layers of PI flexible substrate. The material of the buffer layer 102 may be one or more inorganic materials such as silicon nitride, silicon oxide, silicon oxynitride or silicon dioxide, which may isolate water and oxygen. The material of the active layer 103 may be a metal oxide semiconductor material such as indium gallium zinc oxide or indium zinc oxide. The material of the gate insulating layer 104 may be one or more inorganic materials such as silicon nitride, silicon oxide, silicon oxynitride or silicon dioxide, which may provide insulation protection. The material of the gate insulating layer 104 may also be other organic materials with insulating effects, which may further reduce the inorganic film layers in the array substrate 100. The material of the gate 105 may be a metal material with excellent conductivity such as molybdenum, copper and aluminum.

[0040] In the embodiment of the present application, the bending strength of the material of the second insulating layer 107 is greater than the bending strength of the first insulating layer 106; specifically, the material of the first insulating layer 106 is an inorganic material, and the material of the second insulating layer 107 is an organic material.

[0041] Preferably, the material of the first insulating layer 106 may be one or more inorganic materials such as silicon nitride, silicon oxide or silicon oxynitride, which is used to isolate water and oxygen, play the role of insulation and protection of other functional film layers. The material of the second insulating layer 107 may be one or more organic materials such as acrylic resin, polycarbonate and polystyrene, which is used to relieve the stress generated by the first insulating layer 106, thereby enhancing the bending resistance of the array substrate 100 and avoiding the generation of cracks.

[0042] The array substrate 100 provided in this embodiment sets the first inter-insulating layer 106 to an inorganic material and the second inter-insulating layer 107 to an organic material. Compared with the prior art in which the materials of the intermediate insulating layers are all inorganic materials, the inorganic film layers in the array substrate 100 are effectively reduced, the bending resistance of the array substrate 100 is improved, and cracks are avoided.

[0043] In the embodiment of the present application, the array substrate 100 further includes a first electrode layer 108 disposed on the second inter-insulating layer 107 and in contact with a portion of the covering portion, and a source-drain pattern disposed on the first electrode layer 108, wherein the source-drain pattern includes a source electrode 109 and a drain electrode 110;

[0044] Among them, the array substrate 100 is provided with a first via hole 1081 and a second via hole 1082, and the first via hole 1081 and the second via hole 1082 both penetrate the covering part and the first electrode layer 108; the source 109 is connected to the active part 1031 through the first via hole 1081, and the drain 110 is connected to the active part 1031 through the second via hole 1082.

[0045] In the embodiment of the present application, the material of the source and drain patterns may be a metal material with excellent conductivity such as molybdenum, copper and aluminum; the material of the first electrode layer 108 is at least one of indium tin oxide and indium gallium tin oxide.

[0046] Furthermore, in the top view direction of the array substrate 100, the orthographic projection of the first electrode layer 108 on the substrate 101 is located within the orthographic projection of the source-drain pattern on the substrate 101. This design allows the first electrode layer 108 to separate the source-drain pattern from the inter-insulating layer, thereby avoiding corrosion problems caused by the source-drain pattern made of metal material directly contacting the second inter-insulating layer 107 made of organic material.

[0047] In the embodiment of the present application, in the top view direction of the array substrate 100, the orthographic projection of the source and drain patterns on the substrate 101 is located within the orthographic projection of the corresponding covering portion on the substrate 101. This design can ensure that the covering portion protects the area where the source and drain patterns are located, and reduce the impact of external factors on the performance of the thin film transistor.

[0048] In the embodiment of the present application, the pattern of the covering portion is an irregular pattern, preferably a trapezoid; wherein the covering portion completely covers each surface of the active portion 1031 and the gate 105, and can reduce the coverage area of ​​the first inter-insulating layer 106 to the maximum extent.

[0049] In the embodiment of the present application, the thickness of the first inter-insulating layer 106 is less than the thickness of the second inter-insulating layer 107, so that the covered portion not covered by the first electrode layer 108 is completely filled with the source-drain pattern and the second inter-insulating layer 107. Since the material of the second inter-insulating layer 107 is an organic material, when the array substrate 100 is bent, the stress on the first inter-insulating layer 106 between the source 109 and the drain 110 can be reduced, and the source 109 located in the first via hole 1081 and the drain 110 located in the second via hole 1082 are prevented from being broken, thereby further improving the stability of the device.

[0050] In addition, since the thickness of the first insulating layer 106 is 100 nanometers to 500 nanometers, which is very thick, the thickness of the second insulating layer 107 is set to be greater than the thickness of the first insulating layer 106, so that a certain distance is maintained between the source and drain pattern and the gate 105, avoiding electrostatic interference or signal crosstalk between the source and drain pattern and the gate 105.

[0051] In the embodiment of the present application, in the top view direction of the array substrate 100, the orthographic projection of the covering portion on the substrate 101 is located within the orthographic projection of the corresponding second inter-insulating layer 107 on the substrate 101; such a design can ensure that both ends of the edge of the first inter-insulating layer 106 are completely covered by the second inter-insulating layer 107. Since the material of the second inter-insulating layer 107 is an organic material, when the array substrate 100 is bent, the stress on both ends of the edge of the first inter-insulating layer 106 can be reduced, and the film layer on both ends of the edge of the first inter-insulating layer 106 can be prevented from being broken, thereby further improving the stability of the device.

[0052] In the embodiment of the present application, the plurality of thin film transistors on the array substrate 100 are of a top gate structure, which can greatly improve the parasitic capacitance problem caused by the overlap of the source and drain patterns with the gate 105 in the vertical direction.

[0053] In the embodiment of the present application, the first interlayer insulating layer 106 is patterned and separated from each other on the gate 105, and covers the area where the patterned active layer 103 is located, and the first interlayer insulating layer 106 is filled and planarized with the second interlayer insulating layer 107 of organic insulating material; then, a source-drain pattern is prepared on the second interlayer insulating layer 107, and a layer of indium tin oxide is added between the second interlayer insulating layer 107 and the source-drain pattern to avoid the corrosion problem caused by the source-drain pattern of metal material directly contacting the second interlayer insulating layer 107 of organic material. With this flexible backplane of thin film transistor structure, the island-shaped first interlayer insulating layer 106 can still protect the active layer 103 from external factors, and the continuous second interlayer insulating layer 107 is more resilient and not easy to break when bent.

[0054] In the embodiment of the present application, the material of the first insulating layer 106 needs to be an inorganic material, because the water and oxygen isolation performance of organic materials is weaker than that of inorganic materials; the original intention of the embodiment of the present application is to use inorganic materials to prepare the discrete island-shaped patterned first insulating layer 106, which not only ensures the protection of the active layer 103 area, reduces the influence of external factors on the performance of the thin film transistor, but also prevents the accumulation of stress on a continuous scale when bending. Organic insulating materials are used to achieve flattening. Compared with inorganic materials, organic materials have less stress when bending. The use of the first electrode layer 108 can avoid corrosion caused by direct contact of organic materials with metal electrodes.

[0055] In view of the technical problem that during the bending process of the current display panel, the functional film layer in the thin film transistor is easily broken under the action of bending stress, which causes the metal wire of the source and drain layer to be disconnected, an array substrate 100 provided in an embodiment of the present application includes: a substrate 101, an active layer 103 arranged on the substrate 101, and a first interlayer insulating layer 106 arranged on the active layer 103, the active layer 103 also includes a plurality of patterned active parts 1031, the first interlayer insulating layer 106 includes a plurality of patterned covering parts, one of the covering parts corresponds to one of the active parts 1031, wherein, in the top view direction of the array substrate 100, the orthographic projection of the active part 1031 on the substrate 101 is located within the orthographic projection of the corresponding covering part on the substrate 101; the above-mentioned array substrate 100 is The first inter-insulating layer 106 corresponding to the active layer 103 in the array substrate 100 is patterned to form a plurality of patterned covering portions, and in the top view direction of the array substrate 100, the orthographic projection of the active portion 1031 on the substrate 101 is located within the orthographic projection of the corresponding covering portion on the substrate 101, so that the first inter-insulating layer 106 forms a separated island structure on the substrate 101 while covering the area of ​​the active layer 103, thereby avoiding the design of an insulating layer that forms a continuous structure in the area covering the active layer 103, thereby reducing the stress acting on the active layer 103 and other metal film layers when the array substrate 100 is bent, improving the bending resistance of the array substrate 100, and further improving the product yield of the display panel.

[0056] Embodiment 2

[0057] like Figure 2, which is a schematic diagram of a first cross-sectional structure of an array substrate 100 provided in an embodiment of the present application; wherein the structure of the array substrate 100 in the second embodiment of the present application is the same or similar to the structure of the array substrate 100 in the first embodiment of the present application, and the only difference is that the array substrate 100 includes a first thin film transistor T1 and a second thin film transistor T2 arranged adjacent to each other. The active layer 103 also includes a plurality of patterned active portions 1031, and the first interlayer insulating layer 106 includes a plurality of patterned covering portions, one of the covering portions corresponds to two adjacent active portions 1031, that is, the covering portion extends from the first thin film transistor T1 to the second thin film transistor T2;

[0058] In the top view direction of the array substrate 100 , the orthographic projections of two adjacent active portions 1031 on the substrate 101 are located within the orthographic projections of the corresponding covering portions on the substrate 101 .

[0059] By comparison, it can be seen that the shape of the patterned first interlayer 106 prepared in the second embodiment of the present application is larger than the shape of the patterned first interlayer 106 prepared in the first embodiment of the present application, so that the preparation cost of the array substrate 100 prepared in the second embodiment of the present application is higher than the preparation cost of the array substrate 100 prepared in the first embodiment of the present application. On the other hand, since the first interlayer 106 is an inorganic material, the bending strength of the array substrate 100 prepared in the second embodiment of the present application is lower than the bending strength of the array substrate 100 prepared in the first embodiment of the present application.

[0060] In view of the technical problem that during the bending process of the current display panel, the functional film layer in the thin film transistor is easily broken under the action of bending stress, which causes the metal wire in the source and drain pattern to be disconnected, an array substrate 100 provided in an embodiment of the present application includes: a substrate 101, an active layer 103 arranged on the substrate 101, and a first interlayer insulating layer 106 arranged on the active layer 103, the active layer 103 also includes a plurality of patterned active parts 1031, the first interlayer insulating layer 106 includes a plurality of patterned covering parts, one of the covering parts corresponds to two adjacent active parts 1031, wherein, in the top view direction of the array substrate 100, the orthographic projections of the two adjacent active parts 1031 on the substrate 101 are located within the orthographic projections of the corresponding covering parts on the substrate 101; the array substrate 10 A plurality of patterned covering portions are formed by patterning the first interlayer insulating layer 106 corresponding to the active layer 103 in the array substrate 100, and in the top view direction of the array substrate 100, the orthographic projections of two adjacent active portions 1031 on the substrate 101 are located within the orthographic projections of the corresponding covering portions on the substrate 101, so that the first interlayer insulating layer 106 forms a separated island structure on the substrate 101 while covering the region of the active layer 103, thereby avoiding the design of an insulating layer with a continuous structure in the region covering the active layer 103, thereby reducing the stress acting on the active layer 103 and other metal film layers when the array substrate 100 is bent, improving the bending resistance of the array substrate 100, and further improving the product yield of the display panel.

[0061] Accordingly, see Figure 3 , Figure 3 FIG. 1 is a flow chart of a method for manufacturing the array substrate 100 provided in the present application. Figure 3 As shown, the manufacturing method of the array substrate 100 includes the following steps (taking the first embodiment of the present application as an example):

[0062] S10, forming a buffer layer 102, an active layer 103, a gate insulating layer 104 and a gate 105 in sequence on a substrate 101, wherein the active layer 103 further includes a plurality of patterned active portions 1031;

[0063] S20, forming a patterned first inter-insulating layer 106 on the gate insulating layer 104, wherein the first inter-insulating layer 106 includes a plurality of patterned covering portions, wherein one of the covering portions corresponds to one of the active portions 1031;

[0064] S30, forming a second inter-insulating layer 107 on the gate insulating layer 104, and performing a hole-opening process on the second inter-insulating layer 107 to form a first sub-via hole 1071 and a second sub-via hole 1072, wherein the first sub-via hole 1071 and the second sub-via hole 1072 both penetrate the second inter-insulating layer 107 and expose the first inter-insulating layer 106;

[0065] S40, depositing a conductive layer 20 on the second inter-insulating layer 107, wherein the conductive layer 20 completely covers the second inter-insulating layer 107 and the first inter-insulating layer 106;

[0066] S50, performing a hole-opening process on a portion of the first interlayer insulating layer 106 and a portion of the conductive layer 20 to form a first via hole 1081 and a second via hole 1082, wherein the first via hole 1081 and the second via hole 1082 completely penetrate the conductive layer 20, the first interlayer insulating layer 106 and a portion of the gate insulating layer 104 and expose the active portion 1031;

[0067] S60 , depositing a metal layer on the second inter-insulating layer 107 , wherein the metal layer completely covers the first via hole 1081 and the second via hole 1082 , and defining the first electrode layer 108 and the source and drain patterns by using a photomask.

[0068] The present application embodiment provides a method for manufacturing an array substrate 100, so as to manufacture the array substrate 100 described in the above embodiments. The manufacturing method sequentially forms the buffer layer 102, the patterned active layer 103, the gate insulating layer 104, the gate 105, the first inter-insulating layer 106, the first electrode layer 108, the second inter-insulating layer 107 and the source-drain pattern on the substrate 101; wherein the array substrate 100 is formed by patterning the first inter-insulating layer 106 corresponding to the active layer 103 in the array substrate 100 to form a plurality of patterned covering portions, and in the top view direction of the array substrate 100, two adjacent active layers 103 are formed. The orthographic projection of the portion 1031 on the substrate 101 is located within the orthographic projection of the corresponding covering portion on the substrate 101, so that the first interlayer insulating layer 106 forms a separated island structure on the substrate 101 while covering the area of ​​the active layer 103, thereby avoiding the insulating layer design of forming a continuous structure in the area covering the active layer 103, thereby reducing the stress acting on the active layer 103 and other metal film layers when the array substrate 100 is bent, improving the bending resistance of the array substrate 100, and further improving the product yield of the display panel.

[0069] The manufacturing method of the present application is now described in conjunction with specific embodiments.

[0070] For details, please refer to Figure 3 and Figure 4A-4F The manufacturing method of the array substrate 100 provided in this embodiment includes:

[0071] S10 , forming a buffer layer 102 , an active layer 103 , a gate insulating layer 104 and a gate 105 in sequence on a substrate 101 , wherein the active layer 103 further includes a plurality of patterned active portions 1031 .

[0072] Specifically, the S10 further includes:

[0073] First, a substrate 101 is provided, and the substrate 101 is composed of a flexible substrate of one or more layers of polyimide material; then, a buffer layer 102 is formed on the substrate 101 by chemical vapor deposition (CVD), and the buffer layer 102 can reduce the influence of the substrate 101 on the thin film transistor. The material of the buffer layer 102 can be one or more inorganic materials such as silicon nitride, silicon oxide, silicon oxynitride and silicon dioxide; then, a metal oxide semiconductor layer is deposited on the buffer layer 102 by physical vapor deposition (PVD); and the metal oxide semiconductor layer is patterned to form an active layer 103. Finally, the active layer 103 is annealed at a high temperature of 350°C. The metal oxide semiconductor can be indium gallium zinc oxide or indium zinc oxide, and the active layer 103 also includes a plurality of patterned active parts 1031.

[0074] Then, a gate insulating layer 104 is deposited on the active layer 103 and the buffer layer 102 by chemical vapor deposition, and a gate 105 metal layer is deposited on the gate insulating layer 104 by physical vapor deposition. The gate 105 metal layer is processed by yellow light photolithography and wet etching process to form the gate 105.

[0075] Finally, the two ends of the active layer 103 are subjected to helium conductive treatment by using an alignment process. The gate 105 may be made of molybdenum, copper, aluminum, etc., and the gate insulating layer 104 may be made of one or more inorganic materials such as silicon nitride, silicon oxide, and silicon oxynitride. Figure 4A shown.

[0076] S20 , forming a patterned first inter-insulating layer 106 on the gate insulating layer 104 , wherein the first inter-insulating layer 106 includes a plurality of patterned covering portions, and one of the covering portions corresponds to one of the active portions 1031 .

[0077] Specifically, the S20 further includes:

[0078] First, a first interlayer insulating layer 106 is deposited on the gate insulating layer 104 and the gate 105 by chemical vapor deposition, and the first interlayer insulating layer 106 is etched after yellow light exposure to form the first interlayer insulating layer 106 in the shape of a separated island; wherein the first interlayer insulating layer 106 includes a plurality of patterned covering portions, and one of the covering portions corresponds to one of the active portions 1031. At this time, the first interlayer insulating layer 106 completely covers the surfaces of the active portion 1031 and the gate 105, and can prevent water vapor in the air or in the organic film layer from affecting the active layer 103.

[0079] The material of the first insulating layer 106 can be one or more inorganic materials such as silicon nitride, silicon oxide, and silicon oxynitride, which are used to isolate water and oxygen, and play the role of insulation and protection of other functional film layers, such as Figure 4B shown.

[0080] S30, forming a second inter-insulating layer 107 on the gate insulating layer 104, and performing a hole opening process on the second inter-insulating layer 107 to form a first sub-via 1071 and a second sub-via 1072, wherein the first sub-via 1071 and the second sub-via 1072 both penetrate the second inter-insulating layer 107 and expose the first inter-insulating layer 106.

[0081] Specifically, the S30 further includes:

[0082] In this embodiment, an organic insulating material solution is coated on the gate insulating layer 104 and the first inter-insulating layer 106, and a solid second inter-insulating layer 107 is obtained by baking. Then, the second inter-insulating layer 107 is subjected to a patterning process and a photomask is used to perform a hole opening process, and a large hole of the second inter-insulating layer 107 is first opened at a position where a source and drain via hole is required to form a first sub-via hole 1071 and a second sub-via hole 1072, wherein the first sub-via hole 1071 and the second sub-via hole 1072 both penetrate the second inter-insulating layer 107 and expose the first inter-insulating layer 106.

[0083] The material of the second insulating layer 107 can be one or more organic materials such as acrylic resin, polycarbonate and polystyrene, which can be used to relieve the stress generated by the first insulating layer 106, thereby enhancing the flexibility of the array substrate 100 and avoiding cracks. In addition, the thickness of the first insulating layer 106 is 100 nanometers to 500 nanometers. The thickness of the second insulating layer 107 is greater than the thickness of the first insulating layer 106, and can be set according to actual needs.

[0084] S40 , depositing a conductive layer 20 on the second inter-insulating layer 107 , wherein the conductive layer 20 completely covers the second inter-insulating layer 107 and the first inter-insulating layer 106 .

[0085] Specifically, the S40 further includes:

[0086] A conductive layer 20 is deposited on the second inter-insulating layer 107, and the conductive layer 20 completely covers the second inter-insulating layer 107 and the first inter-insulating layer 106. The conductive layer 20 completely covers the first sub-via hole 1071 and the second sub-via hole 1072, and the material of the conductive layer 20 is at least one of indium tin oxide and indium gallium tin oxide, such as Figure 4D shown.

[0087] S50, performing hole opening processing on a portion of the first inter-insulating layer 106 and a portion of the conductive layer 20 to form a first via hole 1081 and a second via hole 1082, wherein the first via hole 1081 and the second via hole 1082 completely penetrate the conductive layer 20, the first inter-insulating layer 106 and a portion of the gate insulating layer 104 and expose the active portion 1031.

[0088] Specifically, the S50 further includes:

[0089] Using the same mask as in S30, a portion of the first inter-insulating layer 106 and a portion of the conductive layer 20 are further subjected to a hole opening process (corresponding to the positions of the first sub-via hole 1071 and the second sub-via hole 1072, respectively), to form a first via hole 1081 and a second via hole 1082, wherein the first via hole 1081 and the second via hole 1082 completely penetrate the conductive layer 20, the first inter-insulating layer 106 and a portion of the gate insulating layer 104 and expose the active portion 1031; wherein the first via hole 1081 and the second via hole 1082 are source-drain via holes of the array substrate 100, as shown in FIG. Figure 4E shown.

[0090] S60 , depositing a metal layer on the second inter-insulating layer 107 , wherein the metal layer completely covers the first via hole 1081 and the second via hole 1082 , and defining the first electrode layer 108 and the source and drain patterns by using a photomask.

[0091] Specifically, the S60 further includes:

[0092] A metal layer is deposited on the second inter-insulating layer 107 by physical vapor deposition, and the metal layer completely covers the first via hole 1081 and the second via hole 1082. Then, the conductive layer 20 and the metal layer are patterned by yellow light photolithography and wet etching process to define the first electrode layer 108 and the source-drain pattern, and ensure that the surface of the second inter-insulating layer 107 outside the source-drain pattern has no conductive layer 20 residue. The source-drain pattern includes a source electrode 109 and a drain electrode 110. The source electrode 109 is connected to the active layer 103 through the first via hole 1081, and the drain electrode 110 is connected to the active layer 103 through the second via hole 1082. Figure 4F shown.

[0093] The array substrate 100 provided in the embodiment of the present application includes a substrate 101, an active layer 103 having a plurality of patterned active portions 1031, and a first interlayer insulating layer 106 having a plurality of patterned covering portions, wherein a covering portion corresponds to at least one active portion 1031, and in the top view direction of the array substrate 100, an orthographic projection of the active portion 1031 on the substrate 101 is located within an orthographic projection of the corresponding covering portion on the substrate 101;

[0094] Among them, the first insulating layer 106 composed of inorganic materials is a patterned film layer with a separated island shape, and the second insulating layer 107 composed of organic materials completely covers the first insulating layer 106 outside the area where the source and drain electrodes are located, and the second insulating layer 107 is a continuous film layer structure; the discrete island-shaped first insulating layer 106 not only ensures the protection of the area where the active layer 103 is located, reduces the influence of external factors on the performance of the thin film transistor, but also prevents the accumulation of stress on a continuous scale when bending. The second insulating layer 107 prepared using organic insulating materials can achieve film flattening, and compared with inorganic materials, organic materials have less stress when bending. On the other hand, the use of the first electrode layer 108 can avoid corrosion caused by direct contact of organic materials with metal electrodes.

[0095] In the embodiment of the present application, for the flexible display backplane, the thicker inter-insulating layer between the source, drain and gate 105 in the thin-film transistor with a top gate 105 structure will generate greater stress when bent. Excessive stress will cause the inter-insulating layer to break, resulting in broken metal wires in the source and drain patterns, affecting the yield of the product.

[0096] In response to the above problems, the embodiment of the present application proposes a design of separating the first insulating layer 106 with island patterning and the second continuous insulating layer 107, and uses the first electrode layer 108 to prevent electrode corrosion, thereby improving the product yield problem caused by the large bending stress of the flexible display backplane.

[0097] The present application provides an array substrate 100, which includes: a substrate 101, an active layer 103 disposed on the substrate 101, and a first interlayer insulating layer 106 disposed on the active layer 103, wherein the active layer 103 further includes a plurality of patterned active portions 1031, and the first interlayer insulating layer 106 includes a plurality of patterned covering portions, one of the covering portions corresponds to at least one of the active portions 1031, wherein in the top view direction of the array substrate 100, the orthographic projection of the active portion 1031 on the substrate 101 is located within the orthographic projection of the corresponding covering portion on the substrate 101; the array substrate 100 is obtained by: After patterning, an insulating layer 106 forms a plurality of patterned covering portions, and in the top view direction of the array substrate 100, the orthographic projection of the active portion 1031 on the substrate 101 is located within the orthographic projection of the corresponding covering portion on the substrate 101, so that the first insulating layer 106 forms a separated island structure on the substrate 101 while covering the area of ​​the active layer 103, thereby avoiding the insulating layer design of forming a continuous structure in the area covering the active layer 103, thereby reducing the stress acting on the active layer 103 and other metal film layers when the array substrate 100 is bent, improving the bending resistance of the array substrate 100, and further improving the product yield of the display panel.

[0098] Correspondingly, the embodiment of the present application further provides a display panel, comprising an array substrate 100 and a plurality of light-emitting devices disposed on the array substrate 100, wherein the array substrate 100 comprises a substrate 101, an active layer 103 disposed on the substrate 101, and a first interlayer insulating layer 106 disposed on the active layer 103, wherein the active layer 103 further comprises a plurality of patterned active portions 1031, and the first interlayer insulating layer 106 comprises a plurality of patterned covering portions, wherein one of the covering portions corresponds to at least one of the active portions 1031;

[0099] In the top view direction of the array substrate 100 , the orthographic projection of the active portion 1031 on the substrate 101 is located within the orthographic projection of the corresponding covering portion on the substrate 101 .

[0100] Specifically, the display panel is used in flexible displays, mobile terminals and outdoor large-screen displays.

[0101] The above is a detailed introduction to an array substrate 100 and a display panel provided in an embodiment of the present application. Specific examples are used herein to illustrate the principles and implementation methods of the present application. The description of the above embodiments is only used to help understand the method of the present application and its core idea. At the same time, for technical personnel in this field, according to the idea of ​​the present application, there will be changes in the specific implementation method and application scope. In summary, the content of this specification should not be understood as a limitation on the present application.

Claims

1. An array substrate, characterized in that: include: substrate; An active layer, disposed on the substrate, comprising a plurality of patterned active portions; as well as A first insulating layer, disposed on the active layer, comprising a plurality of patterned covering portions, wherein one of the covering portions corresponds to at least one of the active portions; A second insulating layer is disposed on the substrate and partially covers each of the covering portions; In which, the array substrate also includes a first electrode layer arranged on the second insulating layer and in contact with part of the covering part, and a source-drain pattern arranged on the first electrode layer. In the top view direction of the array substrate, the orthographic projection of the active part on the substrate is located within the orthographic projection of the corresponding covering part on the substrate. The material of the second insulating layer is an organic material, and the material of the first electrode layer is at least one of indium tin oxide and indium gallium tin oxide. The first electrode layer separates the source-drain pattern from the second insulating layer.

2. The array substrate according to claim 1, characterized in that: The bending strength of the material of the second insulating layer is greater than the bending strength of the first insulating layer.

3. The array substrate according to claim 2, characterized in that: The material of the first insulating layer is at least one of silicon nitride, silicon oxide and silicon oxynitride, and the material of the second insulating layer is at least one of acrylic resin, polycarbonate and polystyrene.

4. The array substrate according to claim 2, characterized in that: The source-drain pattern includes a source and a drain; wherein a first via and a second via are provided on the array substrate, and both the first via and the second via pass through the covering part and the first electrode layer; the source is connected to the active part through the first via, and the drain is connected to the active part through the second via.

5. The array substrate according to claim 4, characterized in that: In the top view direction of the array substrate, the orthographic projection of the source-drain pattern on the substrate is located within the orthographic projection of the corresponding covering portion on the substrate.

6. The array substrate according to claim 4, characterized in that: In the top view direction of the array substrate, the orthographic projection of the first electrode layer on the substrate is located within the orthographic projection of the source-drain pattern on the substrate.

7. The array substrate according to claim 4, characterized in that: The array substrate further comprises a gate insulating layer and a gate, wherein the gate insulating layer is arranged on the substrate and completely covers the active layer, and the gate is arranged on the gate insulating layer and corresponds to the active layer; The covering portion is disposed on the gate insulating layer and covers the gate, and the second interlayer insulating layer is disposed on the gate insulating layer and covers a portion of the first interlayer insulating layer.

8. The array substrate according to claim 2, characterized in that: In the top view direction of the array substrate, the orthographic projection of the covering portion on the substrate is located within the orthographic projection of the corresponding second inter-insulating layer on the substrate; Wherein, the thickness of the first insulating layer is smaller than the thickness of the second insulating layer.

9. The array substrate according to claim 7, characterized in that: The array substrate further comprises a buffer layer, wherein the buffer layer is disposed between the substrate and the gate insulating layer, and the active portion is disposed on the buffer layer; Wherein, the material of the buffer layer is the same as that of the first insulating layer.

10. A display panel, characterized in that: The invention comprises an array substrate as claimed in any one of claims 1 to 9 and a plurality of light emitting devices arranged on the array substrate, wherein the array substrate comprises: substrate; an active layer, disposed on the substrate, comprising a plurality of patterned active portions; and A first insulating layer, disposed on the active layer, comprising a plurality of patterned covering portions, wherein one of the covering portions corresponds to at least one of the active portions; Wherein, in the top view direction of the array substrate, the orthographic projection of the active portion on the substrate is located within the orthographic projection of the corresponding covering portion on the substrate.

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