Silicon carbide semiconductor device and semiconductor field effect transistor

Abstract

The present invention relates to a silicon carbide semiconductor device and a semiconductor field effect transistor. The semiconductor field effect transistor includes a silicon carbide semiconductor substrate and a trench metal oxide semiconductor field effect transistor. The field effect transistor includes a trench vertically disposed and extending through in a first horizontal direction, a gate insulating layer formed on an inner wall surface of the trench, a first polycrystalline gate formed on the gate insulating layer, a shielding region formed outside the trench and below the trench, and a field plate disposed between a bottom wall of the trench and the shielding region. The field plate has a semiconductor doping and laterally contacts a current diffusion layer to deplete electrons of the current diffusion layer via the field plate when a reverse bias voltage is applied.

Description

Technical Field

[0001] The present invention relates to a semiconductor device, and more particularly to a silicon carbide semiconductor device. Background Art

[0002] Semiconductor power devices generally require a high breakdown voltage in terms of characteristics, and have a minimum on-resistance, low reverse leakage current, and fast switching speed as much as possible to reduce the conduction loss and switching loss during operation. Since silicon carbide (SiC) has characteristics such as a wide bandgap (Bandgap Eg = 3.26 eV), a high critical breakdown electric field strength (2.2 MV / cm), and a high thermal conductivity (4.9 W / cm-K), it is considered an excellent material for power switching devices. Under the same breakdown voltage condition, the thickness of the voltage withstand layer (lightly doped drift layer) of a power device made of silicon carbide is only one-tenth of that of a silicon (Si) power device, and the theoretical on-resistance can reach one-hundredth of that of silicon. Therefore, it plays an important role in certain applications, and there are also areas that need to be improved according to different application requirements. Summary of the Invention

[0003] The present invention relates to a semiconductor device, and more particularly to a silicon carbide semiconductor device.

[0004] The present invention provides a silicon carbide semiconductor device, comprising: a first silicon carbide semiconductor layer having a first conductivity type; a second silicon carbide semiconductor layer having the first conductivity type, the second silicon carbide semiconductor layer including a drift layer disposed on the first silicon carbide semiconductor layer and a current diffusion layer disposed on the drift layer; a third silicon carbide semiconductor layer having a second conductivity type, disposed on an upper surface of the second silicon carbide semiconductor layer; a first semiconductor region having the first conductivity type, disposed in the third silicon carbide semiconductor layer; a trench vertically penetrating the first semiconductor region and the third silicon carbide semiconductor layer to reach the second silicon carbide semiconductor layer, and extending along a first horizontal direction; a second semiconductor region having the second conductivity type, the second semiconductor region including a plurality of portions extending along a second horizontal direction and formed in a first portion of the third silicon carbide semiconductor layer and at least one second portion disposed in the second silicon carbide semiconductor layer below the trench, the first portion and the second portion being adjacent to each other; a gate portion embedded in the trench, including a gate insulating layer formed on a wall surface of the trench and a polycrystalline gate formed on the gate insulating layer; a third semiconductor region disposed outside the trench and having the second conductivity type, including a field plate at least partially formed in the second silicon carbide semiconductor layer and located between the trench and the second portion of the second semiconductor region, the field plate laterally contacting the current diffusion layer; a shielding region having the second conductivity type, the shielding region being located in the second silicon carbide semiconductor layer below the trench and under the field plate; and a metal electrode contacting the first semiconductor region and the gate portion.

[0005] In one embodiment, the gate portion has a first maximum width, the field plate has a second maximum width, the shielding region has a third maximum width, the second maximum width is less than the first maximum width, and the second maximum width is less than the third maximum width.

[0006] In one embodiment, the gate portion has a first maximum width, the field plate has a second maximum width, the shielding region has a third maximum width, the second maximum width is greater than the first maximum width, and the second maximum width is less than the third maximum width.

[0007] In one embodiment, a thickness of the field plate corresponds to a thickness of the current diffusion layer.

[0008] In one embodiment, the trench vertically penetrates the first semiconductor region and the third silicon carbide semiconductor layer such that a bottom wall of the trench approaches a bottom of the third silicon carbide semiconductor layer.

[0009] In one embodiment, the trench vertically penetrates the first semiconductor region and the third silicon carbide semiconductor layer such that a bottom wall of the trench is close to a bottom of the current diffusion layer.

[0010] In one embodiment, the shielding region extends below the trench along the first horizontal direction to form a shielding segment of a continuous structure.

[0011] In one embodiment, the shielding region includes a plurality of shielding blocks that are intermittently arranged below the trench along the first horizontal direction.

[0012] In one embodiment, the shielding blocks have a spacing between 0.5 μm and 3.0 μm in the first horizontal direction.

[0013] In one embodiment, a lateral junction is formed between the field plate and the current diffusion layer, and the lateral junction has a height between 0.5 μm and 1.5 μm.

[0014] In one embodiment, the gate portion and the field plate are separated from each other, and the field plate contacts the shielding region.

[0015] The present invention also provides a trench-type silicon carbide metal oxide semiconductor field effect transistor, including: a silicon carbide semiconductor substrate; and a trench-type metal oxide semiconductor field effect transistor formed on the silicon carbide semiconductor substrate, including a trench vertically disposed and passing through along a first horizontal direction, a gate insulating layer formed on an inner wall surface of the trench, a first polycrystalline gate formed on the gate insulating layer, a shielding region formed outside the trench and below the trench, and a field plate disposed between a bottom wall of the trench and the shielding region, the field plate having a semiconductor doping and laterally contacting a current diffusion layer to deplete electrons of the current diffusion layer via the field plate when a reverse bias is applied.

[0016] In one embodiment, the field plate is located outside the trench.

[0017] In one embodiment, the shielding region extends below the trench along the first horizontal direction to form a continuous structure.

[0018] In one embodiment, the shielding region includes a plurality of shielding blocks that are intermittently arranged below the trench along the first horizontal direction.

[0019] In one embodiment, the shielding blocks have a spacing between 0.5 μm and 3.0 μm in the first horizontal direction.

[0020] In one embodiment, a lateral junction is formed between the second polycrystalline gate and a current diffusion layer, and the lateral junction has a height between 0.5 μm and 1.5 μm. Description of the Drawings

[0021] Figure 1 It is a schematic three-dimensional structure diagram according to an embodiment of the present invention.

[0022] Figure 2 It is Figure 1 the front view schematic diagram of

[0023] Figure 3 It is Figure 1 the three-dimensional sectional view along A-A.

[0024] Figure 4 It is Figure 1 the three-dimensional sectional view along B-B.

[0025] Figure 5 It is a schematic three-dimensional structure diagram according to another embodiment of the present invention.

[0026] Figure 6 It is Figure 5 the front view schematic diagram of

[0027] Figure 7 It is Figure 5 the three-dimensional sectional view along A-A.

[0028] Figure 8 It is Figure 5 the three-dimensional sectional view along B-B.

[0029] Figure 9 The three-dimensional sectional view according to yet another embodiment of the present invention.

[0030] Figure 10 It is the three-dimensional sectional view according to still another embodiment of the present invention. Detailed implementation manners

[0031] In this article, the terms used in the descriptions of various embodiments are only for the purpose of describing specific examples and are not intended to be limiting.

[0032] Unless the context clearly indicates otherwise, or unless the number of elements is not deliberately limited, the singular forms "a", "an", and "the" as used herein also include the plural forms. On the other hand, the terms "comprising" and "including" are intended to be inclusive, meaning that additional elements may exist in addition to the listed elements; when an element is described as "connected" or "coupled" to another element, the element may be directly connected or coupled to the other element or through an intermediate element; when an element of a layer, region, or substrate is referred to as being "on" another element, it means that it may be directly on the other element or there may be an intermediate element therebetween, relatively speaking, when an element is referred to as being "directly on" another element, there is no such intermediate element therebetween; in addition, the order of description of the embodiments should not be construed as implying that operations or steps must depend on the literal order, and alternative embodiments may perform steps, operations, methods, etc. in an order different from that described herein.

[0033] In this document, each layer and / or region is characterized as having a conductivity type such as n-type or p-type, which refers to the types of multiple carriers in the layer and / or region. The n-type material includes a balanced excess of electrons, and the p-type material includes a balanced excess of holes. Some materials can be labeled with "+" or "-" (such as n+, n-, p+, p-) to indicate a relatively larger (+) or smaller (-) carrier concentration compared to another layer or region. This notation does not represent the specific concentration of carriers. In the drawings, the thickness of each layer and / or region is magnified to make the drawings clearer.

[0034] The present invention provides a silicon carbide semiconductor device, specifically a trench-type silicon carbide metal oxide semiconductor field effect transistor. In some embodiments, the silicon carbide semiconductor device may also be a trench-type metal oxide semiconductor field effect transistor integrating other elements, such as a structure of a trench-type metal oxide semiconductor field effect transistor integrating a Schottky diode.

[0035] Refer to Figure 1 and Figure 2 , which are a three-dimensional structural schematic diagram of an embodiment of the present invention and Figure 1 a front view schematic diagram of Figure 3 . For the convenience of description, some elements are presented in dashed lines. The silicon carbide semiconductor device includes a first silicon carbide semiconductor layer 10, a second silicon carbide semiconductor layer 20, a third silicon carbide semiconductor layer 30, a first semiconductor region 40, a second semiconductor region 50, a gate portion 60, a third semiconductor region, a shielding region 80 (shown in

[0036] The first silicon carbide semiconductor layer 10 has a first conduction type. In this embodiment, the first conduction type is n-type, and the first silicon carbide semiconductor layer 10 is an n+-type silicon carbide substrate. A buffer layer 11 is provided above the first silicon carbide semiconductor layer 10, and a metal drain layer 12 is provided below the first silicon carbide semiconductor layer 10. The second silicon carbide semiconductor layer 20 is provided on the buffer layer 11. The second silicon carbide semiconductor layer 20 includes an n-drift layer 20a and an n-type current diffusion layer 20b. The third silicon carbide semiconductor layer 30 is provided on the n-type current diffusion layer 20b. The third silicon carbide semiconductor layer 30 is a p-type base region and is disposed on an upper surface 21 of the second silicon carbide semiconductor layer 20. The first semiconductor region 40 is formed in an upper surface of the third silicon carbide semiconductor layer 30 by ion implantation. The first semiconductor region 40 is an n+-type source region.

[0037] In this embodiment, the thickness of the n-type current diffusion layer 20b is between 0.5 μm and 1.5 μm, the thickness of the third silicon carbide semiconductor layer 30 is between 1.0 μm and 2.0 μm, and the thickness of the first semiconductor region 40 is about 0.5 μm. The n-drift layer 20a has a doping concentration between 5E14 and 5E16; the n-type current diffusion layer 20b has a doping concentration between 1E16 and 5E18, such as 5E17; the p-type base region has a doping concentration between 1E17 and 5E19, such as 1E18; the n+-type source region has a doping concentration between 1E18 and 5E20, such as 1E20. In one embodiment, the buffer layer 11, the second silicon carbide semiconductor layer 20, and the third silicon carbide semiconductor layer 30 are formed by epitaxial growth to form an epitaxial layer.

[0038] The silicon carbide semiconductor device includes a plurality of trenches T. The trenches T are formed by an etching process. The trenches T are spaced apart and extend through along a first horizontal direction. In this embodiment, the first horizontal direction is the Y-axis in the figure. In this embodiment, the trenches T vertically penetrate the first semiconductor region 40 and the third silicon carbide semiconductor layer 30 and reach near a junction between the n-type current diffusion layer 20b and the third silicon carbide semiconductor layer 30, that is, the upper surface 21 of the second silicon carbide semiconductor layer 20. The trenches T have a depth between 1.0 μm and 2.0 μm and a width between 0.5 μm and 2.0 μm.

[0039] Refer to Figure 3 For Figure 1Schematic perspective cross-sectional view along A-A. The second semiconductor region 50 (p+-type implant) has the second conductivity type. The second semiconductor region 50 includes a plurality of first portions 51 and a plurality of second portions 52. The second semiconductor region 50 is a segmented implant region that is spaced apart and extends along a second horizontal direction. It is implanted segmentally and formed in the third silicon carbide semiconductor layer 30 and the second silicon carbide semiconductor layer 20, and thus surrounds the trench T. The second horizontal direction is the X-axis in the figure. From Figure 3 It can be seen that the first portion 51 vertically forms from a region adjacent to the upper surface of the first semiconductor region 40 to a region adjacent to the inside of the n-type current diffusion layer 20b. The second portion 52 is formed in the second silicon carbide semiconductor layer 20 below the trench T. In one embodiment, the implantation depth of the second semiconductor region 50 is between 1.0 μm and 2.5 μm, and this depth is sufficient to make the second semiconductor region 50 deeper than the trench T. In one embodiment, the second semiconductor region 50 (i.e., the first portion 51 and the second portion 52) serves as a p+ pickup.

[0040] The gate portion 60 includes a gate insulating layer 61 and a polycrystalline gate 62 (Poly gate). The gate insulating layer 61 is formed on partial surfaces of the first semiconductor region 40 and the first portion 51, and longitudinally extends along the sidewall of the trench T to cover partial surfaces of the third silicon carbide semiconductor layer 30 and the second silicon carbide semiconductor layer 20. The polycrystalline gate 62 is then formed on the gate insulating layer 61.

[0041] The third semiconductor region is disposed outside the trench T and has the second conductivity type. The third semiconductor region includes a field plate 70. The field plate 70 is located below the trench T. The field plate 70 laterally contacts the current diffusion layer 20b to form a lateral junction. In this embodiment, the thickness of the field plate 70 approximately corresponds to the thickness of the current diffusion layer 20b. In other words, the height of the lateral junction is between 0.5 μm and 1.5 μm. The shielding region 80 is formed in the n-drift layer 20a. The second portion 52 of the second semiconductor region 50 is electrically connected to the field plate 70, as Figure 3 shown. Refer to Figure 4 for Figure 1Schematic perspective cross-sectional view along B-B. The shielding region 80 has the second conductivity type, is located in the second silicon carbide semiconductor layer 20 below the trench T, and is located under the field plate 70. In this embodiment, the shielding region 80 includes a plurality of shielding blocks, and the shielding blocks are arranged segmentally below the trench T along the Y-axis. In this embodiment, both the field plate 70 and the shielding region 80 are P-type doped. The doping concentration of the field plate 70 is between 1E18 and 1E20, and the doping concentration of the shielding region 80 is between 1E18 and 1E20.

[0042] A metal silicide layer 91 is formed on the surfaces of the third silicon carbide semiconductor layer 30 and the first part 51 of the second semiconductor region 50, and a metal layer 92 is formed on the metal silicide layer 91. In this embodiment, the metal silicide layer 91 is nickel silicide (NiSi), and the metal layer 92 is an alloy, such as Ti / TiN. The metal electrode 90 covers the upper surfaces of the metal layer 92 and the gate portion 60. In this embodiment, the metal electrode 90 is AuCu.

[0043] The size relationships of some elements / regions of the silicon carbide semiconductor device will be described below. Considering the manufacturing method, the sizes of these elements / regions are not fixed values. For example, when forming the field plate 70, the ion implantation process may make the dopant profile of the field plate 70 uneven. Therefore, the sizes of these elements / regions are defined by the maximum width. Refer to Figure 3 , the gate portion 60 has a first maximum width W1, the field plate 70 has a second maximum width W2, and the shielding region 80 has a third maximum width W3. In one embodiment, the second maximum width W2 is less than the first maximum width W1 and the third maximum width W3, and the third maximum width W3 is greater than the first maximum width W1. On the other hand, refer to Figure 4 , the shielding blocks of the shielding region 80 are arranged segmentally below the trench T along the Y-axis. The shielding blocks have a spacing W4, and the spacing W4 is between 0.5 μm and 2.0 μm. And the shielding blocks have a separated length W5 along the Y-axis, and the length W5 is between 0.5 μm and 3.0 μm. By using the spaced shielding blocks, the corners of the trench T can be appropriately protected, and more regions (i.e., the n-drift layer 20a where the shielding region 80 is not formed) can be reserved for electrons and / or current to pass through, ensuring a low on-resistance (R ON，SP ).

[0044] However, the structure of the shielding region 80 can be adjusted according to different applications or configurations, and the same applies to the dimensional relationships among the gate portion 60, the field plate 70, and the shielding region 80. For example, referring to Figure 5 , Figure 6 , Figure 7 , Figure 8 , which is a schematic diagram according to another embodiment of the present invention. In this embodiment, the shielding region 80 extends along the Y-axis below the trench T to form a shielding segment with a continuous structure. Or, referring to Figure 9 , in another embodiment, the first maximum width W1 is less than the second maximum width W2 and the third maximum width W3, and the third maximum width W3 is greater than the second maximum width W2.

[0045] Referring to Figure 10 , in other embodiments, the field plate 70 can be adjusted according to the depth of the trench T relative to the second silicon carbide semiconductor layer 20. In the embodiment of Figure 10 , a bottom wall of the trench T is closer to the n-drift layer 20a, and the field plate 70 is formed in the n-drift layer 20a and the current diffusion layer 20b below the trench T. Among them, the field plate 70 still laterally contacts the current diffusion layer 20b to form the lateral junction.

[0046] The present invention utilizes the field plate 70 disposed outside the trench T and laterally contacts the current diffusion layer 20b to form the lateral junction. Thereby, when a reverse bias is applied to the silicon carbide semiconductor element, electrons in the current diffusion layer 20b can be quickly depleted via the field plate 70, thereby improving (reducing) the on-resistance (R ON，SP ) and the gate-drain reverse capacitance C rss , enabling the element to operate at a higher speed.

[0047] According to an embodiment of the present invention, a manufacturing method of the silicon carbide semiconductor element includes the following steps:

[0048] Step A1: Provide a silicon carbide semiconductor substrate, and form the n-drift layer 20a on the semiconductor substrate by an epitaxial process.

[0049] Step A2: Taking the embodiment of Figures 1 to 8 as an example, after completing the n-drift layer 20a, first form the shielding region 80 by ion implantation.

[0050] Step A3: Form the n-type current diffusion layer 20b and the third silicon carbide semiconductor layer 30 by using an epitaxial process. Alternatively, in this step, the third silicon carbide semiconductor layer 30 can be formed by ion implantation. The n-type current diffusion layer 20b has a thickness between 0.5 μm and 1.5 μm, and the third silicon carbide semiconductor layer 30 has a thickness between 1.0 μm and 2.0 μm.

[0051] Step A4: Form the second semiconductor region 50 by ion implantation. The second semiconductor region 50 has a thickness between 1.0 μm and 2.5 μm.

[0052] Step A5: Form the first semiconductor region 40 by ion implantation on the third silicon carbide semiconductor layer 30 between the second semiconductor regions 50. The first semiconductor region 40 has a thickness of approximately 0.5 μm.

[0053] Step A6: Form the trench T by etching. The trench T has a depth between 1.0 μm and 2.0 μm. In this embodiment, a bottom wall of the trench T is close to a bottom of the third silicon carbide semiconductor layer 30, that is, the upper surface 21 of the n-type current diffusion layer 20b.

[0054] Step A7: Form the field plate 70 by ion implantation below the trench T. The thickness of the field plate 70 approximately corresponds to the thickness of the current diffusion layer 20b.

[0055] Step A8: Form the gate portion 60 in the trench T, and then form components such as the metal silicide layer 91, the metal layer 92, and the metal electrode 90.

[0056] According to another embodiment of the present invention, a manufacturing method of the silicon carbide semiconductor device includes the following steps:

[0057] Step B1: Provide a silicon carbide semiconductor substrate, and form the n-drift layer 20a and the n-type current diffusion layer 20b on the semiconductor substrate by using an epitaxial process. The n-type current diffusion layer 20b has a thickness between 0.5 μm and 1.5 μm.

[0058] Step B2: Form the third silicon carbide semiconductor layer 30 by using an epitaxial process. Alternatively, in this step, the third silicon carbide semiconductor layer 30 can be formed by ion implantation. The third silicon carbide semiconductor layer 30 has a thickness between 1.0 μm and 2.0 μm.

[0059] Step B3: Form the second semiconductor region 50 by ion implantation. The second semiconductor region 50 has a thickness between 1.0 μm and 2.5 μm.

[0060] Step B4: Form the first semiconductor region 40 on the third silicon carbide semiconductor layer 30 between the second semiconductor regions 50 by ion implantation. The first semiconductor region 40 has a thickness of approximately 0.5 μm.

[0061] Step B5: Form the trench T by etching. The trench T has a depth between 1.0 μm and 2.0 μm. In this embodiment, a bottom wall of the trench T is close to a bottom of the third silicon carbide semiconductor layer 30, i.e., the upper surface 21 of the n-type current diffusion layer 20b.

[0062] Step B6: Form the shielding region 80 below the trench T by ion implantation.

[0063] Step B7: Form the field plate 70 below the trench T by ion implantation. The thickness of the field plate 70 approximately corresponds to the thickness of the current diffusion layer 20b. In other embodiments, the field plate 70 may be formed first, and then the shielding region 80 may be formed.

[0064] Step B8: Form the gate portion 60 in the trench T, and then form components such as the metal silicide layer 91, the metal layer 92, and the metal electrode 90.

[0065] According to this embodiment, in steps B7 and B8, the tilt angle of the ion implantation can be appropriately adjusted to change the width of the shielding region 80 and / or the field plate 70.

[0066] According to another embodiment of the present invention, a manufacturing method of the silicon carbide semiconductor device includes the following steps:

[0067] Step C1: Provide a silicon carbide semiconductor substrate, and form the n-drift layer 20a and the n-type current diffusion layer 20b on the semiconductor substrate by an epitaxial process. The n-type current diffusion layer 20b has a thickness between 0.5 μm and 1.5 μm.

[0068] Step C2: Form the third silicon carbide semiconductor layer 30 by an epitaxial process. Alternatively, in this step, the third silicon carbide semiconductor layer 30 can be formed by ion implantation. The third silicon carbide semiconductor layer 30 has a thickness between 1.0 μm and 2.0 μm.

[0069] Step C3: Form the second semiconductor region 50 by ion implantation. The second semiconductor region 50 has a thickness between 1.0 μm and 2.5 μm.

[0070] Step C4: Form the first semiconductor region 40 on the third silicon carbide semiconductor layer 30 between the second semiconductor regions 50 by ion implantation. The first semiconductor region 40 has a thickness of approximately 0.5 μm.

[0071] Step C5: Form the trench T by etching, and the trench T has a depth between 1.5 μm and 2.0 μm. In this embodiment, a bottom wall of the trench T is close to a lower surface of the n-type current diffusion layer 20 b.

[0072] Step C6: forming the shielding region 80 below the trench T by ion implantation.

[0073] Step C7: Using an epitaxial process to grow the field plate 70 from the bottom wall of the trench T. The thickness of the field plate 70 approximately corresponds to the thickness of the current diffusion layer 20 b.

[0074] Step C8: forming the gate portion 60 in the trench T, and then forming the metal silicide layer 91 , the metal layer 92 , the metal electrode 90 and other components.

[0075] The above manufacturing methods are only examples, and the present invention is not limited thereto. Other manufacturing methods may also be used according to different requirements.

[0076] [Description of the accompanying drawings]

[0077] 10............First silicon carbide semiconductor layer

[0078] 11............buffer layer

[0079] 12............Metal drain layer

[0080] 20.............Second silicon carbide semiconductor layer

[0081] 20a.............Drift layer

[0082] 20b.............n-type current diffusion layer

[0083] 21.............Upper surface

[0084] 30.............Third silicon carbide semiconductor layer

[0085] 40.............First semiconductor region

[0086] 50.............Second semiconductor region

[0087] 51.............Part 1

[0088] 52.............Part 2

[0089] 60............. Gate section

[0090] 61............. Gate insulating layer

[0091] 62............. Polycrystalline gate

[0092] 70............. Field plate

[0093] 80............. Shielding region

[0094] 90............. Metal electrode

[0095] 91............. Metal silicide layer

[0096] 92............. Metal layer

[0097] T............. Trench

[0098] W1............. First maximum width

[0099] W2............. Second maximum width

[0100] W3............. Third maximum width

[0101] W4............. Spacing

[0102] W5............. Length.

Claims

1. A silicon carbide semiconductor device, characterized in that Comprising: A first silicon carbide semiconductor layer having a first conductivity type; A second silicon carbide semiconductor layer having the first conductivity type, the second silicon carbide semiconductor layer including a drift layer disposed on the first silicon carbide semiconductor layer and a current diffusion layer disposed on the drift layer; A third silicon carbide semiconductor layer having a second conductivity type, disposed on an upper surface of the second silicon carbide semiconductor layer; A first semiconductor region having the first conductivity type, disposed within the third silicon carbide semiconductor layer; A trench vertically penetrating the first semiconductor region and the third silicon carbide semiconductor layer to the second silicon carbide semiconductor layer and extending along a first horizontal direction; A second semiconductor region having the second conductivity type, the second semiconductor region including a plurality of portions extending along a second horizontal direction and formed in a first portion of the third silicon carbide semiconductor layer and at least one second portion disposed within the second silicon carbide semiconductor layer below the trench, the first portion and the second portion being adjacent to each other, and the second semiconductor region serving as a pick-up portion; A gate portion buried within the trench, including a gate insulating layer formed on a wall surface of the trench and a polycrystalline gate formed on the gate insulating layer; A third semiconductor region disposed outside the trench and having the second conductivity type, including a field plate at least partially formed within the second silicon carbide semiconductor layer and located between the trench and the second portion of the second semiconductor region, the field plate laterally contacting the current diffusion layer to form a lateral junction, and depleting electrons in the current diffusion layer via the field plate when a reverse bias is applied to the silicon carbide semiconductor device; A shielding region having the second conductivity type, the shielding region being located within the second silicon carbide semiconductor layer below the trench and under the field plate; And a metal electrode in contact with the first semiconductor region and the gate portion.

2. The silicon carbide semiconductor device according to claim 1, characterized in that The gate portion has a first maximum width, the field plate has a second maximum width, the shielding region has a third maximum width, the second maximum width is less than the first maximum width, and the second maximum width is less than the third maximum width.

3. The silicon carbide semiconductor device according to claim 1, characterized in that The gate portion has a first maximum width, the field plate has a second maximum width, the shielding region has a third maximum width, the second maximum width is greater than the first maximum width, and the second maximum width is less than the third maximum width.

4. The silicon carbide semiconductor device according to claim 1, characterized in that A thickness of the field plate corresponds to a thickness of the current diffusion layer.

5. The silicon carbide semiconductor device according to claim 1, characterized in that The trench vertically penetrates the first semiconductor region and the third silicon carbide semiconductor layer such that a bottom wall of the trench approaches a bottom of the third silicon carbide semiconductor layer.

6. The silicon carbide semiconductor device according to claim 1, characterized in that The trench vertically penetrates the first semiconductor region and the third silicon carbide semiconductor layer such that a bottom wall of the trench approaches a bottom of the current diffusion layer.

7. The silicon carbide semiconductor device according to claim 1, characterized in that The shielding region extends below the trench along the first horizontal direction to form a shielding segment of a continuous structure.

8. The silicon carbide semiconductor device according to claim 1, characterized in that The shielding region includes a plurality of shielding blocks intermittently disposed below the trench along the first horizontal direction.

9. The silicon carbide semiconductor device according to claim 8, characterized in that The shielding blocks have a spacing between 0.5 μm and 3.0 μm in the first horizontal direction.

10. The silicon carbide semiconductor device according to claim 1, characterized in that A lateral junction is formed between the field plate and the current diffusion layer, and the lateral junction has a height between 0.5 μm and 1.5 μm.

11. The silicon carbide semiconductor device according to claim 1, characterized in that The gate portion and the field plate are separated from each other, and the field plate contacts the shielding region.

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