Vertical transistor, display pixel, vertical light-emitting transistor, and display panel

Abstract

The embodiment of the present disclosure provides a vertical transistor, a display pixel, a vertical light-emitting transistor and a display panel, the vertical transistor comprising: a source layer, a first active layer, a gate layer, a second active layer and a drain layer which are sequentially stacked in a vertical direction, the gate layer comprising: a first gate structure and a second gate structure, the first active layer and the second active layer both forming a Schottky contact with the first gate structure; the first gate structure is located in a vertical stacking connection area, and there is a first active overlapping area between the first gate structure and the source layer in the vertical direction, and there is a second active overlapping area between the first gate structure and the gate layer in the vertical direction, the first gate structure adopts a sparse gate material or has a sparse hollow structure, the first active overlapping area is a projection overlapping part of two connection surfaces of the first active layer connected with the source layer and the gate layer, and the second active overlapping area is a projection overlapping part of two connection surfaces of the second active layer connected with the drain layer and the gate layer; the second gate structure is located in a non-vertical stacking connection area.

Description

Technical Field

[0001] This disclosure relates to the field of display and control, and particularly to a vertical transistor, display pixel, vertical light-emitting transistor and display panel. Background Technology

[0002] A gate-source-drain vertically distributed organic field-effect transistor (VOFET) structure is proposed. The structure consists of an active layer and a drain electrode stacked on a planar capacitor unit. This reduces the distance between the source and drain electrodes (the active layer deposition thickness is the channel length) and increases the area of ​​the conductive channel between the source and drain electrodes, thus solving the problem of high operating voltage and low operating current caused by the excessive resistance of organic semiconductors in organic field-effect transistors.

[0003] However, the channel depth is controlled by the gate and can usually only stay at a few nanometers. It cannot adjust the operating current more at the same voltage, nor can it further reduce the operating voltage at the same operating current, resulting in lower device performance. Summary of the Invention

[0004] In view of this, the present disclosure provides a vertical transistor, a display pixel, a vertical light-emitting transistor, and a display panel to solve the following problems of the prior art: existing transistors cannot adjust the operating current more significantly under the same voltage, nor can they further reduce the operating voltage under the same operating current, resulting in low device performance.

[0005] On one hand, this disclosure proposes a vertical transistor, comprising at least: a source layer, a gate layer, a drain layer, a first active layer, and a second active layer; the source layer, the first active layer, the gate layer, the second active layer, and the drain layer are stacked sequentially in a vertical direction; the gate layer comprises: a first gate structure and a second gate structure; both the first active layer and the second active layer form Schottky contacts with the first gate structure; the vertical direction is perpendicular to the substrate; the first gate structure is located in a vertical stacking connection region, and has a first active overlap region with the source layer in the vertical direction, and a second active overlap region with the gate layer in the vertical direction; the first gate structure uses a sparse gate material or has a sparse cutout structure; wherein, the first active overlap region is the projected overlap portion of the two connection surfaces connecting the first active layer with the source layer and the gate layer, and the second active overlap region is the projected overlap portion of the two connection surfaces connecting the second active layer with the drain layer and the gate layer; the second gate structure is located in a non-vertical stacking connection region, connected to the first gate structure, and is used to receive voltage signals.

[0006] In some embodiments, the second gate structure is made of a metallized material and is configured using the drain layer as a mask for self-alignment; the second gate structure is also connected to the second active layer.

[0007] In some embodiments, the sparse gate material includes at least one of the following: nanotubes, nanowires, and graphene; the sparse hollow structure has a hollow pattern that includes at least one of the following: polygons, circles, and ellipses.

[0008] On the other hand, this disclosure provides a display pixel comprising at least: a source layer, a gate layer, a drain layer, a first active layer, and a second active layer; the source layer, the first active layer, the gate layer, the second active layer, and the drain layer are stacked sequentially in a vertical direction; the gate layer comprises: a first gate structure and a second gate structure; both the first active layer and the second active layer form Schottky contacts with the first gate structure; the vertical direction is perpendicular to the substrate; the first gate structure is located in a vertically stacked connection region, and has a first active overlap region with the source layer in the vertical direction, and has a first active overlap region with the gate layer in the vertical direction. A second active overlapping region exists. The first gate structure uses a sparse gate material or has a sparse hollow structure. The first active overlapping region is the projected overlap of the two connection surfaces connecting the first active layer to the source layer and the gate layer. The second active overlapping region is the projected overlap of the two connection surfaces connecting the second active layer to the drain layer and the gate layer. The second gate structure is located in the non-vertical stacked connection region and is connected to the first gate structure for receiving voltage signals. A light-emitting layer is disposed on the drain layer. Alternatively, the vertical stacked connection region of the drain layer is connected to the anode layer, and a light-emitting layer is disposed on the anode layer.

[0009] In some embodiments, the second gate structure is made of a metallized material and is configured using the drain layer as a mask for self-alignment; the second gate structure is also connected to the second active layer.

[0010] In some embodiments, the sparse gate material includes at least one of the following: nanotubes, nanowires, and graphene; the sparse hollow structure has a hollow pattern that includes at least one of the following: polygons, circles, and ellipses.

[0011] On the other hand, this disclosure provides a vertical light-emitting transistor, comprising at least: a source layer, a gate layer, a drain layer, a first active layer, and a second active layer; the source layer, the first active layer, the gate layer, the second active layer, and the drain layer are stacked sequentially in a vertical direction; the gate layer includes: a first gate structure and a second gate structure; both the first active layer and the second active layer form Schottky contacts with the first gate structure; the vertical direction is perpendicular to the substrate; the first gate structure is located in a vertical stacking connection region, and has a first active overlap region with the source layer in the vertical direction, and a second active overlap region with the gate layer in the vertical direction. In the source overlap region, the first gate structure uses a sparse gate material or has a sparse cutout structure. The first active overlap region is the projected overlap of the two connection surfaces connecting the first active layer to the source layer and the gate layer. The second active overlap region is the projected overlap of the two connection surfaces connecting the second active layer to the drain layer and the gate layer. The second gate structure is located in the non-vertical stacked connection region and is connected to the first gate structure for receiving voltage signals. The drain layer, the first active layer, and the second active layer are made of organic semiconductor materials, so that the drain layer emits light through current flowing from the source layer to the second active layer.

[0012] In some embodiments, the second gate structure is made of a metallized material and is configured using the drain layer as a mask for self-alignment; the second gate structure is also connected to the second active layer.

[0013] In some embodiments, the sparse gate material includes at least one of the following: nanotubes, nanowires, and graphene; the sparse hollow structure has a hollow pattern that includes at least one of the following: polygons, circles, and ellipses.

[0014] On the other hand, embodiments of this disclosure provide a display panel that includes at least: a plurality of display pixels as described in any one of the embodiments of this disclosure; and / or a plurality of vertical light-emitting transistors as described in the embodiments of this disclosure.

[0015] In this embodiment, both the first and second active layers form Schottky contacts with the first gate structure. Applying a voltage to the first gate structure controls the height of the Schottky barrier, or in other words, the width of the depletion layer within the active layer surrounding the first gate structure. The sparse first gate structure does not, or cannot, completely shield the electric field between the source and drain. When a voltage difference is formed between the source and drain, a current will be generated between them. Since the first gate structure controls the width of the depletion layer between the source and drain, the current between the source and drain can be modulated. In this embodiment, the channel length of the device is determined by the thickness of the active layer deposition, and the overlap area of ​​the source and drain can be adjusted and can be set to a large value. Low-mobility semiconductor materials can generate sufficient current without the need for precision exposure equipment, enabling a larger operating current at the same voltage or a further reduction in the operating voltage at the same operating current, resulting in better device performance. Attached Figure Description

[0016] To more clearly illustrate the technical solutions in the embodiments of this disclosure or the prior art, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are only some embodiments recorded in this disclosure. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0017] Figure 1 A cross-sectional structural diagram of a vertical transistor provided in an embodiment of this disclosure;

[0018] Figure 2 Top view of the gate layer in a vertical TFT provided in the embodiments of this disclosure. Figure 1 ;

[0019] Figure 3 Top view of the gate layer in a vertical TFT provided in the embodiments of this disclosure. Figure 2 ;

[0020] Figure 4 Top view of the gate layer in a vertical TFT provided in the embodiments of this disclosure. Figure 3 ;

[0021] Figure 5 This is a schematic diagram of the structure of a display device provided in an embodiment of this disclosure;

[0022] Figure 6 A circuit diagram of a display pixel unit provided in an embodiment of this disclosure;

[0023] Figure 7 A schematic cross-sectional view of the pixel structure provided in Embodiment 1 of this disclosure;

[0024] Figure 8This is a schematic cross-sectional view of the pixel structure provided in Embodiment 2 of this disclosure;

[0025] Figure 9 A cross-sectional structural schematic diagram of the vertical light-emitting transistor of Embodiment 3 provided in this disclosure;

[0026] Figure 10 A schematic cross-sectional view of the display pixel structure provided in Embodiment 4 of this disclosure;

[0027] Figure 11 This is a schematic cross-sectional view of the display pixel structure provided in Embodiment 5 of the present disclosure;

[0028] Figure 12 This is a cross-sectional structural diagram of a vertical light-emitting transistor according to Embodiment Six of this disclosure.

[0029] Figure label:

[0030] 100 - Substrate and buffer layer, 201 - Source layer, 202 - First insulating layer, 203 - First active layer, 204 - First gate structure, 205 - Second gate structure, 206 - Second active layer, 207 - Second insulating layer, 208 - Drain layer, 209 - Metallized gate structure, 301 - Planarization layer, 302 - Anode layer, 303 - Pixel definition layer and spacer layer, 304 - Light emitting layer. Detailed Implementation

[0031] To make the objectives, technical solutions, and advantages of the embodiments of this disclosure clearer, the technical solutions of the embodiments of this disclosure will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some, not all, of the embodiments of this disclosure. All other embodiments obtained by those skilled in the art based on the described embodiments of this disclosure without creative effort are within the scope of protection of this disclosure.

[0032] Unless otherwise defined, the technical or scientific terms used in this disclosure shall have the ordinary meaning understood by one of ordinary skill in the art to which this disclosure pertains. The terms “first,” “second,” and similar terms used in this disclosure do not indicate any order, quantity, or importance, but are merely used to distinguish different components. Terms such as “comprising” or “including” mean that the element or object preceding the word encompasses the elements or objects listed following the word and their equivalents, without excluding other elements or objects. Terms such as “connected” or “linked” are not limited to physical or mechanical connections, but can include electrical connections, whether direct or indirect. Terms such as “upper,” “lower,” “left,” and “right” are used only to indicate relative positional relationships, and these relative positional relationships may change accordingly when the absolute position of the described objects changes.

[0033] To keep the following description of the embodiments of this disclosure clear and concise, detailed descriptions of known functions and known components are omitted.

[0034] This disclosure provides a vertical transistor, the cross-sectional structure of which is shown in the figure below. Figure 1 As shown, it includes at least:

[0035] The system comprises a source layer 201, a gate layer, a drain layer 208, a first active layer 203, and a second active layer 206. These layers are stacked vertically. The gate layer includes a first gate structure 204 and a second gate structure 205. Both the first and second active layers form Schottky contacts with the first gate structure. The vertical direction is perpendicular to the substrate. The first gate structure is located in the vertical stacking connection region and has a first active overlap region with the source layer and a second active overlap region with the gate layer in the vertical direction. The first gate structure uses a sparse gate material or has a sparse cutout structure. The first active overlap region is the projected overlap of the two connection surfaces connecting the first active layer to the source and gate layers, and the second active overlap region is the projected overlap of the two connection surfaces connecting the second active layer to the drain and gate layers. The second gate structure is located in the non-vertical stacking connection region and is connected to the first gate structure for receiving voltage signals.

[0036] The aforementioned vertical stacked connection region is a vertical region corresponding to each of the vertically stacked layers. This vertical region includes the various connection surfaces that are stacked together, which may include: the connection surface between the source layer and the first active layer, the connection surface between the first active layer and the first gate structure, the connection surface between the first gate structure and the second active layer, and the connection surface between the second active layer and the drain layer.

[0037] In this embodiment, both the first and second active layers form Schottky contacts with the first gate structure. Applying a voltage to the first gate structure controls the height of the Schottky barrier, or in other words, the width of the depletion layer within the active layer surrounding the first gate structure. The sparse first gate structure does not, or cannot, completely shield the electric field between the source and drain. When a voltage difference is formed between the source and drain, a current will be generated between them. Since the first gate structure controls the width of the depletion layer between the source and drain, the current between the source and drain can be modulated. In this embodiment, the channel length of the device is determined by the thickness of the active layer deposition, and the overlap area of ​​the source and drain can be adjusted and can be set to a large value. Low-mobility semiconductor materials can generate sufficient current without the need for precision exposure equipment, enabling a larger operating current at the same voltage or a further reduction in the operating voltage at the same operating current, resulting in better device performance.

[0038] Figure 2 , Figure 3 and Figure 4 The diagrams show top views of the gate layer in a vertical TFT, where the sparse gate material can be one-dimensional nanotubes (such as carbon nanotubes) or nanowires (such as gold nanowires, silver nanowires, etc.). Figure 2 As shown, it can also be a two-dimensional material such as wrinkled graphene; or it can be a patterned ordinary gate to form a hollowed-out first gate structure, such as... Figure 3 and Figure 4 As shown, the hollowed-out pattern of the sparse hollow structure can be polygonal, circular, or elliptical, etc., and the first gate structure and the second gate structure can be made of the same material.

[0039] The aforementioned second gate structure can be made of a metallized material and set up using the drain layer as a mask for self-alignment. In specific settings, the internal layers can be adaptively adjusted according to the application scenario of the vertical transistor. For example, the second gate structure can also be connected to the second active layer. Specific application scenarios will be described in the following embodiments.

[0040] The aforementioned vertical transistors can be applied in various display devices, such as... Figure 5 As shown. The display device consists of a display area DA and a non-display area ND. The display area DA is used to display graphics, and the non-display area ND is used to house control circuits and electronic components. DA is composed of an array of pixel units PX.

[0041] like Figure 6The diagram shows a circuit diagram of a display pixel unit. Each display pixel PX can be composed of a simple 2T1C (i.e., two TFTs and one capacitor) circuit. This embodiment uses an OLED as an example for illustration; however, different designs can be implemented for LCDs, etc. In implementation, the number of TFTs and capacitors can be greater than or equal to two. Each pixel unit circuit consists of a switching TFT (STFT) and a driving TFT (DTFT). Because the overlapping area of ​​the gate and source / drain electrodes in the driving TFT of this embodiment is large, it has a large parasitic capacitance, saving one capacitor. Of course, in some cases (such as low refresh rates), additional capacitors can be added to ensure sufficient capacitance. The following vertical TFT embodiments are only shown using DTFT and OLED structures as examples. The STFT can also be a vertical structure or a planar TFT structure. Since the OLED is driven by the DTFT to emit light, this embodiment will only use the structural diagrams of DTFT and OLED as examples for illustration.

[0042] Example 1

[0043] This disclosure provides a display pixel, the cross-sectional structure of which is shown in the figure below. Figure 7 As shown, it includes at least:

[0044] The system comprises a source layer 201, a gate layer, a drain layer 208, a first active layer 203, and a second active layer 206. These layers are stacked sequentially in the vertical direction. The gate layer includes a first gate structure 204 and a second gate structure 205. Both the first and second active layers form Schottky contacts with the first gate structure. The vertical direction is perpendicular to the substrate. The first gate structure is located in the vertical stacking connection region, and has a first active overlap region with the source layer in the vertical direction, and a second active overlap region with the gate layer in the vertical direction. In the source overlap region, the first gate structure adopts a sparse gate material or has a sparse hollow structure. The first active overlap region is the projected overlap of the two connection surfaces connecting the first active layer with the source layer and the gate layer. The second active overlap region is the projected overlap of the two connection surfaces connecting the second active layer with the drain layer and the gate layer. The second gate structure is located in the non-vertical stacked connection region and is connected to the first gate structure for receiving voltage signals. The vertical stacked connection region of the drain layer is connected to the anode layer 302, and a light-emitting layer 304 is disposed on the second extension region of the anode layer.

[0045] Since the anode layer 302 in the area covered by the pixel definition layer and the spacer layer 303 does not emit light, and the area where the anode layer 302 connects with the light-emitting layer 304 emits light, the anode layer can simply be placed on the anode layer itself, and does not necessarily have to be placed on the second extension area. In specific settings, the second extension area and the vertically stacked connection area may not have any projection overlap, or they may partially overlap; this is not limited here.

[0046] This embodiment Figure 7 The TFT shown is a rarefied gate field-effect vertical transistor. The operating principle of this transistor is similar to that of a Schottky gate field-effect transistor (MESFET). Schottky gate field-effect transistors conduct electricity using majority carriers, and their operating principle is as follows: A MESFET has no insulating dielectric layer; its gate is an electrode that forms a Schottky barrier with the channel. By controlling the barrier height with the gate voltage, the width of the depletion region of the channel is changed, thereby achieving channel turn-on and turn-off. The following uses an N-type channel as an example to illustrate the operation of a MESFET. When a positive gate voltage VSG is applied to the Schottky gate of the MESFET, the electron depletion region on one side of the channel narrows, thus reducing the channel resistance. At this point, applying a voltage VDS between the source and drain of the channel will allow a lateral current to flow through the channel. If the applied Schottky gate voltage is negative, it will expand the electron depletion region of the channel. When the width of the depletion region reaches the bottom of the channel, the channel resistance increases dramatically, and even with an applied source-drain voltage VDS, there will not be a large lateral current flowing through the channel. Therefore, the channel can be turned on and off by applying a gate voltage, and with a fixed source-drain voltage VDS, the source-drain current IDS is a function of VSG and will vary with the applied VSG magnitude.

[0047] In this embodiment, the first gate structure (sparse gate) 204, the first active layer 203, and the second active layer 206 of the light-emitting transistor form a Schottky contact. Applying a voltage to the first gate structure 204 controls the height of the Schottky barrier, or in other words, controls the width of the depletion layer within the active layer surrounding the first gate structure 204. The sparse first gate structure 204 does not, or cannot, completely shield the electric field between the source layer 201 and the drain layer 208. When a voltage difference is formed between the source and drain, a current is generated between them. Since the first gate structure 204 controls the width of the depletion layer between the source and drain, the current between the source and drain can be modulated. For planar TFTs, using low-mobility devices requires reducing the channel length to achieve sufficient current. Due to the limitations of exposure equipment processes, the device has minimum size requirements. The channel length of this device is determined by the thickness of the active layer deposition, and the overlap area of ​​the source and drain can be large. Low-mobility semiconductor materials can generate sufficient current without the use of sophisticated exposure equipment.

[0048] The pixel fabrication process described above is as follows: 100 serves as the substrate and buffer layer. A source layer 201 is deposited and patterned on the 100 substrate. Then, a first active layer 203 and a first insulating layer 202 are fabricated on the source layer to prevent short circuits between the subsequent gate layers (204 and 205) and the drain layer 201. A first gate structure 204 and a second gate structure 205 (i.e., a sparse gate and a normal gate) are fabricated. The sparse gate has many hollow areas in the middle, which does not shield the electric field between the source and drain. At the same time, the gate can form a Schottky contact with the first active layer, while the normal gate ensures normal gate routing. Then, a second active layer 206 is deposited and patterned. A second insulating layer 207 is then fabricated to prevent short circuits between the gate and drain. Finally, a drain layer 208, a planarization layer 301, an anode layer 302, a pixel definition layer, a spacer layer 303, and a light-emitting layer 304 are fabricated sequentially.

[0049] Example 2

[0050] This disclosure also provides a pixel circuit, the cross-sectional structure of which is shown in the figure below. Figure 8 As shown, relative to Figure 7 For the pixel circuit shown, the basic structure of its source layer 201, gate layer, drain layer 208, first active layer 203, and second active layer 206 remains unchanged, that is, it includes at least:

[0051] The system comprises a source layer 201, a gate layer, a drain layer 208, a first active layer 203, and a second active layer 206. These layers are stacked sequentially in the vertical direction. The gate layer includes a first gate structure 204 and a second gate structure 205. Both the first and second active layers form Schottky contacts with the first gate structure. The vertical direction is perpendicular to the substrate. The first gate structure is located in the vertical stacking connection region and has a first active overlap region with the source layer in the vertical direction. A second active overlapping region exists in the vertical direction. The first gate structure adopts a sparse gate material or has a sparse hollow structure. The first active overlapping region is the projected overlapping part of the two connection surfaces connecting the first active layer with the source layer and the gate layer. The second active overlapping region is the projected overlapping part of the two connection surfaces connecting the second active layer with the drain layer and the gate layer. The second gate structure is located in the non-vertical stacked connection region and is connected to the first gate structure for receiving voltage signals. A light-emitting layer 304 is disposed on the first extension region of the drain layer.

[0052] The light-emitting layer 304 can also be directly disposed in the vertical stacked connection region of the drain layer, but the light-emitting effect of the light-emitting layer disposed in the vertical stacked connection region is relatively worse than that disposed in the first extension region of the drain layer. Therefore, it is preferred to dispose of it in the first extension region of the drain layer.

[0053] Compared to Figure 7 In terms of display pixels, Figure 8 A light-emitting layer is disposed on the first extended region outside the vertically stacked connection region of the drain layer of the display pixel. Therefore, it can be seen that... Figure 8 The display pixels in Figure 7 Based on the corresponding embodiment one, the planarization layer 301 and the anode layer 302 are omitted.

[0054] Example 3

[0055] This disclosure also provides a vertical light-emitting transistor, the cross-sectional structure of which is shown in the figure below. Figure 9 (Light is emitted through the drain layer, so in the image it is equivalent to omitting the drain layer) as shown, including at least:

[0056] The system comprises a source layer 201, a gate layer, a drain layer 208, a first active layer 203, and a second active layer 206. These layers are stacked sequentially in the vertical direction. The gate layer includes a first gate structure 204 and a second gate structure 205. Both the first and second active layers form Schottky contacts with the first gate structure. The vertical direction is perpendicular to the substrate. The first gate structure is located in the vertical stacking connection region and has a first active overlap region with the source layer in the vertical direction, and a second active overlap region with the gate layer in the vertical direction. In the first gate structure, a sparse gate material or a sparse hollow structure is used. The first active overlapping region is the projected overlap of the two connection surfaces connecting the first active layer to the source layer and the gate layer. The second active overlapping region is the projected overlap of the two connection surfaces connecting the second active layer to the drain layer and the gate layer. The second gate structure is located in the non-vertical stacked connection region and is connected to the first gate structure to receive voltage signals. The drain layer, the first active layer, and the second active layer are made of organic semiconductor materials so that the drain layer is excited to emit light by the current from the source layer to the second active layer.

[0057] from Figure 9 In this embodiment, the planarization layer 301, anode layer 302, and drain layer 208 are omitted from the first embodiment. However, the drain layer 208 still exists, but it is made of organic semiconductor material and can also emit light. Essentially, the drain layer 208 and the light-emitting layer 304 are combined. Since the first active layer 203 and the second active layer 206 can have multiple options for energy level matching with the OLED (especially when the active layer is made of organic semiconductor material), the current flows through the source layer and the active layer to emit light. Therefore, in Figure 9 It appears that the drain layer 208 has been omitted.

[0058] Example 4

[0059] This disclosure also provides a display pixel, the cross-sectional structure of which is shown in the figure below. Figure 10 As shown, it includes at least:

[0060] The system comprises a source layer 201, a gate layer, a drain layer 208, a first active layer 203, and a second active layer 206. These layers are stacked sequentially in the vertical direction. The gate layer includes a first gate structure 204 and a second gate structure 205. Both the first and second active layers form Schottky contacts with the first gate structure. The vertical direction is perpendicular to the substrate. The first gate structure is located in the vertical stacking connection region and has a first active overlap region with the source layer and a second active overlap region with the gate layer in the vertical direction. The first gate structure uses a sparse gate material or has a sparse open junction. The structure comprises: a first active overlapping region, which is the projected overlap of the two connection surfaces connecting the first active layer to the source layer and the gate layer; a second active overlapping region, which is the projected overlap of the two connection surfaces connecting the second active layer to the drain layer and the gate layer; a second gate structure located in the non-vertical stacked connection region and connected to the first gate structure for receiving voltage signals; wherein the vertical stacked connection region of the drain layer is connected to the anode layer 302, and a light-emitting layer 304 is disposed on the second extension region of the anode layer; the second gate structure is made of a metallized material and is disposed in a self-aligned manner using the drain layer as a mask; the second gate structure is also connected to the second active layer.

[0061] The second extended region and the vertically stacked connection region do not have any overlapping projection. However, in specific implementation, the implementation can be referenced from the embodiment. Whether there is an overlapping part can be set according to actual needs, and it is not limited here.

[0062] In this embodiment, the ordinary gate 205 is replaced by a second active layer 206 through metallization methods such as medium doping (phosphorus, boron, etc.). The doping of the metallized gate structure 209 in the second active layer 206 can be performed in a self-aligned manner using the drain layer 208 as a mask. This avoids short circuits and leakage between the metallized gate structure 209 and the drain layer 208, and also saves the second insulating layer 207. The doping allows the metallized gate structure 209 and the second active layer 206 to form a PN junction, preventing leakage between the metallized gate structure 209 and the second active layer 206.

[0063] Example 5

[0064] This disclosure also provides a display pixel, the cross-sectional structure of which is shown in the figure below. Figure 11 As shown, the basic structure of its source layer 201, gate layer, drain layer 208, first active layer 203, and second active layer 206 remains unchanged, that is, it includes at least:

[0065] The system comprises a source layer 201, a gate layer, a drain layer 208, a first active layer 203, and a second active layer 206. These layers are stacked sequentially in the vertical direction. The gate layer includes a first gate structure 204 and a second gate structure 205. Both the first and second active layers form Schottky contacts with the first gate structure. The vertical direction is perpendicular to the substrate. The first gate structure is located in the vertical stacking connection region, and it has a first active overlap region with the source layer in the vertical direction, and a second active overlap region with the gate layer in the vertical direction. In the overlapping region, the first gate structure adopts a sparse gate material or has a sparse hollow structure. The first active overlapping region is the projected overlap of the two connection surfaces connecting the first active layer with the source layer and the gate layer. The second active overlapping region is the projected overlap of the two connection surfaces connecting the second active layer with the drain layer and the gate layer. The second gate structure is located in the non-vertical stacked connection region and is connected to the first gate structure for receiving voltage signals. A light-emitting layer 304 is disposed on the vertical stacked connection region of the drain layer, and there is a projected overlap between the light-emitting layer and the vertical stacked connection region.

[0066] This embodiment adopts the method of embodiment two based on embodiment four, omitting the planarization layer 301 and the anode layer 302, so that the drain layer 208 can also serve as the anode.

[0067] Example 6

[0068] This disclosure also provides a vertical light-emitting transistor, the cross-sectional structure of which is shown in the figure below. Figure 12 As shown, the basic structure of its source layer 201, gate layer, drain layer 208, first active layer 203, and second active layer 206 remains unchanged, and the basic structure will not be described again here. Among them, the second gate structure uses a metallized material and is set in a self-aligned manner by using the drain layer as a mask. The second gate structure is also connected to the second active layer. The drain layer, the first active layer, and the second active layer are made of organic semiconductor materials so that the drain layer can be excited to emit light by the current from the source layer to the second active layer.

[0069] Based on Example 4, the method of Example 3 can also form a vertical light-emitting transistor, omitting the planarization layer 301, anode layer 302 and drain layer 208.

[0070] In the embodiments of this disclosure, the sparse gate material includes at least one or more sparse gate materials such as nanotubes, nanowires, and graphene, and the hollow pattern of the sparse hollow structure includes at least one or more patterns such as polygons, circles, and ellipses.

[0071] This disclosure also provides a display panel, which includes at least a plurality of display pixels and / or vertical light-emitting transistors as described in the above embodiments of this disclosure. The structures of the display pixels and vertical light-emitting transistors will not be described in detail here, but can be referred to the above embodiments.

[0072] In all the figures above: the substrate material for the base and buffer layer can be, for example, glass, quartz, polymer resin (polyethersulfone (PES), polyacrylate (PA), polyarylate (PAR), polyetherimide (PEI), polyethylene naphthalate (PEN), polyethylene terephthalate (PET), polyphenylene sulfide (PPS), polyallylate, polyimide (PI), polycarbonate (PC), cellulose triacetate (CAT), cellulose acetate propionate (CAP), or combinations thereof) or combinations thereof. The insulating material can be made of metal materials, etc.; Buffer layer: For PI substrates, a barrier layer can also be included. The material can be a single layer or stack of inorganic insulating materials such as silicon oxide, silicon nitride, silicon oxynitride, aluminum oxide, titanium oxide, tantalum oxide, zinc oxide, hafnium oxide, zirconium oxide, etc., and can have a multilayer structure similar to SiNX / SiO2 or SiO2 / SiNX / SiO2; Source layer and drain layer can be made of materials such as molybdenum (Mo), aluminum (Al), copper (Cu), titanium (Ti), etc. and their alloys, and can have a structure similar to Ti / Al / Ti multilayer structure; the insulating layer can be made of materials such as silicon oxide, silicon nitride, silicon oxynitride, aluminum oxide, titanium oxide, tantalum oxide, zinc oxide, hafnium oxide, zirconium oxide, etc., in single or stacked form; the gate layer can be made of materials such as molybdenum (Mo), aluminum (Al), copper (Cu), titanium (Ti), etc., and their alloys; the active layer can be made of materials such as polycrystalline silicon, amorphous silicon, oxide semiconductor ([(In2O3)a(Ga2O3)b(ZnO)c], where a, b, and c are real numbers, satisfying the conditions a≥0, b≥0, c>0 respectively), organic Semiconductors, etc.; rarefied gates can be made of any rarefied and electroosmotic material, any low-density state conductor, nanostructured conductor or semiconductor, nanopatterned conductor or semiconductor, low-density state semiconductor, low-density state half-metal, such as single-layer or multi-layer graphene, low-density metallic single-wall and multi-wall carbon nanotubes, low-density semiconductor carbon nanotubes and most organic semiconductors, as well as one-dimensional materials with high aspect ratios, such as Si nanowires, zinc oxide nanowires, indium phosphide nanowires, gallium nitride nanowires, silver nanowires, gold nanowires and nickel nanowires, etc.High-precision patterned and hollowed-out ordinary gates, etc.; ordinary gates and wirings can be made of materials such as molybdenum (Mo), aluminum (Al), copper (Cu), titanium (Ti), etc., and their alloys, and can have a multilayer structure similar to Ti / Al / Ti; the planarization layer can be made of one or more organic insulating materials selected from polyimide, polyamide, acrylic resin, BCB, and phenolic resin; the anode layer can be made of materials such as silver (Ag), magnesium (Mg), aluminum (Al), platinum (Pt), palladium (Pd), gold (Au), nickel (Ni), neodymium (Nd), iridium (Ir), chromium (Cr), etc., and their mixtures, forming a reflective layer and a transparent or translucent electrode layer formed on the reflective layer, transparent. The semi-transparent electrode layer may include at least one of indium tin oxide (ITO), indium zinc oxide (IZO), zinc oxide (ZnO), indium oxide (In2O3), indium gallium oxide (IGO), and zinc aluminum oxide (AZO), or may have a multilayer structure similar to ITO / Ag / ITO; the pixel definition layer may be made of one or more organic insulating materials selected from polyimide, polyamide, acrylic resin, BCB, and phenolic resin; the spacer layer may be made of one or more organic insulating materials selected from polyimide, polyamide, acrylic resin, BCB, and phenolic resin; in some cases, the pixel definition layer and the spacer layer may be a single layer, i.e., they may be fabricated simultaneously.

[0073] Furthermore, although exemplary embodiments have been described herein, their scope includes any and all embodiments based on this disclosure that have equivalent elements, modifications, omissions, combinations (e.g., schemes involving intersections of various embodiments), adaptations, or alterations. Elements in the claims will be interpreted broadly based on the language used in the claims and are not limited to the examples described in this specification or during the implementation of this application, and such examples will be interpreted as non-exclusive. Therefore, this specification and examples are intended to be considered illustrative only, and the true scope and spirit are indicated by the full scope of the following claims and their equivalents.

[0074] The above description is intended to be illustrative and not restrictive. For example, the above examples (or one or more thereof) can be used in combination with each other. Other embodiments may be used by those skilled in the art upon reading the above description. Furthermore, in the above detailed description, various features may be grouped together to simplify the disclosure. This should not be construed as an intention that a feature of the disclosure that is not claimed is necessary for any claim. Rather, the subject matter of this disclosure may be less than all the features of a particular disclosed embodiment. Thus, the following claims are incorporated herein by reference as examples or embodiments, wherein each claim is an independent, separate embodiment, and these embodiments are contemplated to be combined with each other in various combinations or arrangements. The scope of this disclosure should be determined by reference to the appended claims and the full scope of their equivalents.

[0075] The foregoing has provided a detailed description of several embodiments of this disclosure. However, this disclosure is not limited to these specific embodiments. Those skilled in the art can make various variations and modifications based on the concept of this disclosure, and all such variations and modifications should fall within the scope of protection claimed by this disclosure.

Claims

1. A vertical transistor, characterized in that, At least including: Source layer, gate layer, drain layer, first active layer, second active layer; The source layer, the first active layer, the gate layer, the second active layer, and the drain layer are stacked sequentially in the vertical direction. The gate layer includes a first gate structure and a second gate structure. The first active layer and the second active layer both form a Schottky contact with the first gate structure. The vertical direction is the direction perpendicular to the substrate. The first gate structure is located in the vertical stacked connection region, and has a first active overlap region with the source layer in the vertical direction, and a second active overlap region with the gate layer in the vertical direction. The first gate structure adopts a sparse gate material or has a sparse hollow structure. The first active overlap region is the projected overlap portion of the two connection surfaces connecting the first active layer with the source layer and the gate layer, and the second active overlap region is the projected overlap portion of the two connection surfaces connecting the second active layer with the drain layer and the gate layer. The second gate structure is located in the non-vertical stacked connection region and is connected to the first gate structure for receiving voltage signals.

2. The vertical transistor as described in claim 1, characterized in that, The second gate structure is made of a metallized material and is set using the drain layer as a mask for self-alignment; the second gate structure is also connected to the second active layer.

3. The vertical transistor as described in claim 1 or 2, characterized in that, The sparse gate material includes at least one of the following: nanotubes, nanowires, and graphene; The sparse openwork structure has an openwork pattern that includes at least one of the following: polygon, circle, or ellipse.

4. A display pixel, characterized in that, At least including: Source layer, gate layer, drain layer, first active layer, second active layer; The source layer, the first active layer, the gate layer, the second active layer, and the drain layer are stacked sequentially in the vertical direction. The gate layer includes a first gate structure and a second gate structure. The first active layer and the second active layer both form a Schottky contact with the first gate structure. The vertical direction is the direction perpendicular to the substrate. The first gate structure is located in the vertical stacked connection region, and has a first active overlap region with the source layer in the vertical direction, and a second active overlap region with the gate layer in the vertical direction. The first gate structure adopts a sparse gate material or has a sparse hollow structure. The first active overlap region is the projected overlap portion of the two connection surfaces connecting the first active layer with the source layer and the gate layer, and the second active overlap region is the projected overlap portion of the two connection surfaces connecting the second active layer with the drain layer and the gate layer. The second gate structure is located in the non-vertical stacked connection region and is connected to the first gate structure for receiving voltage signals; In this embodiment, a light-emitting layer is disposed on the drain layer; or, the vertically stacked connection region of the drain layer is connected to the anode layer, and a light-emitting layer is disposed on the anode layer.

5. The display pixel as described in claim 4, characterized in that, The second gate structure is made of a metallized material and is set using the drain layer as a mask for self-alignment; the second gate structure is also connected to the second active layer.

6. The display pixel as described in claim 4 or 5, characterized in that, The sparse gate material includes at least one of the following: nanotubes, nanowires, and graphene; The sparse openwork structure has an openwork pattern that includes at least one of the following: polygon, circle, or ellipse.

7. A vertical light-emitting transistor, characterized in that, At least including: Source layer, gate layer, drain layer, first active layer, second active layer; The source layer, the first active layer, the gate layer, the second active layer, and the drain layer are stacked sequentially in the vertical direction. The gate layer includes a first gate structure and a second gate structure. The first active layer and the second active layer both form a Schottky contact with the first gate structure. The vertical direction is the direction perpendicular to the substrate. The first gate structure is located in the vertical stacked connection region, and has a first active overlap region with the source layer in the vertical direction, and a second active overlap region with the gate layer in the vertical direction. The first gate structure adopts a sparse gate material or has a sparse hollow structure. The first active overlap region is the projected overlap portion of the two connection surfaces connecting the first active layer with the source layer and the gate layer, and the second active overlap region is the projected overlap portion of the two connection surfaces connecting the second active layer with the drain layer and the gate layer. The second gate structure is located in the non-vertical stacked connection region and is connected to the first gate structure for receiving voltage signals; The drain layer, the first active layer, and the second active layer are made of organic semiconductor materials, so that the drain layer emits light when excited by current flowing from the source layer to the second active layer.

8. The vertical light-emitting transistor as described in claim 7, characterized in that, The second gate structure is made of a metallized material and is set using the drain layer as a mask for self-alignment; the second gate structure is also connected to the second active layer.

9. The vertical light-emitting transistor as described in claim 7 or 8, characterized in that, The sparse gate material includes at least one of the following: nanotubes, nanowires, and graphene; The sparse openwork structure has an openwork pattern that includes at least one of the following: polygon, circle, or ellipse.

10. A display panel, characterized in that, At least including: The display pixels of any one of claims 4 to 6; And / or, The vertical light-emitting transistor according to any one of claims 7 to 9.

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