Power supply system and pulse width modulation method applicable thereto

Abstract

The present disclosure relates to a power supply system and a pulse width modulation method applicable thereto. The power supply system comprises a pulse width modulation device, outputs first to fourth driving signals, and comprises: a control unit, generates a control signal; and a pulse width modulation unit, divides the control signal into positive and negative periodic signals, clamps a portion of the positive periodic signal greater than or equal to a maximum voltage threshold at the maximum voltage threshold to form a first comparison waveform, and clamps the positive periodic signal at a reference voltage level as a second comparison waveform; superimposes a low voltage threshold and a first comparison waveform falling within a first time interval to form a first ramp signal, and superimposes a low voltage threshold and a second comparison waveform falling within the first time interval to form a first pulse width signal, so as to adjust the first and third driving signals through the first ramp signal, and adjust the second and fourth driving signals through the first pulse width signal.

Description

Technical Field

[0001] The present disclosure relates to a power supply system, in particular to a power supply system capable of compensating for output voltage distortion caused by minimum pulse width limitation and a pulse width modulation method applicable thereto Background Art

[0002] In various industrial applications, power systems are often used to convert voltages. The power system includes multiple transistors. Through the switching of multiple transistors, the power system converts the received voltage to provide it to the load.

[0003] In addition, the power system further includes a control unit and a pulse width modulation unit. The control unit outputs a control signal so that the output voltage of the power system can be adjusted accordingly according to the control signal. The pulse width modulation unit generates multiple pulse width signals according to the control signal so that multiple transistors can perform switch switching according to the corresponding pulse width signals.

[0004] Each transistor in the power system usually contains a parasitic diode, and the diode has the characteristic of reverse recovery current, that is, the parasitic diode will have a reverse current for a certain period of time. Therefore, if the corresponding transistor is switched on during the reverse recovery current period, the reverse current on the parasitic diode will be instantly cut off. This sudden current cutoff will cause a surge voltage in the circuit, thereby causing damage to the circuit components of the power system. In order to avoid the above situation, most power systems currently add a minimum pulse width limitation technology to the implementation of switch switching to ensure that the reverse recovery current on the parasitic diode of the transistor can be completely terminated.

[0005] However, since the power system is equipped with a minimum pulse width limitation technology, during the period of the minimum pulse width limitation, the output voltage output by the power system will be clamped according to the minimum pulse width limitation, and cannot accurately follow the control signal output by the control unit to adjust, resulting in the output power output by the power system being distorted during the period of the minimum pulse width limitation.

[0006] Therefore, it is necessary to develop an improved power supply system and a pulse width modulation method applicable thereto to solve the above problems faced by the prior art. Summary of the invention

[0007] The purpose of the present disclosure is to provide a power supply system and a pulse width modulation method applicable thereto, so as to solve the problem that when a traditional power supply system uses a minimum pulse width limiting technology, the output voltage of the power supply system cannot be accurately adjusted according to a control signal output by a control unit within the minimum pulse width limiting period, resulting in distortion of the output electric energy.

[0008] To achieve the above-mentioned purpose, a broader embodiment of the present disclosure is a power system, comprising a power conversion device and a pulse width modulation device, wherein the pulse width modulation device outputs first to fourth driving signals to operate the power conversion device, and the pulse width modulation device comprises: a control unit for generating a control signal, wherein the control signal is a periodic signal; and a pulse width modulation unit, which determines a critical time point of the control signal according to a reference voltage level, and divides the control signal into a positive periodic signal and a negative periodic signal according to the critical time point, wherein the control signal is close to the reference voltage level within an error range at the critical time point; the pulse width modulation unit clamps a portion of the positive periodic signal that is greater than or equal to a maximum voltage threshold at the maximum voltage threshold to form a first comparison waveform, and the pulse width modulation unit also The positive cycle signal is clamped at a reference voltage level to serve as a second comparison waveform, and a pulse width modulation unit samples a first and a second comparison waveform falling within a first time interval from a critical time point to a first predetermined time; wherein the pulse width modulation unit superimposes a low voltage threshold and the first comparison waveform falling within the first time interval to form a first ramp signal; wherein the pulse width modulation unit superimposes a low voltage threshold and the second comparison waveform falling within the first time interval to form a first pulse width signal; wherein within the first time interval, the pulse width modulation unit compares the first ramp signal with the first triangular wave to adjust the first and third driving signals, and the pulse width modulation unit compares the first pulse width signal with the second triangular wave to adjust the second and fourth driving signals, wherein the phase difference between the first and second triangular waves is 180 degrees.

[0009] To achieve the above-mentioned purpose, another broad implementation of the present disclosure is a pulse width modulation method, comprising: receiving a control signal, wherein the control signal is a periodic signal; determining a critical time point of the control signal according to a reference voltage level; dividing the control signal into a positive periodic signal and a negative periodic signal according to the critical time point, wherein the control signal is close to the reference voltage level within an error range at the critical time point; clamping a portion of the positive periodic signal that is greater than or equal to a maximum voltage threshold at the maximum voltage threshold to form a first comparison waveform; clamping the positive periodic signal at the reference voltage level to serve as a second comparison waveform; sampling the positive periodic signal that falls within the critical time point; The invention relates to a first and a second comparison waveform in a first time interval from a time point to a first predetermined time; superimposing a low voltage threshold and the first comparison waveform falling within the first time interval to form a first ramp signal; superimposing a low voltage threshold and the second comparison waveform falling within the first time interval to form a first pulse width signal; comparing the first ramp signal with the first triangular wave in the first time interval to adjust the first and third driving signals; and comparing the first pulse width signal with the second triangular wave in the first time interval to adjust the second and fourth driving signals by a pulse width modulation unit, wherein the phase difference between the first and second triangular waves is 180 degrees. BRIEF DESCRIPTION OF THE DRAWINGS

[0010] Figure 1AIt is a circuit block diagram of a power supply system 1 of a preferred embodiment of the present disclosure;

[0011] Figure 1B for Figure 1A The circuit structure diagram of the first preferred embodiment of the power conversion device 3 shown;

[0012] Figure 1C for Figure 1A The circuit structure diagram of the second preferred embodiment of the power conversion device 3 shown;

[0013] Figure 2 To explain Figure 1A The signal timing diagram of the pulse width modulation unit 21 when in operation is shown;

[0014] Figure 3A A signal timing diagram for explaining the pulse width modulation unit 21 generating the first ramp signal S1a and the first reference waveform S1';

[0015] Figure 3B A signal timing diagram for explaining the pulse width modulation unit 21 generating the first pulse width signal S2a and the second reference waveform S2';

[0016] Figure 4A It is a signal timing diagram of the first triangle wave ePWM1, the second triangle wave ePWM2, the first ramp signal S1a, the first pulse width signal S2a, and the first drive signal P1 to the fourth drive signal P4 in the first time interval ΔT1;

[0017] Figure 4B It is a signal timing diagram of the first triangular wave ePWM1, the second triangular wave ePWM2, the first reference waveform S1', the second reference waveform S2', and the first driving signal P1 to the fourth driving signal P4 in the first time interval ΔT1;

[0018] Figure 5A A signal timing diagram for explaining the pulse width modulation unit 21 generating the second pulse width signal S3a and the third reference waveform S3';

[0019] Figure 5B A signal timing diagram for explaining the pulse width modulation unit 21 generating the second ramp signal S4a and the fourth reference waveform S4';

[0020] Fig. 6A It is a signal timing diagram of the first triangular wave ePWM1, the second triangular wave ePWM2, the second pulse width signal S3a, the second ramp signal S4a, and the first driving signal P1 to the fourth driving signal P4 in the second time interval;

[0021] Figure 6BIt is a signal timing diagram of the first triangular wave ePWM1, the second triangular wave ePWM2, the third reference waveform S3', the fourth reference waveform S4', and the first driving signal P1 to the fourth driving signal P4 in the second time interval;

[0022] Figure 7 A schematic diagram of the waveform of the output current output by a conventional power supply system with the addition of the minimum pulse width limiting technology;

[0023] Figure 8 Schematic diagram of the waveform of the output current output by the power supply system 1 of the present disclosure.

[0024] The reference numerals are described as follows:

[0025] 1: Power system

[0026] Vout: output voltage

[0027] 2: Pulse Width Modulation Device

[0028] 3: Power conversion device

[0029] P1~P4: first drive signal to fourth drive signal

[0030] 30, 30': switch module

[0031] Q1~Q4, Q1a~Q4a: first transistor to fourth transistor

[0032] Vdc: DC voltage source

[0033] T, T1: output nodes

[0034] D1~D4, D1a~D4a: parasitic diodes

[0035] D10: The first diode

[0036] D20: Second diode

[0037] 20: Control unit

[0038] 21: Pulse Width Modulation Unit

[0039] Sc, Sc': control signal

[0040] Sc+: positive cycle signal

[0041] Sc-: Negative periodic signal

[0042] t0, t1, t2, t1', t2: time

[0043] Vmin: low voltage threshold

[0044] Vmax: Maximum voltage threshold

[0045] ePWM1: first triangle wave

[0046] ePWM2: Second triangle wave

[0047] S1a: First ramp signal

[0048] S2a: First pulse width signal

[0049] S3a: Second pulse width signal

[0050] S4a: Second ramp signal

[0051] S1: The first comparison waveform

[0052] S2: Second comparison waveform

[0053] S3: The third comparison waveform

[0054] S4: The fourth comparison waveform

[0055] S1': First reference waveform

[0056] S2': Second reference waveform

[0057] S3': The third reference waveform

[0058] S4': Fourth reference waveform

[0059] ΔT1: First time interval

[0060] ΔT2: Second time interval

[0061] Vref: reference voltage level DETAILED DESCRIPTION

[0062] Some typical embodiments that embody the features and advantages of the present disclosure will be described in detail in the following description. It should be understood that the present disclosure can have various changes in different aspects without departing from the scope of the present disclosure, and the descriptions and drawings therein are essentially used for illustrative purposes rather than for limiting the present disclosure.

[0063] See also Figure 1A , Figure 1B , Figure 1C , Figure 2 , Figure 3A , Figure 3B , Figure 4A and Figure 4B ,in Figure 1A 1 is a circuit block diagram of a power supply system 1 according to a preferred embodiment of the present disclosure. Figure 1B for Figure 1A The circuit structure diagram of the first preferred embodiment of the power conversion device 3 is shown in FIG. Figure 1C for Figure 1A The circuit structure diagram of the second preferred embodiment of the power conversion device 3 is shown in FIG. Figure 2 To explain Figure 1A The signal timing diagram of the pulse width modulation unit 21 during operation is shown in FIG. Figure 3A To explain the signal timing diagram of the pulse width modulation unit 21 generating the first ramp signal S1a and the first reference waveform S1′, Figure 3B To explain the signal timing diagram of the pulse width modulation unit 21 generating the first pulse width signal S2a and the second reference waveform S2', Figure 4A is a signal timing diagram of the first triangular wave ePWM1, the second triangular wave ePWM2, the first ramp signal S1a, the first pulse width signal S2a, and the first drive signal P1 to the fourth drive signal P4 in the first time interval ΔT1, Figure 4B 1 is a schematic diagram of the signal timing of the first triangular wave ePWM1, the second triangular wave ePWM2, the first reference waveform S1', the second reference waveform S2', and the first drive signal P1 to the fourth drive signal P4 in the first time interval ΔT1. Figure 1A-Figure 1C , Figure 2 , Figure 3A-3B and Figure 4A-4B As shown, the power system 1 of the present embodiment is used to convert the received input voltage, such as the DC voltage provided by a battery, a solar panel or a capacitor, into an AC output voltage Vout to provide it to an AC load, such as a motor, a power grid or an industrial product, wherein the output voltage Vout may be but is not limited to a three-phase output voltage. The power system 1 includes a pulse width modulation device 2 and a power conversion device 3. The pulse width modulation device 2 may output a first drive signal P1, a second drive signal P2, a third drive signal P3 and a fourth drive signal P4 to the power conversion device 3 to operate the power conversion device 3. The power conversion device 3 may include a switch module 30, and the switch module 30 may include a plurality of transistors, such as Figure 1B The four transistors Q1-Q4 shown in the power conversion device 3 are used to receive the input voltage, and convert the input voltage into the output voltage Vout when the multiple transistors of the switch module 30 are selectively turned on or off when receiving the first drive signal P1, the second drive signal P2, the third drive signal P3 and the fourth drive signal P4 respectively. The switch module 30 is selectively turned on or off according to the first to fourth drive signals P1~P4, so that the DC voltage is converted into an AC voltage through the switch module 30. Therefore, in this embodiment, the input voltage is a DC voltage source Vdc, and the output voltage Vout is an AC voltage, but the present invention is not limited to this.

[0064] In some embodiments, such as Figure 1BAs shown, the switch module 30 can be an I-type three-stage switch module, and the multiple transistors of the switch module 30 are respectively a first transistor Q1, a second transistor Q2, a third transistor Q3 and a fourth transistor Q4. The first transistor Q1 includes a control terminal, a first terminal and a second terminal, wherein the control terminal of the first transistor Q1 is coupled to the first driving signal P1, and the first terminal of the first transistor Q1 is coupled to the DC voltage source Vdc. The second transistor Q2 includes a control terminal, a first terminal and a second terminal, wherein the control terminal of the second transistor Q2 is coupled to the second driving signal P2, and the first terminal of the second transistor Q2 is coupled to the second terminal of the first transistor Q1. The third transistor Q3 includes a control terminal, a first terminal and a second terminal, wherein the control terminal of the third transistor Q3 is coupled to the third driving signal P3, and the first terminal of the third transistor Q3 is coupled to the second terminal of the second transistor Q2 to form an output node T, and the power conversion device 3 outputs the output voltage Vout via the output node T. The fourth transistor Q4 includes a control terminal, a first terminal and a second terminal, wherein the control terminal of the fourth transistor Q4 is coupled to the fourth driving signal P4, the first terminal of the fourth transistor Q4 is coupled to the second terminal of the third transistor Q3, and the second terminal of the fourth transistor Q4 is coupled to the ground terminal of the DC voltage source Vdc. Figure 3A-3B When the power conversion device 3 receives the input voltage V, the power conversion device 3 adjusts the input voltage to a DC voltage source Vdc acceptable to the switch module 30. In some other embodiments, the DC voltage source Vdc may also be the input voltage directly, but the present invention is not limited thereto.

[0065] In some embodiments, the first transistor Q1 to the fourth transistor Q4 can be respectively formed by a metal-oxide-semiconductor field-effect transistor (MOSFET), but not limited thereto, and can also be a bipolar junction transistor (BJT), etc. In some embodiments, the first to the fourth transistors Q1 to Q4 can be a high voltage conduction semiconductor (such as: N-type MOSFET, NPN-type BJT) or a low voltage conduction semiconductor (such as: P-type MOSFET, PNP-type BJT). In order to facilitate the description of the operation of the present invention, only the first to the fourth transistors Q1 to Q4 are all N-type MOSFET as an example, but the present invention is not limited thereto. In addition, the first end of each of the first to the fourth transistors Q1 to Q4 represents the drain of the N-type MOSFET, and the second end of each of the first to the fourth transistors Q1 to Q4 represents the source of the N-type MOSFET, and the control end of each of the first to the fourth transistors Q1 to Q4 represents the gate of the N-type MOSFET.

[0066] In addition, the first transistor Q1 to the fourth transistor Q4 may further include parasitic diodes D1-D4, respectively, wherein the anode terminal of the parasitic diode D1 is electrically connected to the second end of the first transistor Q1, the cathode terminal of the parasitic diode D1 is electrically connected to the first end of the first transistor Q1, the anode terminal of the parasitic diode D2 is electrically connected to the second end of the second transistor Q2, the cathode terminal of the parasitic diode D2 is electrically connected to the first end of the second transistor Q2, the anode terminal of the parasitic diode D3 is electrically connected to the second end of the third transistor Q3, the cathode terminal of the parasitic diode D3 is electrically connected to the first end of the third transistor Q3, the anode terminal of the parasitic diode D4 is electrically connected to the second end of the fourth transistor Q4, and the cathode terminal of the parasitic diode D4 is electrically connected to the first end of the fourth transistor Q4. In addition, in some embodiments, the switch module 30 may further include a first diode D10 and a second diode D20, wherein the cathode terminal of the first diode D10 is electrically connected between the second end of the first transistor Q1 and the first end of the second transistor Q2, the anode terminal of the first diode D10 is electrically connected to the cathode terminal of the second diode D20, and the anode terminal of the second diode D20 is electrically connected between the second end of the third transistor Q3 and the first end of the fourth transistor Q4.

[0067] Of course, the switch module 30 of the power conversion device 3 can also be a T-type three-level switch module, that is, Figure 1CAs shown, the switch module 30 includes a first transistor Q1, a second transistor Q2, a third transistor Q3, and a fourth transistor Q4. The first transistor Q1 includes a control terminal, a first terminal, and a second terminal, wherein the control terminal of the first transistor Q1 is coupled to the first driving signal P1, and the first terminal of the first transistor Q1 is coupled to the DC voltage source Vdc. The second transistor Q2 includes a control terminal, a first terminal, and a second terminal, wherein the control terminal of the second transistor Q2 is coupled to the second driving signal P2, and the first terminal of the second transistor Q2 is coupled to the DC voltage source Vdc. The third transistor Q3 includes a control terminal, a first terminal, and a second terminal, wherein the control terminal of the third transistor Q3 is coupled to the third driving signal P3, and the second terminal of the third transistor Q3 is coupled to the second terminal of the second transistor Q2. The fourth transistor Q4 includes a control terminal, a first terminal and a second terminal, wherein the control terminal of the fourth transistor Q4 is coupled to the fourth driving signal P4, and the first terminal of the fourth transistor Q4 is commonly coupled to the first terminal of the third transistor Q3 and the second terminal of the first transistor Q1 to jointly form an output node T1, and the power conversion device 3 outputs the output voltage Vout via the output node T1, and the second terminal of the fourth transistor Q4 is coupled to the ground terminal of the DC voltage source Vdc. In addition, the first transistor Q1 to the fourth transistor Q4 may further include parasitic diodes D1a-D4a, respectively, wherein the anode terminal of the parasitic diode D1a is electrically connected to the second end of the first transistor Q1, the cathode terminal of the parasitic diode D1a is electrically connected to the first end of the first transistor Q1, the anode terminal of the parasitic diode D2a is electrically connected to the second end of the second transistor Q2, the cathode terminal of the parasitic diode D2a is electrically connected to the DC voltage source Vdc, the anode terminal of the parasitic diode D3a is electrically connected to the second end of the third transistor Q3, the cathode terminal of the parasitic diode D3a is electrically connected to the first end of the third transistor Q3, the anode terminal of the parasitic diode D4a is electrically connected to the second end of the fourth transistor Q4, and the cathode terminal of the parasitic diode D4a is electrically connected to the first end of the fourth transistor Q4. Figure 1C The actuation of the switch module 30 and Figure 1B The switch modules 30 shown in the figure have the same actuation mode and can achieve the same effect. Therefore, the technical contents mentioned below are only based on Figure 1B The switch module 30 is shown for exemplary purposes.

[0068] The first drive signal P1, the second drive signal P2, the third drive signal P3 and the fourth drive signal P4 output by the pulse width modulation device 2 are respectively provided to the first transistor Q1, the second transistor Q2, the third transistor Q3 and the fourth transistor Q4, so that the first transistor Q1, the second transistor Q2, the third transistor Q3 and the fourth transistor Q4 are respectively switched on or off. In some embodiments, the waveforms of the first drive signal P1 and the third drive signal P3 are complementary, and the waveforms of the second drive signal P2 and the fourth drive signal P4 are complementary. In other words, the operating mode of the first transistor Q1 is complementary to the operating mode of the third transistor Q3, and the operating mode of the second transistor Q2 is complementary to the operating mode of the fourth transistor Q4.

[0069] The pulse width modulation device 2 further includes a control unit 20 and a pulse width modulation unit 21. The control unit 20 is used to generate a control signal Sc to the pulse width modulation unit 21, and the pulse width modulation unit 21 controls the switch module 30 in the power conversion device 3 according to the control signal Sc, wherein the control signal Sc can be but is not limited to a periodic signal. In some embodiments, the control unit 20 further samples the output voltage Vout and the output current of the power conversion device 3 through a voltage sampling element or a current sampling element, etc., so as to adjust the control signal Sc accordingly according to the sampling results. The pulse width modulation unit 21 is based on a reference voltage level Vref, for example Figure 2 The reference voltage level Vref of the zero voltage level is shown, which determines the critical time point of the control signal Sc, and the control signal area Sc is divided into a positive cycle signal Sc+ of a positive half cycle and a negative cycle signal Sc- of a negative half cycle according to the critical time point. Figure 2 As shown, when the critical time point of the control signal Sc is determined by the zero voltage level, the critical time point of the control signal Sc is t0, so the control signal Sc is a positive cycle signal Sc+ after time t0, and the control signal Sc is a negative cycle signal Sc- before time t0, wherein the control signal Sc is close to the reference voltage level Vref within an allowable error range at the critical time point t0.

[0070] In addition, the pulse width modulation unit 21 clamps the portion of the positive cycle signal Sc+ that is greater than or equal to the maximum voltage threshold Vmax at the maximum voltage threshold Vmax to form a first comparison waveform S1, and the pulse width modulation unit 21 also clamps the positive cycle signal Sc+ at the reference voltage level Vref to form a second comparison waveform S2. The pulse width modulation unit 21 samples the critical time point (such as Figure 2 The pulse width modulation unit 21 further superimposes the low voltage threshold Vmin and the first comparison waveform S1 falling within the first time interval ΔT1 to form a first ramp signal S1a (such as Figure 3A As shown), the pulse width modulation unit 21 also superimposes the low voltage threshold Vmin and the second comparison waveform S2 falling within the first time interval ΔT1 to form a first pulse width signal S2a (as shown Figure 3B shown).

[0071] Furthermore, within the first time interval ΔT1, the pulse width modulation unit 21 compares the first ramp signal S1a with the first triangle wave ePWM1 to adjust the first driving signal P1 and the third driving signal P3, and the pulse width modulation unit 21 compares the first pulse width signal S2a with the second triangle wave ePWM2 to adjust the second driving signal S2 and the fourth driving signal P4 (such as Figure 4A As shown), the phase difference between the first triangular wave ePWM1 and the second triangular wave ePWM2 is 180 degrees.

[0072] In the above embodiment, the first time interval ΔT1 is the time interval during which the power system 1 performs minimum pulse width limitation in the positive half cycle of the control signal zone Sc. The low voltage threshold Vmin is the preset value of the output voltage Vout of the power system 1 when the power system 1 performs minimum pulse width limitation.

[0073] Furthermore, if Figure 4A As shown, within the first time interval ΔT1, when the pulse width modulation unit 21 determines that the first ramp signal S1a is greater than the first triangle wave ePWM1, the pulse width modulation unit 21 switches the first drive signal P1 to a high voltage level, and switches the third drive signal P3 to a low voltage level, so that the first transistor Q1 is switched on and the third transistor Q3 is switched off; in addition, within the first time interval ΔT1, when the pulse width modulation unit 21 determines that the first pulse width signal S2a is less than the second triangle wave ePWM2, the pulse width modulation unit 21 switches the second drive signal P2 to a high voltage level, and switches the fourth drive signal P4 to a low voltage level, so that the second transistor Q2 is switched on and the fourth transistor Q4 is switched off.

[0074] In addition, within the first time interval ΔT1, when the pulse width modulation unit 21 determines that the first ramp signal S1a is less than or equal to the first triangle wave ePWM1, the pulse width modulation unit 21 switches the first drive signal P1 to a low voltage level and switches the third drive signal P3 to a high voltage level, so that the first transistor Q1 is switched off and the third transistor Q3 is switched on; and within the first time interval ΔT1, when the pulse width modulation unit 21 determines that the first pulse width signal S2a is greater than or equal to the second triangle wave ePWM2, the pulse width modulation unit 21 switches the second drive signal P2 to a low voltage level and switches the fourth drive signal P4 to a high voltage level, so that the second transistor Q2 is switched off and the fourth transistor Q4 is switched on. Figure 4AIt can be seen that in the positive half cycle of the control signal Sc, the output voltage Vout consists of 0, -Vdc / 2 and Vdc / 2.

[0075] As can be seen from the foregoing, the pulse width modulation unit 21 of the power supply system 1 of the present invention will superimpose the low voltage threshold Vmin and the first comparison waveform S1 falling within the first time interval ΔT1 to form a first ramp signal S1a during the positive half cycle of the control signal Sc and in the first time interval ΔT1 from the critical time point t0 to the first predetermined time, and superimpose the low voltage threshold Vmin and the second comparison waveform S2 falling within the first time interval ΔT1 to form a first pulse width signal S2a. In other words, when the control signal Sc is in the positive half cycle and the power supply system 1 performs the minimum pulse width restriction, the control signal Sc is compensated for the low voltage threshold Vmin. In this way, the power supply system 1 of the present invention can not only meet the minimum pulse width restriction, but also because in the first time interval ΔT1 from the critical time point t0 to the first predetermined time, the first ramp signal S1a superimposes the positive half cycle of the control signal Sc and the first pulse width signal S2a. The low voltage threshold Vmin generated by a is cancelled, so the ideal control signal Sc is maintained and the time zone in which the power system 1 executes the minimum pulse width limitation is satisfied, thereby ensuring the accuracy of the output voltage Vout.

[0076] The operation of the power system 1 when the control signal Sc is in the negative half cycle will be described below. Figure 1A-1B , Figure 2 , and cooperate with Figure 5A , Figure 5B , Fig. 6A and Figure 6B ,in Figure 5A To explain the signal timing diagram of the pulse width modulation unit 21 generating the second pulse width signal S3a and the third reference waveform S3', Figure 5B To explain the signal timing diagram of the pulse width modulation unit 21 generating the second ramp signal S4a and the fourth reference waveform S4', Fig. 6A is a signal timing diagram of the first triangular wave ePWM1, the second triangular wave ePWM2, the second pulse width signal S3a, the second ramp signal S4a, and the first drive signal P1 to the fourth drive signal P4 in the second time interval, Figure 6B1 is a signal timing diagram of the first triangular wave ePWM1, the second triangular wave ePWM2, the third reference waveform S3', the fourth reference waveform S4', the first driving signal P1 to the fourth driving signal P4 in the second time interval. In some embodiments, during the negative half cycle of the control signal Sc, the pulse width modulation unit 21 clamps the negative cycle signal Sc- at the reference voltage level Vref to serve as the third comparison waveform S3, and the pulse width modulation unit 21 inverts the negative cycle signal Sc-, and clamps the portion of the inverted negative cycle signal Sc- that is greater than or equal to the maximum voltage threshold Vmax at the maximum voltage threshold Vmax to form the fourth comparison waveform S4.

[0077] In addition, the pulse width modulation unit 21 can further sample the third comparison waveform S3 and the fourth comparison waveform S4 falling within the second time interval ΔT2 from the critical time point t0 to the second predetermined time t2. The pulse width modulation unit 21 further superimposes the low voltage threshold Vmin and the third comparison waveform S3 falling within the second time interval ΔT2 to form a second pulse width signal S3a, and the pulse width modulation unit 21 also superimposes the low voltage threshold Vmin and the fourth comparison waveform S4 falling within the second time interval ΔT2 to form a second ramp signal S4a.

[0078] Furthermore, in the second time interval ΔT2, the pulse width modulation unit 21 compares the second pulse width signal S3a with the first triangular wave ePWM1 to adjust the first driving signal P1 and the third driving signal P3, and the pulse width modulation unit 21 compares the second ramp signal S4a with the second triangular wave ePWM2 to adjust the second driving signal P2 and the fourth driving signal P4. In the above embodiment, the second time interval ΔT2 is the time interval in which the power system 1 performs the minimum pulse width limitation when the control signal zone Sc is in the negative half cycle.

[0079] What's worse, if Fig. 6A As shown, in the second time interval ΔT2, when the pulse width modulation unit 21 determines that the second pulse width signal S3a is greater than the first triangular wave ePWM1, the pulse width modulation unit 21 switches the first drive signal P1 to a high voltage level, and switches the third drive signal P3 to a low voltage level, so that the first transistor Q1 is switched on and the third transistor Q3 is switched off. In addition, in the second time interval ΔT2, when the pulse width modulation unit 21 determines that the second ramp signal S4a is less than the second triangular wave ePWM2, the pulse width modulation unit 21 switches the second drive signal P2 to a high voltage level, and switches the fourth drive signal P4 to a low voltage level, so that the second transistor Q2 is switched on and the fourth transistor Q4 is switched off.

[0080] In addition, in the second time interval ΔT2, when the pulse width modulation unit 21 determines that the second pulse width signal S3a is less than or equal to the first triangular wave ePWM1, the pulse width modulation unit 21 switches the first drive signal P1 to a low voltage level and switches the third drive signal P3 to a high voltage level, so that the first transistor Q1 is switched off and the third transistor Q3 is switched on; and in the second time interval ΔT2, when the pulse width modulation unit 21 determines that the second ramp signal S4a is greater than or equal to the second triangular wave ePWM2, the pulse width modulation unit 21 switches the second drive signal P2 to a low voltage level and switches the fourth drive signal P4 to a high voltage level, so that the second transistor Q2 is switched off and the fourth transistor Q4 is switched on. Fig. 6A It can be seen that in the negative half cycle of the control signal Sc, the output voltage Vout consists of 0, -Vdc / 2 and Vdc / 2.

[0081] Please refer to Figure 7 and Figure 8 , and cooperate with Figures 1A to 6B ,in Figure 7 This is a waveform diagram of the output current output by a traditional power supply system with the addition of minimum pulse width limitation technology. Figure 8 FIG. 1 is a schematic diagram of the waveform of the output current output by the power supply system 1 of the present disclosure. As shown in the figure, first, according to Figure 7 As shown in the figure, when the control signal Sc' output by the control unit of the conventional power system is close to the zero crossing point, the conventional power system enters the time interval of the minimum pulse width restriction, so the output current (including the U-phase current, the V-phase current and the W-phase current) output by the conventional power system will be distorted. However, since the power system 1 of the present invention compensates the control signal Sc for the low voltage threshold Vmin when the control signal area Sc is in the positive half cycle and the negative half cycle and the power system 1 executes the time interval of the minimum pulse width restriction, Figure 8 As shown, the output current (including U-phase current, V-phase current and W-phase current) output by the power supply system 1 of the present disclosure can greatly improve the distortion phenomenon.

[0082] Please refer to Figure 3A-3B and Figure 4B , and cooperate with Figure 2 In some embodiments, the pulse width modulation unit 21 may sample outside the first time interval ΔT1, for example Figure 3A The first comparison waveform S1 after time t1 is used as the first reference waveform S1', and the pulse width modulation unit 21 also samples outside the first time interval ΔT1, for example Figure 3B The second comparison waveform S2 after time t1 shown in FIG. 1 is used as the second reference waveform S2′, and as shown in FIG. Figure 4BAs shown, the pulse width modulation unit 21 compares the first reference waveform S1' with the first triangular wave ePWM1 to adjust the first drive signal P1 and the third drive signal P3, wherein when the pulse width modulation unit 21 determines that the first reference waveform S1' is greater than the first triangular wave ePWM1, the pulse width modulation unit 21 switches the first drive signal P1 to a high voltage level and switches the third drive signal P3 to a low voltage level. In addition, when the pulse width modulation unit 21 determines that the first reference waveform S1' is less than or equal to the first triangular wave ePWM1, the pulse width modulation unit 21 switches the first drive signal P1 to a low voltage level and switches the third drive signal P3 to a high voltage level. Furthermore, when the pulse width modulation unit 21 determines that the second reference waveform S2' is always less than the second triangular wave ePWM2, the pulse width modulation unit 21 maintains the second drive signal P2 to a high voltage level and maintains the fourth drive signal P4 to a low voltage level.

[0083] Please refer to Figure 5A-Figure 5B and Figure 6B , and cooperate with Figure 2 In some embodiments, the pulse width modulation unit 21 also samples outside the second time interval ΔT2, for example Figure 5A Before the time t2 shown, the third comparison waveform S3 is used as the third reference waveform S3', and the pulse width modulation unit 21 also samples outside the second time interval ΔT2, for example Figure 5B Before the time t2 shown in FIG. 1 , the fourth comparison waveform S4 is used as the fourth reference waveform S4′, and as shown in FIG. Figure 6B As shown, the pulse width modulation unit 21 compares the fourth reference waveform S4' with the second triangular wave ePWM2 to adjust the second drive signal P2 and the fourth drive signal P4, wherein when the pulse width modulation unit 21 determines that the fourth reference waveform S4' is less than the second triangular wave ePWM2, the pulse width modulation unit 21 switches the second drive signal P2 to a high voltage level and switches the fourth drive signal P4 to a low voltage level. In addition, when the pulse width modulation unit 21 determines that the fourth reference waveform S4' is greater than or equal to the second triangular wave ePWM2, the pulse width modulation unit 21 switches the second drive signal P2 to a low voltage level and switches the fourth drive signal P4 to a high voltage level. Furthermore, when the pulse width modulation unit 21 determines that the third reference waveform S3' is always less than the first triangular wave ePWM1, the pulse width modulation unit 21 maintains the first drive signal P1 to a low voltage level and maintains the third drive signal P3 to a high voltage level.

[0084] In some embodiments, the first triangular wave ePWM1 and the second triangular wave ePWM2 are carrier waves of the control signal Sc, and the frequencies of the first triangular wave ePWM1 and the second triangular wave ePWM2 are at least ten times the frequencies of the control signal Sc. Since the frequencies of the first triangular wave ePWM1 and the second triangular wave ePWM2 are more than ten times the frequencies of the control signal Sc, when the waveform is enlarged, the waveform related to the control signal Sc is a straight line for the carrier wave, as shown in FIGS. 4A-4B and Figure 6A-6B shown.

[0085] The following will further describe the steps of the pulse width modulation method of the present disclosure which is applicable to the pulse width modulation device 2 of the power supply system 1 in the above-mentioned embodiment. The pulse width modulation method of the present disclosure includes the following steps.

[0086] First, in step s1 , the PWM unit 21 of the PWM device 2 receives the control signal Sc output by the control unit 20 , wherein the control signal Sc is a periodic signal.

[0087] In step s2 , the PWM unit 21 determines a critical time point of the control signal Sc according to the reference voltage level Vref.

[0088] In step s3 , the PWM unit 21 divides the control signal Sc into a positive period signal Sc+ and a negative period signal Sc− according to a critical time point, wherein the control signal Sc is close to the reference voltage level Vref within an error range at the critical time point.

[0089] In step s4 , the PWM unit 21 clamps the portion of the positive periodic signal Sc+ that is greater than or equal to the maximum voltage threshold Vmax at the maximum voltage threshold Vmax to form a first comparison waveform S1 .

[0090] In step s5 , the PWM unit 21 clamps the positive periodic signal Sc+ to the reference voltage level Vref as the second comparison waveform S2 .

[0091] In step s6, the pulse width modulation unit 21 samples the critical time point (eg Figure 2 The first comparison waveform S1 and the second comparison waveform S2 in the first time interval ΔT1 from the time t0 to the first predetermined time t1 are shown.

[0092] In step s7, the pulse width modulation unit 21 superimposes the low voltage threshold Vmin and the first comparison waveform S1 falling within the first time interval ΔT1 to form a first ramp signal S1a (eg, Figure 3A shown).

[0093] In step s8, the pulse width modulation unit 21 superimposes the low voltage threshold Vmin and the second comparison waveform S2 falling within the first time interval ΔT1 to form a first pulse width signal S2a (eg, Figure 3B shown).

[0094] In step s9 , within the first time interval ΔT1 , the pulse width modulation unit 21 compares the first ramp signal S1 a with the first triangle wave ePWM1 to adjust the first driving signal P1 and the third driving signal P3 .

[0095] In step s10, within the first time interval ΔT1, the pulse width modulation unit 21 compares the first pulse width signal S2a with the second triangular wave ePWM2 to adjust the second driving signal S2 and the fourth driving signal P4 (eg Figure 4A The phase difference between the first triangular wave ePWM1 and the second triangular wave ePWM2 is 180 degrees.

[0096] In addition, when the comparison result of step s9 is that the pulse width modulation unit 21 determines that the first ramp signal S1a is greater than the first triangle wave ePWM1, the pulse width modulation unit 21 switches the first drive signal P1 to a high voltage level, and switches the third drive signal P3 to a low voltage level, so that the first transistor Q1 is switched on and the third transistor Q3 is switched off. When the comparison result of step s10 is that the pulse width modulation unit 21 determines that the first pulse width signal S2a is less than the second triangle wave ePWM2, the pulse width modulation unit 21 switches the second drive signal P2 to a high voltage level, and switches the fourth drive signal P4 to a low voltage level, so that the second transistor Q2 is switched on and the fourth transistor Q4 is switched off.

[0097] On the contrary, when the comparison result of step s9 is that the PWM unit 21 determines that the first ramp signal S1a is less than or equal to the first triangle wave ePWM1, the PWM unit 21 switches the first drive signal P1 to a low voltage level and switches the third drive signal P3 to a high voltage level, so that the first transistor Q1 is switched off and the third transistor Q3 is switched on. When the comparison result of step s10 is that the PWM unit 21 determines that the first pulse width signal S2a is greater than or equal to the second triangle wave ePWM2, the PWM unit 21 switches the second drive signal P2 to a low voltage level and switches the fourth drive signal P4 to a high voltage level, so that the second transistor Q2 is switched off and the fourth transistor Q4 is switched on.

[0098] In some embodiments, the pulse width modulation method of the present disclosure further includes the following steps.

[0099] In step s1 ′, the PWM unit 21 clamps the negative periodic signal Sc- to the reference voltage level Vref as the third comparison waveform S3 .

[0100] In step s2 ′, the PWM unit 21 inverts the negative periodic signal Sc-, and clamps the portion of the inverted negative periodic signal Sc- that is greater than or equal to the maximum voltage threshold Vmax at the maximum voltage threshold Vmax to form a fourth comparison waveform S4 .

[0101] In step s3 ′, the PWM unit 21 may sample the third comparison waveform S3 and the fourth comparison waveform S4 falling within the second time interval ΔT2 from the critical time point t0 to the second predetermined time t2 .

[0102] In step s4 ′, the pulse width modulation unit 21 superimposes the low voltage threshold Vmin and the third comparison waveform S3 falling within the second time interval ΔT2 to form a second pulse width signal S3 a .

[0103] In step s5 ′, the PWM unit 21 superimposes the low voltage threshold Vmin and the fourth comparison waveform S4 falling within the second time interval ΔT2 to form a second ramp signal S4 a .

[0104] In step s6 ′, within the second time interval ΔT2 , the pulse width modulation unit 21 compares the second pulse width signal S3 a with the first triangle wave ePWM1 to adjust the first driving signal P1 and the third driving signal P3 .

[0105] In step s7 ′, the PWM unit 21 compares the second ramp signal S4 a with the second triangle wave ePWM2 to adjust the second driving signal P2 and the fourth driving signal P4 .

[0106] In addition, in step s6', in the second time interval ΔT2, when the pulse width modulation unit 21 determines that the second pulse width signal S3a is greater than the first triangle wave ePWM1, the pulse width modulation unit 21 switches the first drive signal P1 to a high voltage level. In step s7', in the second time interval ΔT2, when the pulse width modulation unit 21 determines that the second ramp signal S4a is less than the second triangle wave ePWM2, the pulse width modulation unit 21 switches the second drive signal P2 to a high voltage level and switches the fourth drive signal P4 to a low voltage level, so that the second transistor Q2 is switched on and the fourth transistor Q4 is switched off.

[0107] On the contrary, in step s6', within the second time interval ΔT2, when the pulse width modulation unit 21 determines that the second pulse width signal S3a is less than or equal to the first triangular wave ePWM1, the pulse width modulation unit 21 switches the first drive signal P1 to a low voltage level and switches the third drive signal P3 to a high voltage level, so that the first transistor Q1 is switched off and the third transistor Q3 is switched on. In step s7', when the pulse width modulation unit 21 determines that the second ramp signal S4a is greater than or equal to the second triangular wave ePWM2, the pulse width modulation unit 21 switches the second drive signal P2 to a low voltage level and switches the fourth drive signal P4 to a high voltage level, so that the second transistor Q2 is switched off and the fourth transistor Q4 is switched on.

[0108] In some embodiments, the control unit mentioned above may include but is not limited to a microcontroller, and the pulse width modulation unit may include but is not limited to a pulse width modulator.

[0109] In summary, the present disclosure provides a power supply system and a pulse width modulation method applicable thereto, wherein the power supply system of the present disclosure can compensate the low voltage threshold of the control signal when the control signal is in the positive half cycle and the negative half cycle and the minimum pulse width limit is executed. Therefore, the output power output by the power supply system of the present disclosure can greatly improve the distortion phenomenon.

[0110] It should be noted that the above are only preferred embodiments for illustrating the present disclosure, and the present disclosure is not limited to the embodiments described. The scope of the present disclosure is determined by the appended claims. Moreover, the present disclosure may be modified in various ways by those skilled in the art, but all of them are within the scope of the protection intended by the appended claims.

Claims

1. A power system, comprising a power conversion device and a pulse width modulation device, wherein the pulse width modulation device outputs a first driving signal to a fourth driving signal to operate the power conversion device, and the pulse width modulation device comprises: a control unit, configured to generate a control signal, wherein the control signal is a periodic signal; and a pulse width modulation unit, which determines a critical time point of the control signal according to a reference voltage level, and divides the control signal into a positive cycle signal and a negative cycle signal according to the critical time point, wherein the control signal is close to the reference voltage level within an error range at the critical time point; wherein the pulse width modulation unit clamps a portion of the positive cycle signal that is greater than or equal to a maximum voltage threshold at the maximum voltage threshold to form a first comparison waveform, and the pulse width modulation unit also clamps the positive cycle signal at the reference voltage level to form a second comparison waveform, and the pulse width modulation unit samples the first comparison waveform and the second comparison waveform that fall within a first time interval from the critical time point to a first predetermined time; The pulse width modulation unit superimposes a low voltage threshold and the first comparison waveform falling within the first time interval to form a first ramp signal; The pulse width modulation unit superimposes the low voltage threshold and the second comparison waveform falling within the first time interval to form a first pulse width signal; In the first time interval, the pulse width modulation unit compares the first ramp signal with a first triangular wave to adjust the first driving signal and the third driving signal, and the pulse width modulation unit compares the first pulse width signal with a second triangular wave to adjust the second driving signal and the fourth driving signal, wherein a phase difference between the first triangular wave and the second triangular wave is 180 degrees.

2. The power supply system according to claim 1, wherein: In the first time interval, if the pulse width modulation unit determines that the first ramp signal is greater than the first triangle wave, the pulse width modulation unit switches the first driving signal to a high voltage level and switches the third driving signal to a low voltage level; If the pulse width modulation unit determines that the first pulse width signal is smaller than the second triangular wave within the first time interval, the pulse width modulation unit switches the second driving signal to the high voltage level and switches the fourth driving signal to the low voltage level.

3. The power supply system according to claim 2, wherein: In the first time interval, if the pulse width modulation unit determines that the first ramp signal is less than or equal to the first triangle wave, the pulse width modulation unit switches the first driving signal to the low voltage level and switches the third driving signal to the high voltage level; Wherein within the first time interval, if the pulse width modulation unit determines that the first pulse width signal is greater than or equal to the second triangle wave, the pulse width modulation unit switches the second driving signal to the low voltage level and switches the fourth driving signal to the high voltage level.

4. The power supply system according to claim 2, wherein: The pulse width modulation unit clamps the negative periodic signal at the reference voltage level to serve as a third comparison waveform; The pulse width modulation unit inverts the negative cycle signal and clamps a portion of the inverted negative cycle signal that is greater than or equal to the maximum voltage threshold at the maximum voltage threshold to form a fourth comparison waveform.

5. The power supply system according to claim 4, wherein: The pulse width modulation unit samples the third comparison waveform and the fourth comparison waveform falling within a second time interval from the critical time point to a second predetermined time; The pulse width modulation unit superimposes the low voltage threshold and the third comparison waveform falling within the second time interval to form a second pulse width signal; wherein the pulse width modulation unit superimposes the low voltage threshold and the fourth comparison waveform falling within the second time interval to form a second ramp signal; In the second time interval, the pulse width modulation unit compares the second pulse width signal with the first triangle wave to adjust the first driving signal and the third driving signal, and the pulse width modulation unit compares the second ramp signal with a second triangle wave to adjust the second driving signal and the fourth driving signal.

6. The power supply system according to claim 5, wherein: In the second time interval, if the pulse width modulation unit determines that the second pulse width signal is greater than the first triangular wave, the pulse width modulation unit switches the first driving signal to the high voltage level and switches the third driving signal to the low voltage level; If the PWM unit determines that the second ramp signal is smaller than the second triangle wave within the second time interval, the PWM unit switches the second driving signal to the high voltage level and switches the fourth driving signal to the low voltage level.

7. The power supply system according to claim 5, wherein: In the second time interval, if the pulse width modulation unit determines that the second pulse width signal is less than or equal to the first triangular wave, the pulse width modulation unit switches the first driving signal to the low voltage level and switches the third driving signal to the high voltage level; If the PWM unit determines that the second ramp signal is greater than or equal to the second triangle wave within the second time interval, the PWM unit switches the second driving signal to the low voltage level and switches the fourth driving signal to the high voltage level.

8. The power supply system according to claim 2, wherein: The pulse width modulation unit further samples the first comparison waveform outside the first time interval as a first reference waveform, and the pulse width modulation unit further samples the second comparison waveform outside the first time interval as a second reference waveform; The pulse width modulation unit compares the first reference waveform with the first triangle wave to adjust the first driving signal and the third driving signal.

9. The power supply system according to claim 8, wherein: If the pulse width modulation unit determines that the first reference waveform is greater than the first triangular wave, the pulse width modulation unit switches the first driving signal to the high voltage level and switches the third driving signal to the low voltage level; If the PWM unit determines that the first reference waveform is less than or equal to the first triangle wave, the PWM unit switches the first driving signal to the low voltage level and switches the third driving signal to the high voltage level.

10. The power supply system according to claim 8, wherein: If the PWM unit determines that the second reference waveform is always smaller than the second triangular wave, the PWM unit maintains the second driving signal to the high voltage level and maintains the fourth driving signal to the low voltage level.

11. The power supply system according to claim 5, wherein: The pulse width modulation unit further samples the third comparison waveform outside the second time interval as a third reference waveform, and the pulse width modulation unit further samples the fourth comparison waveform outside the second time interval as a fourth reference waveform; The pulse width modulation unit compares the fourth reference waveform with the second triangle wave to adjust the second driving signal and the fourth driving signal.

12. The power supply system according to claim 11, wherein: If the pulse width modulation unit determines that the fourth reference waveform is smaller than the second triangular wave, the pulse width modulation unit switches the second driving signal to the high voltage level and switches the fourth driving signal to the low voltage level; If the PWM unit determines that the fourth reference waveform is greater than or equal to the second triangle wave, the PWM unit switches the second driving signal to the low voltage level and switches the fourth driving signal to the high voltage level.

13. The power supply system according to claim 11, wherein: If the PWM unit determines that the third reference waveform is always smaller than the first triangle wave, the PWM unit maintains the first driving signal at the low voltage level and maintains the third driving signal at the high voltage level.

14. The power supply system according to claim 1, wherein: The frequencies of the first triangular wave and the second triangular wave are at least ten times a frequency of the control signal.

15. A pulse width modulation method, comprising: receiving a control signal, wherein the control signal is a periodic signal; Determining a critical time point of the control signal according to a reference voltage level; The control signal is divided into a positive cycle signal and a negative cycle signal according to the critical time point, wherein the control signal is close to the reference voltage level within an error range at the critical time point; Clamping a portion of the positive periodic signal that is greater than or equal to a maximum voltage threshold at the maximum voltage threshold to form a first comparison waveform; Clamping the positive periodic signal at the reference voltage level to serve as a second comparison waveform; Sampling the first comparison waveform and the second comparison waveform falling within a first time interval from the critical time point to a first predetermined time; Superimposing a low voltage threshold and the first comparison waveform falling within the first time interval to form a first ramp signal; Superimposing the low voltage threshold and the second comparison waveform falling within the first time interval to form a first pulse width signal; Comparing the first ramp signal with a first triangle wave within the first time interval to adjust the first driving signal and the third driving signal; and The pulse width modulation unit compares the first pulse width signal with a second triangular wave in the first time interval to adjust the second driving signal and the fourth driving signal, wherein a phase difference between the first triangular wave and the second triangular wave is 180 degrees.

16. The pulse width modulation method according to claim 15, wherein: In the first time interval, if it is determined that the first ramp signal is greater than the first triangle wave, the first driving signal is switched to a high voltage level and the third driving signal is switched to a low voltage level; Wherein, within the first time interval, if it is determined that the first pulse width signal is smaller than the second triangular wave, the second driving signal is switched to the high voltage level and the fourth driving signal is switched to the low voltage level; Wherein, within the first time interval, if it is determined that the first ramp signal is less than or equal to the first triangle wave, the first driving signal is switched to the low voltage level and the third driving signal is switched to the high voltage level; If it is determined that the first pulse width signal is greater than or equal to the second triangular wave within the first time interval, the second driving signal is switched to the low voltage level and the fourth driving signal is switched to the high voltage level.

17. The pulse width modulation method according to claim 15, further comprising: Clamping the negative periodic signal at the reference voltage level to serve as a third comparison waveform; Inverting the negative cycle signal and clamping a portion of the inverted negative cycle signal that is greater than or equal to the maximum voltage threshold at the maximum voltage threshold to form a fourth comparison waveform; Sampling the third comparison waveform and the fourth comparison waveform falling within a second time interval from the critical time point to a second predetermined time; Superimposing the low voltage threshold and the third comparison waveform falling within the second time interval to form a second pulse width signal; superimposing the low voltage threshold and the fourth comparison waveform falling within the second time interval to form a second ramp signal; Comparing the second pulse width signal with the first triangular wave within the second time interval to adjust the first driving signal and the third driving signal; as well as The second ramp signal is compared with a second triangle wave in the second time interval to adjust the second driving signal and the fourth driving signal.

18. The pulse width modulation method according to claim 17, wherein: In the second time interval, if it is determined that the second pulse width signal is greater than the first triangular wave, the first driving signal is switched to a high voltage level and the third driving signal is switched to a low voltage level; Wherein, within the second time interval, if it is determined that the second ramp signal is smaller than the second triangle wave, the second driving signal is switched to the high voltage level and the fourth driving signal is switched to the low voltage level; Wherein, within the second time interval, if it is determined that the second pulse width signal is less than or equal to the first triangular wave, the first driving signal is switched to the low voltage level and the third driving signal is switched to the high voltage level; If it is determined that the second ramp signal is greater than or equal to the second triangle wave within the second time interval, the second driving signal is switched to the low voltage level and the fourth driving signal is switched to the high voltage level.

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