Intelligent terminal mainboard and intelligent terminal

Abstract

The present invention relates to the field of chips, and in particular to a smart terminal mainboard and a smart terminal. The smart terminal mainboard includes: a first memory chip, a second memory chip, an adapter board and a printed circuit board, wherein the first memory chip and the second memory chip have different packaging structures; the first memory chip is connected to the printed circuit board by direct patching; the upper part of the adapter board is connected to the second memory chip, and the lower part of the adapter board is connected to the printed circuit board; the chip pins of the second memory chip are connected to the vacant position after the packaging of the first memory chip through the adapter board. The smart terminal mainboard provided by an embodiment of the present invention connects the chip pins of the second memory chip to the vacant position after the packaging of the first memory chip by using an adapter board, thereby realizing the co-boarding of two memory chips with incompatible packaging structures.

Description

[Technical field]

[0001] The present invention relates to the field of chips, and in particular to an intelligent terminal mainboard and an intelligent terminal. [Background technology]

[0002] Mobile phones and other smart terminals such as tablet computers have the characteristics of high portability and comprehensive functions. Since smart terminals such as mobile phones and tablet computers have high requirements for the size of the device, electronic components such as memory sticks and central processing units are directly soldered on the motherboard and cannot be replaced. In the current mobile phone field, there are two mainstream memory chips of different specifications, namely embedded multi-layer package chips (Embedded Multi-Chip Package, eMCP) and multi-layer package chips based on UNIX file system (UFS-based Multi-chip Package, uMCP). The chip pin signal names and arrangement position diagrams (Ballmap) of these two mainstream memory chips on the package are not fully compatible, but there is a need for compatibility in the actual market or design. In the prior art, one method is to use two separate printed circuit boards (Printed Circuit Board, PCB) as the mobile phone motherboard. The advantage of this method is that both the EMCP signal and the UFS signal are complete signals. However, for mobile phone manufacturers, the cost of maintaining two sets of PCB boards is too high. Another method is to use resistor jumper stickers on the EMMC and UFS signals on the PCB board to achieve compatibility between the two memory chips. However, resistor jumper will affect signal impedance consistency, and PCB routing needs to go to the surface, increasing vias and routing length, which will lead to greater risks in signal integrity of EMMC and UFS, affecting the signal transmission quality of EMMC / UFS. Therefore, how to achieve compatibility between eMCP and uMCP memory chips in a low-cost way is an urgent problem to be solved. [Summary of the invention]

[0003] Based on the above problems, the present invention provides a smart terminal mainboard, namely a smart terminal, to solve the problem in the prior art that two memory chips with different packaging structures cannot share the same board.

[0004] In a first aspect, an embodiment of the present invention provides a smart terminal mainboard, including:

[0005] A first memory chip, a second memory chip, a transfer board, and a printed circuit board, wherein the first memory chip and the second memory chip have different packaging structures;

[0006] The first memory chip is connected to the printed circuit board by direct chip mounting;

[0007] The upper portion of the adapter board is connected to the second storage chip, and the lower portion of the adapter board is connected to the printed circuit board;

[0008] The chip pins of the second memory chip are connected to the vacant positions of the first memory chip after packaging through the adapter board.

[0009] In the embodiment of the present invention, the first memory chip is directly mounted on the printed circuit board, and the second memory chip is mounted on the printed circuit board through the adapter board, so that two memory chips with different packaging structures can be mounted on the same board. In addition, since the pins of the second memory chip in the embodiment of the present invention are connected to the vacant position after the first memory chip is packaged through the adapter board, the space of the printed circuit board is saved while the integrity of the UFS signal is guaranteed.

[0010] In a possible implementation, the chip pins of the second storage chip are connected to the free position in the packaging area of ​​the first storage chip through the adapter board, including:

[0011] The printed circuit board is provided with all chip pin interfaces of the first memory chip, and all chip pin interfaces of the first memory chip correspond one-to-one to each pin of the first memory chip;

[0012] The printed circuit board is also provided with a target chip pin interface of the second storage chip, the target chip pin interface of the second storage chip corresponds one-to-one with the target chip pin of the second chip, and the target chip pin is a chip pin in the second storage chip whose signal name is different from that of each pin of the first storage chip;

[0013] The first storage chip and the second storage chip share the chip pin interface with the same signal name.

[0014] In a possible implementation, the target chip pins include at least one or more combinations of the following chip pins:

[0015] Data line pins, clock pins, command and response multiplexing pins, reset pins, and chip working negative voltage analog signal pins.

[0016] In a possible implementation, the first storage chip is a multi-layer packaged chip based on a UNIX file system, and the second storage chip is an embedded multi-layer packaged chip; the printed circuit board is provided with all chip pin interfaces of the multi-layer packaged chip based on a UNIX file system, and a target chip pin interface of the embedded multi-layer packaged chip.

[0017] In a possible implementation, the first storage chip is an embedded multi-layer packaged chip, and the second storage chip is a multi-layer packaged chip based on a UNIX file system; the printed circuit board is provided with all chip pin interfaces of the embedded multi-layer packaged chip and target chip pin interfaces of the multi-layer packaged chip based on a UNIX file system.

[0018] In a second aspect, an embodiment of the present invention provides a smart terminal, wherein the smart terminal includes the smart terminal mainboard described in the first aspect.

Brief Description of the Drawings

[0019] In order to more clearly illustrate the technical solutions of the embodiments of the present invention, the drawings required for use in the embodiments are briefly introduced below. Obviously, the drawings described below are only some embodiments of this specification. For ordinary technicians in this field, other drawings can be obtained based on these drawings without creative work.

[0020] Figure 1 A schematic diagram of the structure of a smart terminal mainboard provided by an embodiment of the present invention;

[0021] Figure 2 A Ballmap schematic diagram of an eMCP provided in an embodiment of the present invention;

[0022] Figure 3 A Ballmap schematic diagram of a uMCP provided in an embodiment of the present invention;

[0023] Figure 4 A ballmap schematic diagram of a smart terminal mainboard provided by an embodiment of the present invention;

[0024] Figure 5 A schematic diagram of the structure of an intelligent terminal provided by an embodiment of the present invention. [Specific implementation method]

[0025] In order to better understand the technical solution of this specification, the embodiments of the present invention are described in detail below with reference to the accompanying drawings.

[0026] It should be clear that the described embodiments are only part of the embodiments of this specification, not all of the embodiments. Based on the embodiments in this specification, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of this specification.

[0027] It should be noted that when an element is referred to as being "fixed to" another element, it may be directly on the other element or there may be an intermediate element. When an element is considered to be "connected to" another element, it may be directly connected to the other element or there may be an intermediate element at the same time.

[0028] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as those commonly understood by those skilled in the art to which this application belongs. The terms used herein in the specification of this application are only for the purpose of describing specific embodiments and are not intended to limit this application. The term "and / or" used herein includes any and all combinations of one or more of the related listed items.

[0029] In order to solve the problem in the prior art that two storage chips with different packaging structures cannot be mounted on the same board, an embodiment of the present invention provides a smart terminal mainboard, which ensures the integrity of the UFS signal while realizing the storage chips with different packaging structures being mounted on the same board.

[0030] Figure 1 A schematic diagram of the structure of a smart terminal motherboard provided by an embodiment of the present invention is shown in FIG. Figure 1 As shown, the mainboard of the intelligent terminal includes a first memory chip, a second memory chip, an adapter board and a printed circuit board. The packaging structure of the first memory chip and the second memory chip is different. The first memory chip is connected to the printed circuit board by direct patching. The top of the adapter board is connected to the second memory chip, and the bottom of the adapter board is connected to the printed circuit board. That is, the second memory chip is patched on the adapter board, and the adapter board is patched on the printed circuit board.

[0031] Take the two current mainstream memory chips: embedded multi-chip package chip (Embedded Multi-ChipPackage, eMCP) and UNIX file system-based multi-chip package chip (UFS-based Multi-chipPackage, uMCP) as examples. Figure 2 A Ballmap schematic diagram of an eMCP provided in an embodiment of the present invention. Figure 3 A ballmap schematic diagram of a uMCP provided in an embodiment of the present invention. The ballmap diagram includes the signal names of each pin of the chip and the arrangement position diagram on the package. eMCP is a storage chip that packages EMMC flash and LPDDR together. uMCP is a storage chip that packages UFS and LPDDR together. Figure 2 and Figure 3As shown in the figure, the ballmaps of the circled parts in the ballmap diagram of eMCP and uMCP are different. Since the ballmaps of eMCP and uMCP are different, eMCP and uMCP are not fully compatible in terms of packaging. Optionally, the adapter board can be specifically implemented as a PCB adapter board.

[0032] In the smart terminal motherboard provided by the embodiment of the present invention, the chip pins of the second storage chip are connected to the vacant position of the first storage chip after packaging through the adapter board, thereby saving PCB motherboard space while ensuring the integrity of the UFS signals of the first storage chip and the second storage chip.

[0033] Since the original ballmaps of eMCP and uMCP cannot satisfy the intelligent terminal mainboard solution provided by the embodiment of the present invention, the embodiment of the present invention makes corresponding improvements to the ballmap. The printed circuit board is provided with all chip pin interfaces of the first storage chip, and all chip pin interfaces of the first storage chip correspond one-to-one to each pin of the first storage chip. The printed circuit board is also provided with a target chip pin interface of the second storage chip, and the target chip pin interface of the second storage chip corresponds one-to-one to the target chip pin of the second chip, and the target chip pin is a chip pin in the second storage chip whose signal name is different from each pin of the first storage chip. The first storage chip and the second storage chip share a chip pin interface with the same signal name.

[0034] In some embodiments, the target chip pins include at least one or more combinations of the following chip pins: data line pins, clock pins, command and response multiplexing pins, reset pins, and chip working negative voltage analog signal pins.

[0035] For example, when the first storage chip is a UNIX file system based multi-layer package chip (uMCP) and the second storage chip is an embedded multi-layer package chip (eMCP), the printed circuit board is provided with all chip pin interfaces of the UNIX file system based multi-layer package chip (uMCP) and the target chip pin interface of the embedded multi-layer package chip (eMCP). The corresponding ballmap is as follows: Figure 4 shown.

[0036] Figure 4In the ballmap diagram shown in , on the basis of the ballmap diagram of uMCP, some chip pins of eMCP (i.e., target chip pins) are added. For the remaining chip pins other than the target chip pins of eMCP, chip pins with the same name can be found in the ballmap of uMCP. Therefore, when eMCP is needed to work, a complete eMCP ballmap can be formed by using the target chip pins of eMCP and some chip pins of uMCP, so that eMCP can work. Since the target chip pins are set in the vacant position of the ballmap of uMCP, the vacant ball will not affect uMCP. Since the PCB adapter board does not connect the UFS signal of the uMCP below, but only connects the signal connector of EMMC to the ballmap of the eMCP above, the ball of uMCP will not affect the eMCP. Thus, on the basis of realizing the common board of eMCP and uMCP, the integrity of the UFS signals of eMCP and uMCP is guaranteed.

[0037] In some embodiments, the first storage chip may also be an embedded multi-layer package chip (eMCP), and the second storage chip may be a multi-layer package chip based on a UNIX file system (uMCP). The printed circuit board is then provided with all chip pin interfaces of the embedded multi-layer package chip and target chip pin interfaces of the multi-layer package chip based on a UNIX file system.

[0038] In the embodiment of the present invention, by making the first memory chip and the second memory chip share a chip pin interface with the same signal name, and connecting the chip pin interface in the second memory chip with different chip pin names from those in the first memory chip to the free position of the packaging area of ​​the first memory chip through a PCB adapter board, the space occupied in the PCB board is further saved, and the number of pins required when two memory chips with different packaging structures are on the same board is reduced, thereby reducing the hardware cost.

[0039] Corresponding to the above-mentioned intelligent terminal mainboard, an embodiment of the present invention provides an intelligent terminal. Figure 5 As shown, the intelligent terminal includes the intelligent terminal mainboard in the above embodiment.

[0040] The technical features of the above-described embodiments may be arbitrarily combined. To make the description concise, not all possible combinations of the technical features in the above-described embodiments are described. However, as long as there is no contradiction in the combination of these technical features, they should be considered to be within the scope of this specification.

[0041] The above-mentioned embodiments only express several implementation methods of the present invention, and the descriptions thereof are relatively specific and detailed, but they cannot be understood as limiting the scope of the invention patent. It should be pointed out that, for ordinary technicians in this field, several variations and improvements can be made without departing from the concept of the present invention, and these all belong to the protection scope of the present invention. Therefore, the protection scope of the patent of the present invention shall be subject to the attached claims.

Claims

1. A smart terminal mainboard, characterized in that: include: A first memory chip, a second memory chip, a transfer board, and a printed circuit board, wherein the first memory chip and the second memory chip have different packaging structures; The first memory chip is connected to the printed circuit board by direct chip mounting; The upper portion of the adapter board is connected to the second storage chip, and the lower portion of the adapter board is connected to the printed circuit board; The chip pins of the second memory chip are connected to the vacant positions of the first memory chip after packaging through the adapter board; The chip pins of the second memory chip are connected to the free positions in the packaging area of ​​the first memory chip through the adapter board, including: The printed circuit board is provided with all chip pin interfaces of the first memory chip, and all chip pin interfaces of the first memory chip correspond one-to-one to each pin of the first memory chip; The printed circuit board is also provided with a target chip pin interface of the second storage chip, the target chip pin interface of the second storage chip corresponds one-to-one with the target chip pin of the second storage chip, and the target chip pin is a chip pin in the second storage chip whose signal name is different from that of each pin of the first storage chip; The first storage chip and the second storage chip share the chip pin interface with the same signal name; The first storage chip is a multi-layer packaged chip based on the UNIX file system, and the second storage chip is an embedded multi-layer packaged chip; the printed circuit board is provided with all chip pin interfaces of the multi-layer packaged chip based on the UNIX file system, and the target chip pin interface of the embedded multi-layer packaged chip.

2. The intelligent terminal mainboard according to claim 1, characterized in that: The target chip pins include at least one or more combinations of the following chip pins: Data line pins, clock pins, command and response multiplexing pins, reset pins, and chip working negative voltage analog signal pins.

3. A smart terminal mainboard, characterized in that: include: A first memory chip, a second memory chip, a transfer board, and a printed circuit board, wherein the first memory chip and the second memory chip have different packaging structures; The first memory chip is connected to the printed circuit board by direct chip mounting; The upper portion of the adapter board is connected to the second storage chip, and the lower portion of the adapter board is connected to the printed circuit board; The chip pins of the second memory chip are connected to the vacant positions of the first memory chip after packaging through the adapter board; The chip pins of the second memory chip are connected to the free positions in the packaging area of ​​the first memory chip through the adapter board, including: The printed circuit board is provided with all chip pin interfaces of the first memory chip, and all chip pin interfaces of the first memory chip correspond one-to-one to each pin of the first memory chip; The printed circuit board is also provided with a target chip pin interface of the second storage chip, the target chip pin interface of the second storage chip corresponds one-to-one with the target chip pin of the second storage chip, and the target chip pin is a chip pin in the second storage chip whose signal name is different from that of each pin of the first storage chip; The first storage chip and the second storage chip share the chip pin interface with the same signal name; The first storage chip is an embedded multi-layer packaged chip, and the second storage chip is a multi-layer packaged chip based on a UNIX file system; the printed circuit board is provided with all chip pin interfaces of the embedded multi-layer packaged chip and target chip pin interfaces of the multi-layer packaged chip based on a UNIX file system.

4. An intelligent terminal, characterized in that: The smart terminal comprises the smart terminal mainboard according to any one of claims 1 to 3.

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