Using mask manufacturing models in correcting photolithography masks

Abstract

A lithography process is described by a design of a lithography mask and a description of a lithography configuration, which can include a lithography source, collection / illumination optics, projection optics, resist, and / or subsequent manufacturing steps. The actual lithography process uses a lithography mask manufactured from the mask design, which can differ from the nominal mask design. A mask manufacturing model models the process of manufacturing a lithography mask from a mask design. Typically, this is an e-beam process that includes e-beam exposure of a resist on a mask blank, processing the exposed resist to form a patterned resist, and etching the mask blank with the patterned resist. The mask manufacturing model is typically used together with other process models to estimate the result of the lithography process. Mask corrections are then applied to the mask design based on the simulation results.

Description

[0001] Cross-references to related applications

[0002] This application claims priority to U.S. Provisional Patent Application No. 62 / 930134, filed November 4, 2019, entitled “Simulated Lithography Mask in OPC Correction”, the subject matter of which is incorporated herein by reference in its entirety. Technical Field

[0003] This disclosure relates to photolithography (also known as photolithography technique), and more specifically, to modeling mask fabrication in order to improve the design of photolithographic masks. Background Technology

[0004] One step in semiconductor wafer manufacturing involves photolithography. In a typical photolithography process, a source generates light, which is collected and guided by a collecting / illuminating optics to illuminate a photomask. A projection optics relays the pattern generated by the illuminated mask onto the wafer, exposing the resist on the wafer according to the illuminated pattern. The patterned resist is then used in the process of fabricating structures on the wafer.

[0005] Various techniques aim to improve the lithography process, including the design of lithographic masks. In many of these techniques, the lithographic mask design is used as input to a process model, which then predicts some process outcome. This outcome can be used to modify the lithographic mask design. In many cases, the process model can be regressed against data from actual manufacturing experiments. Different lithographic mask designs containing test patterns are used throughout the lithography process. The resulting structures are measured and used to calibrate the process model.

[0006] Current process models typically do not directly address effects that may occur during mask fabrication itself. Instead, the lithographic mask design is used as input to the process model, and any effects of mask fabrication are lumped together with other process effects and may be considered through regression against empirical data. However, as lithography moves toward shorter wavelength ranges (e.g., extreme ultraviolet (EUV) at approximately 13.3 nm to 13.7 nm) and smaller geometries (e.g., 10 nm, 7 nm, and smaller technology nodes with minimum feature sizes of approximately 20 nm, 14 nm, and smaller), the sensitivity to these mask fabrication effects increases, and conventional lumped approaches may result in suboptimal mask designs. Summary of the Invention

[0007] Some aspects relate to a method for improving photolithography mask design. The photolithography process is described through the design and configuration of the photolithography mask, which may include a photolithography source, collection / irradiation optics, projection optics, resist, and / or subsequent fabrication steps. The actual photolithography process uses a photolithography mask fabricated from a mask design, which may differ from the nominal mask design. A mask fabrication model models the process of fabricating a photolithography mask from the mask design. Typically, this is an electron beam (e-beam) process that includes electron beam exposure of the resist on the mask preform, processing the exposed resist to form a patterned resist, and etching the material on the mask preform according to the patterned resist. The mask fabrication model is often used in conjunction with other process models to estimate the results of the photolithography process, such as the spatial image of the irradiated wafer, the printed pattern on the wafer, or the critical dimensions of the printed pattern. Mask corrections are then applied to the mask design based on the estimation results. This process can be repeated for multiple iterations.

[0008] Other aspects include components, equipment, systems, improvements, methods, processes, applications, computer-readable media, and other technologies related to any of the foregoing. Attached Figure Description

[0009] This disclosure will be more fully understood from the detailed description given below and from the accompanying drawings illustrating embodiments of this disclosure. The drawings are provided to give knowledge and understanding of embodiments of this disclosure and are not intended to limit the scope of this disclosure to these particular embodiments. Furthermore, the drawings are not necessarily drawn to scale.

[0010] Figure 1 A flowchart illustrating an improved design for a photomask according to some embodiments of the present disclosure is provided.

[0011] Figure 2A A mask manufacturing process suitable for use with embodiments of this disclosure is described.

[0012] Figure 2B An EUV lithography process suitable for use with embodiments of this disclosure is described.

[0013] According to embodiments of this disclosure, Figure 3A The drawn mask design is described. Figure 3B The corrected mask design is described, and Figure 3C The printed mask pattern is depicted.

[0014] Figure 3D Depicting Figure 3B Corrected mask design Figure 3C A comparison of printed mask patterns.

[0015] Figure 4 A simulation of the photolithography process, including the mask manufacturing process, is depicted.

[0016] Figure 5 A flowchart illustrating an improved design for a photomask according to some embodiments of the present disclosure is provided.

[0017] Figure 6 A flowchart illustrating an improved design for a photomask according to some embodiments of the present disclosure is provided, including mask error correction.

[0018] Figure 7 Flowcharts depict various processes used during the design and manufacture of integrated circuits according to some embodiments of this disclosure.

[0019] Figure 8 An abstract diagram of an example computer system in which embodiments of the present disclosure may operate is depicted. Detailed Implementation

[0020] This disclosure relates to using mask fabrication models to correct photolithography masks. As photolithography moves towards shorter wavelength ranges (e.g., EUV from approximately 13.3 nm to 13.7 nm) and smaller geometries (e.g., 10 nm, 7 nm, and smaller technology nodes with feature sizes of 20 nm, 14 nm, and smaller), the process of designing and simulating the use of photolithography masks in integrated circuit manufacturing becomes more complex. Effects that are absent or negligible at longer wavelengths and larger geometries can no longer be ignored. For example, for the same exposure energy, higher photon energy results in a lower photon count. This can lead to previously negligible or non-existent random defect mechanisms.

[0021] The design of a lithography mask is a crucial part of the entire design process. Typically, mask design utilizes mask correction techniques. First, an "ideal" or "drawn" mask design is generated. However, the drawn mask design does not account for subwavelength, scattering, and other process effects present at advanced technology nodes. Therefore, the drawn mask design is corrected to create a "corrected" mask design. When the "corrected" mask design is used in the actual lithography process, it will produce results close to the drawn design. Mask correction is commonly applied to the entire chip design. Various process models can be used as part of the mask correction process. However, these process models typically do not include a process model for mask fabrication, and mask fabrication processes can introduce non-negligible effects at advanced technology nodes.

[0022] In various embodiments of this disclosure, a mask manufacturing model is incorporated into the mask correction process. Using a separate mask manufacturing model, rather than aggregating mask manufacturing effects into a more general process model, can increase modeling accuracy and improve overall results. In some cases, a separate mask manufacturing model shifts mask variations from being treated as stochastic effects to being treated as systemic effects that can be corrected. One possible effect of this change includes more accurate correction that reduces the number of manufacturing defects (such as broken wires and short circuits) and line edge roughness (LER). This improves wafer yield and reduces stochastic variations, such as changes in critical dimensions (CD), resulting in more uniform device performance.

[0023] Figure 1 A flowchart illustrating an improvement design for a photomask according to some embodiments of this disclosure is provided. This example process is iterative, applying mask correction 150 to the current design 110 of the photomask to improve the mask design until a final design 190 is reached. The iteration begins with the current design 110 of the photomask. The current mask design is used to simulate 130 the photolithography process of interest. This simulation is based on a model for the photolithography process, which includes a mask fabrication model 135 and typically also includes other models for other parts of the photolithography process. Modeling 130 of the photolithography process produces results 139 for the current mask design, such as a spatial image of the illuminated wafer, the printed pattern on the wafer, or the critical dimension (CD) of the printed pattern. The results may also take into account different operating conditions, such as CD under a series of exposure and defocusing conditions. The results may also include calculated quantities or derived indices, such as the normalized image logarithmic slope (NILS = wd(lnI) / dx, where w is the normalized linewidth and d(lnI) / dx is the derivative of the logarithm of the spatial image intensity) and the mask error enhancement factor (MEEF = d(CD) / dx). resist ) / d(CD mask ), of which CD resist It is the CD structure in the resist, and CD mask (This is the CD of the corresponding pattern on the mask). A decision is made at 140 whether to continue with further iterations. If yes, mask correction 150 is applied to the current mask design to further improve the design, and additional iterations are performed. If no, the final mask design 190 is determined. This process can also be run non-iteratively.

[0024] Please refer to Figures 2 and 3 for a more detailed explanation. Figure 1 The process. Figure 2A The process for manufacturing photolithography masks from mask design is described, and Figure 2B The extreme ultraviolet lithography process using a photomask is depicted. Figure 2AIn this design, mask design 202 is used to control the electron beam (e-beam) writer 204. Mask preform 208 is coated with an electron beam resist. To create an EUV lithography mask, the mask preform is typically a substrate coated with alternating Mo and Si layers forming a Bragg reflector, followed by an absorber. Examples of absorbers are compounds of Ta, such as some form of TaBON. A capping layer, such as Ru, may also be present.

[0025] Electron beam writer 204 controls electron beam 205 to expose the resist according to the pattern of mask design 202. The resist is developed, thereby creating a resist pattern on mask blank 208. The material of the blank 208 below is then processed. For example, for an EUV mask, the blank below may contain a multilayer reflector covered by an absorbent layer. Where the resist has been removed, the absorbent material is exposed and can be etched away to expose the reflector below, thereby creating a reflective EUV lithography mask.

[0026] The resulting mask is then used as Figure 2B The photolithography configuration shown includes a photomask 230. In this system, a source 210 generates EUV light, which is collected and directed by a collecting / illuminating optics 220 to illuminate the mask 230. A projection optics 240 relays the pattern generated by the illuminated mask onto a wafer 250, exposing a photoresist on the wafer according to the illumination pattern. The exposed photoresist is then developed, creating a patterned photoresist on the wafer. This is used to fabricate structures on a wafer, for example, through deposition, doping, etching, or other processes.

[0027] exist Figure 2B In this lithography system, the light is in the EUV wavelength range, approximately 13.5 nm or in the range of 13.3 nm to 13.7 nm. At these wavelengths, components are typically reflective rather than transmissive. Mask 230 is a reflective mask, and optics 220 and 240 are also reflective and off-axis. This is just one example. Other types of lithography systems can also be used, including at other wavelengths, using transmissive masks and / or optics, and using positive or negative resists.

[0028] Notice, Figure 2A and Figure 2B There are two different manufacturing processes involved. Figure 2A The fabrication of the photolithography mask is shown. The photolithography mask is then used as... Figure 2B It is a component in the manufacturing process.

[0029] Return to Figure 1 , Figures 3A to 3D Depicting Figure 1 Different masks during the process. Figure 1The process typically begins with a “drawn” design of a photomask, which represents the ideal shape of the resulting structure to be fabricated on the wafer. Figure 3A The drawn mask design is depicted. The drawn design is usually a Manhattan geometry (i.e., the edges are only horizontal and vertical) or sometimes additionally has edges with 45 (and 135) degree angles. Figure 3B The corrected mask design is depicted—that is, the mask design after mask correction has been applied. The corrected mask design still has Manhattan geometry, but the edges have more complex shapes. The various parts of the shape are thicker or thinner than in the drawn design to account for diffraction, scattering, and other effects when the lithography mask is projected onto the wafer.

[0030] Figure 3A and Figure 3B The mask designs of both can be input into Figure 2A The mask writer 204 is used to manufacture the actual photolithography mask. However, the mask manufacturing process also has several effects that cause the pattern on the actual mask ("printed" mask) to differ from the mask design input to the mask writer. Figure 3C Depicting by Figure 3B The mask design produces the printed mask. Figure 3D Comparison Figure 3B Mask design Figure 3C The resulting printed mask pattern. The sharp edges of the mask design have been smoothed in the printed pattern by the mask manufacturing process. Figure 1 The mask manufacturing model 135 in the paper considers the effects introduced by the mask manufacturing process.

[0031] Figure 4 Depicting Figure 2A and Figure 2B The simulation shown includes the mask manufacturing process. Figure 2A The mask manufacturing process is represented by model 405. The input is the mask design 402, such as in... Figure 3B In, and the output is the corresponding printed mask pattern 432, such as in Figure 3CIn this process, if an electron beam process is used to fabricate a photomask, the mask fabrication model 405 can take into account the electron beam exposure of the resist on the mask preform, the treatment of the exposed resist to form a patterned resist, and / or the etching of layers on the mask preform using the patterned resist. Effects encountered during mask fabrication can include backscattered electrons, long-range etching effects, etching bias, and micro-loads. These effects can be taken into account by simulating the underlying process or by modeling the effects in other ways, such as randomly based on empirical data. In one approach, the mask fabrication model is constructed from a combination of Gaussian kernels. This is a reasonable approximation of the electron beam but has little impact on the etching process. The Gaussian parameters (radius, sigma) for each kernel are regressed against the measured mask data so that the model produces a reasonable fit to the empirical data.

[0032] Figure 2B The simulation of the photolithography process is shown in the right column of the box. Irradiation model 422 pairs Figure 2B The source 210 (including the source mask) and the illumination optics 220 are modeled. These are used to predict the light pattern 425 of the illumination mask. Model 442 takes into account the photolithography mask 230 ( Figure 4 The effects of the mask 432 and projection optics 240 are used to predict the exposure of the resist 445. This is sometimes referred to as the spatial image 445. The resist model 452 can include effects such as the exposure of the resist from the spatial image, chemical development, and subsequent removal (whether by etching or other processes). The removal of the resist leaves a layer of patterned resist 454 on the wafer. The wafer fab model 456 then models subsequent processes (such as etching, deposition, doping, implantation, etc.) to obtain the device structure 458 on the wafer.

[0033] For convenience, Figure 4 Separate boxes are shown to correspond to physical components or processes, but the model does not need to be implemented in this way. For example, the illumination model 422 and the resist model 452 are depicted as two separate models separated by the mask optics model 442. However, practical implementations may or may not use separate models 422, 452. In some cases, the source model 422, the projection optics from element 442, and the resist exposure from element 452 can be combined into a single model that predicts the patterned resist or equivalent spatial image obtained from the printed mask pattern 432. This single model includes effects from the source, optics, and resist.

[0034] In some cases, the overall model is a compact model used for full-chip evaluation. The compact model is designed to process the mask design required for the entire chip in a fast manner. This may require up to 10... 18More simulations can be used to perform full-chip calibration on devices such as microprocessors. The model typically simulates the photolithography process, including mask optics, optics, and photoresist treatment. The model may also include the etching process.

[0035] The model can also include a stochastic model. For example, in a first-principles approach, components of the photolithography process, such as photon distribution, secondary electron distribution, photoacid generator (PAG) distribution, quencher distribution, and inhibitor distribution, can be randomized. These are various pseudo-random numbers. This can lead to defects due to issues such as too many photons or too little acid in localized regions.

[0036] Figure 4 The models shown can be based on empirical data. For example, a mask fabrication model can be a parametric model, where parameters are determined based on regression against empirical data. The same approach can be applied to any other model. Compact models of the photolithography process are typically based on empirical data. Measurement data are collected for different mask designs. These can be mask designs with or without corrections. The resulting patterns fabricated on the wafer are measured. These are typically scanning electron microscopy (CDSEM) measurements of the critical dimensions of the photoresist and / or etched structures. Other measurements, such as atomic force microscopy (AFM), can also be used.

[0037] Separate models can regress on different empirical data, which differs from traditional lumped modeling methods, where all effects are considered in a single model and regression is performed on a common set of empirical data. For example, a mask manufacturing model would regress on empirical data collected by mask manufacturers, while other lithography process models would regress on empirical data collected by wafer manufacturers (foundries).

[0038] One measure of the quality of patterned resist 454 is the critical dimension (CD). CD is the dimension of a significant feature in the patterned resist. Typically, CD is the minimum linewidth or space width printed in the resist. Therefore, CD is a measure of the resolution of the resist and the photolithography process. (See again) Figure 1 , Figure 1 The simulation results can include CD. The lithography simulation 130 can use... Figure 4 Any model shown can be used to predict CD for a given lithography configuration and mask design.

[0039] exist Figure 1 Different types of mask correction can also be used 150. Mask correction includes optical proximity correction, subresolution assist, phase-shift masks, reverse lithography, and other types of resolution enhancement techniques. In optical proximity correction (OPC), the geometry in the mask design is disturbed based on the predicted results. Figure 3BThis is an example of a mask design using OPC correction. In subresolution auxiliary features, subwavelength features are added to or removed from the mask design to introduce beneficial diffraction and scattering. In phase-shift masks, different mask shapes introduce different amounts of phase shift to introduce beneficial interference in the resulting illumination pattern.

[0040] Mask correction can be achieved through a "correction set," which is a set of computer instructions that acts as a script or program to perform pattern manipulation on the mask design to achieve mask correction.

[0041] The iteration can end with different rules

[140] . One rule is based on the mask's performance. The iteration ends once the simulation results reach an acceptable level or the improvement drops below a certain rate. Alternatively, the process can run a fixed number of iterations.

[0042] Figure 5 A flowchart illustrating an improved design for a photomask according to some embodiments of the present disclosure is provided. Figure 5 In this process, the mask manufacturing model 535 is used to explicitly calculate the printed mask pattern 536 from the current mask design 510. The printed mask pattern 536 is then used as the mask pattern for the remaining process models 537, thereby generating simulation results 539. For example, the printed mask pattern 536, instead of the mask design 510, can be used as input to an optical device model to estimate the spatial image and the corresponding CD. Note that if the mask design 510 has a linear geometry, the printed mask pattern 536 will typically include curved shapes because sharp corners are rounded. The optical device model 537 will have to accommodate the curved shape. Mask correction 550 is applied iteratively 540 until the final mask design 590 is reached.

[0043] Furthermore, the photolithographic mask and the spatial image can be at different magnifications in the physical system. For example, when imaged onto a wafer, projection optics can reduce the photolithographic mask by a factor of 4:1. In one approach, the mask design 510 is represented in a design database at wafer scale. To model the mask manufacturing process, the mask design 510 is magnified by 4 times, a mask manufacturing model 535 is applied, and the resulting printed mask pattern 536 is then reduced by 4 times to return to wafer scale.

[0044] Figure 6 A flowchart illustrating an improvement in photolithographic mask design according to some embodiments of the present disclosure is provided, including mask error correction. Mask error correction 636 is used as... Figure 2AThe mask manufacturing process shown is applied as part of the process. Instead of using the mask design 510 to drive the electron beam writer 204, the design data can be corrected first and then sent to the electron beam writer. This mask error correction 636 can also be used in... Figure 6 The simulation shown is considered. Note that mask error correction 636 and mask correction 550 are different. Mask error correction 636 is a correction for the mask data used by the electron beam writer to take into account... Figure 2A The effects during the mask manufacturing process. Mask correction 550 is a correction to the mask design to take into account... Figure 2B Effects during the photolithography process.

[0045] Table 1 below shows the results comparing OPC with a separate mask manufacturing model (“M+OPC” correction) with conventional OPC without a separate mask manufacturing model (“OPC” correction). Four different cases #1-4 are compared. Avg CD and St Dev CD are the mean and standard deviation of the measured CD. Count is the number of features measured for that case, and failure is the number of failures within that count. The failure rate is expressed as 1 / X in the last column. The results show that the M+OPC method reduces the defect rate by approximately 50% and the line edge roughness (St Dev of CD) by approximately 20%.

[0046] Table 1: Comparison of OPC results with and without mask manufacturing models

[0047] Case Correction Avg CD St Dev CD count Fault Ratio (1 / X) 1 M&OPC 14.3 2.69 1946 6 321 1 OPC 13.7 3.1 4750 22 216 2 M&OPC 15.0 2.35 1964 2 982 2 OPC 14.8 2.66 4870 10 487 3 M&OPC 14.41 2.66 9838 26 378 3 OPC 13.6 3.93 4690 52 90 4 M&OPC 15.2 2.39 9896 8 1237 4 OPC 14.76 2.71 4868 9 541

[0048] Figure 7 The illustration depicts an example set of processes 700 used during the design, verification, and manufacturing of articles such as integrated circuits to transform and verify design data and instructions representing integrated circuits. Each of these processes can be structured and enabled as multiple modules or operations. The term 'EDA' stands for 'Electronic Design Automation'. These processes begin with creating a product concept 710 using information provided by the designer, which is then transformed to produce an article using a set of EDA processes 712. Upon completion of the design, it is tape-out 734, which is when the artwork (e.g., geometric pattern) of the integrated circuit is sent to a manufacturing plant to create a mask set, which is then used to manufacture the integrated circuit. After tape-out, semiconductor dies are manufactured 736, and packaging and assembly processes 738 are performed to produce the finished integrated circuit 740.

[0049] The specifications of circuits or electronic structures can range from low-level transistor material placement to high-level description languages. Using hardware description languages ​​('HDL') such as VHDL, Verilog, SystemVerilog, SystemC, MyHDL, or OpenVera, circuits and systems can be designed using high-level abstractions. HDL descriptions can be translated into logic-level register-transfer level ('RTL') descriptions, gate-level descriptions, placement-level descriptions, or mask-level descriptions. Each lower level of abstraction (i.e., a less abstract description) adds more useful details to the design description, such as more details about the modules included in that description. Lower levels of abstraction (i.e., less abstract descriptions) can be computer-generated, exported from design libraries, or created by another design automation process. An example of a specification language used to specify lower levels of abstraction for more detailed descriptions is SPICE, used for detailed descriptions of circuits with many analog components. Descriptions at each level of abstraction are enabled for use by the corresponding tools at that layer (e.g., formal verification tools). The design process can use... Figure 7 The sequence described herein. The described process is enabled by an EDA product (or tool).

[0050] During system design phase 714, the functionality of the integrated circuit to be manufactured is specified. The design can be optimized for desired characteristics such as power consumption, performance, area (physical and / or lines of code), and cost reduction. At this stage, the design can be divided into different types of modules or components.

[0051] During logic design and functional verification 717, modules or components in a circuit are specified in one or more description languages, and the functional accuracy of that specification is checked. For example, components of a circuit can be verified to generate outputs that match the specification requirements of the designed circuit or system. Functional verification can use simulators and other programs, such as test bench generators, static HDL checkers, and formal verifiers. In some embodiments, a special system of components referred to as a 'simulator' or 'prototype system' is used to accelerate functional verification.

[0052] During synthesis and design 718 for testing, HDL code is converted into a netlist. In some embodiments, the netlist may be a graphical structure, where the edges of the graphical structure represent components of the circuit, and the nodes of the graphical structure represent how the components are interconnected. Both HDL code and netlist are fabricated layered products that can be used by EDA products to verify whether the integrated circuit performs according to a specified design when it is manufactured. The netlist can be optimized for a target semiconductor manufacturing technology. Additionally, the finished integrated circuit can be tested to verify that the integrated circuit meets the specifications.

[0053] During netlist verification (720), the netlist is checked to ensure it meets timing constraints and corresponds to the HDL code. During design planning (722), the overall planar diagram of the integrated circuit is constructed and analyzed for timing and top-level routing.

[0054] During layout or physical implementation 724, physical placement (placement of circuit components such as transistors or capacitors) and wiring (connection of circuit components through multiple conductors) are performed, and cells can be selected from a library to enable specific logic functions. As used herein, the term 'cell' can specify a collection of transistors, other components, and interconnects that provides Boolean logic functions (e.g., AND, OR, NOT, XOR) or storage functions (e.g., flip-flops or latches). As used herein, a circuit 'block' can refer to two or more cells. Both cells and circuit blocks can be referred to as modules or components and can be enabled for both physical structure and simulation. Parameters such as size are specified for the selected cells (based on 'standard cells') and make them accessible in a database for use in EDA products.

[0055] During Analysis and Extraction 726, circuit functionality is verified at the layout level, which allows for improvements to the layout design. During Physical Verification 728, the layout design is checked to ensure that manufacturing constraints (such as DRC constraints, electrical constraints, and lithographic constraints) are correct and that the circuit functionality matches the HDL design specifications. During Resolution Enhancement 730, the layout geometry is transformed to improve how the circuit design is manufactured.

[0056] During the tape-out process, data is created for the production of a photomask (if appropriate, after the application of lithographic enhancement). During mask data preparation 732, the 'tape-out' data is used to generate a photomask for the production of the finished integrated circuit.

[0057] Computer systems (such as, Figure 8 The storage subsystem of a computer system (800) can be used to store programs or data structures used by some or all of the EDA products described herein, and by products used for developing libraries as well as products used for physical and logical designs that use the libraries.

[0058] Figure 8An example machine of computer system 800 is illustrated, in which a set of instructions can be executed to cause the machine to perform any or one of the methods discussed herein. In alternative embodiments, the machine may be connected (e.g., networked) to other machines in a LAN, intranet, extranet, and / or the Internet. The machine may operate as a server or client machine in a client-server network environment, as a peer-to-peer (or distributed) network environment, or as a server or client computer in a cloud computing infrastructure or environment.

[0059] A machine can be a personal computer (PC), tablet computer, set-top box (STB), personal digital assistant (PDA), cellular phone, network device, server, network router, switch, or bridge, or any machine capable of executing a set of instructions (sequential instructions or other instructions) specifying the actions to be performed by that machine. Furthermore, while a single machine is illustrated, the term "machine" should also be understood to include any collection of machines that individually or collectively execute a set (or more) of instructions to perform any one or more methods discussed herein.

[0060] Example computer system 800 includes processing device 802, main memory 804 (e.g., read-only memory (ROM), flash memory, dynamic random access memory (DRAM) such as synchronous DRAM (SDRAM)), static memory 806 (e.g., flash memory, static random access memory (SRAM) etc.) and data storage device 818, which communicate with each other via bus 830.

[0061] Processing device 802 represents one or more processors, such as microprocessors, central processing units, etc. More specifically, processing device may be a Complex Instruction Set Computing (CISC) microprocessor, a Reduced Instruction Set Computing (RISC) microprocessor, a Very Long Instruction Word (VLIW) microprocessor, or a processor that implements other instruction sets, or a processor that implements combinations of instruction sets. Processing device 802 may also be one or more special-purpose processing devices, such as application-specific integrated circuits (ASICs), field-programmable gate arrays (FPGAs), digital signal processors (DSPs), network processors, etc. Processing device 802 may be configured to execute instructions 826 to perform the operations and steps described herein.

[0062] The computer system 800 may also include a network interface device 808 for communication via a network 820. The computer system 800 may also include a video display unit 810 (e.g., a liquid crystal display (LCD) or a cathode ray tube (CRT)), an alphanumeric input device 812 (e.g., a keyboard), a cursor control device 814 (e.g., a mouse), a graphics processing unit 822, a signal generation device 816 (e.g., a speaker), a graphics processing unit 822, a video processing unit 828, and an audio processing unit 832.

[0063] Data storage device 818 may include machine-readable storage medium 824 (also referred to as non-transitory computer-readable medium) storing one or more instruction sets 826 or software embodying any one or more methods or functions described or functionally herein. During the execution of instruction 826 by computer system 800, instruction 826 may also reside wholly or at least partially in main memory 804 and / or in processing device 802, which also constitute machine-readable storage media.

[0064] In some embodiments, instruction 826 includes instructions for implementing functions corresponding to this disclosure. Although machine-readable storage medium 824 is shown as a single medium in the example embodiment, the term "machine-readable storage medium" should be considered to include a single medium or multiple media (e.g., a centralized or distributed database, and / or associated caches and servers) for storing one or more sets of instructions. The term "machine-readable storage medium" should also be considered to include any medium capable of storing or encoding a set of instructions for execution by a machine and to cause the machine and processing device 802 to perform any one or more of the methods of this disclosure. Therefore, the term "machine-readable storage medium" should be considered to include, but is not limited to, solid-state memory, optical media, and magnetic media.

[0065] Some parts of the foregoing detailed description have been presented based on the algorithms and symbolic representations of operations on data bits within computer memory. These algorithmic descriptions and representations are the methods used by those skilled in the art of data processing to most effectively communicate the essence of their work to others skilled in the art. An algorithm can be a sequence of operations that lead to a desired result. These operations are operations that require physical manipulation of physical quantities. Such quantities can take the form of electrical or magnetic signals that can be stored, combined, compared, and otherwise manipulated. Such signals can be referred to as bits, values, elements, symbols, characters, items, numbers, etc.

[0066] However, it should be remembered that all these and similar terms should be associated with appropriate physical quantities and are merely convenient labels applied to those quantities. Unless otherwise expressly indicated in this disclosure, it should be understood that throughout this description, certain terms refer to the actions and processes of a computer system or similar electronic computing device that manipulate and convert data represented as physical (electronic) quantities within the registers of the computer system into other data, which are similarly represented as physical quantities within the computer system's memory or registers or other such information storage devices.

[0067] This disclosure also relates to means for performing the operations described herein. Such means may be specifically configured for the intended purpose, or it may comprise a computer selectively activated or reconfigured by a computer program stored in the computer. This computer program may be stored in a computer-readable storage medium, such as, but not limited to, any type of disk (including floppy disks, optical disks, CD-ROMs, and magneto-optical disks), read-only memory (ROM), random access memory (RAM), EPROM, EEPROM, magnetic cards, or optical cards, or any type of medium suitable for storing electronic instructions, each coupled to a computer system bus.

[0068] The algorithm and display presented herein are not inherently related to any particular computer or other device. Various other systems may be used with the program based on the teachings herein, or it may be proven easy to construct more specialized devices to execute the method. Furthermore, this disclosure is described without reference to any particular programming language. It should be understood that the teachings of this disclosure as described herein can be implemented using various programming languages.

[0069] This disclosure can be provided as a computer program product or software, which may include a machine-readable medium having instructions stored thereon, which can be used to program a computer system (or other electronic device) to perform processes according to this disclosure. Machine-readable media include any mechanism for storing information in a machine-readable (e.g., computer-readable) form. For example, machine-readable (e.g., computer-readable) media include machine-readable (e.g., computer-readable) storage media, such as read-only memory (“ROM”), random access memory (“RAM”), disk storage media, optical storage media, flash memory devices, etc.

[0070] In the foregoing disclosure, embodiments of the present disclosure have been described with reference to specific exemplary embodiments. It will be apparent that various modifications may be made thereto without departing from the broader spirit and scope of the present disclosure as set forth in the appended claims. Where elements are referred to in the singular in this disclosure, more than one element may be depicted in the drawings, and the same elements may be labeled with the same reference numerals. Therefore, this disclosure and the drawings should be considered illustrative rather than restrictive.

Claims

1. A method for correcting a photomask, comprising: accessing a photomask design used in conjunction with a mask manufacturing process and a lithography process, wherein the mask manufacturing process manufactures a photomask from the photomask design, and the lithography process uses the photomask to manufacture a structure on a wafer; estimating, by a processor, a result of the lithography process, wherein the result includes one or more of a aerial image and a printed wafer pattern and metrics for one or more of the aerial image and the printed wafer pattern, and estimating the result includes: estimating a printed mask pattern for the photomask manufactured from the photomask design using a mask manufacturing model for the mask manufacturing process, and estimating the result of the lithography process using the printed mask pattern estimated by the mask manufacturing model as input to one or more additional process models of the lithography process; and applying a mask correction to the photomask design based on the estimated result.

2. The method of claim 1, wherein the photomask is manufactured using an electron beam process; and the mask manufacturing model accounts for electron beam exposure of a resist on a mask blank, processing the exposed resist to form a patterned resist, and etching the mask blank with the patterned resist.

3. The method of claim 1, wherein the photomask is manufactured using an electron beam process; and the mask manufacturing model accounts for at least one of backscattered electrons, long range etching effects, etch bias, and microloading in the electron beam process used to manufacture the photomask.

4. The method of claim 1, wherein the photomask design consists of straight shapes, and the printed mask pattern includes curved shapes.

5. The method of claim 1, wherein the mask manufacturing model is based on a regression against empirical data, and at least one of the additional process models is based on a separate regression against different empirical data.

6. The method of claim 1, wherein the mask manufacturing model is applied at one scale to estimate the printed mask pattern, and the estimated printed mask pattern is scaled down to a smaller scale to use as input to the one or more additional process models.

7. The method of claim 1, wherein the method is repeated for multiple iterations, and the mask manufacturing model is applied at each iteration.

8. The method of claim 1, wherein the mask manufacturing model is based on a Gaussian kernel.

9. The method of claim 1, wherein estimating the result of the lithography process is further based on mask error correction of the photomask design caused by the mask manufacturing.

10. The method of claim 1, wherein the mask correction includes at least one of optical proximity correction, sub-resolution assist features, phase shift masks, and inverse lithography techniques.

11. A system for correcting a photomask, comprising: a memory storing instructions and a lithography mask design for use in conjunction with a mask manufacturing process and a lithography process, wherein the mask manufacturing process manufactures a lithography mask from the lithography mask design, and the lithography process uses the lithography mask to manufacture structures on a wafer; and a processor coupled with the memory and executing the instructions, which when executed cause the processor to: estimate a result of the lithography process, wherein the result includes at least one or more of aerial images and printed wafer patterns and metrics for one or more of the aerial images and the printed wafer patterns, and estimating the result includes: estimating a printed mask pattern for the lithography mask manufactured from the lithography mask design using a mask manufacturing model for the mask manufacturing process, and estimating the result of the lithography process using the printed mask pattern estimated by the mask manufacturing model as input to one or more additional process models of the lithography process; and applying a mask correction to the lithography mask design based on the estimated result.

12. The system of claim 11, wherein the lithography process operates at an extreme ultraviolet (EUV) wavelength range and a technology node having a feature size of about 20 nm or less.

13. The system of claim 11, wherein the lithography mask design is for an entire integrated circuit die.

14. The system of claim 11, wherein the mask manufacturing model is based on a regression against empirical data, and at least one of the additional process models is based on a separate regression against different empirical data.

15. The system of claim 11, wherein the mask correction includes at least one of optical proximity correction, sub-resolution assist features, phase shift masks, and inverse lithography techniques.

16. A non-transitory computer readable medium comprising stored instructions that, when executed by a processor, cause the processor to: access a lithography mask design for use in conjunction with a mask manufacturing process and a lithography process, wherein the mask manufacturing process manufactures a lithography mask from the lithography mask design, and the lithography process uses the lithography mask to manufacture structures on a wafer; estimate a result of the lithography process, wherein the result includes at least one or more of aerial images and printed wafer patterns and metrics for one or more of the aerial images and the printed wafer patterns, and estimating the result includes: estimate a printed mask pattern for the lithography mask manufactured from the lithography mask design using a mask manufacturing model for the mask manufacturing process, and estimate the result of the lithography process using the printed mask pattern estimated by the mask manufacturing model as input to one or more additional process models of the lithography process; and apply a mask correction to the lithography mask design based on the estimated result.

17. The non-transitory computer readable medium of claim 16, wherein the mask manufacturing model is applied at one scale to estimate the printed mask pattern, and the estimated printed mask pattern is scaled down to a smaller scale to be used as input to the one or more additional process models.

18. The non-transitory computer readable medium of claim 16, wherein the mask manufacturing model is based on a Gaussian kernel.

Images