A semiconductor device and its manufacturing method

Abstract

This application discloses a semiconductor device and a method for manufacturing the same. The semiconductor device includes a substrate (100) and an inductor (200). A shielding layer (300) can be formed between the substrate (100) and the inductor (200). The shielding layer (300) is used to shield the electrical coupling between the substrate (100) and the inductor (200), thereby reducing the coupling current in the substrate (100), reducing the energy loss in the inductor (200), improving the quality factor of the inductor (200), and improving the performance of the semiconductor device.

Description

Technical Field

[0001] This application relates to the field of semiconductor devices, and more particularly to a semiconductor device and a method for manufacturing the same. Background Technology

[0002] With the rapid progress and development of the semiconductor industry, integrating various components, such as resistors, capacitors and inductors, into semiconductor products has become an inevitable trend.

[0003] Taking radio frequency (RF) integrated circuits as an example, in order to integrate the matching components in traditional RF circuits onto a chip, inductors need to be fabricated on the chip, i.e., on-chip integrated inductors. Inductors are key components in RF integrated circuits and are among the most difficult to design and control; their performance parameters directly affect the performance of the RF integrated circuit. On-chip integrated inductors are characterized by low cost, ease of integration, low noise, and low power consumption. More importantly, they are compatible with current CMOS processes, and therefore have been widely used.

[0004] On-chip integrated inductors can be bonding wires connecting different conductive terminals, or planar inductors formed on a semiconductor substrate. However, since on-chip integrated inductors are formed on the substrate, there is electrical coupling between the inductor and the substrate. The current in the inductor will cause coupling current to form on the substrate, which will reduce the quality factor of the inductor, resulting in energy loss in the semiconductor device and affecting the performance of the semiconductor device. Therefore, improving the quality factor of on-chip inductors plays an important role in improving the performance of semiconductor devices. Summary of the Invention

[0005] In view of this, the first aspect of this application provides a semiconductor device and a method for manufacturing the same, to reduce coupling current in the substrate and improve the performance of the semiconductor device.

[0006] A first aspect of this application provides a semiconductor device, comprising:

[0007] Substrates and inductor components;

[0008] A shielding layer is formed between the substrate and the inductor, the shielding layer being used to shield the electrical coupling between the substrate and the inductor.

[0009] In this embodiment, the electrical coupling between the substrate and the inductor can be shielded by the shielding layer, which can reduce the coupling current in the substrate, improve the quality factor of the inductor, and improve the device performance.

[0010] In some possible implementations, the shielding layer is grounded.

[0011] In the embodiments of this application, the shielding layer can be grounded, which can achieve better shielding of the substrate and inductor, reduce coupling current in the substrate, improve the quality factor of the inductor, and improve the performance of the device.

[0012] In some possible implementations, the shielding layer is grounded via a bonding wire, or the shielding layer is grounded via a conductive via penetrating the substrate, or the shielding layer is grounded by connecting to the grounded substrate.

[0013] In the embodiments of this application, the grounding of the shielding layer can be achieved in a variety of ways, thereby providing reliable shielding.

[0014] In some possible implementations, the shielding layer is another functional layer in the semiconductor device.

[0015] In the embodiments of this application, other functional layers in the semiconductor device can be used as shielding layers, eliminating the need for additional shielding layers, thus simplifying the performance process of the semiconductor device and reducing redundant components in the semiconductor device.

[0016] In some possible implementations, the shielding layer is an on-chip capacitor element.

[0017] In the embodiments of this application, on-chip capacitors can be used as shielding layers, which improves the reliability of shielding to a certain extent.

[0018] In some possible implementations, the on-chip capacitor element has a first plate and a second plate, the second plate being grounded through a conductive via, and the area of ​​the second plate being larger than that of the first plate.

[0019] In the embodiments of this application, the capacitor element can be configured as an asymmetric structure, which can improve the quality factor of the capacitor element and thus further improve the device performance.

[0020] In some possible implementations, the doping concentration of the region of the substrate facing the inductor is lower than the doping concentration of other regions.

[0021] In this embodiment, the doping concentration of the substrate region facing the inductor can be reduced, thereby increasing the resistivity in that region, reducing the coupling current in that region, and further improving the quality factor of the inductor.

[0022] In some possible implementations, the thickness of the region of the substrate facing the inductor is less than the thickness of other regions.

[0023] In this embodiment, the thickness of the substrate region facing the inductor can be reduced, thereby increasing the resistivity in that region, thereby reducing the coupling current in that region, and further improving the quality factor of the inductor.

[0024] In some possible implementations, the inductor element is a bonding wire connecting the signal input terminal and the signal output terminal, or a conductor layer connecting the signal input terminal and the signal output terminal.

[0025] In this embodiment, the inductor can be a bonding wire or a conductor layer, which has a certain degree of reliability.

[0026] A second aspect of this application provides another semiconductor device, including:

[0027] A substrate and an inductor; the doping concentration of the region of the substrate facing the inductor is lower than the doping concentration of other regions, and / or the thickness of the region of the substrate facing the inductor is less than the thickness of other regions.

[0028] A third aspect of the embodiments of this application provides yet another semiconductor device, comprising:

[0029] A substrate and a capacitor element; the capacitor element has a first electrode and a second electrode, the second electrode being grounded, and the area of ​​the second electrode being larger than that of the first electrode.

[0030] A fourth aspect of this application provides a method for manufacturing a semiconductor device, comprising:

[0031] Provide substrate;

[0032] A shielding layer and an inductor are sequentially formed on the substrate, wherein the shielding layer is used to shield the electrical coupling between the substrate and the inductor.

[0033] In some possible implementations, the shielding layer is grounded.

[0034] In some possible implementations, the shielding layer is grounded via a bonding wire, or the shielding layer is grounded via a conductive via penetrating the substrate, or the shielding layer is grounded by connecting to the grounded substrate.

[0035] In some possible implementations, the shielding layer is another functional layer in the semiconductor device.

[0036] In some possible implementations, the shielding layer is an on-chip capacitor element.

[0037] In some possible implementations, the on-chip capacitor element has a first plate and a second plate, the second plate being grounded through a conductive via, and the area of ​​the second plate being larger than that of the first plate.

[0038] In some possible implementations, the doping concentration of the region of the substrate facing the inductor is lower than the doping concentration of other regions.

[0039] In some possible implementations, the thickness of the region of the substrate facing the inductor is less than the thickness of other regions.

[0040] In some possible implementations, the inductor element is a bonding wire connecting the signal input terminal and the signal output terminal, or a conductor layer connecting the signal input terminal and the signal output terminal.

[0041] A fifth aspect of this application provides another method for manufacturing a semiconductor device, comprising:

[0042] A substrate is provided; the doping concentration of the region of the substrate facing the inductor is lower than the doping concentration of other regions, and / or the thickness of the region of the substrate facing the inductor is less than the thickness of other regions;

[0043] An inductor is formed on the substrate.

[0044] A sixth aspect of the embodiments of this application provides yet another method for manufacturing a semiconductor device, comprising:

[0045] Provide substrate;

[0046] A capacitor element is formed on the substrate; the capacitor element has a first plate and a second plate, the second plate being grounded, and the area of ​​the second plate being larger than that of the first plate.

[0047] Compared with the prior art, this application has the following advantages:

[0048] Based on the above technical solutions, the semiconductor device provided in this application includes a substrate and an inductor. A shielding layer can be formed between the substrate and the inductor. The shielding layer is used to shield the electrical coupling between the substrate and the inductor. This can reduce the coupling current in the substrate, reduce the energy loss in the inductor, improve the quality factor of the inductor, and improve the performance of the semiconductor device. Attached Figure Description

[0049] To clearly understand the specific embodiments of this application, the accompanying drawings used in describing the specific embodiments of this application will be briefly described below. Obviously, these drawings are only some embodiments of this application.

[0050] Figure 1This is a schematic diagram of the structure of a semiconductor device provided in an embodiment of this application;

[0051] Figure 2 A schematic diagram illustrating the quality factor of an inductor element provided in an embodiment of this application;

[0052] Figure 3 This is a schematic diagram of the structure of another semiconductor device provided in an embodiment of this application;

[0053] Figure 4 This is a schematic diagram of the structure of another semiconductor device provided in the embodiments of this application;

[0054] Figure 5 This is a schematic diagram of the structure of another semiconductor device provided in the embodiments of this application;

[0055] Figure 6 This is a schematic diagram of the structure of another semiconductor device provided in the embodiments of this application;

[0056] Figure 7 This is a schematic diagram of the structure of another semiconductor device provided in the embodiments of this application;

[0057] Figure 8 A schematic diagram illustrating the quality factor of another inductor element provided in an embodiment of this application;

[0058] Figure 9 This is a schematic diagram of the structure of another semiconductor device provided in the embodiments of this application;

[0059] Figure 10 This is a schematic diagram of the structure of another semiconductor device provided in the embodiments of this application;

[0060] Figure 11 This is a schematic diagram of the structure of another semiconductor device provided in the embodiments of this application;

[0061] Figure 12 A schematic diagram illustrating the quality factor of a capacitor element provided in a semi-application embodiment;

[0062] Figure 13 This is a schematic diagram of the structure of another semiconductor device provided in the embodiments of this application;

[0063] Figure 14 A schematic diagram illustrating the quality factor of another capacitor element provided in an embodiment of this application;

[0064] Figure 15 This is a schematic diagram of the structure of another semiconductor device provided in the embodiments of this application;

[0065] Figure 16 A schematic diagram illustrating the quality factor of another inductor element provided in an embodiment of this application;

[0066] Figure 17 This is a schematic diagram of the structure of another semiconductor device provided in the embodiments of this application;

[0067] Figure 18 A schematic diagram illustrating the quality factor of another inductor element provided in an embodiment of this application;

[0068] Figure 19 This is a schematic diagram of the structure of another semiconductor device provided in the embodiments of this application;

[0069] Figure 20 A schematic diagram illustrating the quality factor of another inductor element provided in an embodiment of this application;

[0070] Figure 21 This is a flowchart illustrating a method for manufacturing a semiconductor device according to an embodiment of this application. Detailed Implementation

[0071] In view of this, the first aspect of this application provides a semiconductor device and a method for manufacturing the same, to reduce coupling current in the substrate and improve the performance of the semiconductor device.

[0072] Currently, resistors, capacitors, and inductors can be integrated into semiconductor products. Taking radio frequency (RF) integrated circuits as an example, to integrate matching components from traditional RF circuits onto the chip, inductors need to be fabricated on-chip—that is, on-chip integrated inductors. Inductors are key components in RF integrated circuits and are among the most difficult to design and control; their performance parameters directly affect the performance of the RF integrated circuit. On-chip integrated inductors are characterized by low cost, ease of integration, low noise, and low power consumption. More importantly, they are compatible with current CMOS processes, and therefore have gained widespread application.

[0073] The on-chip integrated inductor can be a bonding wire connecting different conductive terminals, or it can be a planar inductor with a layered structure. On-chip integrated inductors are typically formed on a semiconductor substrate. Figure 1 The diagram shown is a schematic diagram of a semiconductor device provided in an embodiment of this application. The bonding wire serves as an inductor 200 in the semiconductor device, with one end connected to the signal input terminal and the other end connected to the signal output terminal. The signal input terminal and the signal output terminal can be connection terminals of other components on the semiconductor substrate 100.

[0074] The inductor element 200 formed on the semiconductor substrate 100 is relatively close to the substrate 100. This close proximity causes coupling current to form on the substrate 100 due to the current flowing through the inductor element 200, resulting in energy loss in the semiconductor device. This affects the performance of the semiconductor device and reduces the quality factor of the inductor element 200. The quality factor of an inductor element can be defined as the ratio of the energy stored in the inductor element to the energy lost in each oscillation cycle. A higher quality factor indicates lower losses and higher efficiency.

[0075] Taking laterally-diffused metal-oxide-semiconductor (LDMOS) as an example, an LDMOS device includes an inductive element and can have either an insulating or non-insulating substrate. (Reference) Figure 2 The diagram illustrates the quality factor of an inductor element according to an embodiment of this application, comparing the quality factor of the inductor element on an insulating substrate and on a non-insulating substrate. The horizontal axis represents frequency (freq) in GHz, and the vertical axis represents the quality factor of the inductor element (dimensionless). It can be seen that the coupling current in the non-insulating substrate significantly reduces the quality factor of the inductor element, thus degrading the performance of the LDMOS device. Therefore, improving the quality factor of inductors on a chip plays a crucial role in enhancing the performance of semiconductor devices.

[0076] Based on the above technical problems, this application provides a semiconductor device and a method for manufacturing the same. The semiconductor device includes a substrate and an inductor. A shielding layer can be formed between the substrate and the inductor. The shielding layer is used to shield the electrical coupling between the substrate and the inductor. This can reduce the coupling current in the substrate, reduce the energy loss in the inductor, improve the quality factor of the inductor, and improve the performance of the semiconductor device.

[0077] To better understand the specific embodiments of this application, the semiconductor device provided in this application will be described in detail below with reference to the accompanying drawings.

[0078] refer to Figure 3 The diagram shown is a schematic diagram of another semiconductor device provided in the embodiments of this application. The semiconductor device provided in the embodiments of this application may include a substrate 100 and an inductor 200. A shield 300 may be formed between the substrate 100 and the inductor 200. The shield 300 can shield the electrical coupling between the substrate 100 and the inductor 200.

[0079] The substrate 100 can be a semiconductor substrate, such as a Si substrate, a Ge substrate, a SiGe substrate, SOI (Silicon On Insulator), or GOI (Germanium On Insulator). In other embodiments, the substrate 100 can also be a substrate comprising other elemental semiconductors or compound semiconductors, such as GaAs, InP, or SiC, or a stacked structure, such as Si / SiGe, or other epitaxial structures, such as SGOI (Silicon Germanium On Insulator). The substrate 100 may have an isolation region (not shown), which may include silicon dioxide or other materials that can separate the active regions of the device. In this embodiment, the substrate 100 is a bulk silicon substrate.

[0080] An inductor 200 can be formed on the substrate 100. One end of the inductor 200 is connected to a signal input terminal 201, and the other end is connected to a signal output terminal 202. The signal input terminal 201 and the signal output terminal 202 can be disposed on the same metal layer or on different metal layers.

[0081] Optionally, the inductor 200 can be a bonding wire connecting different conductive ports, such as connecting the signal input terminal 201 and the signal output terminal 202. The bonding wire can be copper wire, gold wire, aluminum wire, or other conductive metal wire. The bonding wire usually has a certain length and curvature, which determines the inductance value of the bonding wire. The material and diameter of the bonding wire will also affect the quality factor of the bonding wire.

[0082] Optionally, the inductor 200 can also be a layered conductor layer. This conductor layer can be connected to the signal input terminal 201 and the signal output terminal 202 respectively through conductive vias to form the structure of the inductor 200. The conductor layer can be a metal layer, such as a tungsten metal layer or a copper metal layer. The conductive vias can be vias with metal material formed inside.

[0083] A shielding layer 300 can be formed between the substrate 100 and the inductor 200. The shielding layer 300 can isolate the inductor 200 and the substrate 100, thereby shielding the electrical coupling between the substrate 100 and the inductor 200, reducing the coupling current in the substrate 100, improving the quality factor of the inductor 200, reducing the energy loss of the semiconductor device, and improving the performance of the semiconductor device.

[0084] As one possible implementation, the shielding layer 300 can be a grounded conductive layer or a semiconductor layer. The conductive layer can be a metal layer, such as a tungsten metal layer or a copper metal layer, and the semiconductor layer can be one or more stacks of Si material layers, Ge material layers, SiGe material layers, etc. The shielding layer 300 can be grounded in various ways, see reference... Figure 4, 5 Figures 6 and 7 are schematic diagrams of a semiconductor device provided in an embodiment of this application, wherein, with reference to Figure 4 As shown, the shielding layer 300 can be grounded via the bonding wire 301, see reference. Figure 5 As shown, the shielding layer 300 can be grounded by connecting to the ground wire through the conductive via 302 penetrating the substrate 100, as referenced. Figure 6 As shown, the shielding layer 300 can be grounded by connecting to the grounded substrate 100 through the conductive via 303.

[0085] For example, Figure 6 The inductor element 200 in the middle is equivalent in shape, with reference to Figure 7 The diagram shown illustrates another semiconductor device provided in this application embodiment. The shielding layer 300 can be grounded by connecting to a grounded substrate 100. The distance between one end and the other end of the inductor 200 is 1 mm. The angle between the end segment of the inductor 200 and the surface of the substrate 100 is 80°. The length of the line segment of the inductor 200 parallel to the surface of the substrate 100 is approximately 0.5 mm. The substrate 100 is a highly conductive substrate with a resistivity of 0.015 Ω·cm. (Reference) Figure 8 The diagram shown illustrates the quality factor of another inductor element provided in this application embodiment, including a comparison of the quality factor of the inductor element 200 under conditions of having a grounded shielding layer 300 and not having a grounded shielding layer 300. The horizontal axis represents frequency (freq) in GHz, and the vertical axis represents the quality factor of the inductor element 200, with dimensionless units. It can be seen that the quality factor of the inductor element 200 is effectively improved by using a grounded shielding layer 300.

[0086] As another possible implementation, the shielding layer 300 can also be other functional layers on the substrate 100. These other functional layers may or may not be electrically connected to the inductor element 200. For example, other functional layers can be capacitor elements formed on the substrate 100. These capacitor elements can be planar capacitor elements with a first plate and a second plate. The second plate can be grounded, and the substrate 100 can be close to either the first or the second plate. The second plate can be grounded by connecting to a ground wire via a conductive via, or by connecting to a grounded substrate via a conductive via. (Reference) Figure 9 The diagram shown is a schematic of another semiconductor device provided in the embodiment of this application. The capacitor element may include a first electrode plate and a second electrode plate. The first electrode plate of the capacitor element is an upper electrode plate 3001, and the second electrode plate of the capacitor element is a lower electrode plate 3002. The lower electrode plate 3002 can be connected to the substrate 100 through a conductive via 306. The substrate 100 can be grounded, thus realizing the grounding of the second electrode plate.

[0087] In this embodiment, the capacitor element can isolate the inductor element 200 and the substrate 100, thereby shielding the electrical coupling between the substrate 100 and the inductor element 200, reducing the coupling current in the substrate 100, improving the quality factor of the inductor element 200, reducing the energy loss of the semiconductor device, and improving the performance of the semiconductor device.

[0088] The quality factor of the capacitor element formed on substrate 100 is explained below. The capacitor element formed on substrate 100 can also be referred to as a chip-integrated capacitor element. (Reference) Figure 10 The diagram shown is a schematic representation of another semiconductor device provided in this application. The semiconductor device includes a substrate 100 and a capacitor element on the substrate 100, wherein the lower electrode 3002 of the capacitor element is connected to a ground line 305 through a conductive via 304. (Reference) Figure 11 The diagram shown is a schematic of a semiconductor device according to an embodiment of this application. The semiconductor device includes a substrate 100 and a capacitor element on the substrate 100, wherein the lower electrode 3002 of the capacitor element is connected to the ground substrate 100 through a conductive via 306.

[0089] Because the lower plate 3002 of the capacitor element is grounded through a conductive via, the resistance of the via causes energy loss, leading to a decrease in the quality factor of the capacitor element and consequently a decline in the performance of the semiconductor device. Therefore, improving the quality factor of the capacitor element can reduce energy loss in the semiconductor device, thus improving the performance of the semiconductor device. (Reference) Figure 12 The diagram shown illustrates the quality factor of a capacitor element provided in a semi-application embodiment. The horizontal axis represents the resistance of the grounded conductive via in ohms, and the vertical axis represents the quality factor of the capacitor element connected to the grounded conductive via, with dimensionless units. It can be seen that as the resistance of the grounded conductive via increases, the quality factor of the capacitor element decreases significantly, which will have a significant impact on the performance of the semiconductor.

[0090] Therefore, in this embodiment, the on-chip integrated capacitor element can adopt an asymmetrical capacitor plate form, making the area of ​​the grounded lower plate 3002 larger than the area of ​​the upper plate 3001. This allows the lower plate 3002 to connect to more conductive vias, thereby reducing the equivalent resistance obtained by connecting multiple conductive vias in parallel, and to a certain extent reducing energy loss within the conductive vias, thus improving the quality factor of the capacitor element. (Reference) Figure 13 The diagram shown is a schematic of another semiconductor device provided in an embodiment of this application, wherein the upper electrode 3001 of the asymmetric capacitor element has an area of ​​0.2 mm². 2 The area of ​​the lower electrode plate 3002 is 0.8 mm². 2,refer to Figure 14 The diagram shown illustrates the quality factor of another capacitor element provided in this application embodiment, including a comparison of the quality factors of symmetrical and asymmetrical capacitor elements. The parameters of the asymmetrical capacitor are referenced. Figure 13 As shown, the areas of both the upper plate 3001 and the lower plate 3002 of the symmetrical capacitor are 0.2 mm². 2 , Figure 14 The horizontal axis represents the resistance of the grounded conductive via in ohms, and the vertical axis represents the quality factor of the capacitor connected to the grounded conductive via, with no dimension. It can be seen that asymmetrical capacitors have a higher quality factor.

[0091] Based on the above analysis, using asymmetrical capacitor elements can improve the quality factor of the capacitor elements. Therefore, when using capacitor elements as shielding layer 300, in order to further improve the performance of semiconductor devices, the capacitor elements used as shielding layer 300 can be adjusted to have an asymmetrical structure. (Reference) Figure 15 The diagram shows a schematic representation of another semiconductor device provided in this application, including a substrate 100, an inductor 200, and a capacitor between the substrate 100 and the inductor 200. One end of the inductor 200 is connected to the upper plate 4001 of a first capacitor, and the other end of the inductor 200 is connected to the upper plate 3001 of a second capacitor. The first and second capacitors share a common grounded lower plate 3002. Thus, the two capacitors and the inductor 200 form a π-type circuit. As an example, the distance between one end and the other end of the inductor 200 is 1 mm, the angle between one end of the inductor 200 and the surface of the substrate 100 is 80°, and the line segment parallel to the surface of the substrate 100 is approximately 0.5 mm. (Reference) Figure 16 The diagram shown illustrates the quality factor of another inductor element provided in this application embodiment, including a comparison of the quality factor of the inductor element 200 with and without a capacitor element as a shielding layer 300. The horizontal axis represents frequency (freq) in GHz, and the vertical axis represents the quality factor of the inductor element (Quality_Factor) in dimensionless units. It can be seen that after isolation by the capacitor element, the quality factor of the inductor element 200 is effectively improved in some frequency bands.

[0092] In this embodiment, the performance degradation of the semiconductor device is caused by a decrease in the quality factor of the inductor 200. This decrease in the quality factor is due to the generation of coupling current in the substrate 100. The larger the coupling current, the lower the quality factor of the inductor 200. Therefore, the quality factor of the inductor 200 can be improved by reducing the coupling current in the substrate 100. The coupling current in the substrate 100 is related to the resistivity of the substrate 100. Therefore, by increasing the resistivity of the substrate 100, the coupling current in the substrate 100 can be reduced, thereby reducing energy loss, improving the quality factor of the inductor 200, and improving the performance of the semiconductor device.

[0093] As one possible implementation, the resistivity of the substrate 100 can be adjusted by changing the doping state in the substrate 100. Specifically, the doping concentration of the region 1001 facing the inductor 200 in the substrate 100 can be lower than the doping concentration of other regions 1002. This increases the resistivity of the region 1001 facing the inductor 200, thereby reducing the coupling current that can be generated, which can improve the quality factor of the inductor 200 and improve the performance of the semiconductor device. Other regions are not facing the inductor 200 and will not generate coupling current. The higher doping concentration can ensure the normal operation of the semiconductor substrate.

[0094] refer to Figure 17 The diagram shown illustrates the structure of another semiconductor device provided in this application embodiment. The semiconductor device includes a substrate 100 and an inductor 200. The region in the substrate 100 directly opposite the inductor 200 can be a lightly doped region 1001. The resistivity of the lightly doped region 1001 can be 1.5 Ω·cm. The area of ​​the lightly doped region 1001 can be determined based on the area directly opposite the inductor 200. The depth of the lightly doped region 1001 can be determined based on the characteristics of the inductor 200 and the distance between the inductor 200 and the substrate. Outside the lightly doped region 1001 is a heavily doped active region 1002. The resistivity of the heavily doped active region 1002 can be 0.015 Ω·cm. (Reference) Figure 18 The diagram shown illustrates the quality factor of another inductor element provided in this application embodiment, including a comparison of the quality factor of the inductor element 200 under conditions of partial light doping and complete heavy doping of the substrate 100. The horizontal axis represents frequency (freq) in GHz, and the vertical axis represents the quality factor of the inductor element (Quality_Factor) in dimensionless units. It can be seen that the quality factor of the inductor element 200 is effectively improved after partial light doping of the substrate 100.

[0095] As another possible implementation, the resistivity of the substrate 100 can be adjusted by changing its thickness. Specifically, the thickness of the region 1003 of the substrate 100 directly facing the inductor 200 can be made smaller than the thickness of other regions 1004. This reduces the conducting cross-sectional area of ​​the region 1003 directly facing the inductor 200, thereby increasing the resistivity of the substrate 100 at that location. This increases the resistance of the coupling current path, thus reducing the generated coupling current and improving the quality factor of the inductor 200, thereby improving the performance of the semiconductor device. Meanwhile, the other regions 1004 are not directly facing the inductor 200 and do not generate coupling current. The larger thickness ensures the normal operation of the semiconductor substrate 100.

[0096] refer to Figure 19 The diagram shown illustrates the structure of another semiconductor device provided in this application embodiment. The semiconductor device includes a substrate 100 and an inductor 200. The region of the substrate 100 directly opposite the inductor 200 can be a thinned region 1003, with a substrate thickness of 10 μm. The substrate thickness of the thinned region 1003 is 10 μm, while the substrate thickness of other regions 1004 outside the thinned region 1003 is 100 μm, and the resistivity is 0.015 Ω·cm. (Reference) Figure 20 The diagram shown illustrates the quality factor of another inductor element provided in this application embodiment, including a comparison of the quality factor of the inductor element 200 under conditions of local thinning of the substrate 100 and without local thinning. The horizontal axis represents frequency (freq) in GHz, and the vertical axis represents the quality factor of the inductor element (Quality_Factor) in dimensionless units. It can be seen that the quality factor of the inductor element 200 is effectively improved after local thinning of the substrate 100.

[0097] The above examples demonstrate that localized light doping or localized thinning of the substrate 100 can effectively improve the quality factor of the inductor 200. Therefore, in this embodiment, the substrate in the region directly opposite the inductor 200 can also be locally lightly doped and locally thinned to further improve the quality factor of the inductor 200. Alternatively, with a shielding layer 300 between the substrate 100 and the inductor 200, localized light doping and / or localized thinning of the substrate 100 in the region directly opposite the inductor 200 can be performed to further improve the quality factor of the inductor 200. The methods for setting the shielding layer 300, localized light doping, and localized thinning are described above and will not be repeated here.

[0098] This application provides a semiconductor device including a substrate and an inductor. A shielding layer can be formed between the substrate and the inductor. The shielding layer is used to shield the electrical coupling between the substrate and the inductor, which can reduce the coupling current in the substrate, reduce the energy loss in the inductor, improve the quality factor of the inductor, and improve the performance of the semiconductor device.

[0099] This application also provides another semiconductor device, including a substrate and a capacitor element. The lower electrode 3002 of the capacitor element is connected to a ground wire 305 through a conductive via 304, and can also be connected to a grounded substrate 100 through a conductive via 306. Since the lower electrode 3002 of the capacitor element is grounded through the conductive via, the resistance of the conductive via will cause a certain amount of energy loss, resulting in a decrease in the quality factor of the capacitor element, and thus a decrease in the performance of the semiconductor device. Therefore, improving the quality factor of the capacitor element can reduce the energy loss in the semiconductor device, and also improve the performance of the semiconductor device.

[0100] Therefore, in this embodiment, the on-chip integrated capacitor element can be in the form of an asymmetric capacitor plate, so that the area of ​​the grounded lower plate 3002 is larger than the area of ​​the upper plate 3001. In this way, the lower plate 3002 can connect more conductive vias, thereby reducing the equivalent resistance obtained by connecting multiple conductive vias in parallel, reducing the energy loss in the conductive vias to a certain extent, and thus improving the quality factor of the capacitor element.

[0101] This application also provides another semiconductor device, including a substrate 100 and an inductor 200.

[0102] Specifically, the doping concentration of region 1001 in substrate 100 directly facing inductor 200 is lower than that of other regions 1002. This increases the resistivity of region 1001, thus reducing the coupling current and improving the quality factor of inductor 200, thereby enhancing the performance of the semiconductor device. Other regions, not directly facing inductor 200, do not generate coupling current. The higher doping concentration ensures the normal operation of the semiconductor substrate. (Reference) Figure 17The diagram shown is a schematic diagram of another semiconductor device provided in an embodiment of this application. The semiconductor device includes a substrate 100 and an inductor 200. The region in the substrate 100 facing the inductor 200 can be a lightly doped region 1001. The resistivity of the substrate in the lightly doped region 1001 can be 1.5 Ω·cm. The area of ​​the lightly doped region 1001 can be determined according to the area facing the inductor 200. The depth of the lightly doped region 1001 can be determined according to the characteristics of the inductor 200 and the distance between the inductor 200 and the substrate. Outside the lightly doped region 1001 is a heavily doped active region 1002. The resistivity of the substrate in the heavily doped active region 1002 can be 0.015 Ω·cm.

[0103] Specifically, the thickness of the region 1003 in the substrate 100 directly facing the inductor 200 is less than the thickness of other regions 1004. This reduces the conductive cross-sectional area of ​​the region 1003 directly facing the inductor 200, increasing the resistivity of the substrate 100 at this location. This increases the resistance of the coupling current path, thus reducing the generated coupling current and improving the quality factor of the inductor 200, thereby enhancing the performance of the semiconductor device. The other regions 1004, not directly facing the inductor 200, do not generate coupling current, and the greater thickness ensures the normal operation of the semiconductor substrate 100. (Reference) Figure 19 The diagram shown is a schematic diagram of another semiconductor device provided in the embodiments of this application. The semiconductor device includes a substrate 100 and an inductor 200. The region of the substrate 100 facing the inductor 200 can be a thinning region 1003 with a substrate thickness of 10 μm. The substrate thickness of the thinning region 1003 can be 10 μm, while the substrate thickness of the other regions 1004 outside the thinning region 1003 is 100 μm and the resistivity can be 0.015 Ω·cm.

[0104] Based on the above semiconductor devices, embodiments of this application also provide a method for manufacturing semiconductor devices, referencing... Figure 21 The diagram shown is a flowchart of a method for manufacturing a semiconductor device according to an embodiment of this application. The method may include the following steps:

[0105] S101 provides a substrate.

[0106] The substrate 100 can be a semiconductor substrate, such as a Si substrate, a Ge substrate, a SiGe substrate, SOI (Silicon On Insulator), or GOI (Germanium On Insulator). In other embodiments, the substrate 100 can also be a substrate comprising other elemental semiconductors or compound semiconductors, such as GaAs, InP, or SiC, and can also be a stacked structure, such as Si / SiGe, or other epitaxial structures, such as SGOI (Silicon Germanium On Insulator). The substrate 100 may have an isolation region (not shown), which may include silicon dioxide or other materials that can separate the active regions of the device. In this embodiment, the substrate 100 is a bulk silicon substrate.

[0107] S102, a shielding layer 300 and an inductor element 200 are sequentially formed on the substrate.

[0108] Optionally, the inductor 200 can be a bonding wire connecting different conductive ports, such as connecting the signal input terminal 201 and the signal output terminal 202. The bonding wire can be copper wire, gold wire, aluminum wire, or other conductive metal wire. The bonding wire usually has a certain length and curvature, which determines the inductance value of the bonding wire. The material and diameter of the bonding wire will also affect the quality factor of the bonding wire.

[0109] Optionally, the inductor 200 can also be a layered conductor layer. This conductor layer can be connected to the signal input terminal 201 and the signal output terminal 202 respectively through conductive vias to form the structure of the inductor 200. The conductor layer can be a metal layer, such as a tungsten metal layer or a copper metal layer. The conductive vias can be vias with metal material formed inside.

[0110] A shielding layer 300 can be formed between the substrate 100 and the inductor 200. The shielding layer 300 can isolate the inductor 200 and the substrate 100, thereby shielding the electrical coupling between the substrate 100 and the inductor 200, reducing the coupling current in the substrate 100, improving the quality factor of the inductor 200, reducing the energy loss of the semiconductor device, and improving the performance of the semiconductor device.

[0111] In one possible implementation, the shielding layer 300 can be a grounded conductor layer or a semiconductor layer. The conductor layer can be a metal layer, such as a tungsten metal layer or a copper metal layer, and the semiconductor layer can be one or more stacks of Si material layers, Ge material layers, SiGe material layers, etc. The shielding layer 300 can be grounded through bonding wires 301, or by connecting to a ground wire through conductive vias 302 penetrating the substrate 100, or by connecting to the grounded substrate 100 through conductive vias 303.

[0112] As another possible implementation, the shielding layer 300 can also be other functional layers on the substrate 100. These other functional layers may or may not be electrically connected to the inductor 200. For example, other functional layers may be capacitor elements formed on the substrate 100. These capacitor elements may be planar capacitor elements with a first electrode and a second electrode. The second electrode may be grounded, and the substrate 100 may be close to either the first or the second electrode. The second electrode may be grounded by connecting to a ground wire 305 via a conductive via 304, or by connecting to a grounded substrate 100 via a conductive via 306. (See reference...) Figure 9 The diagram shown is a schematic of another semiconductor device provided in the embodiment of this application. The capacitor element may include a first electrode plate and a second electrode plate. The first electrode plate of the capacitor element is an upper electrode plate 3001, and the second electrode plate of the capacitor element is a lower electrode plate 3002. The lower electrode plate 3002 can be connected to the substrate 100 through a conductive via 306. The substrate 100 can be grounded, thus realizing the grounding of the second electrode plate.

[0113] To further improve the performance of the semiconductor device, the capacitor element serving as the shielding layer 300 can be adjusted to an asymmetric structure. A schematic diagram of another semiconductor device provided in this application embodiment includes a substrate 100 and an inductor 200, as well as a capacitor element between the substrate 100 and the inductor 200. One end of the inductor 200 is connected to the upper plate 4001 of a first capacitor element, and the other end of the inductor 200 is connected to the upper plate 3001 of a second capacitor element. The first and second capacitor elements share a common grounded lower plate 3002. Thus, the two capacitor elements and the inductor 200 constitute a π-type circuit. As an example, the distance between one end and the other end of the inductor 200 is 1 mm, the angle between one end of the inductor 200 and the surface of the substrate 100 is 80°, and the line segment parallel to the surface of the substrate 100 from the inductor 200 is approximately 0.5 mm.

[0114] Specifically, the doping concentration of the region 1001 in the substrate 100 that faces the inductor 200 can be lower than that of other regions 1002. This increases the resistivity of the region 1001 facing the inductor 200, thereby reducing the coupling current and improving the quality factor of the inductor 200 and the performance of the semiconductor device. Other regions that are not facing the inductor 200 will not generate coupling current, and the higher doping concentration ensures the normal operation of the semiconductor substrate.

[0115] Specifically, the thickness of the region 1003 in the substrate 100 directly facing the inductor 200 can be made smaller than the thickness of other regions 1004. This reduces the conducting cross-sectional area of ​​the region 1003 directly facing the inductor 200, increases the resistivity of the substrate 100 at that location, increases the resistance of the coupling current path, and thus reduces the coupling current. This can improve the quality factor of the inductor 200 and improve the performance of the semiconductor device. Meanwhile, other regions 1004 are not directly facing the inductor 200 and will not generate coupling current. The larger thickness can ensure the normal operation of the semiconductor substrate 100.

[0116] The present application provides a method for manufacturing a semiconductor device, in which a shielding layer is formed between a substrate and an inductor. The shielding layer is used to shield the electrical coupling between the substrate and the inductor, thereby reducing the coupling current in the substrate, reducing energy loss in the inductor, improving the quality factor of the inductor, and improving the performance of the semiconductor device.

[0117] This application also provides another method for manufacturing a semiconductor device, including: forming a substrate and a capacitor element on the substrate, wherein the lower electrode of the capacitor element is connected to a ground wire through a conductive via, or connected to a grounded substrate through a conductive via. Since the lower electrode of the capacitor element is grounded through a conductive via, the resistance of the conductive via causes energy loss, leading to a decrease in the quality factor of the capacitor element, and consequently, a decline in the performance of the semiconductor device. Therefore, improving the quality factor of the capacitor element can reduce energy loss in the semiconductor device, and thus improve the performance of the semiconductor device. Therefore, in this application embodiment, the on-chip integrated capacitor element can adopt an asymmetrical capacitor electrode configuration, making the area of ​​the grounded lower electrode larger than the area of ​​the upper electrode. This allows the lower electrode to connect to more conductive vias, thereby reducing the equivalent resistance obtained by connecting multiple conductive vias in parallel, reducing energy loss within the conductive vias to a certain extent, and thus improving the quality factor of the capacitor element.

[0118] This application also provides another method for manufacturing a semiconductor device, including: forming a substrate and an inductor element on the substrate.

[0119] Specifically, the doping concentration of region 1001 in substrate 100 directly facing inductor 200 is lower than that of other regions 1002. This increases the resistivity of region 1001, thus reducing the coupling current and improving the quality factor of inductor 200, thereby enhancing the performance of the semiconductor device. Other regions, not directly facing inductor 200, do not generate coupling current. The higher doping concentration ensures the normal operation of the semiconductor substrate. (Reference) Figure 17The diagram shown is a schematic diagram of another semiconductor device provided in an embodiment of this application. The semiconductor device includes a substrate 100 and an inductor 200. The region in the substrate 100 facing the inductor 200 can be a lightly doped region 1001. The resistivity of the substrate in the lightly doped region 1001 can be 1.5 Ω·cm. The area of ​​the lightly doped region 1001 can be determined according to the area facing the inductor 200. The depth of the lightly doped region 1001 can be determined according to the characteristics of the inductor 200 and the distance between the inductor 200 and the substrate. Outside the lightly doped region 1001 is a heavily doped active region 1002. The resistivity of the substrate in the heavily doped active region 1002 can be 0.015 Ω·cm.

[0120] Specifically, the thickness of the region 1003 in the substrate 100 directly facing the inductor 200 is less than the thickness of other regions 1004. This reduces the conductive cross-sectional area of ​​the region 1003 directly facing the inductor 200, increasing the resistivity of the substrate 100 at this location. This increases the resistance of the coupling current path, thus reducing the generated coupling current and improving the quality factor of the inductor 200, thereby enhancing the performance of the semiconductor device. The other regions 1004, not directly facing the inductor 200, do not generate coupling current, and the greater thickness ensures the normal operation of the semiconductor substrate 100. (Reference) Figure 19 The diagram shown is a schematic diagram of another semiconductor device provided in the embodiments of this application. The semiconductor device includes a substrate 100 and an inductor 200. The region of the substrate 100 facing the inductor 200 can be a thinning region 1003 with a substrate thickness of 10 μm. The substrate thickness of the thinning region 1003 can be 10 μm, while the substrate thickness of the other regions 1004 outside the thinning region 1003 is 100 μm and the resistivity can be 0.015 Ω·cm.

[0121] In this embodiment, the substrate in the region facing the inductor can be locally lightly doped and locally thinned, which can further improve the quality factor of the inductor.

[0122] The various embodiments provided in this application can be referenced to each other; for example, the method embodiments can be referred to the description of the structural embodiments. The above describes the specific implementation of this application. It should be understood that the above-described embodiments are only used to illustrate the technical solutions of this application, and not to limit them. Although this application has been described in detail with reference to the foregoing embodiments, those skilled in the art should understand that modifications can still be made to the technical solutions described in the foregoing embodiments, or equivalent substitutions can be made to some of the technical features; and these modifications or substitutions do not cause the essence of the corresponding technical solutions to deviate from the scope of the technical solutions of the embodiments of this application.

Claims

1. A semiconductor device, characterized in that, include: Substrate and inductor element, wherein the inductor element is a bonding wire; A shielding layer is formed between the substrate and the inductor, and the shielding layer is used to shield the electrical coupling between the substrate and the inductor. The shielding layer is a capacitor element, which includes a first capacitor element and a second capacitor element. One end of the inductor element is connected to the upper plate of the first capacitor element, and the other end of the inductor element is connected to the upper plate of the second capacitor element. The first capacitor element and the second capacitor element have a common grounded lower plate. The area of ​​the lower plate is larger than the area of ​​the upper plate of the first capacitor element and the area of ​​the lower plate is larger than the area of ​​the upper plate of the second capacitor element. The first capacitor element, the second capacitor element, and the inductor element constitute a π-type circuit.

2. The semiconductor device according to claim 1, characterized in that, The shielding layer is grounded.

3. The semiconductor device according to claim 2, characterized in that, The shielding layer is grounded via a bonding wire, or the shielding layer is grounded via a conductive via penetrating the substrate, or the shielding layer is connected to the grounded substrate to achieve grounding.

4. The semiconductor device according to claim 1, characterized in that, The lower electrode plate is grounded through a conductive through-hole.

5. The semiconductor device according to any one of claims 1-4, characterized in that, The inductor is a bonding wire that connects the signal input terminal and the signal output terminal.

6. A method for manufacturing a semiconductor device, characterized in that, include: Provide substrate; A shielding layer and an inductor are sequentially formed on the substrate. The shielding layer is used to shield the electrical coupling between the substrate and the inductor. The inductor is a bonding wire. The shielding layer is a capacitor element, which includes a first capacitor element and a second capacitor element. One end of the inductor element is connected to the upper plate of the first capacitor element, and the other end of the inductor element is connected to the upper plate of the second capacitor element. The first capacitor element and the second capacitor element have a common grounded lower plate. The area of ​​the lower plate is larger than the area of ​​the upper plate of the first capacitor element and the area of ​​the lower plate is larger than the area of ​​the upper plate of the second capacitor element. The first capacitor element, the second capacitor element, and the inductor element constitute a π-type circuit.

7. The method according to claim 6, characterized in that, The shielding layer is grounded.

8. The method according to claim 7, characterized in that, The shielding layer is grounded via a bonding wire, or the shielding layer is grounded via a conductive via penetrating the substrate, or the shielding layer is connected to the grounded substrate to achieve grounding.

9. The method according to claim 6, characterized in that, The lower electrode plate is grounded through a conductive through-hole.

10. The method according to any one of claims 6-9, characterized in that, The inductor is a bonding wire that connects the signal input terminal and the signal output terminal.

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