Display substrate and display panel

Abstract

The present disclosure provides a display substrate, including a base substrate and a driving circuit layer and multiple light-emitting elements formed on the base substrate, the driving circuit layer including multiple pixel circuits corresponding to multiple pixel units, the multiple thin film transistors of the pixel circuits including a data writing transistor and a first light-emitting control transistor, in the same pixel circuit, the active total layer including a first column-oriented active portion, the first column-oriented active portion including an active layer of the data writing transistor, an active layer of the first light-emitting control transistor, and a first active connection portion, the orthographic projection of the first active connection portion on the base substrate at least partially overlaps with the orthographic projection of the corresponding power line on the base substrate, the size of the first active connection portion along the row direction of the pixel unit is smaller than the size of the active layer of the data writing transistor along the row direction of the pixel unit, and the size of the first active connection portion along the row direction of the pixel unit is smaller than the size of the active layer of the first light-emitting control transistor along the row direction of the pixel unit.

Description

Technical Field

[0001] The present disclosure relates to the field of display technology, and in particular, to a display substrate and a display panel. Background Art

[0002] Organic light-emitting diode (OLED) display devices have been widely used due to their advantages such as wide color gamut, solid-state light emission, and the ability to be made into flexible display devices.

[0003] As people's requirements for display clarity become higher and higher, correspondingly, the requirements for the resolution of organic light emitting diode display panels are also getting higher and higher. Summary of the Invention

[0004] The present disclosure aims to provide a display substrate and a display panel.

[0005] As one aspect of the present disclosure, a display substrate is provided, wherein the display substrate includes a base substrate and a driving circuit layer and a plurality of light-emitting elements formed on the base substrate. The display substrate is divided into a plurality of pixel units arranged in multiple rows and columns. The driving circuit layer includes a plurality of pixel circuits corresponding to the plurality of pixel units. The pixel circuits are used to drive the light-emitting elements to emit light.

[0006] Along the thickness direction of the display substrate, the driving circuit layer includes an active pattern layer and a source-drain pattern layer, the source-drain pattern layer is arranged on a side of the active pattern layer away from the base substrate, and the source-drain pattern layer includes a plurality of power lines and a plurality of data lines, the length direction of the power lines and the data lines being the same as the column direction of the pixel units, each column of pixel units corresponding to the power lines and the data lines, and the power lines and data lines corresponding to the same column of pixel units are arranged on the same side of the column of pixel units;

[0007] The pixel circuit includes a plurality of thin film transistors, and in a same pixel unit, the active layers of the thin film transistors of the pixel circuit are formed into an active total layer with an integrated structure, and the active graphic layer includes a plurality of the active total layers;

[0008] The multiple thin film transistors of the pixel circuit include a data writing transistor and a first light emitting control transistor. In the same pixel circuit, the active total layer includes a first column-oriented active portion, and the first column-oriented active portion includes the active layer of the data writing transistor, the active layer of the first light emitting control transistor, and a first active connection portion connected between the active layer of the data writing transistor and the active layer of the first light emitting control transistor. The positive projection of the first active connection portion on the substrate at least partially overlaps with the positive projection of the corresponding power line on the substrate. The size of the first active connection portion along the row direction of the pixel unit is smaller than the size of the active layer of the data writing transistor along the row direction of the pixel unit, and the size of the first active connection portion along the row direction of the pixel unit is smaller than the size of the active layer of the first light emitting control transistor along the row direction of the pixel unit.

[0009] Optionally, the plurality of thin film transistors of the pixel circuit include a first reset transistor, and the first reset transistor is used to reset the anode of the light emitting element;

[0010] The driving circuit layer includes a first gate pattern layer and a second gate pattern layer stacked along the thickness direction of the display substrate, wherein the first gate pattern layer and the second gate pattern layer are both located between the active pattern layer and the source / drain pattern layer, and the second gate layer is located on a side of the first gate layer away from the active pattern layer;

[0011] The first gate pattern layer includes a reset signal line, the second gate pattern layer includes an initial signal line, and the source-drain pattern layer further includes an initialization connector, one end of the initialization connector is electrically connected to the initialization signal line through a via, and the other end of the initialization connector is connected to a portion of the active layer corresponding to the first reset transistor through a via, the length direction of the initialization connector is consistent with the column direction of the pixel unit, and the distance between the column center lines of the vias at both ends of the initialization connector does not exceed a predetermined distance.

[0012] Optionally, the predetermined distance is between 0.1 μm and 0.5 μm.

[0013] Optionally, an orthographic projection of the via hole at one end of the initialization connector on a reference line extending along the row direction overlaps with an orthographic projection of the via hole at the other end of the initialization connector on the reference line.

[0014] Optionally, the active total layer includes a second column-oriented active portion, the second column-oriented active portion includes the active layer of the first reset transistor, and the orthographic projection of the initialization connection member on the base substrate partially overlaps with the orthographic projection of the second column-oriented active portion on the base substrate.

[0015] Optionally, the pixel circuit includes a second reset transistor and a driving transistor, wherein the second reset transistor is used to reset the gate of the driving transistor;

[0016] The active overall layer further includes a third column-oriented active portion and a fourth column-oriented active portion, the third column-oriented active portion being connected to the second column-oriented active portion via a second active connection portion, the fourth column-oriented active portion being connected to the third column-oriented active portion via a third active connection portion, and one end of the third column-oriented active portion being connected to the second active connection portion, and the other end of the third column-oriented active portion being connected to the third active connection portion, a corresponding reset signal line sequentially passing through the second column-oriented active portion, the third column-oriented active portion, and the fourth column-oriented active portion, a portion of the second column-oriented active portion through which the reset signal line passes forms an active layer of the first reset transistor, and portions of the third column-oriented active portion and the fourth column-oriented active portion through which the reset signal line passes form an active layer of the second reset transistor;

[0017] A via hole corresponding to the other end of the initialization connector is located on the second active connection portion.

[0018] Optionally, the first gate pattern layer further includes a plurality of gate lines, each row of the pixel units corresponds to the gate line, and the pixel circuit includes a compensation transistor.

[0019] The gate line includes a transverse portion and a longitudinal portion, each pixel unit corresponds to a longitudinal portion, and the active layer of the compensation transistor includes a portion of the active layer passing through the transverse portion and a portion of the active layer passing through the longitudinal portion.

[0020] Optionally, every four adjacent pixel units form a pixel unit group, and the four pixel units are respectively a red pixel unit, two green pixel units and one blue pixel unit.

[0021] Optionally, in the same pixel unit group, the arrangement order of the four pixel units along the row direction is:

[0022] A blue pixel unit, a green pixel unit, a red pixel unit and a green pixel unit.

[0023] Optionally, the display substrate further comprises a planarization layer, a pixel opening corresponding to the pixel unit is formed on the planarization layer, and a portion of the light emitting element except the anode is arranged in the opening.

[0024] Among the four pixel units in the same pixel unit group, the pixel opening corresponding to the blue pixel unit has the largest size along the row direction, and the pixel opening corresponding to the red pixel unit has the smallest size along the row direction.

[0025] Optionally, the display substrate further includes a plurality of width pads arranged in the same layer as the data lines, each of the red pixel units is provided with the width pad, and the width pad is arranged on a side of the red pixel unit away from the blue pixel unit.

[0026] Optionally, the orthographic projection of the width pad on the base substrate is located in an overlapping portion of the orthographic projection of the anode pattern of the red pixel unit arranged on the width pad on the base substrate and the orthographic projection of the pixel opening of the red pixel unit on the base substrate.

[0027] Optionally, the length direction of the width pad is consistent with the length direction of the data line.

[0028] Optionally, the source-drain pattern layer includes a plurality of anode connectors, each light-emitting element corresponds to an anode connector, and the anode connector is electrically connected to the anode pattern of the corresponding light-emitting element. In the same row of pixel units, the anode connectors corresponding to the light-emitting elements are arranged in a row, and the blue pixel opening, the red pixel opening, and the green pixel opening located on the side of the red pixel opening away from the blue pixel opening are located on one side of the row formed by the anode connectors, and the green pixel opening located between the red pixel opening and the blue pixel opening is located on the other side of the row formed by the anode connectors.

[0029] As a second aspect of the present disclosure, a display panel is provided, wherein the display panel includes the above-mentioned display substrate provided by the present disclosure. BRIEF DESCRIPTION OF THE DRAWINGS

[0030] The accompanying drawings are used to provide a further understanding of the present invention and constitute a part of the specification. Together with the following detailed description, they are used to explain the present invention but do not constitute a limitation of the present invention. In the accompanying drawings:

[0031] Figure 1 is an equivalent circuit diagram of a pixel circuit of a display panel provided by an embodiment of the present disclosure;

[0032] Figure 2 is a schematic diagram of a top view of a pixel circuit in a display panel provided by an embodiment of the present disclosure;

[0033] Figure 3 It is a structural diagram of an active total layer;

[0034] Figure 4 is a schematic diagram of the source and drain pattern layer, where the unfilled boxes represent the via locations;

[0035] Figure 5 is a schematic diagram of a first gate pattern layer;

[0036] Figure 6 is a schematic diagram of a second gate pattern layer;

[0037] Figure 7 The relative position relationship between the wiring pattern layer and the pixel opening;

[0038] Figure 8 is a schematic diagram showing the overlapping relationship between the first active connection portion and the power line;

[0039] Figure 9 It is a schematic diagram showing the relative positional relationship between the initialization connection member and the second column active portion. DETAILED DESCRIPTION

[0040] The following describes the specific embodiments of the present invention in detail with reference to the accompanying drawings. It should be understood that the specific embodiments described herein are only used to illustrate and explain the present invention and are not intended to limit the present invention.

[0041] As a first aspect of the present disclosure, a display substrate is provided, comprising a base substrate, a drive circuit layer formed on the base substrate, and a plurality of light-emitting elements. The display substrate is divided into a plurality of pixel units arranged in multiple rows and columns, and the drive circuit layer includes a plurality of pixel circuits corresponding to the plurality of pixel units, wherein the pixel circuits are configured to drive the light-emitting elements to emit light.

[0042] In this disclosure, the specific circuit structure of the pixel circuit is not particularly limited. It should be noted that in order to implement the data writing function, the pixel circuit should have a data writing transistor, and in order to control the light-emitting element's light-emitting timing, the pixel circuit should have at least a first light-emitting control transistor.

[0043] As an optional implementation, the pixel circuit may be a 7T1C pixel circuit. Figure 1 The figure shows a 7T1C pixel circuit. Specifically, the pixel circuit includes a compensation transistor T1, a second reset transistor T2, a drive transistor T3, a data write transistor T4, a first emission control transistor T5, a second emission control transistor T6, a first reset transistor T7, and a compensation capacitor Cst. Accordingly, the second trace includes a gate line Gate, a reset signal line Reset, an initial signal line Int, and an emission control signal line EM.

[0044] The gate of the driving transistor T3 is electrically connected to the first electrode of the compensation capacitor Cst, the source S3 of the driving transistor T3 is electrically connected to the drain D5 of the first light emitting control transistor T5, and the drain D3 of the driving transistor T3 is electrically connected to the first electrode of the compensation capacitor Cst.

[0045] A second electrode of the compensation capacitor Cst is electrically connected to the power line VDD.

[0046] The source S4 of the data writing transistor T4 is electrically connected to the data line Data, the drain D4 of the data writing transistor T4 is electrically connected to the source S3 of the driving transistor T3 , and the gate of the data writing transistor T4 is electrically connected to the scan line Gate.

[0047] The gate of the compensation transistor T1 is electrically connected to the gate line Gate, the source S1 of the compensation transistor T1 is electrically connected to the source S6 of the second light emitting control transistor T6, and the drain D1 of the compensation transistor T1 is electrically connected to the first electrode of the compensation capacitor Cst.

[0048] The gate of the first emission control transistor T5 is electrically connected to the emission control signal line EM, the source S5 of the first emission control transistor T5 is electrically connected to the power line VDD, and the drain D5 of the first emission control transistor T5 is electrically connected to the source S5 of the driving transistor T3.

[0049] The gate of the second emission control transistor T6 is electrically connected to the emission control signal line EM, the source S6 of the second emission control transistor T6 is electrically connected to the drain D3 of the driving transistor T3, and the drain D6 of the second emission control transistor T6 is electrically connected to the anode of the light emitting element.

[0050] A gate of the first reset transistor T7 is electrically connected to the reset signal line Reset, a source S7 of the first reset transistor T7 is electrically connected to the initial signal line Int, and a drain D7 of the first reset transistor T7 is electrically connected to the anode of the light emitting element.

[0051] The gate of the second reset transistor T2 is electrically connected to the reset signal line Reset, the source S2 of the second reset transistor T2 is electrically connected to the initial signal line Int, and the drain D2 of the second reset transistor T2 is electrically connected to the gate of the driving transistor T3.

[0052] Along the thickness direction of the display substrate, the driving circuit layer includes an active pattern layer and a source-drain pattern layer, and the source-drain pattern layer is arranged on a side of the active pattern layer away from the base substrate. Figure 2 As shown, the source-drain pattern layer includes multiple power lines VDD and multiple data lines Data. The length direction of the power lines DD and the data lines Data is the same as the column direction of the pixel units. Each column of pixel units corresponds to a power line VDD and a data line Data. Moreover, the power lines VDD and data lines Data corresponding to the same column of pixel units are arranged on the same side of the column of pixel units. Figure 2 In the embodiment shown in , the power line VDD and the data line Data are arranged on the right side of the pixel unit.

[0053] In the same pixel unit, the active layers of the thin film transistors of the pixel circuit are formed into an active total layer with an integrated structure, and the active graphic layer includes a plurality of the active total layers.

[0054] like Figure 2 and Figure 3 As shown, in the same pixel circuit, the active total layer includes a first column-directed active portion, the first column-directed active portion includes an active layer CH4 of the data writing transistor T4, an active layer CH5 of the first light emission control transistor T5, and a first active connection portion A connected between the active layer CH4 of the data writing transistor T4 and the active layer CH5 of the first light emission control transistor T5, and an orthographic projection of the first active connection portion A on the base substrate at least partially overlaps with an orthographic projection of the corresponding power line VDD on the base substrate (at the bottom of the substrate). Figure 2 In the embodiment, such “at least partial overlap” is manifested as the first active connection portion A being blocked by the power line VDD. Figure 8 , showing an overlapping relationship between the first active connection portion A and the power line VDD), a size of the first active connection portion A along the row direction of the pixel unit (i.e., a width of the first active connection portion) is smaller than a size of the active layer CH4 of the data writing transistor T4 along the row direction of the pixel unit, and a size of the first active connection portion A along the row direction of the pixel unit is smaller than a size of the active layer CH5 of the first light emitting control transistor T5 along the row direction of the pixel unit.

[0055] The display substrate provided by the present disclosure cooperates with the light-emitting element layer and the encapsulation layer to form a display panel. The light-emitting element layer includes multiple light-emitting elements, and the driving circuit layer is used to drive the multiple light-emitting elements to emit light.

[0056] In a display panel, the number of pixel units is the same as the number of light-emitting elements. The higher the resolution of the display panel, the more pixel units there are. Correspondingly, the size of each pixel unit is also smaller. In the present disclosure, the active layers of each thin-film transistor in the same pixel circuit are formed into an active total layer with an integrated structure. That is, a relatively large active total layer is formed using a patterning process, which can provide an active layer for each thin-film transistor in the same pixel unit, thereby reducing the precision requirements for manufacturing equipment and thereby reducing manufacturing costs.

[0057] In the present disclosure, both the power line VDD and the data line Data are metal traces. In the display substrate, the metal traces and the active total layer of each pixel unit are non-light-transmitting film layers that account for a large proportion in the backplane circuit, which will have a significant impact on the transmittance of the display panel including the display substrate. Since the width of the first active connection portion is small and the power line VDD overlaps with the first active connection portion A, the proportion of the non-light-transmitting film layer in the pixel unit is reduced, thereby improving the transmittance of the display panel. After the transmittance of the display panel is improved, more pixel units can be arranged in a limited space, thereby improving the resolution of the display panel.

[0058] The display substrate provided by the present disclosure can improve resolution while reducing manufacturing costs.

[0059] In the present disclosure, there is no particular limitation on the material of the active overall layer. For example, the active overall layer may be made of polysilicon material.

[0060] like Figure 3 As shown in the embodiment of the present disclosure, the active layers of the compensation transistor T1, the second reset transistor T2, the drive transistor T3, the data writing transistor T4, the first emission control transistor T5, the second emission control transistor T6, and the first reset transistor T7 are formed into an integrated active layer. To further simplify the manufacturing process, the active layers corresponding to multiple pixel units in the same column can optionally be formed into an integrated structure.

[0061] The transistor T1, the second reset transistor T2, the driving transistor T3, the data writing transistor T4, the first light emission control transistor T5, the second light emission control transistor T6, and the first reset transistor T7 may have a top gate structure. That is, in the display substrate, in the direction away from the base substrate, the active pattern layer including each active layer, the first gate pattern layer (see Figure 5 , including the gate line Gate, the light emitting control signal line EM, the reset signal line Rese, the first electrode Cst1 of the compensation capacitor Cst), the second gate pattern layer (see Figure 6 , including the initial signal line Int, the second electrode Cst2 of the compensation capacitor Cst, and the voltage stabilizing pattern L), the source and drain pattern layer (see Figure 4 , including data line Data and power line VDD).

[0062] It should be noted that an inorganic insulating spacer is provided between the active pattern layer and the first gate pattern layer, an inorganic insulating spacer is provided between the first gate pattern layer and the second gate pattern layer, and an inorganic insulating spacer is also provided between the second gate pattern layer and the source / drain pattern layer.

[0063] There is no special restriction on the specific layout of each graphic layer. Figure 2 、 Figure 4 In the specific implementation shown in , the data line Data and the power line VDD corresponding to the same column of pixel units are adjacently arranged and located on the same side of the pixel units.

[0064] In the same pixel unit, since the gate G1 of the compensation transistor T1 and the gate G4 of the data write transistor T4 are both electrically connected to the gate line Gate, for ease of arrangement, the compensation transistor T1 and the data write transistor T4 can be arranged side by side with an interval. Since the data write transistor T4 needs to be electrically connected to the data line Data, the data write transistor T4 is arranged closer to the data line Data than the compensation transistor T1.

[0065] The gate line G5 of the first emission control transistor T5 and the gate G6 of the second emission control transistor T6 are both electrically connected to the emission control signal line EM. For ease of arrangement, the first emission control transistor T5 and the second emission control transistor T6 can be arranged side by side with an interval. Since the source S5 of the first emission control transistor T5 needs to be electrically connected to the power line VDD, the first emission control transistor T5 is arranged closer to the power line VDD than the second emission control transistor T6.

[0066] As described above, the data line Data and the power line VDD are connected and are both arranged on the same side of the pixel unit. Accordingly, the data is written into the active layer ( Figure 3 CH4 in) and the active layer of the first light emission control transistor T5 ( Figure 3 CH5 in FIG1 is also located on the same side of the pixel unit.

[0067] exist Figure 1 In the pixel circuit shown in , the first reset transistor T7 is used to reset the anode of the light-emitting element. In the present disclosure, the first gate pattern layer may further include an initialization connector B. One end of the initialization connector B is electrically connected to the initialization signal line Int through a via hole, and the other end of the initialization connector B is connected to the portion corresponding to the first reset transistor T7 on the active layer through a via hole. The length direction of the initialization connector B is consistent with the column direction of the pixel unit. The distance between the column center lines of the via holes at both ends of the initialization connector (i.e., Figure 9 The distance W2 between the column-wise center line L1 and the column-wise center line L2 does not exceed a predetermined distance.

[0068] It should be noted that the “column center line” mentioned here refers to a line passing through the center of the via hole and extending along the column direction (ie, Figure 9 The column-wise center line L1 and the column-wise center line L2).

[0069] As described above, since the distance between the column center lines of the two via holes of the initialization connection member B does not exceed the predetermined distance, this means that the initialization connection member B has a substantially linear structure and a smaller area, which is beneficial to improving the transmittance of the pixel unit.

[0070] In the present disclosure, there is no particular limitation on the predetermined distance, as long as the initialization connector B is a substantially linear structure. As an optional embodiment, the predetermined distance is between 0.1 μm and 0.5 μm.

[0071] In order to further ensure that the initialization connection member B is a substantially linear structure, optionally, the orthographic projection d1 of the via hole at one end of the initialization connection member B on the reference line O extending along the row direction overlaps with the orthographic projection d2 of the via hole at the other end of the initialization connection member B on the reference line (i.e., Figure 9 d3 in FIG). The overlap between the orthographic projection d1 of the via hole at one end of initialization connector B on reference line O extending along the row direction and the orthographic projection d2 of the via hole at the other end of initialization connector B on the reference line indicates that the deviation between the two ends of the initialization connector is not large. As an optional embodiment, the width of initialization connector B does not exceed two-thirds the width of power line VDD, and the width d3 between the orthographic projection d1 of the via hole at one end of initialization connector B on reference line O extending along the row direction and the orthographic projection d2 of the via hole at the other end of initialization connector B on the reference line is not less than one-half the width of initialization connector B.

[0072] In order not to improve the transmittance of the pixel unit, optionally, the active layer includes a second column-oriented active portion, such as Figure 3 As shown, the second column active portion includes the active layer CH7 of the first reset transistor T7. Figure 2 As shown, the orthographic projection of the B initialization connecting member on the substrate partially overlaps with the orthographic projection of the second column active portion on the substrate ( Figure 9 W1 shows the overlap width).

[0073] The second reset transistor T2 is used to reset the gate of the driving transistor T3. Since the first reset transistor T7 and the second reset transistor T7 share a reset signal line Reset, the first reset transistor T7 and the second reset transistor T2 can be arranged adjacent to each other. Correspondingly, the active layer also includes a third column-oriented active portion and a fourth column-oriented active portion. The third column-oriented active portion is connected to the second column-oriented active portion via a second active connection portion C, and the fourth column-oriented active portion is connected to the third column-oriented active portion via a third active connection portion D. One end of the third column-oriented active portion is connected to the second active connection portion C, and the other end of the third column-oriented active portion is connected to the third active connection portion D. A corresponding reset signal line passes through the second, third, and fourth column-oriented active portions in sequence. The portion of the second column-oriented active portion where the reset signal line Reset passes forms the active layer CH7 of the first reset transistor, and the portions of the third and fourth column-oriented active portions where the reset signal line Reset passes form the active layer CH2 of the second reset transistor. It can be seen that the second reset transistor CH2 has a dual-gate structure.

[0074] In order to facilitate the provision of the initialization connection member B having a substantially straight structure, a via hole corresponding to the other end of the initialization connection member B is located on the second active connection portion C.

[0075] The relative positions of the first reset transistor T7 and the second reset transistor T2 in the pixel unit have been described above. For ease of arrangement, as an optional implementation, the compensation transistor T1, the driving transistor T3 and the second light-emitting control transistor T6 can be arranged in sequence along the column direction on one side of the first reset transistor T7.

[0076] To facilitate the formation of the active layer, the active layer CH1 of the compensation transistor T1 and the active layer CH6 of the second emission control transistor T6 can be located on the same straight line, forming a fourth column-oriented active portion. Furthermore, the column-oriented active portion, including the active layer CH1 of the compensation transistor T1 and the active layer CH6 of the second emission control transistor T6, is spaced apart from the fourth column-oriented active portion, including the active layer CH4 of the data write transistor T4 and the active layer CH5 of the first emission control transistor T5. The active layer of the drive transistor T3 is connected between the fourth column-oriented active portion, including the active layer CH1 of the compensation transistor T1 and the active layer CH6 of the second emission control transistor T6, and the first column-oriented active portion, including the active layer CH4 of the data write transistor T4 and the active layer CH5 of the first emission control transistor T5.

[0077] To improve the switching performance of the compensation transistor T1, the compensation transistor T1 may optionally have a dual-gate structure. In the present disclosure, the gate line Gate may be configured to include a transverse gate line portion Gate1 and a longitudinal gate line portion Gate2 formed on the transverse gate line portion, with each transverse gate line portion Gate1 being provided with multiple longitudinal gate line portions Gate2. The length direction of the transverse gate line portion Gate1 is aligned with the row direction of the pixel unit.

[0078] By arranging the active layer to pass through the horizontal gate line portion Gate1 and the vertical gate line portion Gate2 in the same pixel unit, a compensation transistor T1 with a double-gate structure can be realized.

[0079] As described above, the pixel circuit further includes a first light emission control transistor T5, a second light emission control transistor T6, a driving transistor T3, a compensation transistor T1 and a compensation capacitor Cst.

[0080] As described above, for ease of layout, the first electrode Cst1 of the compensation capacitor Cst can be disposed on the same layer as the gate line Gate, the light-emission control signal line EM, and the reset signal line Reset. In the present disclosure, the first gate pattern layer may further include multiple capacitor connectors E, each of which is provided in each pixel unit. One end of each capacitor connector E is electrically connected to the first electrode Cst1 of the compensation capacitor Cst through a via, and the other end of each capacitor connector E is connected to the active main layer through a via to form the drain electrode D1 of the compensation transistor T1.

[0081] In the present application, the first electrode Cst1 of the compensation capacitor Cst and the second electrode Cst2 of the compensation capacitor Cst are respectively located in different layers, and the interlayer spacing between the second electrode Cst2 of the compensation capacitor Cst and the capacitor connector E is smaller. In order to facilitate the electrical connection of the capacitor connector E to the first electrode Cst1 of the compensation capacitor Cst through a via, the compensation capacitor Cst2 can be configured to have a capacitor opening, the orthographic projection of the capacitor opening on the substrate overlaps with the orthographic projection of the first electrode Cst1 of the compensation capacitor Cst on the substrate, thereby facilitating the formation of a via connecting the capacitor connector E and the first electrode Cst1.

[0082] In the present disclosure, the shape of the active layer CH3 of the driving transistor T3 may also be consistent with a portion of the outer contour of the first electrode Cst1 of the compensation capacitor Cst.

[0083] exist Figure 4 In addition to showing the shapes of the various components in the source and drain pattern layer, the shapes of the vias electrically connected to the various components in the second wiring pattern layer are also shown. Figure 4 The via holes shown in FIG. 1 are all via holes that penetrate the inorganic insulating layer.

[0084] like Figure 4 As shown in FIG, two via holes are formed at both ends of the initialization connection member B, and two via holes are formed at both ends of the capacitor connection member E. Figure 4 From bottom to top, three vias are provided on the power line VDD (i.e., for the same pixel unit, the power line VDD corresponds to three vias), namely a via connected to the active layer of the first light-emitting control transistor T5 (hereinafter referred to as the lower via for ease of description), a via electrically connected to the second electrode of the compensation capacitor Cst (hereinafter referred to as the middle via for ease of description), and a via connected to the portion of the active layer between the active layer of the compensation transistor T1 and the active layer of the second reset transistor T2 (hereinafter referred to as the upper via for ease of description). That is, in the same pixel unit, of the three vias corresponding to the power line VDD, except for the middle via, the upper and lower vias are all electrically connected to the active layer.

[0085] The portion of the power line VDD connected to the lower via corresponds to the source of the first light-emitting control transistor T5. The portion of the power line VDD connected to the middle via corresponds to the drain of the second reset transistor T2, which is electrically connected to the gate of the drive transistor T3 and the drain of the compensation transistor T1.

[0086] The display substrate may include a plurality of pixel unit groups, wherein every three adjacent pixel units or every four adjacent pixel units may form a pixel unit group.

[0087] In the case where a pixel unit group includes four pixel units, the four pixel units may be a red pixel unit, two green pixel units, and one blue pixel unit. Accordingly, the light-emitting element in the red pixel unit is a red organic light-emitting diode, the light-emitting element in the green pixel unit is a green organic light-emitting diode, and the light-emitting element in the blue pixel unit is a blue organic light-emitting diode.

[0088] exist Figure 7 In the specific embodiment shown in , the arrangement order of the four pixel units in the same pixel unit group along the row direction is: blue pixel unit (showing the anode pattern Bp and pixel opening Bo of the blue light-emitting element), green pixel unit (showing the anode pattern Gp and pixel opening Go of the green light-emitting element), red pixel unit (showing the anode pattern Rp and pixel opening Ro of the red light-emitting element) and green pixel unit (showing the anode pattern Gp and pixel opening Go of the green light-emitting element).

[0089] Accordingly, the source-drain pattern includes anode connectors corresponding to anode patterns of light-emitting diodes of three colors. Specifically, Figure 4As shown in FIG, the source-drain pattern layer includes an anode connector Pb of a blue light emitting diode, an anode connector Pg of a green light emitting diode, and an anode connector Pg of a red light emitting diode.

[0090] The display substrate may further include a planarization layer covering the source / drain pattern layer, wherein pixel openings corresponding to the respective pixel units are formed on the planarization layer, and a portion of the light emitting element except the anode is formed in the pixel opening.

[0091] In the present disclosure, the specific structure of the light emitting element other than the anode is not particularly limited. For example, when the light emitting element is an organic light emitting diode, the light emitting element includes a light emitting layer and a cathode in addition to the anode.

[0092] As an optional embodiment, the light-emitting layer may include a hole transport layer, an organic light-emitting layer, and an electron transport layer sequentially arranged in a direction away from the anode.

[0093] To facilitate manufacturing, the cathodes of different light-emitting elements are formed into an integrated structure.

[0094] Figure 7 1 shows the opening shapes of four pixel units in the same pixel unit group. As shown in the figure, in the row direction, a blue pixel unit, a green pixel unit, a red pixel unit and a green pixel unit are arranged in sequence.

[0095] The display substrate further includes a planarization layer, on which a pixel opening corresponding to the pixel unit is formed, and a portion of the light emitting element except the anode is disposed in the opening.

[0096] Among the four pixel units in the same pixel unit group, the pixel opening Bo corresponding to the blue pixel unit has the largest size along the row direction, and the pixel opening Ro corresponding to the red pixel unit has the smallest size along the row direction.

[0097] To facilitate obtaining a smooth planarization layer, as an optional embodiment, the display substrate further includes multiple width spacers H disposed in the same layer as the data lines. Each red pixel unit is provided with a width spacer H, located on the side of the red pixel unit away from the blue pixel unit. As mentioned above, the pixel opening Ro of the red pixel unit is smallest along the row direction. Therefore, the planarization layer in the row direction of the red pixel unit occupies a larger area, and its flatness has a greater impact on the light-emitting effect of the red pixel unit.

[0098] When forming a planarization layer, the organic material used to form the planarization layer is first applied, followed by a curing process. The presence of a width spacer H in the red pixel unit R facilitates the leveling of the organic material after application, thereby forming a planarization layer with a flat surface during the curing process. As an optional embodiment, the length of the width spacer H aligns with the length of the data line Data.

[0099] Specifically, the orthographic projection of the width pad H on the base substrate is located in the overlapping portion of the orthographic projection of the anode pattern Rp of the red pixel unit arranged on the width pad H on the base substrate and the orthographic projection of the pixel opening Ro of the red pixel unit on the base substrate.

[0100] In the present disclosure, there is no special limitation on the arrangement of the pixel openings in the same pixel unit group. Figure 7 In the embodiment shown in , in the same row of pixel units, the anode connectors (anode connector Pb, anode connector Pg, anode connector Pr and anode connector Pb) of the light-emitting elements are arranged in a row, the blue pixel opening, the red pixel opening, and the green pixel opening located on the side of the red pixel opening away from the blue pixel opening are located on one side of the row in which the anode connectors are arranged, and the green pixel opening located between the red pixel opening and the blue pixel opening is located on the other side of the row in which the anode connectors are arranged.

[0101] As a second aspect of the present disclosure, a display panel is further provided, comprising the above-mentioned display substrate provided by the present disclosure.

[0102] Compared with a display panel in the related art that does not adopt the display substrate provided by the present disclosure, the transmittance of the display panel that adopts the display substrate provided by the present disclosure is increased by at least 3%.

[0103] Optionally, the display panel may further include a packaging cover for packaging the display substrate, and other structures.

[0104] It is understood that the above embodiments are merely exemplary embodiments for illustrating the principles of the present disclosure, and the present disclosure is not limited thereto. Those skilled in the art may make various modifications and improvements without departing from the spirit and substance of the present disclosure, and such modifications and improvements are also considered to be within the scope of protection of the present disclosure.

Claims

1. A display substrate, characterized in that: The display substrate includes a base substrate and a driving circuit layer and a plurality of light-emitting elements formed on the base substrate. The display substrate is divided into a plurality of pixel units arranged in a plurality of rows and columns. The driving circuit layer includes a plurality of pixel circuits corresponding to the plurality of pixel units. The pixel circuits are used to drive the light-emitting elements to emit light. Along the thickness direction of the display substrate, the driving circuit layer includes an active pattern layer and a source-drain pattern layer, the source-drain pattern layer is arranged on a side of the active pattern layer away from the base substrate, and the source-drain pattern layer includes a plurality of power lines and a plurality of data lines, the length direction of the power lines and the data lines being the same as the column direction of the pixel units, each column of pixel units corresponding to the power lines and the data lines, and the power lines and data lines corresponding to the same column of pixel units are arranged on the same side of the column of pixel units; The pixel circuit includes a plurality of thin film transistors, and in a same pixel unit, the active layers of the thin film transistors of the pixel circuit are formed into an active total layer with an integrated structure, and the active graphic layer includes a plurality of the active total layers; The plurality of thin film transistors of the pixel circuit include a data writing transistor and a first light emission control transistor. In the same pixel circuit, the active overall layer includes a first column-oriented active portion, the first column-oriented active portion including an active layer of the data writing transistor, an active layer of the first light emission control transistor, and a first active connection portion connected between the active layer of the data writing transistor and the active layer of the first light emission control transistor. The orthographic projection of the first active connection portion on the substrate at least partially overlaps with the orthographic projection of the corresponding power line on the substrate. The dimension of the first active connection portion along the row direction of the pixel unit is smaller than the dimension of the active layer of the data writing transistor along the row direction of the pixel unit, and the dimension of the first active connection portion along the row direction of the pixel unit is smaller than the dimension of the active layer of the first light emission control transistor along the row direction of the pixel unit. The plurality of thin film transistors of the pixel circuit include a first reset transistor, wherein the first reset transistor is used to reset the anode of the light emitting element; Along the thickness direction of the display substrate, the driving circuit layer includes a first gate pattern layer and a second gate pattern layer stacked together, the first gate pattern layer and the second gate pattern layer are both located between the active pattern layer and the source / drain pattern layer, and the second gate pattern layer is located on a side of the first gate pattern layer away from the active pattern layer; The first gate graphic layer includes a reset signal line, the second gate graphic layer includes an initial signal line, and the source-drain graphic layer further includes an initialization connector, one end of the initialization connector is electrically connected to the initial signal line through a via, and the other end of the initialization connector is connected to a portion of the active layer corresponding to the first reset transistor through a via, the length direction of the initialization connector is consistent with the column direction of the pixel unit, and the distance between the column center lines of the vias at both ends of the initialization connector does not exceed a predetermined distance.

2. The display substrate according to claim 1, wherein: The predetermined distance is between 0.1 μm and 0.5 μm.

3. The display substrate according to claim 1, wherein An orthographic projection of the via hole at one end of the initialization connector on a reference line extending along the row direction overlaps with an orthographic projection of the via hole at the other end of the initialization connector on the reference line.

4. The display substrate according to claim 1, wherein The active overall layer includes a second column-oriented active portion, which includes an active layer of the first reset transistor. The orthographic projection of the initialization connector on the base substrate partially overlaps with the orthographic projection of the second column-oriented active portion on the base substrate.

5. The display substrate according to claim 4, wherein: The pixel circuit includes a second reset transistor and a driving transistor, wherein the second reset transistor is used to reset the gate of the driving transistor; The active overall layer further includes a third column-oriented active portion and a fourth column-oriented active portion, the third column-oriented active portion being connected to the second column-oriented active portion via a second active connection portion, the fourth column-oriented active portion being connected to the third column-oriented active portion via a third active connection portion, and one end of the third column-oriented active portion being connected to the second active connection portion, and the other end of the third column-oriented active portion being connected to the third active connection portion, a corresponding reset signal line sequentially passing through the second column-oriented active portion, the third column-oriented active portion, and the fourth column-oriented active portion, a portion of the second column-oriented active portion through which the reset signal line passes forms an active layer of the first reset transistor, and portions of the third column-oriented active portion and the fourth column-oriented active portion through which the reset signal line passes form an active layer of the second reset transistor; A via hole corresponding to the other end of the initialization connector is located on the second active connection portion.

6. The display substrate according to claim 1, wherein: The first gate pattern layer further includes a plurality of gate lines, each row of pixel units corresponds to a gate line, and the pixel circuit includes a compensation transistor. The gate line includes a transverse portion and a longitudinal portion, each pixel unit corresponds to a longitudinal portion, and the active layer of the compensation transistor includes a portion of the active layer passing through the transverse portion and a portion of the active layer passing through the longitudinal portion.

7. The display substrate according to any one of claims 1 to 4, characterized in that: Every four adjacent pixel units form a pixel unit group, and the four pixel units are respectively a red pixel unit, two green pixel units and one blue pixel unit.

8. The display substrate according to claim 7, wherein: In the same pixel unit group, the arrangement order of the four pixel units along the row direction is: A blue pixel unit, a green pixel unit, a red pixel unit and a green pixel unit.

9. The display substrate according to claim 8, wherein: The display substrate further includes a planarization layer, which is disposed on a side of the source / drain pattern layer away from the base substrate. A pixel opening corresponding to a pixel unit is formed on the planarization layer, and a portion of the light-emitting element except the anode is disposed in the pixel opening. Among the four pixel units in the same pixel unit group, the pixel opening corresponding to the blue pixel unit has the largest size along the row direction, and the pixel opening corresponding to the red pixel unit has the smallest size along the row direction.

10. The display substrate according to claim 9, wherein: The display substrate further includes a plurality of width pads arranged in the same layer as the data lines. Each of the red pixel units is provided with the width pads, and the width pads are arranged on a side of the red pixel unit away from the blue pixel unit.

11. The display substrate according to claim 10, wherein: The orthographic projection of the width pad on the base substrate is located in an overlapping portion of an orthographic projection of an anode pattern of a red pixel unit arranged on the width pad on the base substrate and an orthographic projection of a pixel opening of the red pixel unit on the base substrate.

12. The display substrate according to claim 11, wherein: The length direction of the width pad is consistent with the length direction of the data line.

13. The display substrate according to claim 9, wherein: The source-drain pattern layer includes a plurality of anode connectors, one anode connector corresponding to each light-emitting element, and the anode connector is electrically connected to the anode pattern of the corresponding light-emitting element. In the same row of pixel units, the anode connectors corresponding to the light-emitting elements are arranged in a row. The blue pixel opening, the red pixel opening, and the green pixel opening located on the side of the red pixel opening away from the blue pixel opening are located on one side of the row formed by the anode connectors, and the green pixel opening located between the red pixel opening and the blue pixel opening is located on the other side of the row formed by the anode connectors.

14. A display panel, characterized in that: The display panel includes the display substrate according to any one of claims 1 to 13.

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