Switching elements

Abstract

A switching element having multiple trench-type gate electrodes. The semiconductor substrate comprises: an n-type drift region in contact with a gate insulating film at the bottom and side surfaces of each trench; a p-type body region in contact with the gate insulating film above the drift region; multiple p-type bottom regions arranged directly below the trenches and spaced apart from the gate insulating film; and a p-type connection region connecting each of the bottom regions to the body region. Half the depletion layer extension distance required to deplete the gap between adjacent bottom regions is longer than both the depletion layer extension distance required to deplete the gap between the body region and the lower end of the trench and the depletion layer extension distance required to deplete the gap between the bottom region and the lower end of the trench.

Description

Technical Field

[0001] The technology disclosed in this specification relates to a switching element. Background Art

[0002] Japanese Patent Application Publication No. 2009-158681 discloses a trench-gate switching element. This switching element has a p-type bottom region (bottom p-type layer) directly below the trench and separated from the gate insulating film. The bottom region is surrounded by an n-type drift region. When the switching element is off, a depletion layer extends from the body region and the bottom region into the drift region. This depletion layer extending from the bottom region suppresses electric field concentration near the lower end of the trench. Summary of the Invention

[0003] Problems to be solved by the invention

[0004] Figure 9 The results of a simulation of the distribution of the depletion layer in a process in which a switching element having a bottom region is switched from on to off are shown. Figure 9 The switching element has a bottom region 910, a drift region 912, a body region 914, and a gate electrode 916 provided in a trench. Figure 9 In FIG, reference numeral 910x represents a depletion layer extending from each bottom region 910 into the drift region 912. The depletion layers extending from each bottom region 910 are connected to each other, thereby forming a layered depletion layer 910x. Reference numeral 914x represents a depletion layer extending from the body region 914 into the drift region 912. Reference numerals 924 and 926 represent undepleted regions (hereinafter referred to as non-depleted regions) within the drift region 912. Figure 9 In this manner, if the depletion layers extending from each bottom region 910 connect to each other before connecting to the depletion layer 914x extending from the body region 914, forming a layered depletion layer 910x, a non-depleted region 924 remains between the depletion layer 910x and the depletion layer 914x. In this state, since the non-depleted region 924 is separated from the non-depleted region 926, the potential of the non-depleted region 924 becomes floating. In this case, the non-depleted region 924 is difficult to deplete and remains until the voltage applied to the switching element increases. If the non-depleted region 924 remains in the area adjacent to the trench, a high electric field is easily applied to the gate insulating film, which is likely to degrade the gate insulating film. This specification proposes a switching element structure that makes it difficult for a non-depleted region to remain in a floating state within the drift region.

[0005] Means for solving problems

[0006] The switching element disclosed in this specification comprises: a semiconductor substrate; a plurality of trenches provided on the upper surface of the semiconductor substrate; a plurality of gate insulating films covering the inner surfaces of the corresponding trenches; and a plurality of gate electrodes disposed within the corresponding trenches and insulated from the semiconductor substrate by the corresponding gate insulating films. The semiconductor substrate comprises: an n-type drift region in contact with the gate insulating film at the bottom and side surfaces of each trench; a p-type body region in contact with the gate insulating film at the side surfaces of each trench above the drift region; an n-type source region in contact with the gate insulating film at the side surfaces of each trench above the body region and separated from the drift region by the body region; a plurality of p-type bottom regions disposed directly below the corresponding trenches and spaced apart from the gate insulating film; and a p-type connection region connecting each bottom region to the body region. The depth of the bottom end of each trench and the distance between the bottom end and the body region are defined by a distance L1. The n-type impurity concentration of the drift region within the range between the depth of the lower end of each trench and the body region is concentration N1. The distance between the depth of the lower end of each trench and the depth of the upper end of each bottom region is distance L2. The n-type impurity concentration of the drift region within the range between the depth of the lower end of each trench and the depth of the upper end of each bottom region is concentration N2. The distance between adjacent bottom regions is distance L3. The n-type impurity concentration of the drift region within the range between adjacent bottom regions is N3. The following relationship is satisfied: Formula 1 and Formula 2.

[0007] [Formula 1]

[0008]

[0009]

[0010] If equations 1 and 2 are satisfied, when the switching element is turned off, the depletion layer extending from the body region connects with the depletion layer extending from each bottom region before the depletion layers extending from each bottom region connect with each other. This prevents the presence of a floating, non-depleted region within the drift region. Consequently, in this switching element, the gate insulating film is less likely to degrade. BRIEF DESCRIPTION OF THE DRAWINGS

[0011] Figure 1 It is a perspective view including a cross section of the MOSFET of the embodiment.

[0012] Figure 2 yes Figure 1 Cross-sectional view at plane II.

[0013] Figure 3 yes Figure 1 Cross-sectional view at plane III.

[0014] Figure 4 This is a diagram showing the drift region divided into sections.

[0015] Figure 5 It is a cross-sectional view showing the extension of the depletion layer.

[0016] Figure 6 It is a cross-sectional view showing the extension of the depletion layer.

[0017] Figure 7 is a cross-sectional view showing the extension of the depletion layer.

[0018] Figure 8 It is a cross-sectional view showing the extension of the depletion layer.

[0019] Figure 9 This is a cross-sectional view showing the distribution of the depletion layer when a non-depleted region in a floating state remains. DETAILED DESCRIPTION

[0020] The following are additional features of the configuration disclosed in this specification. In addition, each of the features listed below is useful independently.

[0021] In the switching element of one example disclosed in this specification, the relationship of the following formula 3 can also be satisfied.

[0022] [Formula 2]

[0023]

[0024] By satisfying Expression 3, the loss generated in the switching element can be reduced.

[0025] In the switching element of one example disclosed in this specification, the relationship N2 < N1 can also be satisfied.

[0026] By satisfying the relationship N2 < N1, the loss generated in the switching element can be reduced.

[0027] (Example 1) Figures 1 to 3 A MOSFET (metal-oxide-semiconductor field effect transistor) 10 according to Example 1 is shown. MOSFET 10 includes a semiconductor substrate 12. Hereinafter, a direction parallel to an upper surface 12a of semiconductor substrate 12 is referred to as the x-direction, a direction parallel to upper surface 12a and perpendicular to the x-direction is referred to as the y-direction, and the thickness direction of semiconductor substrate 12 is referred to as the z-direction. Figure 2 yes Figure 1 The cross-sectional view at plane II, Figure 3 yes Figure 1 The cross-sectional view at plane III of Figure 2、 3 As shown in FIG. 1 , electrodes, an insulating film, etc. are provided on the upper surface 12a of the semiconductor substrate 12. Figure 1 In FIG. 1 , for the sake of explanation, illustration of electrodes and insulating films on the upper surface 12 a of the semiconductor substrate 12 is omitted.

[0028] The semiconductor substrate 12 is made of silicon carbide (SiC). A plurality of grooves 22 are provided on the upper surface 12a of the semiconductor substrate 12. Figure 1 As shown, multiple trenches 22 extend parallel to each other on the upper surface 12a. The multiple trenches 22 extend linearly and elongated along the y-direction on the upper surface 12a. The multiple trenches 22 are arranged at intervals in the x-direction. A gate insulating film 24 and a gate electrode 26 are disposed within each trench 22.

[0029] The gate insulating film 24 covers the inner surface of the trench 22. The gate insulating film 24 includes a side insulating film 24a covering the side surfaces of the trench 22 and a bottom insulating film 24b covering the bottom surface of the trench 22. The gate insulating film 24 is made of silicon oxide.

[0030] The gate electrode 26 is disposed in the trench 22. The gate electrode 26 is insulated from the semiconductor substrate 12 by the gate insulating film 24. Figure 2 、 3 As shown, the upper surface of the gate electrode 26 is covered with an interlayer insulating film 28 .

[0031] like Figure 2 、 3 As shown, a source electrode 70 is disposed on the upper surface 12a of the semiconductor substrate 12. The source electrode 70 covers the upper surface 12a and the interlayer insulating film 28. The source electrode 70 is in contact with the upper surface 12a of the semiconductor substrate 12 in the portion where the interlayer insulating film 28 is not provided. The source electrode 70 is insulated from the gate electrode 26 by the interlayer insulating film 28. A drain electrode 72 is disposed on the lower surface 12b of the semiconductor substrate 12. The drain electrode 72 is in contact with the lower surface 12b of the semiconductor substrate 12.

[0032] like Figure 1 As shown, a plurality of source regions 30 , a body region 32 , a plurality of bottom regions 36 , a drift region 34 , and a drain region 35 are provided inside the semiconductor substrate 12 .

[0033] Each source region 30 is an n-type region. Figure 1 、 2 As shown in FIG. 1 , a plurality of source regions 30 are arranged in each of the semiconductor regions (hereinafter referred to as inter-trench regions) sandwiched between two adjacent trenches 22. Figure 1 As shown, in each inter-trench region, a plurality of source regions 30 are arranged at intervals along the y direction. Figure 2As shown, each source region 30 is disposed in an area facing the upper surface 12a of the semiconductor substrate 12 and is in ohmic contact with the source electrode 70. Each source region 30 is in contact with two trenches 22 located on either side of the inter-trench region. Each source region 30 is in contact with the side insulating film 24a at the upper end of the trench 22.

[0034] The body region 32 is a p-type region and includes a plurality of body contact regions 32 a and a low-concentration body region 32 b.

[0035] Each body contact region 32a is a p-type region with a high p-type impurity concentration. Figure 1 As shown, each body contact region 32a is provided in the inter-trench region. Each body contact region 32a is arranged in the range facing the upper surface 12a of the semiconductor substrate 12. A plurality of body contact regions 32a are arranged in each inter-trench region. In each inter-trench region, the source regions 30 and the body contact regions 32a are arranged alternately along the y direction. Therefore, the body contact region 32a is arranged between the two source regions 30. Figure 3 As shown, each body contact region 32 a is in ohmic contact with the source electrode 70 .

[0036] The low-concentration body region 32b is a p-type region having a lower p-type impurity concentration than the body contact region 32a. Figures 1 to 3 As shown, the low-concentration body region 32b is arranged on the lower side of each source region 30 and each body contact region 32a. The low-concentration body region 32b is connected to each source region 30 and each body contact region 32a from the lower side. The low-concentration body region 32b is distributed over the entire area below each source region 30 and each body contact region 32a. Figure 2 As shown, the low-concentration body region 32b is in contact with the side-surface insulating film 24a below the source region 30. The lower end of the low-concentration body region 32b is arranged above the lower end of the gate electrode 26.

[0037] like Figure 1 、 3 As shown, a connection region 38 extending downward from the low-concentration body region 32b is provided directly below the body contact region 32a. The connection region 38 extends to the lower side than the lower end of the trench 22. Figure 1 、 2 As shown, there is no connection region 38 directly below the source region 30. Figure 1 As shown, similar to the body contact region 32 a , the plurality of connection regions 38 are arranged at intervals in the y direction.

[0038] The drift region 34 is an n-type region with a low n-type impurity concentration. Figures 1 to 3As shown, the drift region 34 is arranged on the lower side of the body region 32 (more specifically, the low-concentration body region 32b) and the connection region 38. The drift region 34 is connected to the low-concentration body region 32b and the connection region 38. The drift region 34 is separated from each source region 30 by the low-concentration body region 32b. The drift region 34 is distributed from the inter-trench region to the region below the lower end of each trench 22. The drift region 34 is connected to the side insulating film 24a and the bottom insulating film 24b below the low-concentration body region 32b in a range where the connection region 38 does not exist. Below the lower end of the connection region 38, the drift region 34 is distributed over substantially the entire area of the semiconductor substrate 12 in the x-direction and the y-direction.

[0039] The drain region 35 is an n-type region having a higher n-type impurity concentration than the drift region 34. Figures 1 to 3 As shown, the drain region 35 is disposed below the drift region 34. The drain region 35 contacts the drift region 34 from below. The drain region 35 is provided in an area facing the lower surface 12b of the semiconductor substrate 12 and is in ohmic contact with the drain electrode 72.

[0040] like Figures 1 to 3 As shown, each bottom region 36 is arranged directly below the corresponding trench 22. Each bottom region 36 is arranged at a position away from the bottom surface of the corresponding trench 22. In other words, each bottom region 36 is arranged at a position away from the corresponding bottom insulating film 24b. In other words, a gap is provided between the bottom insulating film 24b and the bottom region 36. Figure 1 As shown, the bottom region 36 extends longer in the y direction along the bottom surface of the groove 22. Figure 2 In the cross section of , the bottom region 36 is surrounded by the drift region 34. Therefore, the drift region 34 is arranged in the gap between the bottom insulating film 24b and the bottom region 36. At the top of each bottom region 36, the drift region 34 is in contact with the bottom insulating film 24b. Figure 2 In the cross section of , the bottom region 36 is connected to the drift region 34 on its upper surface, side surface and lower surface. Figure 3 In the cross-section of FIG, each bottom region 36 is connected to the lower end of the connection region 38. As described above, the upper end of the connection region 38 is connected to the low-concentration body region 32b. Therefore, each bottom region 36 is connected to the low-concentration body region 32b via the connection region 38. Therefore, each bottom region 36 is connected to the source electrode 70 via the connection region 38, the low-concentration body region 32b, and the body contact region 32a. Therefore, the potential of the bottom region 36 is approximately equal to the potential of the source electrode 70.

[0041] Figure 4 FIG shows a diagram in which the drift region 34 is divided according to the position in the z direction. Figure 4, the drift region 34 is divided into an upper drift region 34a, a middle drift region 34b, and a lower drift region 34c. The upper drift region 34a is a portion of the drift region 34 that is within a range above the depth D1 of the lower end of each trench 22 (i.e., within a range between the depth of the lower end of each trench 22 and the body region 32). The middle drift region 34b is a portion of the drift region 34 that is within a range between the depth D1 of the lower end of each trench 22 and the depth D2 of the upper end of each bottom region 36. The lower drift region 34c is a portion that is within a range below the depth D2 of the upper end of each bottom region 36 (i.e., within a range between the depth D2 of the upper end of each bottom region 36 and the drain region 35). Hereinafter, the n-type impurity concentration in the upper drift region 34a is referred to as concentration N1, the n-type impurity concentration in the middle drift region 34b is referred to as concentration N2, and the n-type impurity concentration in the lower drift region 34c is referred to as concentration N3. Furthermore, hereinafter, the thickness of the upper drift region 34a (the distance between the depth D1 at the lower end of each trench 22 and the body region 32) is referred to as distance L1, and the thickness of the middle drift region 34b (the distance between the depth D1 at the lower end of each trench 22 and the depth D2 at the upper end of each bottom region 36) is referred to as distance L2. Furthermore, the distance between the bottom regions 36 (the distance in the x-direction) is referred to as distance L3.

[0042] In Example 1, N1 = N2 = N3. In Example 1, the relationships of L1 < L3 / 2, L2 < L3 / 2, and L2 < L1 are satisfied.

[0043] Next, the operation of the MOSFET 10 of Example 1 is described. When the MOSFET 10 is used, the MOSFET 10 and the load (e.g., a motor) are connected in series to the power supply. A power supply voltage is applied to the series circuit of the MOSFET 10 and the load. The power supply voltage is applied to the MOSFET 10 in such a direction that the drain electrode 72 becomes a voltage higher than the source electrode 70. If a voltage higher than the gate threshold is applied to the gate electrode 26, a channel is formed in the body region 32 in the area in contact with the gate insulating film 24, and the MOSFET 10 is turned on. When the MOSFET 10 is turned on, the depletion layer does not extend to the drift region 34. If the voltage applied to the gate electrode 26 is reduced to less than the gate threshold, the MOSFET 10 is turned off.

[0044] When the MOSFET 10 is turned off, the potential of the drain electrode 72 rises. The drift region 34 is connected to the drain electrode 72 via the drain region 35. The body region 32 is connected to the source electrode 70. In addition, the bottom region 36 is connected to the body region 32 via the connection region 38. Therefore, the potential of the bottom region 36 is approximately equal to the potential of the body region 32 (i.e., the potential of the source electrode 70). Therefore, if the potential of the drain electrode 72 rises relative to the potential of the source electrode 70, voltages are applied in opposite directions to the pn junction at the interface between the body region 32 and the drift region 34 and the pn junction at the interface between the bottom region 36 and the drift region 34. Therefore, the depletion layer expands from these pn junctions into the drift region 34. That is, as Figure 5 As shown, the depletion layer 32x extends from the body region 32 into the drift region 34, and the depletion layer 36x extends from each bottom region 36 into the drift region 34. As the potential of the drain electrode 72 increases, the depletion layers 32x and 36x expand.

[0045] The extension distance X1 of the depletion layer 32x extending from the body region 32 has the relationship shown in the following equation 4. Furthermore, the extension distance X2 of the depletion layer 36x extending upward from the bottom region 36 has the relationship shown in the following equation 5. Furthermore, the extension distance X3 of the depletion layer 36x extending laterally from the bottom region 36 has the relationship shown in the following equation 6.

[0046] [Formula 3]

[0047]

[0048]

[0049]

[0050] In equations 4 to 6, ε is the dielectric constant of the drift region 34 , Vds is the voltage applied between the drain electrode 72 and the source electrode 70 , and is the built-in potential of the pn junction, and q is the elementary charge. From equations 4 to 6, we know that the extension distances X1 to X3 satisfy the following equations 7 to 9.

[0051] [Formula 4]

[0052]

[0053]

[0054]

[0055] As described above, in Example 1, N1=N2=N3, and therefore X1=X2=X3.

[0056] As described above, when MOSFET 10 is turned off, voltage Vds rises. As voltage Vds rises, extension distances X1, X2, and X3 increase. That is, as voltage Vds rises, depletion layers 32x and 36x expand. When voltage Vds rises to a certain value, extension distances X1, X2, and X3 reach distance L2. At this stage, Figure 6 As shown, the depletion layer 36x is in contact with the bottom surface of the trench 22 (i.e., the bottom insulating film 24b). Thus, the bottom surface of the trench 22 is covered by the depletion layer 36x, thereby suppressing the electric field concentration on the gate insulating film 24 at the lower end of the trench 22. This can suppress degradation of the gate insulating film 24.

[0057] In addition, if Figure 4 As shown, L2<L1, so in Figure 6 In the stage of , the extension distance X1 of the depletion layer 32x does not reach the distance L1. Figure 6 As shown in FIG. 1 , the depletion layer 32x does not reach the bottom end of the trench 22. Therefore, the depletion layer 32x is not connected to the depletion layer 36x. In this state, since an electron accumulation layer exists in the region near the gate insulating film 24 within the depletion layer 32x, the electrons flow along the path indicated by the arrow 100. Thus, even when the depletion layer has expanded to a certain extent, electrons flow through the MOSFET 10. Thereafter, if the extension distances X1, X2, and X3 are further increased to reach the distance L1, as shown in FIG. Figure 7 As shown, the depletion layer 32x is connected to the depletion layer 36x. At this stage, the electron path 100 (refer to Figure 6 ) is cut off, and the current stops. Therefore, the current can flow with low loss until the path 100 is cut off, and the current can be stopped abruptly when the path 100 is cut off. In this way, by satisfying L2 < L1, the MOSFET 10 can operate with low loss.

[0058] In addition, if Figure 4 As shown in FIG. 3 , the interval L3 between adjacent bottom regions 36 satisfies the relationship L1 < L3 / 2 and L2 < L3 / 2. Figure 6 Thus, when the extension distances X1, X2, and X3 reach the distance L1, the depletion layers 36x between the adjacent bottom regions 36 are not connected. In other words, the non-depleted region 37 remains between the depletion layers 36x extending from the adjacent bottom regions 36. Thus, before the depletion layers 36x are connected to each other, each depletion layer 36x is connected to the depletion layer 32x. Therefore, in the MOSFET 10 of the first embodiment, no depletion layer 36x is formed. Figure 9 Thus, the electric field concentration on the gate insulating film 24 near the lower end of the trench 22 can be suppressed. Figure 9Forming a floating non-depleted region in this manner increases the capacitance between the gate electrode 26 and the drift region 34 (i.e., feedback capacitance), slowing down the switching speed. In the MOSFET 10 of the first embodiment, since no floating non-depleted region is formed, the feedback capacitance is small, enabling high-speed switching.

[0059] After that, if the voltage Vds rises further, Figure 8 In this way, the depletion layers 36x extending from the adjacent bottom regions 36 are connected to each other. Thereafter, when the voltage Vds further increases, the depletion layer spreads to the entire drift region 34. Thus, the MOSFET 10 is completely turned off.

[0060] As described above, the MOSFET 10 of the first embodiment can prevent the formation of a floating non-depleted region in the drift region 34 during the on-to-off switching process. This prevents degradation of the gate insulating film and reduces feedback capacitance.

[0061] (Example 2) In Example 2, the relationship between the concentrations N1, N2, and N3 and the distances L1, L2, and L3 is different from that in Example 1. In Example 2, N3 = N2 < N1. In addition, in Example 2, the following equations 10 to 12 are satisfied.

[0062] [Formula 5]

[0063]

[0064]

[0065]

[0066] In Example 2, L2>L1 in the range satisfying Formulas 10 to 12. However, L2=L1 or L2<L1 may also be satisfied.

[0067] When the MOSFET 10 of the second embodiment is turned off, the depletion layers 32x and 36x expand as the voltage Vds rises, similarly to the first embodiment. When the extension distance X2 of the depletion layer 36x reaches the distance L2, Figure 6 Similarly, the depletion layer 36x is in contact with the bottom surface of the trench 22. This suppresses the degradation of the gate insulating film 24. In addition, at this stage, the extension distance X1 of the depletion layer 32x satisfies X1 = L2 (N2 / N1) according to the above formula 7 and the relationship X2 = L2. 1 / 2 According to this relationship and the above formula 12, the relationship X1<L1 is satisfied. That is, at this stage, Figure 6 Similarly, the depletion layer 32x does not reach the bottom end of the trench 22. Therefore, at this stage, it is possible to Figure 6The electrons flow along the same path as the arrow 100. Afterwards, if the extension distance X1 of the depletion layer 32x reaches the distance L1, Figure 7 Similarly, the depletion layer 32x is connected to the depletion layer 36x. At this time, the extension distance X3 of the depletion layer 32x satisfies X3 = L1 (N1 / N3) according to the above formula 8 and the relationship X1 = L1. 1 / 2 According to this relationship and the above formula 10, the relationship X3<L3 / 2 is satisfied. That is, at this stage, Figure 7 Similarly, a non-depleted region 37 exists between the depletion layers 32x extending from the adjacent bottom region 36. Therefore, a floating non-depleted region is not formed within the drift region 34. This suppresses electric field concentration on the gate insulating film 24 near the lower end of the trench 22. Furthermore, feedback capacitance can be reduced. Subsequently, the depletion layer expands throughout the drift region 34 as the voltage Vds rises. Thus, the MOSFET 10 is completely turned off.

[0068] As described above, the MOSFET of Example 2 can also prevent the formation of a floating non-depleted region in the drift region 34 during the on-to-off switching process. This prevents degradation of the gate insulating film and reduces feedback capacitance.

[0069] Furthermore, in Example 2, concentration N1 is greater than concentrations N2 and N3. Consequently, the depletion layer 32x expands at a relatively slow rate within the upper drift region 34a. Consequently, the electron path indicated by arrow 100 can be maintained for a longer period of time. This further reduces losses in the MOSFET. Furthermore, since concentrations N2 and N3 are lower than concentration N1, the depletion layer can expand more rapidly within the middle drift region 34b and the lower drift region 34c. Consequently, after the electron path is cut off, the current flow can be quickly stopped.

[0070] In Examples 1 and 2, N2 = N3, but N2 and N3 may be different. Furthermore, in Examples 1 and 2, Formula 12 is satisfied, but this does not necessarily have to be the case. In this case, as long as Formulas 10 and 11 are satisfied, the formation of a floating non-depleted region can be prevented.

[0071] In addition, although MOSFETs are described in Examples 1 and 2, the technology disclosed in this specification can also be applied to other switching elements such as IGBTs (insulated gate bipolar transistors). When the switching element is an IGBT, the source region is sometimes referred to as the emitter region.

[0072] In addition, in the first and second embodiments, each connection region 38 is connected to a plurality of bottom regions 36 , but the connection region 38 may be provided so as to be divided for each bottom region 36 .

[0073] In Examples 1 and 2, the concentration N2 and the concentration N3 are equal, but the concentration N2 and the concentration N3 may be different.

[0074] While the embodiments have been described in detail above, they are merely illustrative and do not limit the scope of the claims. The technologies described in the claims include various variations and modifications of the specific examples illustrated above. The technical elements described in this specification or the drawings demonstrate technical practicality individually or in various combinations, and are not limited to the combinations described in the claims at the time of filing. Furthermore, the technologies illustrated in this specification or the drawings achieve multiple objectives simultaneously, and achieving one of these objectives alone is technically practical.

Claims

1. A switching element, characterized in that: have: semiconductor substrates; a plurality of grooves provided on the upper surface of the semiconductor substrate; a plurality of gate insulating films, respectively covering inner surfaces of the corresponding trenches; as well as a plurality of gate electrodes, each disposed in the corresponding trench and insulated from the semiconductor substrate by the corresponding gate insulating film; The semiconductor substrate has: an n-type drift region in contact with the gate insulating film at the bottom and side surfaces of each of the trenches; a p-type body region, which is in contact with the gate insulating film on the side surface of each of the trenches on the upper side of the drift region; an n-type source region, which is in contact with the gate insulating film on the side surface of each of the trenches above the body region and is separated from the drift region by the body region; A plurality of p-type bottom regions are respectively arranged directly below the corresponding trenches and at positions away from the gate insulating film; as well as a p-type connection region connecting each of the bottom regions to the body region; The depth of the lower end of each groove and the distance between the body region are L1, The n-type impurity concentration of the drift region within the range between the depth of the lower end of each trench and the body region is concentration N1. The distance between the depth of the lower end of each groove and the depth of the upper end of each bottom area is L2. The n-type impurity concentration of the drift region within a range between the depth of the lower end of each trench and the depth of the upper end of each bottom region is concentration N2. The distance between adjacent bottom areas is L3. The n-type impurity concentration of the drift region between adjacent bottom regions is N3, satisfying the following relationship: [Formula 1] as well as [Formula 2] 2. The switching element according to claim 1, wherein Satisfies the following relationship: [Formula 3] 3. The switching element according to claim 1 or 2, characterized in that The relationship N2<N1 is satisfied.

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