Semiconductor light emitting element and method for manufacturing the same

Abstract

Provided are a semiconductor light emitting element and a method for manufacturing the same that can alleviate multiple peaks in a light emission spectrum and make them single peaks. In a semiconductor light emitting element having a second conductive type cladding as a light extraction side, the arithmetic mean deviation Ra of the surface of the light extraction surface of the second conductive type cladding is set to be greater than 0.07 μm and less than 0.7 μm, and the skewness Rsk is set to be a positive value.

Description

Technical Field

[0001] The present invention relates to a semiconductor light emitting element and a manufacturing method thereof, and in particular to an infrared emitting semiconductor light emitting element. Background Art

[0002] Conventionally, semiconductor light emitting elements that emit light in the mid-infrared region with a wavelength of 3400 nm or longer are known. For example, semiconductor light emitting elements that emit light in the mid-infrared region are widely used in applications such as sensors and gas analysis.

[0003] When the emission wavelength of such a semiconductor light-emitting element is set to the mid-infrared region of 3400 nm to 4500 nm, an InAsSb-based III-V semiconductor containing In, As, and Sb is generally used in the light-emitting layer. Conventionally, when an InAsSb-based III-V semiconductor layer such as an InAsSb layer is epitaxially grown, an InAs substrate is used as a growth substrate in order to lattice match the growth substrate with the InAsSb-based III-V semiconductor layer containing In and As.

[0004] For example, in Patent Document 1, an InAsSbP active layer is formed after forming an InSbP layer on an InAs substrate. In Patent Document 1, an InAs substrate that is conductive at a wavelength of 2.6 to 4.7 μm is used directly for a light emitting element.

[0005] Prior art literature

[0006] Patent Literature

[0007] Patent Document 1: Japanese Patent Application No. 2015-534270 Summary of the invention

[0008] Problem that the invention aims to solve

[0009] In recent years, the efficiency of light-emitting elements and the sensitivity of light-receiving elements have been sought to be further improved in the characteristics of semiconductor optical devices. The inventors of the present invention have taken the lead in attempting to develop the following junction-type semiconductor optical device: an InAsSbP-based III-V compound semiconductor containing at least In and As is grown through an etching stop layer formed by a GaAsSb-based III-V compound semiconductor containing at least Ga and Sb grown on an InAs growth substrate, the support substrate is bonded via a metal bonding layer, and the growth substrate is removed. As a result, the light output is successfully increased compared to the previous non-bonding type. However, the inventors of the present invention have confirmed for the first time that for this junction-type semiconductor light-emitting element, in the luminescence spectrum with the wavelength on the horizontal axis and the luminescence intensity on the vertical axis, in addition to the luminescence peak with the luminescence center wavelength having the maximum luminescence intensity, there are also multiple luminescence peaks (hereinafter referred to as "multi-peaks" in this specification). Here, the luminescence peak (hereinafter sometimes abbreviated as "peak") refers to the point where the slope reaches 0 and obtains a maximum value when the slope of the change of the vertical axis (luminescence intensity) relative to the change of the horizontal axis (wavelength) is taken in the luminescence spectrum measured in a manner that the wavelength interval of the horizontal axis becomes less than 15nm. In addition, the above peak does not include a peak whose relative intensity is less than 0.1 with respect to the luminescence intensity of the luminescence peak at the luminescence center wavelength.

[0010] It should be noted that in the case of a non-bonded semiconductor light-emitting element based on the prior art, there is usually no peak in the emission spectrum except for the emission peak of the emission center wavelength (there is only the emission peak of the emission center wavelength, hereinafter referred to as "single peak" in this specification), and in the case of a reflective layer, there is also a concern about the generation of multiple peaks. In a semiconductor light-emitting element that emits the above-mentioned multiple peaks of radiated light, there are emission peaks of different wavelengths with a relative intensity of 0.1 or more relative to the emission intensity of the emission peak of the emission center wavelength, so when such a semiconductor light-emitting element is used for sensor applications, etc., there is a risk of causing adverse conditions.

[0011] Therefore, an object of the present invention is to provide a semiconductor light emitting element and a method for manufacturing the same, which can alleviate multiple peaks in the emission spectrum into a single peak in a semiconductor light emitting element including a cladding layer formed of an InAsSbP-based III-V compound semiconductor containing at least In and As.

[0012] Solutions for solving problems

[0013] The inventors of the present invention have conducted in-depth research on ways to solve the above-mentioned problems. It is believed that when infrared light with a wavelength of 3400 to 4500 nm emitted from the light-emitting layer is incident on the cladding on the light extraction side, when the cladding is InAs, since the refractive index of InAs is about 3.5 for infrared light, when light is directly extracted from the cladding toward the atmosphere (refractive index 1), most of the light obliquely incident on the interface is reflected and returned to the inner side of the semiconductor layer. On the other hand, in a semiconductor light-emitting element having a reflective layer between the light-emitting layer and the substrate, the infrared light emitted from the light-emitting layer toward the substrate is reflected by the reflective layer, and the reflected light based on the reflection is incident on the cladding on the light extraction side via the light-emitting layer. Here, the total thickness of the semiconductor layer in the semiconductor light-emitting element is about several μm to 15 μm, which falls within the range of the coherence length of infrared light and is prone to interference. It should be noted that the coherence length of light with a central emission wavelength of 4150nm and a half-value width of 1100nm is 15.7μm, and the coherence length of light with a central emission wavelength of 4500nm and a half-value width of 1100nm is 18.4μm. For this reason, the present inventors considered that multiple peaks may be observed in the emission spectrum because the reflected light at the interface of the cladding on the light extraction side interferes with the reflected light based on the reflective layer. In addition, this phenomenon also occurs when light is extracted from the cladding toward the atmosphere through a protective layer formed by a dielectric having a refractive index less than InAs. Therefore, the present inventors thought of roughening the surface of the light extraction surface of the cladding, and found that the multiple peaks can be eliminated by this surface roughening, thereby completing the present invention.

[0014] That is, the gist of the present invention is as follows.

[0015] (1) A semiconductor light emitting device, characterized in that it comprises:

[0016] substrate;

[0017] a reflective layer on the substrate;

[0018] A first conductivity type cladding layer formed of an InAsSbP series III-V group compound semiconductor containing at least In and As on the reflective layer;

[0019] an active layer on the first conductivity type cladding layer, the light emission center wavelength of which is not less than 3400 nm and not more than 4500 nm; and

[0020] a second conductivity type cladding layer formed of an InAsSbP series III-V group compound semiconductor containing at least In and As on the active layer;

[0021] The semiconductor light emitting element uses the second conductivity type cladding layer as a light extraction side,

[0022] The arithmetic mean surface deviation Ra of the light extraction surface of the second conductivity type cladding layer is greater than or equal to 0.07 μm and less than or equal to 0.7 μm, and the skewness Rsk is a positive value.

[0023] (2) A semiconductor light emitting device, characterized in that it comprises:

[0024] support base plate;

[0025] a metal bonding layer on the support substrate;

[0026] a reflective layer on the metal bonding layer;

[0027] A first conductivity type cladding layer formed of an InAsSbP series III-V group compound semiconductor containing at least In and As on the reflective layer;

[0028] an active layer on the first conductivity type cladding layer, the light emission center wavelength of which is not less than 3400 nm and not more than 4500 nm; and

[0029] a second conductivity type cladding layer formed of an InAsSbP series III-V group compound semiconductor containing at least In and As on the active layer;

[0030] The semiconductor light emitting element uses the second conductivity type cladding layer as a light extraction side,

[0031] The arithmetic mean surface deviation Ra of the light extraction surface of the second conductivity type cladding layer is greater than or equal to 0.07 μm and less than or equal to 0.7 μm, and the skewness Rsk is a positive value.

[0032] (3) The semiconductor light emitting element according to (1) or (2), wherein the light emission spectrum obtained from the light extraction surface is a single peak.

[0033] (4) The semiconductor light emitting element according to any one of (1) to (3), wherein an arithmetic mean deviation Ra of the surface of the light extraction surface is greater than or equal to 0.1 μm and less than or equal to 0.4 μm, and a skewness Rsk is greater than or equal to 0.1 and less than or equal to 0.7.

[0034] (5) The semiconductor light emitting element according to any one of (1) to (4) above, further comprising a protective film on the light extraction surface.

[0035] (6) A method for manufacturing a semiconductor light emitting element, characterized in that it comprises the following steps:

[0036] In a first step, a reflective layer, a first conductivity type cladding layer formed of an InAsSbP series III-V compound semiconductor containing at least In and As, an active layer having a light emission center wavelength of 3400 nm to 4500 nm, and a second conductivity type cladding layer formed of an InAsSbP series III-V compound semiconductor containing at least In and As are sequentially formed on a substrate; and

[0037] In the second step, the surface of the light extraction surface of the second conductivity type cladding layer is roughened so that the arithmetic mean deviation Ra of the surface becomes 0.07 μm or more and 0.7 μm or less and the skewness Rsk becomes a positive value.

[0038] (7) A method for manufacturing a semiconductor light-emitting element according to (6), wherein, in the second step, the surface roughening is performed in such a manner that the arithmetic mean deviation Ra of the surface of the light extraction surface becomes greater than 0.1 μm and less than 0.4 μm, and the skewness Rsk becomes greater than 0.1 and less than 0.7.

[0039] (8) A method for manufacturing a semiconductor light emitting element, characterized in that it comprises the following steps:

[0040] a semiconductor layer forming step of sequentially forming, on a growth substrate, an etching stopper layer formed of a GaAsSb-based III-V compound semiconductor containing at least Ga and Sb, a second conductivity type cladding layer formed of an InAsSbP-based III-V compound semiconductor containing at least In and As, an active layer having a light emission center wavelength of not less than 3400 nm and not more than 4500 nm, and a first conductivity type cladding layer formed of an InAsSbP-based III-V compound semiconductor containing at least In and As;

[0041] a reflection layer forming step of forming a reflection layer on the first conductive type cladding layer, wherein the reflection layer reflects light emitted from the semiconductor active layer;

[0042] a bonding step of bonding the reflective layer to the support substrate via at least the metal bonding layer;

[0043] a substrate removal step of removing the growth substrate; and

[0044] The surface roughening step is to roughen the surface of the light extraction surface of the second conductive type cladding layer after the substrate removal step so that the arithmetic mean deviation Ra of the surface becomes 0.07 μm or more and 0.7 μm or less and the skewness Rsk becomes a positive value.

[0045] (9) A method for manufacturing a semiconductor light-emitting element according to (8), wherein, in the surface roughening treatment step, the surface roughening is performed in such a manner that the arithmetic mean deviation Ra of the surface of the light extraction surface becomes greater than 0.1 μm and less than 0.4 μm, and the skewness Rsk becomes greater than 0.1 and less than 0.7.

[0046] (10) The method for manufacturing a semiconductor light-emitting element according to (8) or (9), further comprising the following step: a top surface electrode forming step, in which a second conductive type electrode is formed on the second conductive type cladding layer through the III-V compound semiconductor etching stop layer in a top surface electrode forming region of the second conductive type cladding layer other than the light extraction surface.

[0047] (11) A method for manufacturing a semiconductor light emitting element, characterized in that it comprises the following steps:

[0048] In a first step, a reflective layer, a first conductivity type cladding layer formed of an InAsSbP series III-V compound semiconductor containing at least In and As, an active layer having a light emission center wavelength of 3400 nm to 4500 nm, and a second conductivity type cladding layer formed of an InAsSbP series III-V compound semiconductor containing at least In and As are sequentially formed on a substrate; and

[0049] In the second step, the surface of the light extraction surface of the second conductivity type cladding layer is roughened using nitric acid.

[0050] (12) The method for manufacturing a semiconductor light-emitting element according to (11) above, wherein the nitric acid used has a concentration of 11M to 20M (mol / L).

[0051] Effects of the Invention

[0052] According to the present invention, a semiconductor light emitting element including a cladding layer formed of an InAsSbP-based III-V compound semiconductor containing at least In and As can be provided, which can alleviate multiple peaks in the emission spectrum to a single peak, and a method for manufacturing the same. BRIEF DESCRIPTION OF THE DRAWINGS

[0053] Figure 1 This is a schematic cross-sectional view showing an example of the semiconductor light emitting element of the present invention.

[0054] Figure 2 It is a schematic cross-sectional view for explaining the manufacturing process of an example of the semiconductor light emitting element of the present invention.

[0055] Figure 3 It is used for Figure 2A schematic cross-sectional view illustrating a manufacturing process of an example of the semiconductor light emitting element of the present invention.

[0056] Figure 4 It is used for Figure 3 A schematic cross-sectional view illustrating a manufacturing process of an example of the semiconductor light emitting element of the present invention.

[0057] Figure 5 It is used for Figure 4 A schematic cross-sectional view illustrating a manufacturing process of an example of the semiconductor light emitting element of the present invention.

[0058] Figure 6 It is used for Figure 5 A schematic cross-sectional view illustrating a manufacturing process of an example of the semiconductor light emitting element of the present invention.

[0059] Figure 7 It is used for Figure 6 A schematic cross-sectional view illustrating a manufacturing process of an example of the semiconductor light emitting element of the present invention.

[0060] Figure 8 (A) to (C) are diagrams showing rough surface shapes obtained using a height difference meter in Example 1, Example 2, and Comparative Example 2.

[0061] Fig. 9 (A) to (C) are the emission spectra obtained in Example 1, Comparative Example 1 and Comparative Example 2.

[0062] Fig.10 (A) to (C) are microscope photographs showing the three-dimensional rough surface shapes obtained using a shape analysis laser microscope in Example 1, Example 2, and Comparative Example 2.

[0063] Fig.11 (A) to (C) are surface photographs of the semiconductor light emitting elements produced in Example 1, Comparative Example 1, and Comparative Example 2. DETAILED DESCRIPTION

[0064] Before describing the embodiments of the present invention, the following aspects will be described in advance.

[0065] <Composition>

[0066] First, when the composition ratio of the III-V compound is not explicitly stated in this specification and is abbreviated as "AlInGaAsSbP", it means that the chemical composition ratio of group III elements (the sum of Al, In, and Ga) to group V elements (As, Sb, and P) is 1:1, and it is any compound in which the ratios of Al, In, and Ga as group III elements and the ratios of As, Sb, and P as group V elements are respectively uncertain. At this time, it includes cases where group III elements do not contain any one or two of Al, In, and Ga, and in addition, it includes cases where group V elements do not contain any one or two of As, Sb, and P. Among them, when it is clearly stated as "at least containing" any one or both of specific group III elements and group V elements, the content of each of the group III elements and group V elements as the object of description exceeds 0% and is 100% or less. For example, in "AlInGaAsSbP" that "at least contains In and Sb", the content of each of In and Sb exceeds 0% and is 100% or less. At this time, it may respectively contain Al and Ga as well as As and P in addition to In and Sb, or may not contain them. In addition, the "system" III-V compound semiconductor of AlInGaAsSbP may contain any dopant. It should be noted that the component composition ratio of each III-V element of AlInGaAsSbP can be measured by photoluminescence measurement, X-ray diffraction measurement, etc.

[0067] On the other hand, when recording by removing specific group III elements or group V elements from the expression "AlInGaAsSbP", the group III elements or group V elements as the object are not included in the composition. For example, when denoted as "InAsSbP", its composition is represented by the general formula: InAs x Sb y P z ) and does not include Al and Ga. It should be noted that at this time, for the composition ratio of each element, the following relationship holds, and the total composition ratio of group V elements is 1. In addition, the total composition ratio of group III elements is also 1.

[0068] z = 1 - x - y, 0 ≤ x ≤ 1, 0 ≤ y ≤ 1, 0 ≤ z ≤ 1.

[0069] <p-Type, n-Type, and Doping Concentration>

[0070] In this specification, a layer that functions as a p-type electrically is called a p-type semiconductor layer (sometimes abbreviated as "p-type layer"), and a layer that functions as an n-type electrically is called an n-type semiconductor layer (sometimes abbreviated as "n-type layer"). On the other hand, in the case where specific impurities such as Si, Zn, S, Sn, Mg, and Te are not actively added, it is called "undoped". An undoped III-V compound semiconductor layer may have the incorporation of inevitable impurities during the manufacturing process. Specifically, the doping concentration is low (for example, less than 5 × 1016 atoms / cm 3 ), it is considered as “undoped” in this specification. Also, no impurities are actively added to the III-V compound semiconductor layer, but the content of unavoidable impurities (O, C, H, etc.) in the manufacturing process accompanied by the decomposition of the raw material gas is 5×10 16 atoms / cm 3 The above are also considered as undoped. It should be noted that, with regard to InAs, even if it is not doped, it functions electrically as an n-type, so all undoped or n-type InAs layers are InAs layers that function as n-type. In addition, the impurity concentration values ​​of Si, Zn, S, Sn, Mg, Te, etc. are based on SIMS analysis. It should be noted that near the boundary of each semiconductor layer, the value of the doping concentration changes significantly, so the value of the doping concentration at the center of the film thickness direction of each layer is taken as the value of the doping concentration.

[0071] <Thickness and composition of each layer>

[0072] In addition, the thickness of each layer formed can be calculated by cross-sectional observation based on a scanning electron microscope or a transmission electron microscope. Furthermore, the thickness of each layer can be calculated by cross-sectional observation of the growth layer based on a transmission electron microscope. In addition, in the case where the thickness of each layer is small, such as in a superlattice structure, TEM-EDS can be used to measure the thickness. It should be noted that in the cross-sectional view, when a specified layer has an inclined surface, the thickness of the layer uses the maximum height of the flat surface of the layer directly below the layer.

[0073] <Surface roughness Ra and skewness Rsk>

[0074] The surface roughness Ra used in this specification represents the arithmetic mean deviation (μm) of the measured distance. In addition, the skewness Rsk is a value representing the symmetry of the hills and valleys with the average line as the center. When Rsk is zero, it is symmetrical up and down relative to the average line (normal distribution). If it is positive, it means that it is offset to the lower side (valley side) relative to the average line, and if it is negative, it means that it is offset to the upper side (hill side) relative to the average line. The definitions of surface roughness Ra and skewness Rsk are based on ISO 4287-1997. Furthermore, the surface roughness Sa used in this specification is a value representing the arithmetic mean deviation (μm) in the same way as the above-mentioned surface roughness Ra, which is based on ISO 25178. Furthermore, the skewness Ssk is a value representing the symmetry of the hills and valleys with the average line as the center in the same way as the above-mentioned skewness Rsk, which is based on ISO 25178. Surface roughness Ra and skewness Rsk are measured values ​​measured by a two-dimensional profile curve method based on ISO 4287-1997, while surface roughness Sa and skewness Ssk are measured values ​​measured by three-dimensional surface properties based on ISO 25178. In the method for measuring surface roughness Ra and skewness Rsk, a stylus-type height difference meter (e.g., a contact height difference meter "P-6" manufactured by Tencor) can be used for measurement. The shape of the needle used is set to a stylus tip radius of 2 μm, a stylus pressure of 2 mg, a scanning speed of 2 μm / second, and a sampling frequency of 50 Hz. The measurement distance (reference length) is set to 200 μm. In addition, in the method for measuring surface roughness Sa and skewness Ssk, a non-stylus-type shape analysis laser microscope (VK-X1000 / 1100 manufactured by KEYENCE) can be used for measurement. Regarding the measurement conditions in the example (experimental example 2) of this specification, the lens magnification was set to 150 times, and the number of pixels was set to 2048×1536.

[0075] <Random rough surface>

[0076] In addition, in this specification, "random rough surface" means that the concavity and convexity have no periodicity, and does not include the following case, for example: in the result of measuring the surface of the light extraction side using the above-mentioned contact height difference meter, it is observed that the shape of grooves is formed periodically, and the surface roughness Ra of the part without grooves is less than 0.010μm. If the light extraction side is a "random rough surface", the single peak as the effect of the present invention can be obtained more reliably in any part of the in-plane direction. In addition, the method of forming a random rough surface is simpler than forming a periodic rough surface, so a random rough surface is more preferable.

[0077] (Semiconductor Light Emitting Element 100)

[0078] Reference Figure 1, an example of an embodiment of the semiconductor light emitting element of the present invention is described. The semiconductor light emitting element 100 comprises: a substrate 15, a reflective layer 75 on the substrate 15, a first conductive type cladding layer 47 formed of an InAsSbP-based III-V compound semiconductor containing at least In and As on the reflective layer 75, an active layer 45 having a light emission center wavelength of 3400 nm or more and 4500 nm or less on the first conductive type cladding layer 47, and a second conductive type cladding layer 41 formed of an InAsSbP-based III-V compound semiconductor containing at least In and As on the active layer 45, with the second conductive type cladding layer 41 being a light extraction side. In addition, the surface of the light extraction surface of the second conductive type cladding layer 41 is a rough surface, the arithmetic mean deviation Ra of which is 0.07 μm or more and 0.7 μm or less, and the skewness Rsk is a positive value.

[0079] For details on each component, refer to Figure 2 to Figure 7 The manufacturing method of the semiconductor light emitting element 200 described above will be described in detail later while referring to the same structure of the two-digit number. It should be noted that, regarding the substrate 15, when the bonding type technology described later in the manufacturing method of the semiconductor light emitting element 200 is used, the support substrate 80 can be applied, and when the bonding method is not used, the growth substrate 10 can be applied in order to make each semiconductor layer epitaxially grow. Regarding the reflective layer 75, when the above-mentioned bonding type technology is used, a reflective layer 71 such as a metal reflective layer can be used, and when the bonding method is not used, a DBR (distributed Bragg reflector) type semiconductor reflective layer can be used. It should be noted that the semiconductor light emitting element 100 can form a top surface electrode 91 (equivalent to the n-type electrode 91 in the semiconductor light emitting element 200) including a pad portion and a wiring portion on the second conductive type cladding layer 41, and can also further form a back electrode on the back of the support substrate (the back electrode is not shown). In addition, the second conductive type cladding layer 41 can further include a layer for reducing resistance called a contact layer on the top surface electrode side. In the present invention, there is no difference between the cladding layer and the contact layer, and both are recorded as cladding layers. When the reflective layer 75 is a metal reflective layer, the first conductivity type cladding layer 47 may include a contact layer on the reflective layer 75 side.

[0080] Then, if Figure 1 As shown, in the semiconductor light emitting element 100 , light emitted from the active layer 45 is roughly divided into light L1 directed toward the second conductivity type cladding layer 41 and light L2 directed toward the first conductivity type cladding layer 47 . Figure 1 In the embodiment, the surface of the second conductive type cladding layer 41, which emits the light L1 and L2 reflected by the reflective layer 75 to the outside (mainly the atmosphere), except for the top surface electrode 91, is called the "light extraction surface". Figure 1As shown in the figure, the "light extraction surface" refers to: a surface that emits light to the outside in the same surface (top surface) as the surface forming the top electrode. It should be noted that light is also extracted from the side of the semiconductor light emitting element 100. However, the light extraction from the side has little effect on the generation of multiple peaks, so the side surface may or may not be roughened. Among them, from the viewpoint of improving the light output, it is preferred that the side surface is also roughened.

[0081] In the semiconductor light emitting element 100, the "light extraction surface" of the second conductive type cladding layer 41 is a rough surface. In addition, the arithmetic mean deviation Ra of the surface of the light extraction surface is greater than or equal to 0.07 μm and less than or equal to 0.7 μm, and the skewness Rsk is a positive value. More preferably, the arithmetic mean deviation Ra is greater than or equal to 0.1 μm and less than or equal to 0.4 μm, and the skewness Rsk is greater than or equal to 0.1 and less than or equal to 0.7. In addition, as Figure 1 As shown, a top surface electrode 91 is provided on a flat portion of the surface of the second conductive type cladding layer 41 .

[0082] According to the experiments of the inventors, it is confirmed that even if the skewness Rsk is positive, if the depth of the concave-convex is shallow and the surface roughness Ra is less than 0.07 μm, it cannot become a single peak. Therefore, by making the surface roughness Ra above 0.07 μm, preferably above 0.1 μm, a single peak of light can be obtained. As the upper limit of the surface roughness, it is preferably below 0.7 μm, more preferably below 0.4 μm. This is because: if the surface roughness is too large, it is possible to have an adverse effect on the lateral expansion of the current. In addition, it is known that: even if the surface roughness Ra is above 0.07 μm, if the skewness Rsk is negative and a large number of flat surfaces or nearly flat parts are formed at the top of the light extraction side, the multi-peaks in the luminous spectrum cannot be reduced and become a single peak. Therefore, it is more preferred that the skewness Rsk is positive (ie, Rsk>0), 0.1≤Rsk≤0.7. In order to increase the luminous output, the surface roughness Ra is further preferably above 0.25 μm.

[0083] It should be noted that the upper limit of the surface roughness Ra is at least less than the thickness of the second conductive type cladding layer to be surface roughened, for example, 2 μm. As an upper limit of the skewness Rsk suitable for both improving the luminous efficiency and reducing the multi-peak, for example, it is 0.7. In addition, for the same reasons as above, the surface roughness Sa of the surface of the light extraction surface is preferably greater than 0.05 μm, and more preferably greater than 0.1 μm. As an upper limit, it is preferably less than 0.7 μm. Furthermore, the skewness Ssk of the surface of the light extraction surface is preferably greater than -0.5, and preferably less than 0.7. In order to increase the luminous output, the surface roughness Sa is further preferably greater than 0.25 μm.

[0084] It should be noted that when the conductivity type of the first conductivity type cladding layer 47 is set to n type, the second conductivity type cladding layer 41 is set to p type. Conversely, when the conductivity type of the first conductivity type cladding layer 47 is set to p type, the second conductivity type cladding layer 41 is set to n type.

[0085] Next, an example of a method for manufacturing a semiconductor light emitting element based on the present invention is described, including details of each structure. The method for manufacturing a semiconductor light emitting element based on the present invention comprises at least: a semiconductor layer forming step, a reflective layer forming step, a bonding step, a substrate removing step, and a surface roughening step.

[0086] If you refer to Figure 2 In the above-mentioned semiconductor layer forming step, an etching stopper layer 30 formed of a GaAsSb-based III-V compound semiconductor containing at least Ga and Sb, a second conductive type cladding layer 41 formed of an InAsSbP-based III-V compound semiconductor containing at least In and As, an active layer 45 having a light emission center wavelength of 3400 nm to 4500 nm, and a first conductive type cladding layer 47 formed of an InAsSbP-based III-V compound semiconductor containing at least In and As are sequentially formed on the growth substrate 10. Figure 4 In S70, in the above-mentioned reflection layer forming step, a reflection layer 71 is formed on the first conductive type cladding layer 47, and the reflection layer 71 reflects the light emitted from the active layer 45. Figure 5 In the above-mentioned bonding step, the reflective layer 71 is bonded to the support substrate 80 via at least the metal bonding layer 79. Figure 5 In step S90, the growth substrate is removed in the substrate removal step. Figure 7 In S120, in the above-mentioned surface roughening treatment step, after the substrate removal step, the surface roughening is performed in such a way that the arithmetic mean deviation Ra of the surface of the light extraction surface of the second conductive cladding 41 becomes greater than 0.07 μm and less than 0.7 μm, and the skewness Rsk becomes a positive value.

[0087] In the example of the embodiment of the present manufacturing method, an initial buffer layer 20 (see Figure 2 S20), a power distribution unit 60 may also be formed (refer to Figure 3 S40, S50 and Figure 4 S60), the initial buffer layer 20 can be removed (refer to Figure 6 The etching stop layer 30 may be removed (see S100 in the figure), and the electrode 95 may be formed (see Figure 6 S110). They are optional steps. Hereinafter, including the above optional steps, each step and each structure will be described in sequence.

[0088] <Semiconductor Layer Formation Step>

[0089] Reference Figure 2 S10 to S30. In the semiconductor layer forming step, an initial buffer layer 20 may be optionally formed on the growth substrate 10, and then an etching stop layer 30 may be formed on the growth substrate 10 via the initial buffer layer 20 as required (S10, S20). Furthermore, on the etching stop layer 30, a second conductive type cladding layer 41 formed of an InAsSbP-based III-V compound semiconductor containing at least In and As, an active layer 45 having a light emission center wavelength of 3400 nm to 4500 nm, and a first conductive type cladding layer 47 formed of an InAsSbP-based III-V compound semiconductor containing at least In and As are sequentially formed. Hereinafter, the semiconductor stack including the second conductive type cladding layer 41, the active layer 45, and the first conductive type cladding layer 47 are collectively referred to as the "semiconductor stack 40". For the sake of convenience, the second conductive type cladding layer 41 is sometimes further abbreviated as the "n-type cladding layer 41", and the first conductive type cladding layer 47 is sometimes abbreviated as the "p-type cladding layer 47".

[0090] <<Growth substrate>>

[0091] Reference Figure 2 The growth substrate 10 may be appropriately selected so as to be lattice-matched with the semiconductor composition of the etching stopper layer 30. For example, any of a generally available n-type InAs substrate, an undoped InAs substrate, and a p-type InAs substrate may be used for the growth substrate 10.

[0092] <<Etch Stop Layer>>

[0093] Reference Figure 2 S20 to S30. An etching stopper layer 30 formed of a GaAsSb-based III-V compound semiconductor containing at least Ga and Sb is formed on the growth substrate 10. It should be noted that, as described above, before forming the etching stopper layer 30, an initial buffer layer 20 ( Figure 2 At this time, an etching stopper layer 30 is formed on the initial buffer layer 20.

[0094] - Composition range of etching stop layer -

[0095] If the As composition ratio is denoted as x E , the composition range of the GaAsSb-based III-V compound semiconductor of the etching stop layer 30 is GaAs xE Sb 1-xE Indicates. And, As forms x E Preferably 0≤xE ≤0.4. If As constitutes x E If the As composition ratio x is greater than 0.4, etching may occur even with the etching solution described later. E If the As composition ratio x is within this range, the etching stop layer 30 has insolubility in the etching solution described later and can be epitaxially grown on the growth substrate 10. In addition, the GaAsSb-based III-V compound semiconductor preferably contains at least Ga, As, and Sb. That is, the As composition ratio x E More preferably 0 <x E , and more preferably 0.02≤x E ≤0.13. If the As composition ratio x E When the crystal thickness is within this range, the lattice constant difference with the growth substrate can be reduced.

[0096] -Layer structure of etching stop layer-

[0097] It should be noted that the etching stopper layer 30 may have a single layer structure or a multilayer structure. Furthermore, it is also preferred that the etching stopper layer 30 has a superlattice stack, and the superlattice stack has a layer containing Ga, As, and Sb. Figure 2 In the embodiment, the etching stop layer 30 has a superlattice stack formed by repeatedly stacking the first layer 30a and the second layer 30b in this order. For example, even if it is difficult to grow a composition that matches the lattice of the growth substrate in the form of a single layer, the strain can be compensated by forming a superlattice structure with a composition having a large lattice constant and a composition having a small lattice constant relative to the growth substrate with a thickness below the critical film thickness. By making the lattice constant of the overall average composition of the etching stop layer 30 of the superlattice structure approximate to the lattice constant of the growth substrate, an etching stop layer with good crystallinity and sufficient film thickness can be obtained. In addition, the composition of the first layer 30a is shown as GaAs xE1 Sb 1-xE1 When , it can be set to 0.08≤x E1 ≤0.80, preferably 0.10≤x E1 ≤0.40. In addition, the component composition of the second layer 30b is shown as GaAs xE2 Sb 1-xE2 When , it can be set to 0≤x E2 ≤0.08, preferably 0≤x E2 ≤0.05. At this time, when the film thickness of the first layer 30a is represented by t1 and the film thickness of the second layer 30b is represented by t2, the average composition x E3 You can use (x E1 ×t1+x E2 × t2) / (t1+t2). The average composition x E3 Can be set to 0≤x E3≤0.4, more preferably 0.02≤x E3 ≤0.13.

[0098] -Thickness of etching stop layer-

[0099] The total thickness of the etching stop layer 30 is not limited, and can be, for example, 10 nm to 200 nm. When the etching stop layer 30 includes a superlattice stack, the thickness of each layer can be 0.05 nm to 10.0 nm, and the number of groups can be 10 to 200.

[0100] - Initial Buffer Layer -

[0101] As described above, the initial buffer layer 20 can be formed on the surface of the growth substrate 10. This is because it is possible to prevent the influence of the oxide film and contamination on the substrate surface of the growth substrate 10 when the etching stop layer 30 is directly formed on the growth substrate 10. For example, by growing the initial buffer layer 20 formed of InAs on the growth substrate 10 formed of an InAs substrate, it is expected that the interface between the etching stop layer 30 and the initial buffer layer 20 will be clean. As a result, it is also expected that the crystallinity of the semiconductor layer to be epitaxially grown can be improved and the surface stability after the growth substrate is removed can be achieved.

[0102] -Growth method-

[0103] Each semiconductor layer can be formed by epitaxial growth, for example, by a known thin film growth method such as metal organic chemical vapor deposition (MOCVD), molecular beam epitaxy (MBE), sputtering, etc. For example, by using trimethyl indium (TMIn) as an In source, trimethyl gallium (TMGa) and triethyl gallium (TEGa) as a Ga source, arsine (AsH3) and tert-butyl arsine (TBAs) as an As source, trimethyl antimony (TMSb), triethyl antimony (TESb), tri(dimethylamino) antimony (TDMASb) as an Sb source, phosphine (PH3) and tert-butyl phosphine (TBP) as a P source in a predetermined mixing ratio, and using a carrier gas to make these raw material gases undergo vapor phase growth, an InGaAsSbP layer can be formed with a desired thickness according to the growth time. It should be noted that other semiconductor layers to be epitaxially grown can also be formed by the same method. When doping each layer to p-type or n-type, it is only necessary to use the desired doping source gas. It should be noted that even if InAs is not doped, 1×10 16 atoms / cm 3Since the Te from the raw material is about 10%, an n-type semiconductor may be formed. In this case, even if the n-type dopant is not actively doped and the n-type InAs layer is not doped, the same is true in the following steps of forming each semiconductor layer.

[0104] -Formation of semiconductor stack-

[0105] Reference Figure 2 S30. A semiconductor stack 40 including the n-type cladding layer 41, the active layer 45, and the p-type cladding layer 47 is formed.

[0106] <<Semiconductor stack>>

[0107] The semiconductor stack 40 can be made into a double heterogeneous (DH) structure in which an active layer 45 is sandwiched between an n-type cladding layer 41 and a p-type cladding layer 47. At this time, the InAsSbP-based III-V compound semiconductor constituting the active layer 45 preferably contains In, As and Sb. In addition, in order to improve light output by suppressing crystal defects, it is also preferred that the active layer 45 has a multi-quantum well (MQW) structure. The active layer 45 having the multi-quantum well structure can be formed by a structure in which well layers 45w and barrier layers 45b are alternately repeated. In addition, the well layer 45w can be made into InAsSb containing at least In, As and Sb. In addition, the barrier layer 45b can be set to InAsSbP with a larger band gap than the well layer 45w. The emission center wavelength of the active layer 45 is set to be greater than 3400nm and less than 4500nm, which can be adjusted by changing the composition of the active layer 45.

[0108] - Composition of the active layer -

[0109] For example, the component composition of the well layer 45w is shown as InAs xw Sb 1-xw When , it can be set to 0.7≤xw≤1.0, preferably 0.8≤xw≤1.0. In addition, the component composition of the barrier layer 45b is shown as InAs xb P 1-xb When , it can be set to 0.5≤xb≤1, preferably 0.8≤xb≤1. It should be noted that in the case of a quantum well structure, it is also preferred to adjust the composition difference between the well layer 45w and the barrier layer 45b on the basis of changing the composition of the InAsP series III-V compound to apply strain to the well layer.

[0110] -Composition of the cladding-

[0111] The n-type cladding layer 41 and the p-type cladding layer 47 are layers formed of an InAsSbP-based III-V compound semiconductor containing at least In and As, preferably an InAsP-based III-V compound semiconductor. By making the n-type cladding layer 41 and the p-type cladding layer 47 free of Ga, the etching of each cladding layer can be reliably prevented when removing the etching stopper layer 30. In addition, as the n-type cladding layer 41, it is particularly preferred to use n-type InAs, and as the p-type cladding layer 47, it is particularly preferred to use p-type InAs.

[0112] -Film thickness of semiconductor stack-

[0113] The overall film thickness of the semiconductor stack 40 is not limited, and can be set to, for example, 2 μm to 10 μm. In addition, the film thickness of the n-type cladding layer 41 is also not limited, and can be set to, for example, 0.5 μm to 5 μm. Furthermore, the film thickness of the active layer 45 is also not limited, and can be set to, for example, 3 nm to 2000 nm. In addition, the film thickness of the p-type cladding layer 47 is also not limited, and can be set to, for example, 0.1 μm to 5 μm. When the active layer 45 has a quantum well structure, the film thickness of the well layer 45w can be set to 3 nm to 20 nm, the thickness of the barrier layer 45b can be set to 5 to 50 nm, and the number of groups of the two can be set to 1 to 50.5 groups. It should be noted that it is also preferred to form the barrier layer 45b first, and then alternately stack the well layer 45w and the barrier layer 45b (film thickness: 8 nm) in N groups (N is an integer), forming a total of 40.5 groups. At this time, both ends of the quantum well structure become barrier layers 45b.

[0114] -Other semiconductor layers in the semiconductor stack-

[0115] In addition, although not shown in the figure, the semiconductor stack 40 is preferably further provided with a contact layer having a higher doping concentration than each cladding layer on the side of the n-type cladding layer 41 and the p-type cladding layer 47 opposite to the active layer 45 (i.e., the side where the electrode described later is formed). In addition, the semiconductor stack 40 may include an i-type spacer layer between the n-type cladding layer 41 and the active layer 45 and between the active layer 45 and the p-type cladding layer 47. In addition, a p-type electron blocking layer may be provided between the active layer 45 and the p-cladding layer 47.

[0116] <Power Distribution Unit Forming Process>

[0117] After the semiconductor layer forming step and before the reflective layer forming step described in detail later, a power distribution unit forming step of forming a power distribution unit 60 on the p-type cladding layer 47 (on the contact layer when a contact layer is further provided), the power distribution unit 60 includes a transparent insulating layer 61 having a through hole 61A and an ohmic electrode unit 65 provided in the through hole 61A. The specific method of forming the power distribution unit 60 is not particularly limited, and the order of various steps can also be selected. Figure 3S40~S50 and Figure 4 S60 of FIG. 1 illustrates a specific method for forming the power distribution unit 60 .

[0118] First, the transparent insulating layer 61 is formed on the semiconductor stack 40 ( Figure 3 As a film forming method, a known method such as a plasma CVD method and a sputtering method can be applied. Thereafter, a resist pattern is formed on the transparent insulating layer 61 using a photomask. Next, using the resist pattern, a portion of the transparent insulating layer 61 is removed by etching to form a through hole 61A ( Figure 3 S50). By providing the through hole 61A, a part of the outermost surface of the semiconductor stack 40 is exposed. After that, if the ohmic electrode portion 65 is formed and then peeled off using the resist pattern, the power distribution portion 60 ( Figure 4 S60). The power distribution unit 60 is provided with a transparent insulating layer 61 and an ohmic electrode unit 65 in parallel. It should be noted that, here, the resist pattern when etching the transparent insulating layer 61 and the resist pattern when stripping the ohmic electrode unit 65 can use the same pattern, or can be re-patterned separately. It should be noted that in the accompanying drawings, for the sake of simplicity, the through hole 61A is illustrated in the form of the ohmic electrode unit filling the through hole, but it is not limited to this. Although not illustrated, when etching is performed using a combination of resist patterns and the resist pattern, the etching of the portion covered by the resist pattern will expand, so a gap can also be generated between the transparent insulating layer 61 and the ohmic electrode unit.

[0119] The ohmic electrode portion 65 may be formed by being dispersed in a predetermined pattern in an island shape. Figure 6 If the n-type electrode 91 is not disposed directly above the ohmic electrode portion 65, the ohmic electrode portion 65 is preferably configured in an aligned manner. As the ohmic electrode portion 65, for example, Au, AuZn, AuBe, AuTi, etc. can be used, and their stacked structures are also preferably used. For example, Ti / Au can be made into the ohmic electrode portion 65. The film thickness (or total film thickness) of the ohmic electrode portion 65 is not limited, and can be set to 300 to 1300 nm, and more preferably 350 nm to 800 nm.

[0120] It should be noted that, although not shown in the figure, the relationship between the film thickness H1 of the transparent insulating layer 61 and the film thickness H2 of the ohmic electrode portion 65 can be set to H1≥H2, or H1>H2. Under this condition, the film thickness of the transparent insulating layer 61 can be set to, for example, 360nm to 1600nm, and more preferably to 410nm to 1100nm. In addition, it is also preferred to set the difference H1-H2 between the film thickness H1 of the transparent insulating layer 61 and the film thickness H2 of the ohmic electrode portion 65 to be greater than 10nm and less than 100nm. In addition, when a contact layer is further provided as described above, the contact layer can be formed in a manner that only remains in the through hole 61A. In this case, the total thickness of the contact layer and the ohmic electrode portion can be set to the film thickness H2.

[0121] Furthermore, SiO2, SiN, ITO, Al2O3, AlN, etc. can be used as the transparent insulating layer 61, and it is particularly preferable that the transparent insulating layer 61 is formed of SiO2 because SiO2 can be easily etched using BHF or the like.

[0122] <Reflective Layer Forming Step>

[0123] As shown in S70, a reflective layer 71 is formed on the p-type cladding layer 47 (on the distribution unit 60 when the distribution unit 60 is provided). The reflective layer 71 may use a DBR structure or may be composed of a reflective metal. When the reflective layer 71 is formed of a metal material, it is preferred that its composition contains 50% by mass or more of Au. Au is more preferably 80% by mass or more. The reflective layer 71 may include a plurality of metal layers, and the metal constituting the reflective layer 71 may include Al, Pt, Ti, Ag, etc. in addition to Au. For example, the reflective layer 71 may be a single layer consisting only of Au, or the reflective layer 71 may include two or more Au metal layers. In order to reliably perform bonding in the subsequent bonding process, it is preferred that the outermost layer of the reflective layer 71 (the surface on the opposite side of the semiconductor stack 40) is an Au metal layer.

[0124] If you refer to Figure 4 In S70, for example, the reflective layer 71 can be formed by forming each metal layer in the order of Al, Au, Pt, and Au on the power distribution unit 60 (including the gap when the gap is provided). The thickness of one layer of the Au metal layer in the reflective layer 71 can be set to, for example, 400 nm to 2000 nm, and the thickness of the metal layer formed of metals other than Au can be set to, for example, 5 nm to 200 nm. The reflective layer 71 can be formed by using a general method such as a vapor deposition method.

[0125] <Joining process>

[0126] Reference Figure 5In the bonding step, the previously formed reflective layer 71 is bonded to the support substrate 80 with at least the metal bonding layer 79 sandwiched therebetween. Before the bonding step, the metal bonding layer 79 may be formed on the surface of the support substrate 80 by sputtering, evaporation, or the like. For example, the metal bonding layer 79 and the reflective layer 71 are arranged opposite to each other and attached, and then heated and compressed at a temperature of about 250°C to 500°C to bond the two.

[0127] <<Metallic Bonding Layer>>

[0128] The metal bonding layer 79 can be formed by using metals such as Ti, Pt, Au, and metals that form a eutectic alloy with gold (Sn, etc.), and it is preferred to stack them to form the metal bonding layer 79. For example, the metal bonding layer 79 can be formed by stacking Ti with a thickness of 400nm to 800nm, Pt with a thickness of 5nm to 20nm, and Au with a thickness of 700 to 1200nm in order from the surface of the supporting substrate 80. It should be noted that when the reflective layer 71 is used to bond with the metal bonding layer 79, in order to achieve reliable bonding, it is preferred that the outermost layer of the metal bonding layer 79 is set to an Au metal layer, and the outermost layer of the reflective layer 71 is also set to Au, and Au is bonded to each other based on Au-Au diffusion.

[0129] <<Support substrate>>

[0130] The supporting substrate 80 can be any substrate as long as it is a substrate of a different type from the growth substrate 10. In addition to semiconductor substrates such as Si, Ge, metal substrates such as Mo, Cu-W, etc., ceramic substrates such as AlN can also be used as a support substrate for the base. In order to use the above-mentioned bonding method, the supporting substrate 80 may be lattice mismatched with each semiconductor layer formed. In addition, the supporting substrate 80 may be insulating depending on the purpose, but is preferably a conductive substrate. From the perspective of processability and price, it is preferred to use a Si substrate for the supporting substrate 80. By using a Si substrate, the thickness of the supporting substrate 80 can be significantly smaller than before, and it is also suitable for combined installation with various semiconductor devices. In addition, Si substrates are also advantageous in terms of heat dissipation compared to InAs substrates.

[0131] <Substrate Removal Process>

[0132] Reference Figure 5S90. In the substrate removal process, the growth substrate 10 is removed. It should be noted that the "removal" mentioned here is not limited to the "complete removal" of the growth substrate 10. If the etching stop layer 30 is exposed after the "removal" of this process, and the growth substrate 10 can be easily removed together with the etching stop layer 30, part of the growth substrate 10 can be allowed to remain. When an InAs substrate is used as the growth substrate 10, in order to remove the growth substrate 10 using the etching stop layer 30, the growth substrate 10 can be etched only with concentrated hydrochloric acid, or an etching solution other than concentrated hydrochloric acid can be used in the stage before the etching stop layer 30 is exposed. For example, a sulfuric acid-hydrogen peroxide mixture and a hydrochloric acid-hydrogen peroxide mixture can also be used to etch InAs. However, the etching solution containing these mixed solutions will also etch to the etching stop layer 30. Therefore, when only the above-mentioned mixed solution is used, it is difficult to stop etching at a predetermined position. Therefore, in the process of removing the growth substrate 10, it is preferred to etch only with concentrated hydrochloric acid in the final stage of exposing the etching stop layer 30. In addition, a part of InAs can be removed by mechanical processing such as dry etching, grinding, etc., other than wet etching. The InAs substrate can be finally removed by wet etching using concentrated hydrochloric acid of 8M or more (e.g., 12M concentrated hydrochloric acid), and the etching can be terminated by at least the etching stopper 30. It should be noted that the etching stopper 30 is a GaAsSb-based III-V compound semiconductor, and therefore will not be removed by concentrated hydrochloric acid. For example, an ammonia-hydrogen peroxide mixture can be used to remove the etching stopper 30 by wet etching.

[0133] - Etching conditions -

[0134] As described above, when the growth substrate 10 is an InAs substrate, it can be wet-etched using concentrated hydrochloric acid of 8M or more (e.g., 12M concentrated hydrochloric acid). However, the etching rate is slow, and if productivity is taken into consideration, the following etching conditions are preferably adopted. For example, from the perspective of productivity, it is preferred to increase the etching rate by maintaining the liquid temperature of the etching solution containing 12M concentrated hydrochloric acid to above 35°C, and to remove the InAs substrate in a short time. In addition, it is also preferred to use an etching solution with a fast etching rate and capable of flat etching without anisotropy (e.g., a sulfuric acid-hydrogen peroxide mixture) to remove the InAs substrate halfway, and then, in the final stage of exposing the etching stop layer 30, use concentrated hydrochloric acid with etching selectivity to completely remove the InAs substrate.

[0135] - Initial buffer layer removal process and etching stop layer removal process -

[0136] It should be noted that if we refer to Figure 6In S100, when the initial buffer layer 20 is provided, the initial buffer layer 20 can be removed using etching conditions that match the semiconductor composition. When the initial buffer layer 20 is InAs, it is removed together with the growth substrate 10. Next, the etching stopper layer 30 can also be removed.

[0137] <Surface Roughening Process>

[0138] In the surface roughening process, the surface roughening is performed in such a manner that the arithmetic mean deviation Ra of the surface of the light extraction surface of the n-type cladding layer 41 becomes greater than or equal to 0.07 μm and less than or equal to 0.7 μm, and the skewness Rsk becomes a positive value. It should be noted that the surface roughening can be performed in such a manner that the concave-convex pattern of the surface of the light extraction surface becomes a random rough surface. Figure 6 S110 and Figure 7 The surface roughening treatment step is described below with reference to S120.

[0139] First, if a photoresist or the like is formed on the n-type cladding layer 41, and the n-type electrode 91 is formed by sputtering, electron beam evaporation, resistance heating, etc., the n-type electrode 91 can be used as a mask for roughening the surface of the n-type cladding layer 41. Among the surfaces of the n-type cladding layer 41, the portion other than the portion where the n-type electrode 91 is formed will become the light extraction surface of the n-type cladding layer 41, so the surface is roughened by etching or the like. Nitric acid is preferably used as the etching liquid. As the nitric acid used for the surface roughening treatment, nitric acid with a concentration of 11M to 20M (mol / L) is preferably used, and nitric acid with a concentration of 12M to 16M (mol / L) is more preferably used. This is because: nitric acid with a concentration of less than 11M has a concern that the etching speed is fast and the etching surface is nearly flat, and concentrated nitric acid with a concentration of 21M or more has a concern that the etching speed is too slow and the surface roughening takes time. In addition, the liquid temperature of nitric acid is preferably set to a temperature in the range of 5°C to 30°C. The etching time can be appropriately selected according to the concentration and liquid temperature. For example, the surface of the n-type cladding layer 41 can be roughened by immersing the entire wafer for 5 to 60 seconds. The degree of surface roughening can be adjusted by adjusting the temperature and concentration of the etching solution to meet the above conditions. Figure 7S120 of FIG. 1 shows a schematic diagram in which only the top surface of the n-type cladding 41 is surface roughened, but it is preferred that: by adding a step of etching or cutting a portion of the semiconductor stack (for example, cutting a predetermined position) before the surface roughening treatment, the side surface of the n-type cladding 41 is also surface roughened. In this way, the semiconductor light-emitting element 200 can be manufactured. It should be noted that when the surface roughening treatment is performed, a protective film for covering the n-type electrode 91 can be temporarily formed before immersing in the etching solution. As a protective film covering the n-type electrode 91, an anti-etching layer that is easy to temporarily form and remove can be used, and it is preferably formed with a minimum area covering the top surface and side surface of the n-type electrode 91. When the etching amount relative to the bonding portion between the n-type cladding 41 and the n-type electrode 91 is large during the surface roughening treatment, the n-type electrode 91 may be peeled off. Therefore, temporarily forming a protective film is effective in preventing the peeling of the n-type electrode 91 when Ra is large.

[0140] The semiconductor light emitting element 200 manufactured in this way includes a support substrate 80, a metal bonding layer 79 on the support substrate 80, a reflective layer 71 on the metal bonding layer 79, a p-type cladding layer 47 on the reflective layer 71, an active layer 45 on the p-type cladding layer 47, and an n-type cladding layer 41 on the active layer 45, and the n-type cladding layer 41 is used as a light extraction side. In addition, the arithmetic mean deviation Ra of the surface of the light extraction surface of the n-type cladding layer 41 is greater than or equal to 0.07 μm and less than or equal to 0.7 μm, and the skewness Rsk is a positive value.

[0141] It should be noted that in the surface roughening treatment step, in order to reliably obtain the effect of the present invention, it is also preferred to perform surface roughening in such a manner that the arithmetic mean deviation Ra of the surface of the light extraction surface becomes greater than 0.1 μm and less than 0.4 μm, and the skewness Rsk becomes greater than 0.1 and less than 0.7.

[0142] In addition, if Figure 7 As shown in S120 of FIG. 8 , a p-type electrode 95 may be provided on the back surface of the support substrate 80. The p-type electrode 95 may be formed before or after the surface roughening treatment.

[0143] <<Protective film forming step>>

[0144] In addition, although not shown in the figure, a semiconductor light-emitting element can be obtained by providing a protective film on the light extraction surface of the n-type cladding 41 after the surface roughening treatment process. The protective film can be formed by a known method such as a plasma CVD method and a sputtering method. SiO2, SiN, ITO, AlN, etc. can be used for the protective film. This is because the protective film has the effect of suppressing the refractive index difference between the n-type cladding 41 and the air and improving the light extraction. It should be noted that a protective film can be further provided to protect the side of the semiconductor stack 40.

[0145] Although not shown in the figure, it is also a preferred embodiment to use the etching stopper layer 30 as a contact layer and leave the etching stopper layer 30 between the n-type cladding layer 41 and the n-type electrode 91 .

[0146] It should be noted that in the example of the manufacturing method of the above-mentioned semiconductor light-emitting element 200, for the sake of convenience of explanation, the second conductive type cladding 41 is recorded as "n-type cladding 41" and the first conductive type cladding 47 is recorded as "p-type cladding 47", but it should of course be understood that the conductivity type of each semiconductor layer formed on the growth substrate 10 can be reversed between n-type / p-type.

[0147] In addition, the above manufacturing method example describes a manufacturing method of a junction type semiconductor light emitting element 200, but the effect achieved by the surface roughening conditions described in the present invention can also be applied to a non-junction type semiconductor light emitting element. Figure 1 , then the manufacturing method of the semiconductor light-emitting element according to another example of the present invention includes the following steps: a first step, forming a reflective layer 75 having a DBR structure, a first conductive cladding layer 47 formed of an InAsSbP III-V compound semiconductor containing at least In and As, an active layer 40 having a light emission center wavelength of 3400 nm or more and 4500 nm or less, and a second conductive cladding layer 41 formed of an InAsSbP III-V compound semiconductor containing at least In and As on a substrate 15 in sequence; and a second step, roughening the surface in such a manner that the arithmetic mean deviation Ra of the surface of the light extraction surface of the second conductive cladding layer 41 becomes 0.07 μm or more and 0.7 μm or less, and the skewness Rsk becomes a positive value. In addition, it is also preferred to roughen the surface in such a manner that the concave-convex pattern of the surface becomes a random rough surface. In order to reliably obtain the effect of the present invention, it is preferred that: in the second step, the surface roughening is performed in such a manner that the arithmetic mean deviation Ra of the surface of the light extraction surface becomes greater than 0.1 μm and less than 0.4 μm, and the skewness Rsk becomes greater than 0.1 and less than 0.7. It should be noted that, if the junction type is compared with the non-junction type, the junction type can increase the luminous efficiency.

[0148] In addition, regarding the non-bonded type, if the same as the above description is referred to Figure 1, then the method for manufacturing a semiconductor light-emitting element according to another example of the present invention includes the following steps: a first step, sequentially forming a reflective layer 75 having a DBR structure, a first conductive cladding layer 47 formed of an InAsSbP-based III-V compound semiconductor containing at least In and As, an active layer 40 having a light emission center wavelength of 3400 nm or more and 4500 nm or less, and a second conductive cladding layer 41 formed of an InAsSbP-based III-V compound semiconductor containing at least In and As on a substrate 15; and a second step, using nitric acid to roughen the surface of the light extraction surface of the second conductive cladding layer 41. Furthermore, in order to reliably obtain the effect of the present invention, it is preferred that: in the second step, nitric acid with a concentration of 11M to 20M (mol / L) is used for surface roughening. Since the steps described above for the details of the first step and the second step can be appropriately applied, repeated descriptions are omitted.

[0149] When nitric acid is used to roughen the surface of GaAs and AlGaAs, which have shorter wavelengths than InAs and are used for light-emitting elements, a rough surface with a negative skewness Rsk is formed. When InAsSbP and InAs that do not contain Al and Ga are subjected to surface roughening treatment, it is not known what kind of etching solution is used at what concentration. When the inventors of the present invention conducted an in-depth study on the rough surface conditions (surface roughness Ra and skewness Rsk) of the above-mentioned second conductive type cladding, they obtained the following insight: by using nitric acid of the above-mentioned concentration, the multiple peaks in the luminescence spectrum can be relaxed to form a single peak.

[0150] Example

[0151] Hereinafter, the present invention will be described in more detail using examples, but the present invention is not limited to the following examples at all.

[0152] (Example 1)

[0153] Hereinafter, the present invention will be described in more detail using examples, but the present invention is not limited to the following examples at all. Figure 2 to Figure 7 The semiconductor light emitting device described in Example 1 was manufactured according to the flowchart of the method for manufacturing a junction type semiconductor light emitting device shown in . The details are as follows.

[0154] First, a 100 nm undoped InAs layer (initial buffer layer) was formed on the (100) surface of an undoped InAs substrate (substrate thickness: 475 μm). Next, an undoped GaSb layer (film thickness: 0.9 nm) was formed by bonding the GaAs substrate to the undoped GaSb layer. 0.34 Sb 0.66Next, an undoped n-type InAs cladding layer (thickness: 3 μm), an active layer of a quantum well structure with a main emission wavelength of 4100 nm (total thickness: 1.6 μm), a Zn-doped p-type AlInAs electron blocking layer (thickness: 15 nm), and a Zn-doped p-type InAs cladding layer (thickness: 1 μm) were sequentially formed on the superlattice stack using the MOCVD method. It should be noted that when forming the active layer of the quantum well structure, when forming the InAs 0.99 P 0.01 After the barrier layer (thickness: 30nm), InAs 0.85 Sb 0.15 Well layer (thickness: 10nm) and InAs 0.15 P 0.85 The barrier layers (thickness: 30 nm) were stacked alternately in 40 layers, and 40.5 layers were set including the first barrier layer. It should be noted that the InAs cladding layer grown in an undoped manner in Example 1 contained 1×10 16 atoms / cm 3 Since the Te is of n-type, it is described as "n-type InAs cladding layer" as described above, and is also described as n-type cladding layer.

[0155] Next, a transparent insulating layer (thickness: 550 nm) made of SiO2 was formed on the entire surface of the p-type InAs cladding layer by plasma CVD. An electrode pattern that was aligned with the n-type electrode when viewed from above was formed on the p-type InAs cladding layer by resist (see Fig.11 A portion of SiO2 is removed by wet etching based on BHF to form a through hole, exposing the p-type InAs cladding layer. Next, a p-type ohmic electrode portion (Ti / Au, total thickness: 540nm) is vapor-deposited in the through hole, and the resist pattern is peeled off, thereby forming a transparent insulating layer and a p-type ohmic electrode portion in parallel to form a power distribution portion (functioning as a current diffusion layer).

[0156] Next, a metal reflective layer (Al / Au / Pt / Au) was formed on the entire surface of the power distribution unit by vapor deposition. The thickness of each metal layer of the metal reflective layer was 10 nm, 650 nm, 100 nm, and 900 nm, respectively.

[0157] On the other hand, a metal bonding layer (Ti / Pt / Au) was formed on a conductive Si substrate (substrate thickness: 200 μm) serving as a support substrate. The thicknesses of the metal layers of the metal bonding layer were 650 nm, 20 nm, and 900 nm, respectively.

[0158] The metal reflective layer and the metal bonding layer were arranged opposite to each other and were heated and compressed at 300°C. The entire wafer was immersed in 12M concentrated hydrochloric acid (manufactured by Kanto Chemical Co., Ltd.) in a beaker, and at least the InAs substrate, the initial buffer layer, and the etching stop layer were immersed in the concentrated hydrochloric acid for 6 hours, thereby removing the InAs substrate and the initial buffer layer and leaving the GaSb layer and the GaAs 0.34 Sb 0.66 Next, after washing with pure water and drying, the superlattice stack (etching stop layer) is removed by wet etching using an ammonia-hydrogen peroxide mixed solution, thereby exposing the n-type InAs cladding layer.

[0159] Next, by forming a resist pattern, vapor-depositing an n-type electrode, and removing the resist pattern, an n-type electrode (Ti (film thickness: 150 nm) / Au (film thickness: 1250 nm)) was formed in a pattern on the n-type InAs cladding layer. Fig.11 (A) shows a photograph of an n-type electrode after the surface roughening treatment described later.

[0160] Furthermore, a back electrode (Ti (thickness: 10 nm) / Pt (thickness: 50 nm) / Au (thickness: 200 nm)) was formed on the back side of the Si substrate and heat treated at 300°C for 1 minute to perform alloying. Thereafter, the entire wafer was immersed in a 13M nitric acid solution (manufactured by Kanto Chemical Co., Ltd.) maintained at 8°C for 5 seconds to roughen the surface of the n-type InAs cladding layer on the outermost surface. Thereafter, after being immersed in ammonia water for 1 minute, it was cleaned with pure water for more than 2 minutes.

[0161] Finally, the chip was singulated by dicing to produce the semiconductor light emitting element described in Example 1. It should be noted that the chip size was 500 μm×500 μm. Fig.11 (A) shows a photograph of the n-type electrode and the surface of the n-type InAs cladding layer after the surface roughening.

[0162] (Example 2)

[0163] The semiconductor light emitting element described in Example 2 was produced in the same manner as in Example 1 except that the nitric acid temperature was set to 7° C. in the surface roughening treatment after alloying.

[0164] (Example 3)

[0165] In the surface roughening treatment after alloying, the nitric acid temperature was changed to 10°C. Furthermore, before the surface roughening treatment, the following steps were added: forming a resist pattern in a manner covering the n-type electrode to protect the electrode, and removing the resist layer protecting the electrode after cleaning in the surface roughening treatment. Except for this, the semiconductor light emitting element described in Example 3 was manufactured in the same manner as in Example 1.

[0166] (Example 4)

[0167] In the surface roughening treatment after alloying, the nitric acid temperature was changed to 30°C. Furthermore, before the surface roughening treatment, the following steps were added: forming an anti-etching pattern in a manner covering the n-type electrode to protect the electrode, and removing the anti-etching layer protecting the electrode after cleaning in the surface roughening treatment. Except for this, the semiconductor light-emitting element described in Example 4 was manufactured in the same manner as in Example 1.

[0168] (Comparative Example 1)

[0169] A semiconductor light emitting element described in Comparative Example 1 was produced in the same manner as in Example 1 except that the surface of the n-type InAs cladding layer was not subjected to surface roughening treatment. Fig.11 (B) shows a photograph of the n-type electrode and the surface of the n-type InAs cladding layer.

[0170] (Comparative Example 2)

[0171] The semiconductor light emitting element described in Comparative Example 2 was produced in the same manner as in Example 1 except that the surface roughening treatment described below was performed. In Comparative Example 2, a concave-convex pattern was produced on the surface of the n-type InAs cladding layer with reference to Japanese Patent Application Publication No. 2018-101675.

[0172] In Comparative Example 2, after the alloying treatment, a regular pattern was formed on the surface of the n-type InAs cladding layer using a positive photoresist. Then, a mixed liquid etching solution of phosphoric acid and hydrogen peroxide (phosphoric acid: hydrogen peroxide = 1:1) was used and shaken for 1 minute to etch a portion of the n-type InAs cladding layer. As a result, a concave-convex pattern was formed. Fig.11 (C) shows a photograph of the n-type electrode and the surface of the n-type InAs cladding layer after the surface roughening.

[0173] <Measurement of Roughness of Rough Surface>

[0174] The rough surface shape of the n-type cladding surface was measured using a contact-type height difference meter "P-6" manufactured by Tencor Corporation for the chips (cut wafers) after surface roughening treatment in Examples 1 to 4 and Comparative Examples 1 and 2 (wherein the surface roughening treatment was not performed in Comparative Example 1). The shape of the needle used was set to a probe tip radius of 2 μm, a probe pressure of 2 mg, a scanning speed of 2 μm / second, and a sampling frequency of 50 Hz. The measurement distance (reference length) was set to 200 μm. The value of the surface roughness Ra and the value of the skewness Rsk were automatically calculated using the height difference meter.

[0175] As a representative example, the data of the height difference meter in Examples 1, 2 and Comparative Example 2 are shown in Figure 8 (A)~(C).

[0176] In Examples 1 to 2, irregular convexoconcaves are formed, and the hills and valleys are sharp. In contrast, in Comparative Example 2, the spacing between the concave and convexoconcaves is uniform due to pattern formation, and the valleys of the concave portions are deep. It should be noted that Comparative Example 1 is flat because no surface roughening treatment has been performed. When measuring the data of the height difference meter, the Amplitude parameters (Rp, Rv, Rz, Rc, Rt, Ra, Rq, Rsk, Rku) based on ISO 4287-1997 are automatically calculated. Ra and Rsk are shown in the following Table 1. In addition, according to Figure 8 (A) and Figure 8 (B) In Examples 1 and 2, since no portion without regularly spaced grooves as in Comparative Example 2 was observed on the surface on the light extraction side, Examples 1 and 2 were evaluated as "randomly rough surfaces".

[0177] [Table 1]

[0178]

[0179] <Evaluation of output and Vf>

[0180] The semiconductor light-emitting elements of Examples 1 to 4 and Comparative Examples 1 and 2 were fixed on the transistor output head (TO-18) using silver paste, and the top surface electrodes were bonded using gold wires. In addition, the luminous output (Po) and forward voltage (Vf) of the Examples and Comparative Examples were measured by passing a current of 300 mA respectively. It should be noted that an integrating sphere was used in the measurement of the luminous output (Po). In addition, the forward voltage (Vf) was set to the voltage value of a constant current voltage device (manufactured by ADC: Model 6243) when 300 mA was passed. The average values ​​of the three measurements are shown in Table 1.

[0181] <Evaluation of Luminescence Spectrum>

[0182] A current of 300 mA was passed, and an FT-IR interferometer (model: FTIR-OEM000-ZNSE-USB, detector: FTIR-OEM000-060-2TE) manufactured by ARCoptix was used to measure the emission spectra in the wavelength range of 2000 to 6000 nm of the semiconductor light-emitting elements of Examples 1 to 4 and Comparative Examples 1 and 2. It should be noted that the wavelength interval in the measurement of the emission spectra between 2000 and 6000 nm is in the range of 1.6 nm to 14.6 nm.

[0183] The measured luminescence spectrum was evaluated according to the following criteria. In the wavelength region with a luminescence intensity of 0.1 or more when the vertical axis (luminescence intensity) of the luminescence spectrum is represented by a line axis using a relative intensity with the maximum intensity set to 1, when a luminescence peak (a maximum value of 0 at the slope) is observed in addition to the luminescence peak of the central wavelength where the luminescence intensity reaches the maximum in the luminescence spectrum, it is recorded as the presence of multiple peaks. When no luminescence peak is observed other than the luminescence peak of the central wavelength but a single peak is observed, it is recorded as the absence of multiple peaks.

[0184] As a representative example, the emission spectra of Example 1, Comparative Example 1 and Comparative Example 2 are shown in Fig. 9 (A) to (C). In addition, the emission peak wavelength (λp) in Example 1 is 4150 nm. The emission spectrum of Example 2 is substantially the same as that of Example 1.

[0185] From Table 1 and Fig. 9 The results show that if the surface concavo-convex shape and surface parameters of the light extraction surface of the semiconductor light emitting element satisfy the conditions of the present invention as in Examples 1 to 4, there will be no multiple peaks and the emission spectrum will become a single peak.

[0186] In addition, when Example 1 is compared with Example 3, it can be observed that the light emission output tends to increase with a larger surface roughness Ra. On the other hand, in Example 4 where the surface roughness Ra exceeds 0.4, it is observed that the lateral spread of the current is affected and the Vf value tends to increase.

[0187] With respect to Examples 1 to 4 and Comparative Examples 1 and 2, three-dimensional information on the roughness of the rough surface was acquired as follows.

[0188] <Measurement of Roughness of Three-Dimensional Rough Surface>

[0189] The rough surface shape of the n-type cladding surface of the chip (after dicing) after surface roughening treatment (however, surface roughening treatment was not performed in Comparative Example 1) was measured using a shape analysis laser microscope (Keyence VK-X1000 / 1100). The lens magnification was set to 150 times and the number of pixels was set to 2048×1536.

[0190] During the data measurement, the parameters of the surface roughness (Sa, Sz, Str, Spc, Sdr, Ssk, etc.) based on ISO 25178 were automatically calculated. The values ​​are shown in Table 2 below. In addition, as representative examples, microscopic photographs of the surface of the n-type cladding layer after the surface roughening treatment in Examples 1 and 2 and Comparative Example 2 are shown in Tables 1 and 2, ... Fig.10 (A)~(C). Fig.10 (A) Fig.10 As shown in (B), it was observed that a random rough surface was formed on the surface of the n-type cladding layer of Example 1. Fig.10 As shown in (C), it was observed that the surface of the n-type cladding layer of Comparative Example 2 had flat pattern portions (Ra was 0.010 μm or less) and grooves arranged in a specific pattern, and it was confirmed that it was not a random rough surface.

[0191] [Table 2]

[0192]

[0193] Industrial Applicability

[0194] According to the present invention, a semiconductor light emitting element including a cladding layer formed of an InAsSbP-based III-V compound semiconductor containing at least In and As can be provided, which can alleviate multiple peaks in the emission spectrum to a single peak, and a method for manufacturing the same.

[0195] Description of Reference Numerals

[0196] 10 Growth substrate

[0197] 15 substrate

[0198] 20 Initial Buffer

[0199] 30 Etch stop layer

[0200] 41 Second conductivity type (n-type) cladding layer

[0201] 45 Active layer

[0202] 45w well layer

[0203] 45b Barrier layer

[0204] 47 First conductivity type (p-type) cladding layer

[0205] 60 Power Distribution Department

[0206] 61 Transparent insulation layer

[0207] 61A Through hole

[0208] 65 Ohm Metal Division

[0209] 71 Reflection layer

[0210] 75 Reflection layer

[0211] 79 Metal bonding layer

[0212] 80 Support base plate

[0213] 91 Top (n-type) electrode

[0214] 95 Back (p-type) electrode

[0215] 99 protective film

[0216] 100 Semiconductor light emitting device

[0217] 200 Semiconductor light emitting element

Claims

1. A semiconductor light emitting element, characterized in that: It has: substrate; a reflective layer on the substrate; A first conductivity type cladding layer formed of an InAsSbP series III-V group compound semiconductor containing at least In and As on the reflective layer; an active layer on the first conductivity type cladding layer, the light emission center wavelength of which is not less than 3400 nm and not more than 4500 nm; and a second conductivity type cladding layer formed of an InAsSbP series III-V group compound semiconductor containing at least In and As on the active layer; The semiconductor light emitting element uses the second conductivity type cladding layer as a light extraction side, The arithmetic mean surface deviation Ra of the light extraction surface of the second conductivity type cladding layer is greater than or equal to 0.07 μm and less than or equal to 0.7 μm, and the skewness Rsk is a positive value.

2. A semiconductor light emitting element, characterized in that: It has: support base plate; a metal bonding layer on the support substrate; a reflective layer on the metal bonding layer; A first conductivity type cladding layer formed of an InAsSbP series III-V group compound semiconductor containing at least In and As on the reflective layer; an active layer on the first conductivity type cladding layer, the light emission center wavelength of which is not less than 3400 nm and not more than 4500 nm; and a second conductivity type cladding layer formed of an InAsSbP series III-V group compound semiconductor containing at least In and As on the active layer; The semiconductor light emitting element uses the second conductivity type cladding layer as a light extraction side, The arithmetic mean surface deviation Ra of the light extraction surface of the second conductivity type cladding layer is greater than or equal to 0.07 μm and less than or equal to 0.7 μm, and the skewness Rsk is a positive value.

3. The semiconductor light emitting element according to claim 1 or 2, wherein: The emission spectrum obtained from the light extraction surface is a single peak.

4. The semiconductor light emitting element according to claim 1 or 2, wherein: The arithmetic mean deviation Ra of the surface of the light extraction surface is greater than or equal to 0.1 μm and less than or equal to 0.4 μm, and the skewness Rsk is greater than or equal to 0.1 and less than or equal to 0.

7.

5. The semiconductor light emitting element according to claim 1 or 2, wherein: A protective film is provided on the light extraction surface.

6. A method for manufacturing a semiconductor light emitting element, characterized in that: It includes the following steps: In a first step, a reflective layer, a first conductivity type cladding layer formed of an InAsSbP series III-V compound semiconductor containing at least In and As, an active layer having a light emission center wavelength of 3400 nm to 4500 nm, and a second conductivity type cladding layer formed of an InAsSbP series III-V compound semiconductor containing at least In and As are sequentially formed on a substrate; as well as In the second step, the surface of the light extraction surface of the second conductivity type cladding layer is roughened so that the arithmetic mean deviation Ra of the surface becomes 0.07 μm or more and 0.7 μm or less and the skewness Rsk becomes a positive value.

7. The method for manufacturing a semiconductor light emitting element according to claim 6, wherein: In the second step, the surface of the light extraction surface is roughened so that the arithmetic mean deviation Ra of the surface becomes 0.1 μm or more and 0.4 μm or less and the skewness Rsk becomes 0.1 or more and 0.7 or less.

8. A method for manufacturing a semiconductor light emitting element, characterized in that: It includes the following steps: a semiconductor layer forming step of sequentially forming, on a growth substrate, an etching stopper layer formed of a GaAsSb-based III-V compound semiconductor containing at least Ga and Sb, a second conductivity type cladding layer formed of an InAsSbP-based III-V compound semiconductor containing at least In and As, an active layer having a light emission center wavelength of not less than 3400 nm and not more than 4500 nm, and a first conductivity type cladding layer formed of an InAsSbP-based III-V compound semiconductor containing at least In and As; a reflection layer forming step of forming a reflection layer on the first conductive type cladding layer, wherein the reflection layer reflects light emitted from the active layer; a bonding step of bonding the reflective layer to the support substrate via at least the metal bonding layer; A substrate removal step of removing the growth substrate; as well as The surface roughening step is to roughen the surface of the light extraction surface of the second conductive type cladding layer after the substrate removal step so that the arithmetic mean deviation Ra of the surface becomes 0.07 μm or more and 0.7 μm or less and the skewness Rsk becomes a positive value.

9. The method for manufacturing a semiconductor light emitting element according to claim 8, wherein: In the surface roughening step, the surface is roughened so that the arithmetic mean deviation Ra of the surface of the light extraction surface becomes 0.1 μm or more and 0.4 μm or less and the skewness Rsk becomes 0.1 or more and 0.7 or less.

10. The method for manufacturing a semiconductor light emitting element according to claim 8 or 9, further comprising the following steps: The top surface electrode forming step is to form a second conductivity type electrode on the second conductivity type cladding layer via the etching stopper layer in a top surface electrode forming region of the second conductivity type cladding layer excluding the light extraction surface.

11. A method for manufacturing a semiconductor light emitting element, characterized in that: It includes the following steps: In a first step, a reflective layer, a first conductivity type cladding layer formed of an InAsSbP series III-V compound semiconductor containing at least In and As, an active layer having a light emission center wavelength of 3400 nm to 4500 nm, and a second conductivity type cladding layer formed of an InAsSbP series III-V compound semiconductor containing at least In and As are sequentially formed on a substrate; as well as In the second step, the light extraction surface of the second conductive type cladding layer is roughened using nitric acid so that the arithmetic mean deviation Ra of the surface of the light extraction surface of the second conductive type cladding layer becomes greater than or equal to 0.07 μm and less than or equal to 0.7 μm and the skewness Rsk becomes a positive value.

12. The method for manufacturing a semiconductor light emitting element according to claim 11, characterized in that: The nitric acid used has a concentration of 11M to 20M (mol / L).

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