Circuit for mitigating single event transients

Abstract

A circuit for mitigating single-event transients (SETs) comprising: a first sub-circuit comprising a first p-type transistor arrangement configured to produce a first output and a first n-type transistor arrangement configured to produce a second output; and a second sub-circuit comprising a connected p-type transistor arrangement and a connected n-type transistor arrangement connected in series, wherein the first output and the second output are electrically coupled to each other by the second sub-circuit.

Description

TECHNICAL FIELD

[0001] The present invention relates to a circuit for mitigating single-event transients. BACKGROUND

[0002] In high-reliability (high-rel) applications, including space and autonomous vehicles, the robustness of integrated circuits (ICs) in their electronic systems is one of the most important design considerations. These ICs can be subject to various possible radiation effects caused by charged heavy-ion particles, alpha particles, protons, etc.

[0003] A possible radiation effect is a single-event effect (SEE) that is caused by a charged particle hitting an IC. One of the SEEs is a single-event transient (SET), in which a single event (e.g., a charged particle) hitting at a transistor node causes a charge that produces a transient pulse on the transistor node. The transient pulse can be detrimental to the function of the IC. For example, in digital circuits, the transient pulse can cause a single-event upset (SEU) from a flipped logic state in a sequential logic, resulting in an error.

[0004] Since the occurrence rate of SEEs in ICs is expected to be high when using advanced nanometer-scale manufacturing processes (e.g., <90 nm feature size) and / or in severe irradiation environments, it is highly desirable to mitigate SETs (and thus SEUs) to enhance the overall robustness of the ICs for high-reliability applications.

[0005] Among the currently available methods to mitigate SETs / SEUs, an IC can be rad-hard by a dedicated IC manufacturing process, a design technique, or a combination thereof. Rad-hard processes are rare because these processes are not readily available and their costs are often prohibitive. On the other hand, existing Rad-hard design techniques, commonly known as radiation-hardened design (RHBD), are more accepted and practiced because such design techniques can be incorporated into existing technology’s commercial manufacturing processes.

[0006] Existing RHBD designs include transistor size enlargement, complex dual-interlocked cell (DICE) design, and triple modular redundancy (TMR) design. However, despite the maturity of RHBD, one major drawback of existing RHBD design techniques, including RHBD sequential and memory designs, is that they have a high overhead compared to non-rad-hard equivalent technologies, where the overhead is in terms of power consumption, silicon area, and delay. This high overhead limits the use of ICs based on existing technology RHBD designs to applications that can tolerate the high overhead, such as space applications.

[0007] For example, FIG. 1A (prior art) depicts a prior conventional inverter 100 (NOT gate) having a PMOS transistor 102 and an NMOS transistor 104. A gate terminal of the PMOS transistor 102 and a gate terminal of the NMOS transistor 104 can be controlled by an input A 110. A drain terminal of the PMOS transistor 102 and a drain terminal of the NMOS transistor 104 can be connected together to produce an output Y 112, which should always be the inverse of the input A 110. A source terminal of the PMOS transistor 102 can be connected to a supply voltage V DD . A source terminal of the NMOS transistor 104 can be connected to ground V SS . The inverter 100 can not be designed to accommodate SEE, including SET. The PMOS transistor 102 and the NMOS transistor 104 can have W / L (width / length) dimensions of x2114 and x1116, respectively. The W / L dimensions of the PMOS transistor 102 and the NMOS transistor 104 can be small because these dimensions can be designed to drive the output Y 112 so that the inverter 100 operates at a desired speed, or consumes a desired amount of power or occupies a desired amount of silicon area.

[0008] To mitigate SEE in prior RHBD devices, the inverter 100 can be redesigned as an RHBD inverter 150 as shown in FIG. IB (prior art), where the PMOS transistor 152 and the PMOS transistor 154 can be designed to be 10 times larger in size, i.e., x20164 for the PMOS transistor 152 and x10166 for the NMOS transistor 154, respectively. The inverter 150 with the increased size can operate at a higher speed, but at the cost of a higher power overhead and a larger area overhead than the inverter 100. However, the inverter 150 with the increased size can be able to suppress SET. The low occurrence of SET can result in a low error rate for digital circuits including inverters.

[0009] The conventional inverter 100 without the increased size can be susceptible to SET. FIG. 2A (prior art) depicts an example scenario where the input A 110 of the inverter 100 is at logic “1” and the corresponding output Y 112 is accordingly at logic “0”. The NMOS transistor 104 is on, ready to allow a current I N 202 to discharge the output Y 112. The current I N 202 is proportional to the W / L of the NMOS transistor 104. The PMOS transistor 102 is off. When a high-energy particle 204 strikes at the drain of the PMOS transistor 102, a positive charge can be induced. The amount of the positive charge can depend on the linear energy transfer (LET) associated with the particle 204. The higher the LET level, the larger the amount of the positive charge induced. If the amount of the positive charge induced is larger than a threshold to sufficiently overcome the current IN 202, then a positive SET can cause output Y 112 to change to a logic "1" instead of "0" when input A 110 is at a logic "1". This threshold is referred to as the critical charge of change. crit_p 206 is the critical charge of change that produces a positive SET.

[0010] Similarly, FIG. 2B (prior art) depicts another example scenario in which input A 110 of a conventional inverter 100 is at a logic "0" and the corresponding output Y 112 can be at a logic "1". PMOS transistor 102 is on, ready to allow current I P 252 to charge output Y 112. Current I P 252 is proportional to the W / L of PMOS transistor 102. NMOS transistor 104 is off. When a high-energy particle 254 strikes at the drain of NMOS transistor 104, a negative charge can be induced. The amount of negative charge can depend on the LET associated with particle 254. The higher the LET level, the greater the amount of negative charge induced. If the amount of negative charge induced is greater than the threshold to sufficiently overcome current I P 252, then a negative SET can cause output Y 112 to change to a logic "0" instead of "1" when input A 110 is at a logic "0". crit_n 256 is the critical charge of change that produces a negative SET.

[0011] For silicon, a LET of 1 MeV-cm 2 / mg can induce approximately 10.4 fC of charge per unit of chord length (in pm). Chord length is used to estimate the sensitive volume in which electron-hole charge can be induced by a charged particle. In a 180 nm CMOS process, chord length can typically be between 0.5 pm and 2 pm. For other process technologies, chord length can be different. For some RHBD circuits, a LET threshold of 5 MeV-cm 2 / mg can be considered, equivalent to a change of approximately 52 fC of critical charge per unit of chord length (in pm). For some high-end RHBD circuits, a LET threshold of 50 MeV-cm 2 / mg can be considered, equivalent to a change of 520 fC of critical charge per unit of chord length (in pm).

[0012] Consider the RHBD inverter 150 of FIG. IB (prior art) with increased size, in which PMOS transistor 152 and NMPS transistor 154 can be 10 times larger, and the corresponding associated currents I P and I N may be I P and I N10 times larger. In short, the critical charge that can need to change per unit of chord length in a scaled-up inverter 150 can need to be larger in order to more effectively suppress SETs caused by high-energy particles.

[0013] However, transistor scaling-up techniques can be area / power inefficient for composite gates, especially when transistors are connected in series. FIG. 3 (PRIOR ART) depicts a prior art tri-state latch 300 in which two PMOS transistors 302, 304 are connected in series, while two NMOS transistors 306, 308 are connected in series. Input A 310 controls PMOS transistor 302 and NMOS transistor 306. Input B 312 controls NMOS transistor 308. Input B 312 also controls a scaled-up RHBD inverter 150 to produce a signal nB 314 that controls PMOS transistor 304. Output Y 316 is the output. When input B 312 is at logic “1”, output Y 316 has a logic state opposite that of input A 310. When input B 312 is at logic “0”, tri-state latch 300 can be in a high-impedance state in which output Y 316 is floating. To mitigate SETs, all transistors 302, 304, 306, 308 within tri-state latch 300 need to be scaled up. For example, RHBD inverter 150 can have the same transistor sizes as shown in FIG. IB. In FIG. 3, if output Y 316 has the same hardness as signal nB 314 driven by scaled-up RHBD inverter 150, then PMOS transistors 302, 304 will each need to be sized at x40, while NMOS transistors 306, 308 will each need to be sized at x20. This sizing adjustment is intended to provide similar large current drive capability (as in scaled-up RHBD inverter 150) to achieve approximately the same critical charge per unit of chord length change in order to mitigate SETs. However, this sizing adjustment will be expensive in terms of power consumption and silicon area.

[0014] In view of the high overhead of prior RHBD designs, there is a need for circuit designs that mitigate SETs with lower overhead characteristics. SUMMARY

[0015] A circuit for mitigating SETs in digital circuits is disclosed that includes embodiments of circuits with reduced overhead and for use in combinational logic, sequential logic, and memory usage. While the circuit can mitigate SETs caused by radiation effects, the circuit can be used for other applications, such as autonomous vehicles that can not be affected by radiation. In short, the circuit is hardened against SETs that can be caused by a variety of causes including, but not limited to, radiation.

[0016] According to a first aspect, there is provided a circuit for mitigating single effect transients (SETs), the circuit comprising: a first sub-circuit comprising a first p-type transistor arrangement configured to produce a first output and a first n-type transistor arrangement configured to produce a second output; and a second sub-circuit comprising a connected p-type transistor arrangement and a connected n-type transistor arrangement connected in series, wherein the first output and the second output can be electrically coupled to each other by the second sub-circuit.

[0017] Each p-type transistor arrangement can comprise at least one p-type transistor, and wherein each n-type transistor arrangement can comprise at least one n-type transistor.

[0018] A drain terminal of one p-type transistor in the connected p-type transistor arrangement can be electrically coupled to a drain terminal of one n-type transistor in the connected n-type transistor arrangement.

[0019] The first output can be electrically coupled to a drain terminal of one p-type transistor in the first p-type transistor arrangement and to a source terminal of one p-type transistor in the connected p-type transistor arrangement, and the second output can be electrically coupled to a drain terminal of one n-type transistor in the first n-type transistor arrangement and to a source terminal of one n-type transistor in the connected n-type transistor arrangement.

[0020] A source terminal of one p-type transistor in the first p-type transistor arrangement can be electrically coupled to V DD , and a source terminal of one n-type transistor in the first n-type transistor arrangement can be electrically coupled to V SS .

[0021] A gate terminal of one n-type transistor in the connected n-type transistor arrangement can be electrically coupled to V DD , and a gate terminal of one p-type transistor in the connected p-type transistor arrangement can be electrically coupled to V SS .

[0022] The circuit further comprises a second p-type transistor arrangement and a second n-type transistor arrangement, the first output can be further electrically coupled to a drain terminal of one p-type transistor in the second p-type transistor arrangement, the second output can be further electrically coupled to a drain terminal of one n-type transistor in the second n-type transistor arrangement, a gate terminal of one p-type transistor in the connected p-type transistor arrangement and a gate terminal of one n-type transistor in the second n-type transistor arrangement can be controlled by a first of two complementary inputs, a gate terminal of one n-type transistor in the connected n-type transistor arrangement and a gate terminal of one p-type transistor in the second p-type transistor arrangement can be controlled by a second of the two complementary inputs, and a source terminal of one p-type transistor in the second p-type transistor arrangement can be electrically coupled to V DDand a source terminal of one of the n-type transistors in the second n-type transistor arrangement can be electrically coupled to V SS .

[0023] The circuit can further include a third sub-circuit including a last p-type transistor arrangement configured to produce a third output and a last n-type transistor arrangement configured to produce a fourth output, the first output can be connected with a gate terminal of one of the p-type transistors in the last p-type transistor arrangement, the second output can be connected with a gate terminal of one of the n-type transistors in the last n-type transistor arrangement, and a source terminal of one of the p-type transistors in the last p-type transistor arrangement can be electrically coupled to V DD and a source terminal of one of the n-type transistors in the last n-type transistor arrangement can be electrically coupled to V SS .

[0024] The last p-type transistor arrangement can include two p-type transistors connected in series, and the last n-type transistor arrangement can include two n-type transistors connected in parallel.

[0025] A reset signal can be input to a gate of one of the two p-type transistors in the last p-type transistor arrangement, and input to a gate of one of the two n-type transistors in the last n-type transistor arrangement.

[0026] The last p-type transistor arrangement can include two p-type transistors connected in parallel, and the last n-type transistor arrangement can include two n-type transistors connected in series.

[0027] A set signal can be input to a gate of one of the two p-type transistors in the last p-type transistor arrangement, and input to a gate of one of the two n-type transistors in the last n-type transistor arrangement.

[0028] The first p-type transistor arrangement can receive a first input to control a first output, and the first n-type transistor arrangement can receive a second input to control a second output.

[0029] The first input and the second input can be the same input.

[0030] A third input can control the p-type transistor arrangement, and a fourth input can control the n-type transistor arrangement.

[0031] The first p-type transistor arrangement can include at least a first p-type transistor and a second p-type transistor, the first p-type transistor and the second p-type transistor can be connected in one of series or parallel.

[0032] The first p-type transistor arrangement can further comprise a third p-type transistor, which can be connected in series with the first and second p-type transistors when the first and second p-type transistors are connected in parallel, and which can be connected in parallel with the first and second p-type transistors when the first and second p-type transistors are connected in series.

[0033] The first n-type transistor arrangement can comprise at least a first transistor and a second transistor, which can be connected in one of series or parallel.

[0034] The first n-type transistor arrangement can further comprise a third n-type transistor, which can be connected in series with the first and second n-type transistors when the first and second n-type transistors are connected in parallel, and which can be connected in parallel with the first and second n-type transistors when the first and second n-type transistors are connected in series.

[0035] The third and fourth outputs can be electrically coupled to produce one output.

[0036] The circuit can further comprise: a write data signal; a read control signal; a bit line signal;

[0037] a write sub-circuit comprising two p-type transistors connected in series between V DD and the third output, and two n-type transistors connected in series between V SS and the fourth output; and a read sub-circuit comprising two n-type transistors connected in series between V SS and the bit line signal; wherein the third input controls one of the two n-type transistors of the write sub-circuit, the fourth input controls one of the two p-type transistors of the write sub-circuit, the write data signal controls the other of the two p-type transistors of the write sub-circuit and the other of the two n-type transistors of the write sub-circuit, the third and fourth outputs can be electrically coupled to each other and to the two p-type transistors of the write sub-circuit and the two n-type transistors of the write sub-circuit, the third and fourth outputs control one of the two n-type transistors of the read sub-circuit, and the read control signal controls the other of the two n-type transistors of the read sub-circuit.

[0038] The circuit can further comprise: a write data signal; a read control signal; a bit line signal;

[0039] a write sub-circuit comprising two p-type transistors connected in series between V DD and the third output, and two n-type transistors connected in series between V SS and the fourth output; and a read sub-circuit comprising two n-type transistors connected in series between V SStwo n-type transistors between the bit line signal and the first output, wherein the last p-type transistor arrangement can comprise a plurality of p-type transistors connected in series, the last n-type transistor arrangement can comprise a plurality of n-type transistors connected in series, the p-type transistors in the last p-type transistor arrangement and the n-type transistors in the last n-type transistor arrangement can be connected in series and their gate terminals can be connected to V SS and V DD one of the two n-type transistors of the write control sub-circuit,

[0040] one of the two p-type transistors of the write control sub-circuit, the write data signal controls the other of the two p-type transistors of the write control sub-circuit and the other of the two n-type transistors of the write control sub-circuit, the third output can be electrically coupled with the first input, the two p-type transistors of the write control sub-circuit, and the last p-type transistor arrangement, the fourth output can be electrically coupled with the second input, the two n-type transistors of the write control sub-circuit, and the last n-type transistor arrangement, and controls one of the two n-type transistors of the read control sub-circuit, and the read control signal controls the other of the two n-type transistors of the read control sub-circuit.

[0041] According to a second aspect, there is provided a circuit arrangement comprising a plurality of the circuit of the first aspect electrically coupled to each other.

[0042] A reset signal can be input to at least one of the plurality of circuits.

[0043] A set signal can be input to at least one of the plurality of circuits.

[0044] The plurality of circuits can comprise a first circuit and a second circuit; one output of the first circuit can be electrically coupled with one input of the second circuit and one output of the second circuit; a first of the two complementary inputs of the first circuit can be electrically coupled with a second of the two complementary inputs of the second circuit; and a second of the two complementary inputs of the first circuit can be electrically coupled with the first of the two complementary inputs of the second circuit.

[0045] The plurality of circuits can include a first circuit, a second circuit, a third circuit, and a fourth circuit; one output of the first circuit can be electrically coupled with one input of the second circuit, one output of the second circuit, and one input of the third circuit, and one output of the third circuit can be electrically coupled with one input of the fourth circuit and one output of the fourth circuit; a first of two complementary inputs of the first circuit can be electrically coupled with a second of two complementary inputs of the second circuit, a second of two complementary inputs of the third circuit, and a first of two complementary inputs of the fourth circuit; and a second of the two complementary inputs of the first circuit can be electrically coupled with the first of the two complementary inputs of the second circuit, the first of the two complementary inputs of the third circuit, and a second of the two complementary inputs of the fourth circuit.

[0046] The present description does not describe an exhaustive list of all aspects of the presently disclosed circuitry for mitigating SETs. It is contemplated that the presently disclosed circuitry includes all methods, apparatus, and systems that can be practiced from all suitable combinations and permutations of the various aspects in the present description and those described below. Such combinations and permutations can have particular advantages not specifically described in the present description. BRIEF DESCRIPTION OF DRAWINGS

[0047] In order that the present application can be fully understood and readily put into practical effect, there shall now be described by way of non-limiting example only exemplary embodiments of the present application, the description referring to the illustrative accompanying drawings.

[0048] FIG. 1A (prior art) is a schematic diagram of a prior conventional inverter.

[0049] FIG. 1B (prior art) is a schematic diagram of a prior RHBD inverter.

[0050] FIG. 2A (prior art) is a schematic diagram showing how a single event transient (SET) is generated in a first operating scenario of the inverter of FIG. 1A.

[0051] FIG. 2B (prior art) is a schematic diagram showing how a single event transient (SET) is generated in a second operating scenario of the inverter of FIG. 1A.

[0052] FIG. 3 (prior art) is a schematic diagram of a prior tri-state inverter buffer.

[0053] Figure 4 is a schematic diagram of an exemplary embodiment of circuitry for mitigating SETs.

[0054] Figure 5 is a schematic diagram of an exemplary embodiment of circuitry for mitigating SETs configured as a buffer.

[0055] Figure 6is a schematic diagram of an exemplary embodiment of a circuit for mitigating SETs configured as a composite gate.

[0056] Figure 7 is a schematic diagram of an exemplary embodiment of a circuit for mitigating SETs configured as a tri-state buffer.

[0057] Figure 8 is a schematic diagram of an exemplary embodiment of a circuit for mitigating SETs configured as a resettable tri-state buffer.

[0058] Figure 9 is a schematic diagram of an exemplary embodiment of a circuit for mitigating SETs configured as a settable tri-state buffer.

[0059] Figure 10A , Figure 10B and Figure 10C is a schematic diagram of an exemplary embodiment of a circuit arrangement forming a latch.

[0060] Figure 11A , Figure 11B and Figure 10C is a schematic diagram of an exemplary embodiment of a circuit arrangement forming a flip-flop.

[0061] Figure 12 is a schematic diagram of an exemplary embodiment of a circuit for mitigating SETs configured as a memory circuit.

[0062] Figure 13 is a schematic diagram of an exemplary alternative embodiment of a circuit for mitigating SETs configured as a memory circuit. DETAILED DESCRIPTION

[0063] The following detailed description references the drawings, which illustrate specific details in accordance with exemplary embodiments of the presently disclosed circuit for mitigating SETs. The description taken with the drawings is intended to be illustrative, and not limiting. Other embodiments can be utilized, and structural, logical, electrical, and input changes can be made without departing from the scope of the present disclosure. Various embodiments can be combined with one or more other embodiments to form new embodiments, and the various embodiments are not necessarily mutually exclusive.

[0064] Embodiments described in the context of one of the circuits or designs are similarly applicable to the other circuit or design. Similarly, embodiments described in the context of a design are similarly applicable to a circuit, and vice versa.

[0065] Features described in the context of an embodiment can correspondingly apply to the same or similar features in other embodiments. Features described in the context of an embodiment can correspondingly apply to other embodiments even if not explicitly described in those other embodiments. Furthermore, additions and / or combinations and / or alternatives of features described in the context of an embodiment can correspondingly apply to the same or similar features in other embodiments.

[0066] In the context of various embodiments, the term“about” applied to a numerical value includes the exact value and a reasonable variance.

[0067] As used herein, the term“and / or” includes any and all combinations of one or more of the associated listed items. In addition, as used herein, the phrase“at least one of A or B” can include A or B, or both A and B.

[0068] Various embodiments can provide ultra-low error rate circuits (e.g., digital circuits having various transistor configurations) and ultra-low error rate circuit arrangements (e.g., multiple digital circuits arranged to perform a particular function).

[0069] Various embodiments can relate to resistive network techniques to charge / discharge capacitive loads within circuits, and can relate to RHBD techniques to mitigate SEE in digital (logic) gates, e.g., for high-reliability applications including space and autonomous vehicles.

[0070] Various embodiments can provide resistive network techniques to virtually eliminate any SET. For example, various embodiments can provide resistive network techniques for digital circuits in which high-energy particles (e.g., heavy ions) caused by included electric charges can be less likely to cause any soft errors of the digital circuits. This technique can address limitations of known transistor size upscaling and other RHBD techniques for digital circuits.

[0071] Various embodiments can include a digital circuit design having at least one transistor, which can include a gate terminal, a source terminal, and a drain terminal. The gate terminal of the transistor can be configured to control the transistor by electrically connecting the source terminal and the drain terminal or by isolating the source terminal and the drain terminal. The source terminal and the drain terminal of the transistor can be interchangeable. For simplicity, the drain terminal can refer to the output of the transistor.

[0072] Various embodiments can include a digital circuit design having at least one transistor, which can include a gate terminal, a source terminal, and a drain terminal. The gate terminal of the transistor can be configured to control the transistor by electrically connecting the source terminal and the drain terminal or by isolating the source terminal and the drain terminal. The source terminal and the drain terminal of the transistor can be interchangeable. For simplicity, the drain terminal can refer to the output of the transistor.

[0073] Various embodiments can include different types of transistors, including bulk CMOS, silicon-on-insulator (SOI), FinFET, etc. A transistor can be an n-type transistor, where its well / substrate is p-type material and its diffusion region is n-type material. An n-type transistor can include an NMOS transistor. A transistor can be a p-type transistor, where its well / substrate is n-type material and its diffusion region is p-type material. A p-type transistor can include a PMOS transistor. In the description, for simplicity, the terms NMOS transistor and PMOS transistor are used to refer to n-type transistors and p-type transistors, respectively.

[0074] Various embodiments can include networks of transistors. A network can include at least one transistor. For networks with two or more transistors, the transistors can be arranged in parallel or in series or a combination of both.

[0075] Figure 4 An exemplary embodiment of a circuit 400 for mitigating SET is depicted, which can be configured for use in various applications as will be described in more detail below. The circuit 400 includes a first sub-circuit 450, a second sub-circuit 460, and a third sub-circuit 470. In alternative embodiments, the first sub-circuit 450 and the second sub-circuit 460 can form another circuit. The first sub-circuit 450 includes a first PMOS transistor arrangement 402 and a first NMOS transistor arrangement 404. The second sub-circuit 460 includes a connected PMOS transistor arrangement 406 and a connected NMOS transistor arrangement 408 connected in series. The third sub-circuit 470 includes a PMOS output transistor arrangement 410 and an NMOS output transistor arrangement 412, which are also referred to as a last PMOS transistor arrangement 410 and a last NMOS transistor arrangement 412, respectively. In this embodiment, each PMOS transistor arrangement includes only one PMOS transistor and each NMOS transistor arrangement includes only one NMOS transistor. In other embodiments, each PMOS transistor arrangement or NMOS transistor arrangement can include one or more PMOS transistors or one or more NMOS transistors, respectively, as will be described in more detail below.

[0076] The input Inl 420 controls the first PMOS transistor 402 to generate a first output Outl 430, while the input In2 422 controls the first NMOS transistor 404 to generate a second output Out2 432. In the second sub-circuit 460, the first output Outl 430 and the second output Out2 432 are connected through a series connection of a connected PMOS transistor arrangement 406 and a connected NMOS transistor arrangement 408. The source terminal of the connected PMOS transistor arrangement 406 is connected to the first output Outl 430, while the source terminal of the connected NMOS transistor arrangement 408 is connected to the second output Out2 432. The first output Outl 430 also controls a last PMOS transistor 410 to generate a third output Out3 434. The second output Out2 432 also controls a last NMOS transistor 412 to generate a fourth output Out4 436. The input In3 424 controls the connected PMOS transistor arrangement 406, while the input In4 426 controls the connected NMOS transistor arrangement 408. The drain of the connected PMOS transistor arrangement 406 is connected to the drain of the connected NMOS transistor arrangement 408, thereby having an intermediate signal n 428. The source terminal of the first PMOS transistor 402 and the source terminal of the last PMOS transistor 410 are connected to a supply voltage VDD 440. The source terminal of the first NMOS transistor 404 and the source terminal of the last NMOS transistor 412 are connected to a ground VSS 442. The input Inl 420 is connected to the gate of the first PMOS transistor 402, the input In2 422 is connected to the gate of the first NMOS transistor 404, the input In3 424 is connected to the gate of the last PMOS transistor 410, and the input In4 426 is connected to the gate of the last NMOS transistor 412. The first output Outl 430 is connected to the gate of the last PMOS transistor 410, and the second output Out2 432 is connected to the gate of the last NMOS transistor 412. The third output Out3 434 is connected to the gate of the first PMOS transistor 402, and the fourth output Out4 436 is connected to the gate of the first NMOS transistor 404. DD The source terminal of the connected NMOS transistor arrangement 402 and the source terminal of the last NMOS transistor 412 are connected to a ground V SS Different embodiments of the circuit 400 can be implemented for various functions depending on the input configuration and the output configuration and / or the associated enhancement of the transistors / other circuits. For example, each of the PMOS transistors 402, 406, 410 (whether PMOS or NMOS) 402, 404, 406, 408, 410, 412 can be provided as a network of one or more transistors.

[0077] The connected PMOS transistor arrangement 406 and the connected NMOS transistor arrangement 408 in the second sub-circuit 460 form a resistive network when both are turned on. The signals Outl 430 and Out2 432 are electrically connected through the second sub-circuit 460.

[0078] Figure 5An exemplary embodiment of a circuit 500 configured as a buffer 500 to mitigate SET is depicted. The buffer 500 has an input and an output Y that should be in the same logic state as the input A. The buffer 500 includes a first sub-circuit 550, a second sub-circuit 560, and a third sub-circuit 570. The first sub-circuit 550 includes a first PMOS transistor arrangement 502 and a first NMOS transistor arrangement 504. The second sub-circuit 560 includes a connected PMOS transistor arrangement 506 and a connected NMOS transistor arrangement 508. The third sub-circuit 570 includes a last PMOS transistor arrangement 510 and a last NMOS transistor arrangement 512, respectively. In this embodiment, each PMOS transistor arrangement includes only one PMOS transistor and each NMOS transistor arrangement includes only one NMOS transistor.

[0079] The input A controls the first PMOS transistor 502 to generate a first intermediate signal Outl 530 and controls the first NMOS transistor 504 to generate a second intermediate signal Out2 2532. The signals Outl 530 and Out2 532 are connected through the second sub-circuit 560 including the connected PMOS transistor arrangement 506 and the connected NMOS transistor arrangement 508 connected in series. The source terminal of the connected PMOS transistor arrangement 506 is connected to the signal Outl 530 and the source terminal of the connected NMOS transistor arrangement 508 is connected to the signal Out2 532. The signal Outl 530 also controls the last PMOS transistor 510 to generate a third output Out3. The signal Out2 532 also controls the last NMOS transistor 512 to generate a fourth output Out4. The third output Out3 is electrically coupled to the fourth output Out4 to generate one output Y. The gate terminal of the connected PMOS transistor arrangement 506 is connected to ground V SS and the gate terminal of the connected NMOS transistor arrangement 508 is connected to the supply voltage V DD . Both the connected PMOS transistor arrangement 506 and the connected NMOS transistor arrangement 508 are turned on. The drain terminal of the connected PMOS transistor arrangement 506 is connected with the drain terminal of the connected NMOS transistor arrangement 508, thereby having an intermediate signal n 528. The source terminal of the first PMOS transistor 502 and the source terminal of the last PMOS transistor 510 are connected to V DD . The source terminal of the first NMOS transistor 502 and the source terminal of the last NMOS transistor 512 are connected to V SS .

[0080] Note that the final PMOS transistor 510 and the final NMOS transistor 512 are preferentially enlarged in size to mitigate SET; the enlarged transistors are marked with an asterisk (*) 540. The size of the final PMOS transistor 510 and the final NMOS transistor 512 can be determined based on how much critical charge is expected to change per unit chord length. Other transistors 502, 504, 506, and 508 may not require enlargement.

[0081] When input A is at logic "0", this causes the first NMOS transistor 504 to turn off and the first PMOS transistor 502 to turn on. The first PMOS transistor 502 charges signal Out1 530 to logic "1", and also charges signals n 528 and Out2 532 to logic "1" via the second sub-circuit 560. Signals Out1 530 and n 528 are in a state with V DD The full voltage level is a strong logic "1", while the signal Out2 532 is in a state with V DD -V tn The weak logic "1" of the voltage level (due to the threshold voltage drop across the NMOS transistor connected to the 508 array, the threshold voltage of the NMOS transistor is called V). tn Finally, PMOS transistor 510 turns off, while NMOS transistor 512 turns on, thereby discharging output Y to logic "0" (i.e., the same logic as A).

[0082] Similarly, when input A is at logic "1", this causes the first PMOS transistor 502 to turn off and the first NMOS transistor 504 to turn on. The first NMOS transistor 504 discharges Out2 532 to logic "0", and also discharges signals n 528 and Out1 530 to logic "0" via the second sub-circuit 560. Signals Out2 532 and n 528 are at a strong logic "0" with a voltage of 0V (i.e., ground), while signal Out1 530 is at a strong logic "0" with a voltage of 0V (i.e., ground). tp The weak logic "0" of the voltage level (due to the threshold voltage drop across the PMOS transistor arrangement 506, the threshold voltage of the PMOS voltage transistor is called V). tp Finally, NMOS transistor 512 turns off, while PMOS transistor 510 turns on, thereby charging output Y to logic "1" (i.e., the same logic as A).

[0083] Now will describe Figure 5The depicted buffer 500 can mitigate SET. A charged particle can hit the buffer circuit 500 at any of the locations of the outputs Y, signal Outl 530, n 528 and Out2 532, and input A, and cause a SET to occur at that location. Consider the case where a SET occurs at the location of the output Y. To prevent a SET at Y, the last PMOS transistor 510 and the last NMOS transistor 512 need to be increased in size so that these two transistors 510, 512 have large current driving capability to cancel out any induced charge. The larger the transistor size of the transistors 510 and 512, the higher the resistance to SET (at the cost of higher power consumption and larger area).

[0084] Consider the case of a SET occurring at any of the locations of signals Outl 530, n 528, and Out2 532. In a first scenario where input A is at logic "0", the internal signals Outl 530, n 528, and Out2 532 will be at logic "1" to cause output Y to be at logic "0". To cause an output Y error of logic "1", the last PMOS transistor 510 needs to be turned on by having a logic "0" at signal Outl 530. If a SET occurs at signal Outl 530, because signal Outl 530 is connected to the drain terminal of first PMOS transistor 502 and to the source terminal of second PMOS 506, no negative SET will be caused at signal Outl 530 due to these transistors 502, 506 being PMOS transistors. If a SET occurs at the drain terminal of the NMOS transistor arrangement 508, a negative SET can be caused at signal n 528. However, any negative charge induced on signal n 528 is distributed across signals Outl 530 and Out2 532. By charge distribution, the voltage on signal Outl 530 will not likely change from logic "1" to logic "0", thus the last PMOS transistor 510 is not likely to turn on, preventing an output Y error of logic "1". Even if a SET occurs at signal Out2 532, the induced negative charge is not likely to be able to get past signal n 528 to signal Outl 530 and turn on the last PMOS transistor 510 to cause an output Y error of logic "1". The transistor sizes of PMOS transistors 502 and 506 are used to limit the charge sharing from signal n 528 to signal Outl 530. Specifically, the first PMOS transistor 502 has a greater drive capability than the drive capability of the connected PMOS transistor arrangement 506. This is accomplished by keeping the aspect ratio W / L of the first PMOS transistor 502 at a standard size, but making the connected PMOS transistor arrangement 506 weaker by having a larger L. Alternatively, the W / L of the connected PMOS transistor arrangement 506 can be kept at a standard size, but the first PMOS transistor 502 can be made stronger by having a large W.

[0085] Similarly, in a second scenario where input A is at logic "1", internal signals Outl 530, n 528 and Out2 532 will be at logic "0" to cause output Y to be at logic "1". To cause an output error of logic "0", the last NMOS transistor 540 needs to be turned on by having a logic "1" at signal Out2 532. If a SET occurs at signal Out2 532, because signal Out2 532 is only connected to the drain terminal of the first NMOS transistor 504 and the source terminal of the connected NMOS transistor arrangement 508, no positive SET will be caused due to these transistors 504, 508 being NMOS transistors. If a SET occurs at the drain terminal of the connected PMOS transistor arrangement 506, a positive SET can be caused at signal n 528. However, any induced positive charge on signal n 528 is distributed over signals Outl 530 and Out2 532. By charge distribution, the voltage on signal Out2 532 will not likely change from logic "0" to logic "1", thus the last NMOS transistor 512 is not likely to turn on, preventing an output Y error of logic "0". Even if a SET occurs at signal Outl 530, the induced positive charge is not likely to be able to get past signal n 528 to signal Out2 532 and turn on the last NMOS transistor 512 to cause an output Y error of logic "0". The transistor size of NMOS transistors 504 and 508 is used to limit the charge sharing from signal n 528 to signal Out2 532. Specifically, the first NMOS transistor 504 has a greater drive capability than the drive capability of the connected NMOS transistor arrangement 508. This is achieved by keeping the aspect ratio W / L of the first NMOS transistor 504 to a standard size, but weakening the connected NMOS transistor arrangement 508 by having a large L. Alternatively, the W / L of the connected NMOS transistor arrangement 508 can be kept to a standard size, but the first NMOS transistor 504 can be strengthened by having a large W.

[0086] For consideration of small area, the connected PMOS transistor arrangement 506 and the connected NMOS transistor arrangement 508 in the second sub-circuit 560 preferably have weak drive capability, i.e., by having a larger L for both transistors 506 and 508.

[0087] In the case of a SET occurring at input A, the SET pulse can be mitigated by driving input A with a drive circuit of increased size. The drive circuit can be the RHBD inverter 150 as depicted in FIG. IB.

[0088] For simplicity, as long as input A and output Y are driven by large current drive capability transistors (e.g., transistors 152 and 154 in FIG. IB as the drive circuit for input A, while Figure 5The transistors 510 and 512 are used for one output Y) drive, Figure 5 The RHBD buffer circuit 500 in the is less likely to be affected by any SET without requiring an increase in the size of all other transistors in the circuit 500. Specifically, the signals Outl 530, n 528, and Out2 532 are partially protected by the second sub-circuit 560 such that the transistors 510 and 512 in the third sub-circuit 570 are less likely to be accidentally triggered by a SET.

[0089] In alternative embodiments, each of the transistors 502, 504, 506, 508, 510, 512 described above with reference to Figure 5 may be embodied as a network comprising a plurality of transistors. For example, the first PMOS transistor 502 can be embodied as a first PMOS network. The first NMOS transistor 504 can be embodied as a first NMOS network. The connected PMOS transistor arrangement 506 can be embodied as a second PMOS network. The connected NMOS transistor arrangement 508 can be embodied as a second NMOS network. The last PMOS transistor 510 can be embodied as a last PMOS network. The last NMOS transistor 512 can be embodied as a last NMOS network. Each of the first PMOS network, the second PMOS network, the third PMOS network, and the last PMOS network comprises a plurality of PMOS transistors. Each of the first NMOS network, the second NMOS network, the third NMOS network, and the last NMOS network comprises a plurality of NMOS transistors.

[0090] Figure 6 Another exemplary embodiment of a circuit 600 configured as a compound gate to perform an AND- or OR operation is depicted for mitigating SETs. The circuit 600 includes a first sub-circuit 650, a second sub-circuit 660, and a third sub-circuit 670. The first sub-circuit 650 receives a set of input signals (i.e., Al, A2, and A3). The first sub-circuit 650 includes a first PMOS transistor arrangement 602 and a first NMOS transistor arrangement 604. The second sub-circuit 660 includes a connected PMOS transistor arrangement 606 and a connected NMOS transistor arrangement 608, each of which includes only one PMOS transistor 606 and only one NMOS transistor 608, respectively. The third sub-circuit 670 includes a last PMOS transistor arrangement 610 and a last NMOS transistor arrangement 612, each of which includes only one last PMOS transistor 610 and only one last NMOS transistor 612, respectively.

[0091] The first PMOS transistor arrangement 602 comprises a network of three PMOS transistors 602a, 602b, 602c. The PMOS transistors 602b and 602c are connected in parallel to each other. The transistor PMOS 602a is connected in series with the PMOS transistors 602b and 602c. The PMOS transistors 602a, 602b and 602c together form a pull-up network, which transistors are grouped and collectively used as the first PMOS transistor arrangement 602.

[0092] The first NMOS transistor arrangement 604 comprises a network of three NMOS transistors 604a, 604b, 604c. The transistors 604b and 604c are connected in series and together in parallel with the transistor 604a. The NMOS transistors 604a, 604b and 604c together form a pull-down network, which transistors are grouped and collectively used as the first NMOS transistor 604.

[0093] The input A1 controls the PMOS transistor 602a and the NMOS transistor 604a. The input A2 controls the PMOS transistor 602b and the NMOS transistor 604b. The input A3 controls the PMOS transistor 602c and the NMOS transistor 604c. The PMOS transistors 602a, 602b and 602c drive the signal Outl 630 and control the gate terminal of the last PMOS transistor 610 to produce the third output Out3. The NMOS transistors 604a, 604b and 604c drive the signal Out2 632 and control the gate terminal of the last NMOS transistor 612 to produce the fourth output Out4. The third output Out3 is electrically coupled to the fourth output Out4 to produce one output Y 622.

[0094] The connected PMOS transistor arrangement 606 and the connected NMOS transistor arrangement 608 are connected in series, their drain connections are connected such that the connected PMOS transistor arrangement 606 and the connected NMOS transistor arrangement 608 are used as a resistive network to mitigate SETs, such that any SET will not affect the last PMOS transistor 640 or the last NMOS transistor 612. The SET protection mechanism of the internal signals Outl 630, n 628 and Out2632 is the same as described above in Figure 5 The circuit design 600 in Figure 6 The circuit design 600 in

[0095] In alternative embodiments of the circuit 600 (not shown), the first p-type transistor arrangement 602 can include multiple (e.g., two) p-type transistors connected in series or in parallel, while the first n-type transistor arrangement 604 can include multiple (e.g., two) n-type transistors connected in series or in parallel. Notably, when the p-type transistors in the first p-type transistor arrangement 602 are connected in series, the n-type transistors in the first n-type transistor arrangement 604 should be connected in parallel. Similarly, when the p-type transistors in the first p-type transistor arrangement 602 are connected in parallel, the n-type transistors in the first n-type transistor arrangement 604 should be connected in series.

[0096] For completeness, in various embodiments of the inventive circuit, any function logic gate can be implemented by providing a pull-up network (e.g., as the first PMOS transistor arrangement 602) and a pull-down network (e.g., as the first NMOS transistor arrangement 604) in a first sub-circuit. For example, the pull-up network and the pull-down network can have one, two, three, or any other number of inputs. The first sub-circuit can then control a third sub-circuit to drive an output Y with a separate transistor configuration (e.g., the last PMOS transistor 610 and the last NMOS transistor 612) controlled by a second sub-circuit. The second sub-circuit includes PMOS transistors (e.g., the connected PMOS transistor arrangement 606) and NMOS transistors (e.g., the connected NMOS transistor arrangement 608) connected in series as a resistive network, and the PMOS transistors of the second sub-circuit are connected to the PMOS pull-up network of the first sub-circuit, while the NMOS transistors of the second sub-circuit are connected to the NMOS pull-down network of the first sub-circuit.

[0097] Figure 7 Another exemplary embodiment of a circuit 700 configured to mitigate SET is depicted, which is a tri-state buffer 700 somewhat similar to the buffer 500 described above with reference to Figure 5 FIG. 4. The tri-state buffer 700 includes a first sub-circuit 750, a second sub-circuit 760, and a third sub-circuit 770. Figure 7 The first sub-circuit 750 in the circuit 700 is the same as the first sub-circuit 550 shown in Figure 5 FIG. 5. Figure 7 The third sub-circuit 770 in the circuit 700 is the same as the third sub-circuit 570 shown in Figure 5The third sub-circuit 570 shown is identical. However, the second sub-circuit 760 includes not only the series-connected PMOS transistor arrangement 706 and the series-connected NMOS transistor arrangement 708, but also a second PMOS transistor arrangement 714 and a second NMOS transistor arrangement 716. In this configuration, the series-connected PMOS transistor arrangement 706 includes only one PMOS transistor 706, the series-connected NMOS transistor arrangement 708 includes only one NMOS transistor 708, the second PMOS transistor arrangement 714 includes only one PMOS transistor 714, and the second NMOS transistor arrangement 716 includes only one NMOS transistor 716. The source terminal of the second PMOS transistor 714 is connected to the first output Out1 730, while the source terminal of the second NMOS transistor 716 is connected to the second output Out2 732. The gate terminals of the series-connected PMOS transistor arrangement 706 and the second NMOS transistor 716 are controlled by input B. The gate terminals of the series-connected NMOS transistor arrangement 708 and the second PMOS transistor 714 are controlled by input nB 726. Input B 724 and input nB 726 are complementary. Therefore, with respectively in Figure 5 and Figure 6 The second sub-circuits 560 and 660 shown are different. In sub-circuit 760, inputs B 724 and nB726 are controllable and are not permanently bound to V. SS and V DD .

[0098] When inputs B724 and nB726 are at logic "0" and "1" respectively, the PMOS transistor arrangement 706 and the NMOS transistor arrangement 708 are turned on, while the second PMOS transistor 714 and the second NMOS transistor 716 are turned off. In this case, the tri-state buffer 700 can be used as a buffer, which has the same characteristics as... Figure 5 The buffer 500 described in the text has the same function and the same strong SET hardness / relief.

[0099] When inputs B 724 and nB 726 are at logic "1" and "0" respectively, the PMOS transistor arrangement 706 and the NMOS transistor arrangement 708 are turned off, while the second PMOS transistor 714 and the second NMOS transistor 716 are turned on. Output Y is in a high-impedance state. Note that SET can interrupt internal signals Out1 730, n 728, and Out2 732 to unexpectedly trigger either the last PMOS transistor 710 or the last NMOS transistor 712.

[0100] In an alternative embodiment (not shown), each PMOS transistor arrangement may include multiple PMOS transistors, and each NMOS transistor arrangement may include multiple NMOS transistors.

[0101] Figure 8 An exemplary embodiment of circuitry 800 for mitigating SET, configured as a resettable tri-state buffer 800, is depicted, which is consistent with the above-referenced... Figure 7 The described tri-state buffer 700 is somewhat similar. The resettable tri-state buffer 800 includes a first sub-circuit 850, a second sub-circuit 860, and a third sub-circuit 870. The first sub-circuit 850 is similar to... Figure 7 The first sub-circuit 750 shown is the same. The second sub-circuit 860 is the same. Figure 7 The second sub-circuit 760 shown is identical. The third sub-circuit 870 includes a final PMOS transistor arrangement 810 and a final NMOS transistor arrangement 812. The final PMOS transistor arrangement 810 includes two PMOS transistors 810a and 810b and generates a third output Out3. The final NMOS transistor arrangement 812 includes two NMOS transistors 812a and 812b and generates a fourth output Out4. The third output Out3 is electrically coupled to the fourth output Out4 to generate an output Y822. PMOS transistors 810a and 810b are connected in series at V DD Between one output Y 822 and NMOS transistors 812a and 812b connected in parallel to V SS Between an output Y 822.

[0102] PMOS transistor 810b and NMOS transistor 812b are controlled by reset signal R 834. When reset signal R 834 is at logic "1", this discharges output Y 822 to logic "0"—a reset operation. When reset signal R 834 is at logic "0", the resettable tri-state buffer 800 functions similarly to... Figure 7 The tri-state buffer 700 is the same. To alleviate SET, the PMOS transistors 810a and 810b and NMOS transistors 812a and 812b in the third sub-circuit may need to be enlarged (and they are marked with an asterisk (*) 840).

[0103] Figure 9 An exemplary embodiment of circuitry 900 for mitigating SET (Set-Off) is depicted, configured as a configurable tri-state buffer 900, which is somewhat similar to a resettable tri-state buffer 800. The configurable tri-state buffer 900 includes a first sub-circuit 950, a second sub-circuit 960, and a third sub-circuit 970. The first sub-circuit 950 is connected to... Figure 8 The first sub-circuit 850 shown is the same. The second sub-circuit 960 is the same.Figure 8 The second sub-circuit 860 is shown to be identical to the first sub-circuit 850. The third sub-circuit 970 includes a last PMOS transistor arrangement 910 and a last NMOS transistor arrangement 912. The last PMOS transistor arrangement 910 includes two PMOS transistors 910a, 910b and generates a third output Out3. The last NMOS transistor arrangement 912 includes two NMOS transistors 912a, 912b and generates a fourth output Out4. The third output Out3 is electrically coupled to the fourth output Out4 to generate an output Y 922. The PMOS transistors 910a and 910b are connected in parallel between VDD and the output Y 922, while the NMOS transistors 912a and 912b are connected in series between VSS and the output Y 922. DD The PMOS transistors 910a and 910b are connected in parallel between VDD and the output Y 922, while the NMOS transistors 912a and 912b are connected in series between VSS and the output Y 922. SS The PMOS transistors 910a and 910b are connected in parallel between VDD and the output Y 922, while the NMOS transistors 912a and 912b are connected in series between VSS and the output Y 922.

[0104] The PMOS transistors 910b and the NMOS transistors 912b are controlled by a set signal S 934. When the set signal S 934 is at logic “0”, this charges the output Y 922 to logic “1” - a set operation. When the set signal S 934 is at logic “1”, the settable tri-state buffer 900 is functionally identical to the tri-state buffer 700 in Figure 7 The PMOS transistors 910a and 910b and the NMOS transistors 912a and 912b in the third sub-circuit are preferably increased in size (and they are marked with a star (*) 940) in order to mitigate SET. The set signal S 934 is also preferably increased in size (and it is marked with a star (*) 942) in order to mitigate SET.

[0105] Tri-state buffers are the most critical building blocks that make up sequential logic, including latches and flip-flops. Figure 10A An exemplary design of a latch 1000 is depicted, which includes two circuits configured as tri-state buffers 700a, 700b, both of which are identical to the tri-state buffer 700 described above with reference to FIG. 7. Figure 7The depicted tri-state buffer 700 is identical. The two tri-state buffers 700a and 700b are connected in a feedback fashion to some extent, where one output Y of the first buffer 700a is electrically coupled to one input A of the second buffer and to one output Y of the second buffer 700b, where the B signal of the first buffer 700a is electrically coupled to the nB signal of the second buffer 700b, and where the B signal of the second buffer 700b is electrically coupled to the nB signal of the first buffer 700a. The inputs are D 1002, CLK 1004, and nCLK 1006, where CLK 1004 and nCLK 1008 are complementary. The output is Q 1008. When CLK 1002 and nCLK 1004 are at logic “1” and logic “0”, respectively, the tri-state buffer 700a is in a transparent state, where the output Q 1008 follows the input D 1002, while the tri-state buffer 700b is in an opaque state. Conversely, when CLK 1002 and nCLK 1004 are at logic “0” and logic “1”, respectively, the output Q 1008 is maintained by the tri-state buffer 700b in a transparent state, while the tri-state buffer 700a is in an opaque state.

[0106] Figure 10B An exemplary design of a resettable latch 1020 is depicted, which includes two circuits configured as resettable tri-state buffers 800a, 800b, both of which are identical to the above-described resettable tri-state buffer 800. Figure 8 The depicted resettable tri-state buffer 800 is identical. The two resettable tri-state buffers 800a and 800b are connected in a feedback fashion to some extent, where one output Y of the first buffer 800a is electrically coupled to one input A of the second buffer and to one output Y of the second buffer 800b, where the B signal of the first buffer 800a is electrically coupled to the nB signal of the second buffer 800b, and where the B signal of the second buffer 800b is electrically coupled to the nB signal of the first buffer 800a. The inputs are R 1030, D 1022, CLK 1024, and nCLK 1026, where CLK 1024 and nCLK 1026 are complementary. The output is Q 1028. With the input R 1030 at logic “1”, where both resettable tri-state buffers 800a and 800b are reset; the output Q is at logic “0”. Conversely, with the input R 1030 at logic “0”, where the resettable latch design 1020 is functionally identical to the latch design 1000 depicted in Figure 10A The latch design 1000 depicted in

[0107] Figure 10CAn exemplary design of a resettable latch 1040 is depicted, which includes two circuits of resettable tri-state buffers 900a, 900b configured as a resettable tri-state buffer 900, both of which are identical to the resettable tri-state buffer 900 described above with reference to Figure 9 The two resettable tri-state buffers 900a and 900b are connected in a feedback fashion in a sense that one output Y of the first buffer 900a is electrically coupled to one input A of the second buffer and to one output Y of the second buffer 900b, where the B signal of the first buffer 900a is electrically coupled to the nB signal of the second buffer 900b, and where the B signal of the second buffer 900b is electrically coupled to the nB signal of the first buffer 900a. The inputs are S 1050, D 1042, CLK 1044, and nCLK 1046, where CLK 1044 and nCLK 1046 are complementary. The output is Q 1048. With the input S 1050 at logic “1”, where both settable tri-state buffers 900a and 900b are set, the output Q 1048 is at logic “1”. Conversely, with the input S 1050 at logic “0”, where the settable latch design 1040 is functionally identical to the latch design 1000 depicted in Figure 10A

[0108] Figure 11A An exemplary design of a D flip-flop 1100 is depicted, which includes two latches 1000a and 1000b connected in series, where the output O of the first latch 1000a is electrically coupled to the input D of the second latch 1000b. The latches 1000a and 1000b are identical to the latch 1000 depicted above with reference to Figure 10A The two latches 1000a and 1000b form a master-slave latch structure. The inputs are D 1102, CLK 1104, and nCLK 1106, where CLK 1104 and nCLK 1106 are complementary. The output is Out 1110. When the signals CLK 1104 and nCLK 1106 are at logic “1” and logic “0”, respectively, the latch 1000a is in a transparent state, where the signal nl 1108 follows the input Inl 1102, while the latch 1000b is still latching the previous signal, where the output Out 1110 is not charged. Conversely, when the signals CLK 1104 and nCLK 1106 are at logic “0” and logic “1”, respectively, the latch 100b is in a transparent state, where the output Out 1110 follows the signal nl 1108, while the latch 1000a is still latching the signal nl 1108.

[0109] Figure 11B ​An exemplary design of a D flip-flop 1120 is depicted that includes two resettable latches 1020a and 1020b connected in series, where the output Q of the first latch 1020a is electrically coupled to the input D of the second latch 1020b. The latches 1020a and 1020b are both the same as the latch 1000 depicted above. Figure 10B The two resettable latches 1020a and 1020b form a master-slave latch structure. The inputs are R 1132, D 1122, CK 1124, and nCK 1126, where CK 1124 and nCK 1126 are complementary. The output is Out 1130. With the signal R 1132 at logic “1”, both resettable latches 1020a and 1020b are reset, where the signal nl 1128 and the output Out 1130 are at logic “0”. Conversely, with the signal R 1132 at logic “0”, the resettable D flip-flop design 1120 is functionally the same as the D flip-flop design 1100 depicted in Figure 11A

[0110] Figure 11C An exemplary design of a D flip-flop 1140 is depicted that includes two settable latches 1040a and 1040b connected in series, where the output O of the first latch 1040a is electrically coupled to the input D of the second latch 1040b. The latches 1040a and 1040b are both the same as the latch 1040 depicted above. Figure 10C The two settable latches 1040a and 1040b form a master-slave latch structure. The inputs are S 1152, D 1142, CK 1144, and nCK 1146, where CK 1144 and nCK 1146 are complementary. The output is Out 1150. With the signal S 1152 at logic “0”, both settable latches 1040a and 1040b are set, where the signal nl 1148 and the output Out 1150 are at logic “1”. With the signal S 1152 at logic “1”, the settable D flip-flop design 1140 is functionally the same as the D flip-flop design 1100 depicted in Figure 11A

[0111] In alternative embodiments (not shown), other latch and flip-flop designs can be implemented, including designs with set, with reset, with an enable signal, with other control signals. The latch and flip-flop designs can also be optimized by merging / sharing parts of the same circuit or including additional circuitry.

[0112] Figure 12 An exemplary embodiment of a circuit 1200 for mitigating SETs is depicted that is configured as a memory circuit 1200. The memory circuit 1200 includes the exemplary embodiment of the circuit 1200 described above with reference to Figure 7 ​​A tri-state buffer 700, a write sub-circuit 1250, and a read sub-circuit 1260 are described. Input signals are WC 1202, n WC 1204, D 1206, and RC 1208. Signals WC 1202 and n WC 1204 are complementary. An output signal is BL 1210. The output Y of the tri-state buffer 700 is connected to its input A 720, thereby collectively generating a signal n2 1212 to the memory circuit 1200. The write sub-circuit 1250 includes two PMOS transistors 1220, 1222 connected in series with each other and two NMOS transistors 1224, 1226 connected in series with each other. The read sub-circuit 1260 includes two NMOS transistors 1228, 1230 connected in series with each other. The signal n2 1212 is connected to the drain terminal of the PMOS transistor 1222 and the drain terminal of the NMOS transistor 1224 of the write sub-circuit 1250. The signal n2 1212 also controls the NMOS transistor 1228 of the read sub-circuit 1260. The write control signals WC 1202 and nWC 1204 control the signals B 724 and nB 726 of the tri-state buffer 700, respectively. The write control signals WC 1202 and nWC 1204 control the NMOS transistor 1224 and the PMOS transistor 1222 of the write sub-circuit 1250, respectively. The write data signal D 1206 controls the PMOS transistor 1220 and the NMOS transistor 1226 of the write sub-circuit 1250. The read control signal RC 1208 controls the NMOS transistor 1230 of the read sub-circuit 1260. The bit line BL 1210 is connected to the drain of the NMOS transistor 1230 of the read sub-circuit 1260.

[0113] In a scenario of waiting for a read operation, the write control signals WC 1202 and nWC 1204 are at logic “0” and “1”, respectively, and the signal n2 1212 is latched by the tri-state buffer 700. The signal RC 1208 is at logic “1”, such that the logic “1” stored at the signal n2 1212 controls the NMOS transistor 1228 to discharge the bit line BL 1212 to logic “0”, or otherwise, the logic “0” stored at the signal n2 1212 can not control the NMOS transistor 1228, leaving the bit line BL 1212 at logic “1” (assuming the bit line BL 1212 is at logic “1”). The signal RC 1208 is at logic “0”, indicating no read operation.

[0114] In the write operation scenario, write control signals WC 1202 and nWC 1204 are at logic "1" and "0" respectively, and the tri-state buffer 700 is in a high-impedance state. However, the write sub-circuit 1250 can write new data into signal n21212. Data D 1206 is at logic "1", thereby controlling the NMOS transistor 1226 of the write sub-circuit 1250 to discharge signal n21212 to logic "0". Data D 1206 is at logic "0", thereby controlling the PMOS transistor 1220 of the write sub-circuit 1250 to charge signal n21212 to logic "1".

[0115] for Figure 12 The memory cell 1200 depicted in the figure has mutually exclusive write and read operations.

[0116] Figure 13 Another exemplary embodiment of circuitry 1300 configured as memory circuitry 1300 for mitigating SET is depicted. Memory circuitry 1300 includes storage circuitry 1370, write sub-circuit 1350, and read sub-circuit 1360. Input signals are WC 1380, nWC 1382, D ​​1384, and RC 1386. Signals WC 1380 and nWC 1382 are complementary. The output signal is signal BL 1388. Storage circuitry 1370 is... Figure 4 A variation of the embodiment of circuit 400 shown. Storage circuit 1370, like circuit 400, includes a first sub-circuit, a second sub-circuit, and a third sub-circuit. The first sub-circuit includes a first PMOS transistor arrangement containing a single PMOS transistor 1302 and a first NMOS transistor arrangement containing a single NMOS transistor 1304. The second sub-circuit is similar to... Figure 7 to Figure 9 The second sub-circuits 760, 860, and 960 in circuits 700, 800, and 900, respectively, are shown in the diagram. The third sub-circuit includes a final PMOS transistor arrangement and a final NMOS transistor arrangement. The final PMOS transistor arrangement includes two PMOS transistors 1314 and 1318 connected in series, while the final NMOS transistor arrangement includes two NMOS transistors 1316 and 1320 connected in series. PMOS transistor 1318 and NMOS transistor 1320 are also connected in series, and their gate terminals are respectively connected to V... SS and V DD The write sub-circuit 1350 includes two PMOS transistors 1322 and 1324 connected in series and two NMOS transistors 1326 and 1328 connected in series. The read sub-circuit 1360 includes two NMOS transistors 1330 and 1320 connected in series.

[0117] PMOS transistor 1302 drives signal Out1 1334, which controls PMOS transistor 1314. NMOS transistor 1304 drives signal Out2 1336, which controls NMOS transistor 1316. Signals Out1 1334 and Out2 1336 are electrically connected via PMOS transistor 1306 and NMOS transistor 1308, where PMOS transistor 1306 and NMOS transistor 1308 serve as a resistor network, or are otherwise charged to the supply voltage V by PMOS transistor 1310. DD The signal is discharged to ground Vss by NMOS transistor 1312. PMOS transistor 1314 drives signal Out3 1336, which controls PMOS transistor 1302. NMOS transistor 1316 drives signal Out4 1338, which controls NMOS transistor 1304. Signals Out3 1336 and Out4 1338 are electrically connected by PMOS transistor 1318 and NMOS transistor 1320, which act as a resistor network. Signal Out3 1336 is driven by PMOS transistors 1222 and 1224 in the write sub-circuit 1250. Signal Out4 1338 is driven by NMOS transistors 1226 and 1228 in the write sub-circuit 1250. Signal Out4 1338 controls NMOS transistor 1330 in the read sub-circuit 1260.

[0118] In a scenario awaiting a read operation, write control signals WC 1380 and nWC 1382 are at logic "0" and "1" respectively, and signals Out3 1336 and Out4 1338 are latched by storage circuit 1370. The following will explain how signals Out3 1336 and Out4 1338 are latched.

[0119] First consider the signal Out3 1336 (i.e., V) which is in a strong logic "1". DD The signal Out4 1338 is in a weak logic "1" state (i.e., V). DD -V tn It controls NMOS transistor 1304 to discharge signal Out2 1336 to V. SS When PMOS transistor 1306 and NMOS transistor 1308 are turned on, signal Out1 1334 is electrically connected to signal Out2 1336 and is in a weak logic "0" (i.e., V). tp The signal Out1 1334 controls the PMOS transistor 1314 to maintain the signal Out3 1336 at a strong logic "1".

[0120] Now consider the case of strong logic "0" (i.e., V). SSSignal Out4 1338 and signal Out3 1336 are in a weak logic "0" (i.e., V). tp It controls PMOS transistor 1302 to charge signal Out1 1334 to V. DD When PMOS transistor 1306 and NMOS transistor 1308 are turned on, signal Out2 1336 is electrically connected to signal Out1 1334 and is in a weak logic "1" state (i.e., V). DD -V tn The signal Out2 1336 can control the NMOS transistor 1316 to maintain the signal Out4 1336 at a strong logic "0".

[0121] In the scenario described above, where write control signals WC 1380 and nWC 1382 are at logic "0" and "1" respectively, signal RC1388 being at logic "1" causes the weak logic "1" stored at signal Out4 1338 to control NMOS transistor 1330 to discharge bit line BL 1388 to logic "0". Alternatively, the strong logic "0" stored at signal Out4 1338 may not control NMOS transistor 1330, keeping bit line BL 1338 at logic "1" (assuming bit line BL 1338 is initialized to logic "1"). Signal RC1386 being at logic "0" indicates no read operation.

[0122] In a write operation scenario, write control signals WC 1202 and nWC 1204 are at logic "1" and "0" respectively, and the storage circuit 1370 may not drive signals Out3 1336 and Out4 1338. However, the write sub-circuit 1350 can write new data to either signal Out3 1336 or signal Out4 1338. When data D 1384 is at logic "1", this controls the NMOS transistor 1328 of the write sub-circuit 1350 to discharge signal Out4 1338 to logic "0". Conversely, when data D 1384 is at logic "0", this controls the PMOS transistor 1322 of the write sub-circuit 1350 to charge signal Out3 1336 to logic "1".

[0123] for Figure 13 The memory cell 1300 is depicted in which write and read operations are mutually exclusive.

[0124] In an alternative embodiment (not shown), the second PMOS transistor 1381 may include an arrangement of multiple PMOS transistors, while the NMOS transistor 1320 may include an arrangement of multiple NMOS transistors.

[0125] Notably, transistors 1318 and 1320 are always on, which can mitigate SET. In this case, transistors 1314, 1316, 1318, and 1320 can not need to be size increased.

[0126] It should be appreciated that the techniques disclosed herein can be readily applied to any combinational circuit (e.g., NAND, AND, NOR, OR, XOR, XNOR, AOI (AND / OR / INVERTER), OAI (OR / AND / INVERTER), etc.) and any sequential logic circuit (e.g., latch, flip-flop, state holding circuit, or memory cell) or other circuit. Any modification including a change in transistor configuration or a change in input signal is made without departing from the concept or idea of a resistive network for electrically connecting a pull-up network and a pull-down network of a circuit. A resistive network having PMOS transistors connected with a pull-up network of a circuit and having NMOS transistors connected with a pull-down network of a circuit can mitigate SET at an output of the circuit.

[0127] As noted above, in the context of various embodiments, a circuit is provided in which at least some or only some of the transistors of the circuit are size increased to mitigate SEE. The circuit is a combinational circuit, a tristate buffer, a memory cell circuit, or other circuit. One or more circuit arrangements (e.g., digital logic circuits, such as sequential logic circuits) can also be provided, where each circuit arrangement can have a plurality of circuits electrically coupled to one another, where at least one of the circuits is a circuit as described above (e.g., a tristate buffer having size increased transistors). In some embodiments, each of the plurality of circuits is a circuit as described above (e.g., a tristate buffer having size increased transistors).

[0128] Various embodiments employed in various applications, including but not limited to high reliability applications. For example, one possible application involves space and satellite applications. In space, radiation effects are severe, and various embodiments can help satellite applications (e.g., pico satellites, nano satellites, macro satellites in low earth orbit (LEO), and large satellites in GEO) mitigate SEE, thus making these satellites more versatile and extending their useful life. Another possible application involves the vehicle industry, such as autonomous vehicles. For autonomous vehicles, the error rate of digital circuits must be very low for safety considerations, and the techniques disclosed herein can help address this issue. A third possible application involves high reliability medical applications. For example, implantable electronic devices need high reliability for safety considerations, and the techniques disclosed herein can help address this issue. However, it should be appreciated that the techniques disclosed herein and various embodiments can also be used for various other applications, including applications where reliability is an issue.

[0129] While the application has been particularly shown and described with reference to particular embodiments, it will be understood by those skilled in the art that various changes in form and details can be made therein without departing from the spirit and scope of the application as defined by the appended claims. For example, the terms PMOS and NMOS used in the above description can be used interchangeably with the terms p-type and n-type, respectively, as other p-type and n-type transistors, respectively, can be used in addition to the described PMOS and NMOS transistors. The scope of the application is therefore indicated by the appended claims, and all changes which come within the meaning and range of equivalents are intended to be embraced therein.

[0130] References

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Claims

1. A circuit for mitigating single-effect transient SET, the circuit having a first input, a second input, a first complementary input, a second complementary input, a first output, and a second output, and comprising: The first sub-circuit includes: The first p-type transistor arrangement includes at least one p-type transistor configured to generate the first output, and The first n-type transistor arrangement includes at least one n-type transistor configured to generate the second output. Wherein, the first p-type transistor arrangement receives the first input to control the first output, the first n-type transistor arrangement receives the second input to control the second output, and The second sub-circuit includes: A connection of p-type transistors, including at least one p-type transistor, and The n-type transistor arrangement includes at least one n-type transistor connected in series with the p-type transistor arrangement. Wherein, the drain terminal of at least one p-type transistor in the p-type transistor arrangement is electrically coupled to the drain terminal of at least one n-type transistor in the n-type transistor arrangement, and The second p-type transistor arrangement includes at least one p-type transistor, and, The second n-type transistor arrangement includes at least one n-type transistor. The first output is also electrically coupled to the drain terminal of at least one p-type transistor in the second p-type transistor arrangement, and the second output is also electrically coupled to the drain terminal of at least one n-type transistor in the second n-type transistor arrangement. The gate terminals of at least one p-type transistor in the p-type transistor arrangement and at least one n-type transistor in the second n-type transistor arrangement are controlled by the first complementary input, and the gate terminals of at least one n-type transistor in the n-type transistor arrangement and at least one p-type transistor in the second p-type transistor arrangement are controlled by the second complementary input. The source terminal of at least one p-type transistor in the second p-type transistor arrangement is connected to V DD Electrically coupled, and the source terminal of the at least one n-type transistor in the second n-type transistor arrangement is connected to V. SS Electrical coupling, The first output and the second output are electrically coupled to each other via the second sub-circuit through the connection p-type transistor arrangement and the connection n-type transistor arrangement of the second sub-circuit.

2. The circuit according to claim 1, wherein, The first output is electrically coupled to the drain terminal of at least one p-type transistor in the first p-type transistor arrangement and to the source terminal of at least one p-type transistor in the connected p-type transistor arrangement, and the second output is electrically coupled to the drain terminal of at least one n-type transistor in the first n-type transistor arrangement and to the source terminal of at least one n-type transistor in the connected n-type transistor arrangement.

3. The circuit according to claim 1, wherein, The source terminal of at least one p-type transistor in the first p-type transistor arrangement is connected to V DD Electrically coupled, and wherein the source terminal of at least one n-type transistor in the first n-type transistor arrangement is connected to V. SS Electrical coupling.

4. The circuit according to claim 1, further comprising a third output and a fourth output, and including: The third sub-circuit includes: The third p-type transistor arrangement includes at least one p-type transistor configured to generate the third output, and The third n-type transistor arrangement includes at least one n-type transistor configured to generate the fourth output. Wherein, the first output is connected to the gate terminal of at least one p-type transistor in the third p-type transistor arrangement, the second output is connected to the gate terminal of at least one n-type transistor in the third n-type transistor arrangement, and the source terminal of the at least one p-type transistor in the third p-type transistor arrangement is connected to V. DD Electrically coupled, and the source terminal of at least one n-type transistor in the third n-type transistor arrangement is connected to V. SS Electrical coupling.

5. The circuit according to claim 4 further comprises a reset input, wherein, The third p-type transistor arrangement includes two p-type transistors connected in series, and the third n-type transistor arrangement includes two n-type transistors connected in parallel. The reset input is electrically coupled to the gate of one of the two p-type transistors in the third p-type transistor arrangement and the gate of one of the two n-type transistors in the third n-type transistor arrangement.

6. The circuit according to claim 4 further comprises a setting input, wherein, The third p-type transistor arrangement includes two p-type transistors connected in parallel, and the third n-type transistor arrangement includes two n-type transistors connected in series. The setting input is electrically coupled to the gate of one of the two p-type transistors in the third p-type transistor arrangement and the gate of one of the two n-type transistors in the third n-type transistor arrangement.

7. The circuit according to claim 1, wherein, The first input and the second input are the same input.

8. The circuit of claim 1, wherein the first complementary input controls the connection p-type transistor arrangement, and wherein the second complementary input controls the connection n-type transistor arrangement.

9. The circuit according to claim 1, wherein, The first p-type transistor arrangement includes at least a first p-type transistor and a second p-type transistor, wherein the first p-type transistor and the second p-type transistor are connected in either series or parallel.

10. The circuit according to claim 9, wherein, The first p-type transistor arrangement further includes a third p-type transistor, wherein when the first p-type transistor and the second p-type transistor are connected in parallel, the third p-type transistor is connected in series with the first p-type transistor and the second p-type transistor, and wherein when the first p-type transistor and the second p-type transistor are connected in series, the third p-type transistor is connected in parallel with the first p-type transistor and the second p-type transistor.

11. The circuit according to claim 1, wherein, The first n-type transistor arrangement includes at least a first n-type transistor and a second n-type transistor, wherein the first n-type transistor and the second n-type transistor are connected in series or in parallel.

12. The circuit according to claim 11, wherein, The first n-type transistor arrangement further includes a third n-type transistor, wherein when the first n-type transistor and the second n-type transistor are connected in parallel, the third n-type transistor is connected in series with the first n-type transistor and the second n-type transistor, and wherein when the first n-type transistor and the second n-type transistor are connected in series, the third n-type transistor is connected in parallel with the first n-type transistor and the second n-type transistor.

13. The circuit according to claim 4, wherein, The third output is electrically coupled to the fourth output to produce a single output.

14. The circuit of claim 13, wherein the first input and the second input are the same input, and the circuit further comprises: Write data input; Read control input; Bit line output; Write sub-circuits, including those connected in series in V DD The two p-type transistors between the third output and the V-type transistor, and the transistor connected in series with the third output. SS The two n-type transistors between the fourth output; as well as Read sub-circuits, including those connected in series at V SS The two n-type transistors between the bit line output; in The first complementary input controls one of the two n-type transistors in the write sub-circuit. The second complementary input controls one of the two p-type transistors in the write sub-circuit. The write data input controls one of the two p-type transistors in the write sub-circuit and the other of the two n-type transistors in the write sub-circuit. The output is electrically coupled to the two p-type transistors and the two n-type transistors of the write sub-circuit, wherein the output controls one of the two n-type transistors of the read sub-circuit. The read control input controls the other of the two n-type transistors in the read sub-circuit.

15. The circuit according to claim 4, further comprising: Write data input; Read control input; Bit line output; Write sub-circuits, including those connected in series in V DD The two p-type transistors between the third output and the V-type transistor, and the transistor connected in series with the third output. SS The two n-type transistors between the fourth output; as well as The readout sub-circuit includes two n-type transistors connected in series between VSS and the bit line output; in The third p-type transistor arrangement includes multiple p-type transistors connected in series. The third n-type transistor arrangement includes multiple n-type transistors connected in series. The p-type transistors in the third p-type transistor arrangement and the n-type transistors in the third n-type transistor arrangement are connected in series, and their gate terminals are respectively connected to V. SS and V DD , The first complementary input controls one of the two n-type transistors in the write sub-circuit. The second complementary input controls one of the two p-type transistors in the write sub-circuit. The write data input controls one of the two p-type transistors in the write sub-circuit and the other of the two n-type transistors in the write sub-circuit. The third output is electrically coupled to the first input, the two p-type transistors of the writing sub-circuit, and the third p-type transistor. The fourth output is electrically coupled to the second input, the two n-type transistors of the write sub-circuit, and the third n-type transistor, and controls one of the two n-type transistors of the read sub-circuit. The read control input controls the other of the two n-type transistors in the read sub-circuit.

16. The circuit according to claim 4, wherein, The first output drives only p-type transistors, and the second output drives only n-type transistors.

17. A circuit arrangement comprising a plurality of circuits according to claim 13 electrically coupled to each other.

18. The circuit arrangement according to claim 17, wherein, The plurality of circuits includes a first circuit and a second circuit; and wherein, an output of the first circuit is electrically coupled to a first input of the second circuit, a second input of the second circuit, and an output of the second circuit; a first complementary input of the first circuit is electrically coupled to a second complementary input of the second circuit; and the second complementary input of the first circuit is electrically coupled to a first complementary input of the second circuit.

19. The circuit arrangement according to claim 17, wherein, The plurality of circuits includes a first circuit, a second circuit, a third circuit, and a fourth circuit; wherein an output of the first circuit is electrically coupled to an input of the second circuit, an output of the second circuit, and an input of the third circuit, wherein an output of the third circuit is electrically coupled to an input of the fourth circuit and an output of the fourth circuit; wherein a first complementary input of the first circuit is electrically coupled to a second complementary input of the second circuit, a second complementary input of the third circuit, and a first complementary input of the fourth circuit; and wherein a second complementary input of the first circuit is electrically coupled to a first complementary input of the second circuit, a first complementary input of the third circuit, and a second complementary input of the fourth circuit.

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