Bias circuit and signal amplification device

Abstract

The bias circuit includes a current mirror circuit, an operational amplifier and a bias signal generating circuit. The current mirror circuit includes a reference branch circuit and at least one mirror branch circuit. The reference branch circuit generates a reference current according to a base current, and the at least one mirror branch circuit generates at least one mirror current according to the reference current. The operational amplifier is coupled to the reference branch circuit and the at least one mirror branch circuit, receives a first voltage and a second voltage, and generates a control voltage according to the second voltage to adjust the first voltage. The bias signal generating circuit is coupled to the at least one mirror branch circuit, and generates a bias signal according to the at least one mirror current. The first voltage is a voltage on the reference branch circuit, and the second voltage is a voltage on the at least one mirror branch circuit or an adjusted voltage on the at least one mirror branch circuit.

Description

Technical Field

[0001] The invention relates to a bias circuit, in particular to a bias circuit capable of generating a stable bias signal according to a mirror current. Background Art

[0002] Ideally, the voltage source is used to provide a reference voltage with a fixed voltage value so that the bias circuit can generate a bias signal according to the reference voltage. However, due to uncontrollable process variations or other factors, the voltage value of the reference voltage may be offset, thereby affecting the stability of the bias signal. Summary of the invention

[0003] One embodiment of the present invention provides a bias circuit, which includes a current mirror circuit, an operational amplifier, and a bias signal generating circuit. The current mirror circuit includes a reference branch circuit and at least one mirror branch circuit. The reference branch circuit generates a reference current according to a reference current, and the at least one mirror branch circuit generates at least one mirror current according to the reference current. The operational amplifier is coupled to the reference branch circuit and the at least one mirror branch circuit, receives a first voltage and a second voltage, and generates a control voltage according to the second voltage to adjust the first voltage. The bias signal generating circuit is coupled to the at least one mirror branch circuit, and generates a bias signal according to the at least one mirror current. The first voltage is a voltage on the reference branch circuit, and the second voltage is a voltage on the at least one mirror branch circuit or an adjusted voltage on the at least one mirror branch circuit.

[0004] Another embodiment of the present invention provides a signal amplification device. The signal amplification device includes a bias circuit, an input terminal, an output terminal and an amplifier. The bias circuit includes a current mirror circuit, an operational amplifier and a bias signal generating circuit. The current mirror circuit receives a reference voltage and includes a reference branch circuit and at least one mirror branch circuit. The reference branch circuit generates a reference current according to a reference current, and at least one mirror branch circuit generates at least one mirror current according to the reference current. The operational amplifier is coupled to the reference branch circuit and the at least one mirror branch circuit, receives a first voltage and a second voltage, and generates a control voltage according to the reference second voltage to adjust the first voltage. The bias signal generating circuit is coupled to the at least one mirror branch circuit, and generates a bias signal according to the at least one mirror current. The first voltage is a voltage on the reference branch circuit, and the second voltage is a voltage on the at least one mirror branch circuit or a voltage on the at least one mirror branch circuit that has been adjusted. The input terminal receives a radio frequency signal, and the output terminal outputs an amplified radio frequency signal. The amplifier is coupled between the input terminal of the signal amplification device and the output terminal of the signal amplification device, receives a bias signal and amplifies the radio frequency signal. BRIEF DESCRIPTION OF THE DRAWINGS

[0005] Figure 1 FIG. 4 is a schematic diagram of a bias circuit according to an embodiment of the present invention.

[0006] Figure 2 is a schematic diagram of a bias circuit according to another embodiment of the present invention.

[0007] Figure 3 is a schematic diagram of a bias circuit according to another embodiment of the present invention.

[0008] Figure 4 is a schematic diagram of a bias circuit according to another embodiment of the present invention.

[0009] Figure 5 is a schematic diagram of a bias circuit according to another embodiment of the present invention.

[0010] Figure 6 FIG. 4 is a schematic diagram of a signal amplifying device according to an embodiment of the present invention.

[0011] Figure 7 is a schematic diagram of a signal amplifying device according to another embodiment of the present invention.

[0012] Explanation of symbols

[0013] 10, 20: Signal amplification device

[0014] 100 to 500, 1001 to 1003, 2001 to 2003: Bias circuit

[0015] 110, 510: Current mirror circuit

[0016] 112, 512: Reference branch circuit

[0017] 114, 514, 516: Mirror branch circuit

[0018] 120, 520: Operational amplifier

[0019] 130, 530: Bias signal generating circuit

[0020] 132, 532, 560: voltage stabilizing circuit

[0021] 240, 440, 540: Startup circuit

[0022] 350, 450, 550: Voltage selection circuit

[0023] 671 to 673, 771, 772: Low dropout regulator

[0024] AMP, AMP1 to AMP3: Amplifier

[0025] C1A, C2A, C1B to C4B, C0: capacitors

[0026] CSA, CSB: Current Source

[0027] D1A, D2A, D1B to D4B: Diodes

[0028] IB: Reference current

[0029] Im1, Im2: mirror current

[0030] Iref: reference current

[0031] Is: Starting current

[0032] N1 to N3: Node

[0033] NB, NB1 to NB3: Bias terminal

[0034] P1: External pin

[0035] R1A to R3A, R1B to R4B: Resistors

[0036] RFIN: Input terminal

[0037] RFOUT: output terminal

[0038] Sbias, Sbias1 to Sbias3: bias signals

[0039] Srf1, Srf2: radio frequency signal

[0040] T1A to T5A, T1B to T6B: Transistors

[0041] V1: first voltage

[0042] V2: Second voltage

[0043] Vctrl: control voltage

[0044] VDD1, VDD2: operating voltage terminals

[0045] VN1 to VN3: Voltage

[0046] VR1 to VR3: Reference voltage

[0047] Vref, Vref1 to Vref3: reference voltage terminals

[0048] Vset1: first default voltage

[0049] Vset2: Second default voltage

[0050] VSP: Supply voltage terminal

[0051] VSS: reference voltage terminal DETAILED DESCRIPTION

[0052] Figure 1 FIG. 1 is a schematic diagram of a bias circuit 100 according to an embodiment of the present invention. The bias circuit 100 includes a current mirror circuit 110 , an operational amplifier 120 and a bias signal generating circuit 130 .

[0053] The current mirror circuit 110 may include a reference branch circuit 112 and a mirror branch circuit 114. The reference branch circuit 112 may generate a reference current Iref according to the base current IB, and the mirror branch circuit 114 may generate a mirror current Im1 according to the reference current Iref.

[0054] The operational amplifier 120 may be coupled to the reference branch circuit 112 and the mirror branch circuit 114 to receive the first voltage V1 and the second voltage V2, and may be used to generate a control voltage Vctrl according to the second voltage V2 to adjust the first voltage V1 so that the first voltage V1 and the second voltage V2 tend to be equal. In some embodiments, the first voltage V1 may be a voltage on the reference branch circuit 112, and the second voltage V2 may be a voltage on the mirror branch circuit 114 or an adjusted voltage on the mirror branch circuit 114. The bias signal generating circuit 130 may be coupled to the mirror branch circuit 114, and may generate a bias signal Sbias according to the mirror current Im1.

[0055] In some embodiments, the bias signal generating circuit 130 may provide the bias signal Sbias to the amplifier AMP. For example, the amplifier AMP may amplify the RF signal Srf1 received from the input terminal RFIN to output the amplified RF signal Srf2 from the output terminal RFOUT, and the bias signal generating circuit 130 may output the bias signal Sbias to the bias terminal NB of the amplifier AMP, so that the amplifier AMP can operate at an appropriate bias to maintain the performance of the amplifier AMP. In some embodiments, the bias signal Sbias may be a current signal.

[0056] exist Figure 1In the embodiment, the current mirror circuit 110 may further include a current source CSA and a transistor T3A, and the reference branch circuit 112 may include a node N1, transistors T1A and T4A. The current source CSA may be coupled to the operating voltage terminal VDD1 to generate a reference current IB. The transistor T3A has a first terminal, a second terminal and a control terminal. The first terminal of the transistor T3A may be coupled to the current source CSA to receive the reference current IB, the second terminal of the transistor T3A may be coupled to the reference voltage terminal VSS, and the control terminal of the transistor T3A may be coupled to the first terminal of the transistor T3A. The node N1 may be disposed between the transistors T1A and T4A. The transistor T1A may have a first terminal, a second terminal and a control terminal. The first terminal of the transistor T1A may be coupled to the reference voltage terminal Vref, and the second terminal of the transistor T1A may be coupled to the node N1. The transistor T4A has a first terminal, a second terminal and a control terminal. The first terminal of transistor T4A can be coupled to node N1, the second terminal of transistor T4A can be coupled to reference voltage terminal VSS, and the control terminal of transistor T4A can be coupled to the control terminal of transistor T3A. That is, transistors T3A and T4A can form a current mirror structure for mirroring reference current IB to generate reference current Iref.

[0057] In addition, the mirror branch circuit 114 may include a node N2 and a transistor T2A. The node N2 may be disposed between the transistor T2A and the bias signal generating circuit 130. The transistor T2A has a first terminal, a second terminal, and a control terminal. The first terminal of the transistor T2A may be coupled to the reference voltage terminal Vref, the second terminal of the transistor T2A may be coupled to the node N2, and the control terminal of the transistor T2A may be coupled to the control terminal of the transistor T1A. In this way, the voltage difference between the control terminal and the first terminal of the transistor T1A may be substantially equal to the voltage difference between the control terminal and the first terminal of the transistor T2A, and the transistors T1A and T2A may form a current mirror structure for mirroring the reference current Iref to generate the mirror current Im1. In some embodiments, the designer may select the size of the transistors T1A and T2A (i.e., the width-to-length ratio of the transistors T1A and T2A) to adjust the ratio between the reference current Iref and the mirror current Im1. For example, the size of the transistor T2A may be larger than the size of the transistor T1A, so that the mirrored current Im1 is larger than the reference current Iref.

[0058] exist Figure 1 In the embodiment, the operational amplifier 120 may have a first input terminal, a second input terminal and an output terminal. The first input terminal of the operational amplifier 120 may be coupled to the node N1, the second input terminal of the operational amplifier 120 may be coupled to the node N2, and the output terminal of the operational amplifier 120 may be coupled to the control terminal of the transistor T1A and the control terminal of the transistor T2A. Figure 1As an example, the first voltage V1 is the voltage VN1 on the node N1 (ie, the voltage on the reference branch circuit 112 ), and the second voltage V2 is the voltage VN2 on the node N2 (ie, the voltage on the mirror branch circuit 114 ).

[0059] In some embodiments, the bias signal generating circuit 130 may include a voltage stabilizing circuit 132, a transistor T5A, a resistor R1A, and a capacitor C1A. The voltage stabilizing circuit 132 has a first end and a second end. The first end of the voltage stabilizing circuit 132 may be coupled to the node N2, and the second end of the voltage stabilizing circuit 132 may be coupled to the reference voltage end VSS. The voltage stabilizing circuit 132 may include a resistor R2A, a diode D1A, and a diode D2A. The resistor R2A has a first end and a second end. The first end of the resistor R2A may be coupled to the first end of the voltage stabilizing circuit 132. The diode D1A has a first end and a second end. The first end of the diode D1A may be coupled to the second end of the resistor R2A. The diode D2A has a first end and a second end. The first end of the diode D2A may be coupled to the second end of the diode D1A, and the second end of the diode D2A may be coupled to the second end of the voltage stabilizing circuit 132. The transistor T5A has a first end, a second end, and a control end. The first end of the transistor T5A can be coupled to the operating voltage terminal VDD2, and the control end of the transistor T5A can be coupled to the second end of the resistor R2A. The resistor R1A has a first end and a second end. The first end of the resistor R1A can be coupled to the second end of the transistor T5A, and the second end of the resistor R1A can be coupled to the bias terminal NB of the amplifier AMP and can be used to output the bias signal Sbias. The capacitor C1A has a first end and a second end. The first end of the capacitor C1A can be coupled to the control end of the transistor T5A, and the second end of the capacitor C1A can be coupled to the reference voltage terminal VSS.

[0060] In some embodiments, in order to enable the reference current Iref to be accurately mirrored to generate a stable mirrored current Im1, not only the voltage difference between the control terminal and the first terminal of the transistor T1A and the voltage difference between the control terminal and the first terminal of the transistor T2A need to be designed to be substantially equal, but also the voltage difference between the second terminal and the first terminal of the transistor T1A and the voltage difference between the second terminal and the first terminal of the transistor T2A need to be designed to be substantially equal. Further, when the mirrored current Im1 flows through the voltage stabilizing circuit 132, the resistor R2A will generate a voltage drop and turn on the diodes D1A and D2A. In this case, the second voltage V2 (i.e., the voltage VN2) can be regarded as the sum of the voltage drop of the resistor R2A and the turn-on voltage of the diodes D1A and D2A. The transistor T1A and the operational amplifier 120 can form a negative feedback loop, so the first input terminal and the second input terminal of the operational amplifier 120 can have a virtual short circuit characteristic. That is, the control voltage Vctrl generated by the operational amplifier 120 can be used to make the first voltage V1 follow the change of the second voltage V2, so that when the bias circuit 100 operates in the operation mode, the first voltage V1 and the second voltage V2 can be substantially equal. In this way, the voltage difference between the second end and the first end of the transistor T1A can be substantially equal to the voltage difference between the second end and the first end of the transistor T2A, so that the reference current Iref can be accurately mirrored to generate a stable mirror current Im1, and the bias signal generating circuit 130 can generate a stable bias signal Sbias accordingly.

[0061] In some embodiments, the bias signal generating circuit 130 and the amplifier AMP may be disposed in a first die, and the current mirror circuit 110 and the operational amplifier 120 may be disposed in a second die.

[0062] In some embodiments, when the system is just powered on, the first voltage V1 and the second voltage V2 may be the voltage on the reference voltage terminal VSS (e.g., 0V) or the voltage on the reference voltage terminal Vref (e.g., 3V), causing the current mirror circuit 110 to not operate normally. To solve the problem that the first voltage V1 and the second voltage V2 may be the voltage on the reference voltage terminal VSS, the bias circuit 100 may further include a startup circuit, which is used to enable the second voltage V2 to have an appropriate operating potential when the bias circuit 100 is started, so as to adjust the first voltage V1 accordingly.

[0063] Figure 22 is a schematic diagram of a bias circuit 200 according to another embodiment of the present invention. The bias circuit 200 has a similar structure to 100 and can operate according to a similar principle. However, the bias circuit 200 can also include a startup circuit 240. The startup circuit 240 can be coupled to the reference voltage terminal Vref and the node N2, and can generate a startup current Is to make the voltage VN2 reach a default value when the bias circuit 200 operates in the startup mode, and the second voltage V2 will also reach a default value and have an appropriate operating potential. That is, Figure 2 The second voltage V2 is taken as an example to be the voltage on the regulated mirror branch circuit 114. In some embodiments, the startup current Is can be a pulse signal. In this way, the operational amplifier 120 can output the control voltage Vctrl accordingly, so that the first voltage V1 changes from the initial value to follow the default value of the second voltage V2, and when the bias circuit 200 enters the operation mode, the first voltage V1 will tend to be equal to the second voltage V2. Therefore, the current mirror circuit 110 can operate normally, so that the reference current Iref can be accurately mirrored to generate a stable mirror current Im1, and then the bias signal generating circuit 130 can generate a stable bias signal Sbias accordingly.

[0064] Moreover, since the startup circuit 240 can pre-increase the second voltage V2 to a default value when the bias circuit 200 is started, the time for the operational amplifier 120 to adjust the first voltage V1 can be shortened, and the current mirror circuit 110 can be ensured to operate in a stable state to provide a stable mirror current Im1. In addition, the temperature of the amplifier AMP increases with the operation time, resulting in a decrease in gain. However, the startup current Is generated by the startup circuit 240 when the bias circuit 200 is started can also be used to preheat the amplifier AMP, which helps the amplifier AMP to maintain the gain within a predetermined range during subsequent operations.

[0065] Figure 31 is a schematic diagram of a bias circuit 300 according to another embodiment of the present invention. The bias circuit 300 has a similar structure to 100 and can operate according to a similar principle. However, the bias circuit 300 may further include a voltage selection circuit 350. The voltage selection circuit 350 may be coupled to the second input terminal of the operational amplifier 120 and the node N2. The voltage selection circuit 350 may set the second voltage V2 according to the voltage VN2. For example, when the voltage VN2 is greater than an upper limit voltage, the voltage selection circuit 350 may set the second voltage V2 to a first default voltage Vset1 that is less than or equal to the upper limit voltage. In some embodiments, the upper limit voltage may be less than the voltage on the reference voltage terminal Vref, and the first default voltage Vset1 may be, for example but not limited to, 2.8V. Alternatively, when the voltage VN2 is less than a lower limit voltage, the voltage selection circuit 350 may set the second voltage V2 to a second default voltage Vset2 that is greater than or equal to the lower limit voltage. In some embodiments, the second default voltage Vset2 may be, for example but not limited to, 2V. In some embodiments, the first default voltage Vset1 and the second default voltage Vset2 may be set to satisfy the operating voltage of the operational amplifier 120 and the operating voltage of the current mirror formed by the transistors T3A and T4A. Alternatively, when the voltage VN2 is between the upper limit voltage and the lower limit voltage, the voltage selection circuit 350 may set the second voltage V2 to be equal to the voltage VN2. In other words, Figure 3 The second voltage V2 is taken as an example to be the regulated voltage on the mirroring branch circuit 114 or the voltage on the mirroring branch circuit 114. In some embodiments, the second voltage V2 may be set to a value that enables the transistors T1A and T2A to operate in a saturation region.

[0066] Since the voltage selection circuit 350 can adjust the second voltage V2 according to the magnitude of the voltage VN2, the second voltage V2 can be set to an appropriate voltage value when the bias circuit 300 is started, so that the operational amplifier 120 can adjust the first voltage V1 accordingly. When the bias circuit 300 enters the operation mode, the first voltage V1 will tend to be equal to the second voltage V2. In this way, not only can the problem of voltage dropout be solved, but also the problem of voltage dropout can be solved. Figure 1 In the embodiment, the first voltage V1 and the second voltage V2 may be the voltage on the reference voltage terminal VSS or the voltage on the reference voltage terminal Vref, which can also shorten the time for the operational amplifier 120 to adjust the first voltage V1 and ensure that the current mirror circuit 110 can operate in a stable state to provide a stable mirror current Im1.

[0067] Figure 44 is a schematic diagram of a bias circuit 400 according to another embodiment of the present invention. The bias circuit 400 has a similar structure to the bias circuits 200 and 300 and can operate according to similar principles. However, the bias circuit 400 can include a startup circuit 440 and a voltage selection circuit 450. For example, in the startup mode, the bias circuit 400 can not only use the voltage selection circuit 450 to set the second voltage V2 according to the voltage VN2, but also use the startup circuit 440 to preheat the amplifier AMP. In this way, not only can the problem of the bias circuit 400 being unable to be solved, but also the problem of the bias circuit 400 being unable to be solved can be solved. Figure 1 In the embodiment, the first voltage V1 and the second voltage V2 may be the voltage on the reference voltage terminal VSS or the voltage on the reference voltage terminal Vref, which can also shorten the time for the operational amplifier 120 to adjust the first voltage V1 and ensure that the current mirror circuit 110 can operate in a stable state to provide a stable mirror current Im1. In addition, it is also helpful to maintain the gain of the amplifier AMP within a predetermined range. In other words, Figure 4 The second voltage V2 is taken as an example to be the regulated voltage on the mirror branch circuit 114 or the voltage on the mirror branch circuit 114 .

[0068] In some embodiments, when the amplifier AMP is in operation, the RF signal Srf1 may leak from the input terminal RFIN to the mirror branch circuit 114 via the bias signal generating circuit 130, causing the stability of the voltage VN2 to be affected, thereby affecting the stability of the second voltage V2. However, in the bias circuits 100 to 400, the resistor R2A and the capacitor C1A in the bias signal generating circuit 130 can be used as a low-pass filter to filter out the undesired RF signal Srf1 to reduce the interference of the RF signal Srf1 on the voltage VN2, thereby maintaining the stability of the second voltage V2. In addition, the bias circuits 100 to 400 may also include a resistor R3A and a capacitor C2A. The resistor R3A has a first end and a second end. The first end of the resistor R3A can be coupled to the second input terminal of the operational amplifier 120, and the second end of the resistor R3A can be coupled to the node N2. The capacitor C2A has a first end and a second end. The first end of the capacitor C2A can be coupled to the first end of the resistor R3A, and the second end of the capacitor C2A can be coupled to the reference voltage terminal VSS. The resistor R3A and the capacitor C2A can also be used as a low-pass filter to filter out the undesired RF signal Srf1 to reduce the interference of the RF signal Srf1 on the second voltage V2. In some embodiments, in order to improve the stability of the second voltage V2, another mirror branch circuit can be added to the current mirror circuit 110.

[0069] Figure 5is a schematic diagram of a bias circuit 500 according to another embodiment of the present invention. The bias circuit 500 has a similar structure to 400 and can operate according to a similar principle. However, the current mirror circuit 510 of the bias circuit 500 may include a reference branch circuit 512, a mirror branch circuit 514, and a mirror branch circuit 516. The mirror branch circuit 514 may generate a mirror current Im1 according to the reference current Iref, and the mirror branch circuit 516 may generate a mirror current Im2 according to the reference current Iref. In this case, the bias signal generating circuit 530 may generate a bias signal Sbias according to the mirror current Im1.

[0070] exist Figure 5 In the embodiment, the current mirror circuit 510 may further include a current source CSB and a transistor T3B, and the reference branch circuit 512 may include a node N1, transistors T1B and T4B. The current source CSB may be coupled to the operating voltage terminal VDD1 to generate a reference current IB. The transistor T3B has a first terminal, a second terminal and a control terminal. The first terminal of the transistor T3B may be coupled to the current source CSB to receive the reference current IB, the second terminal of the transistor T3B may be coupled to the reference voltage terminal VSS, and the control terminal of the transistor T3B may be coupled to the first terminal of the transistor T3B. The node N1 may be disposed between the transistors T1B and T4B. The transistor T1B has a first terminal, a second terminal and a control terminal. The first terminal of the transistor T1B may be coupled to the reference voltage terminal Vref, and the second terminal of the transistor T1B may be coupled to the node N1. The transistor T4B has a first terminal, a second terminal and a control terminal. The first terminal of transistor T4B can be coupled to node N1, the second terminal of transistor T4B can be coupled to reference voltage terminal VSS, and the control terminal of transistor T4B can be coupled to the control terminal of transistor T3B. That is, transistors T3B and T4B can form a current mirror structure for mirroring reference current IB to generate reference current Iref.

[0071] The mirror branch circuit 516 may include a node N2, a transistor T2B, and a voltage regulator circuit 560. The node N2 may be disposed between the transistor T2B and the voltage regulator circuit 560. The transistor T2B has a first terminal, a second terminal, and a control terminal. The first terminal of the transistor T2B may be coupled to the reference voltage terminal Vref, the second terminal of the transistor T2B may be coupled to the node N2, and the control terminal of the transistor T2B may be coupled to the control terminal of the transistor T1B. The voltage regulator circuit 560 has a first terminal and a second terminal. The first terminal of the voltage regulator circuit 560 may be coupled to the node N2, and the second terminal of the voltage regulator circuit 560 may be coupled to the reference voltage terminal VSS. The voltage regulator circuit 560 may include a resistor R4B, a diode D3B, and a diode D4B. The resistor R4B has a first terminal and a second terminal. The first terminal of the resistor R4B may be coupled to the first terminal of the voltage regulator circuit 560. The diode D3B has a first terminal and a second terminal. The first terminal of the diode D3B may be coupled to the second terminal of the resistor R4B. The diode D4B has a first end and a second end. The first end of the diode D4B can be coupled to the second end of the diode D3B, and the second end of the diode D4B can be coupled to the second end of the voltage stabilizing circuit 560 .

[0072] The operational amplifier 520 may have a first input terminal, a second input terminal and an output terminal. The first input terminal of the operational amplifier 520 may be coupled to the node N1, the second input terminal of the operational amplifier 520 may be coupled to the node N2, and the output terminal of the operational amplifier 520 may be coupled to the control terminal of the transistor T1B and the control terminal of the transistor T2B.

[0073] The mirror branch circuit 514 may include a node N3 and a transistor T6B. The node N3 may be disposed between the transistor T6B and the bias signal generating circuit 530. The transistor T6B has a first terminal, a second terminal and a control terminal. The first terminal of the transistor T6B may be coupled to the reference voltage terminal Vref, the second terminal of the transistor T6B may be coupled to the node N3, and the control terminal of the transistor T6B may be coupled to the control terminal of the transistor T2B. In this way, the voltage difference between the control terminal and the first terminal of the transistor T1B, the voltage difference between the control terminal and the first terminal of the transistor T2B, and the voltage difference between the control terminal and the first terminal of the transistor T6B may be substantially equal, and the transistors T1B, T2B and T6B may form a current mirror structure for mirroring the reference current Iref to generate mirror currents Im2 and Im1 respectively.

[0074] In addition, the bias signal generating circuit 530 may include a voltage stabilizing circuit 532, a transistor T5B, a resistor R1B, and a capacitor C1B. The voltage stabilizing circuit 532 may have a first terminal and a second terminal. The first terminal of the voltage stabilizing circuit 532 may be coupled to the node N3, and the second terminal of the voltage stabilizing circuit 532 may be coupled to the reference voltage terminal VSS. Figure 5In the embodiment, the voltage stabilizing circuit 532 and the voltage stabilizing circuit 560 may have similar structures. For example, the voltage stabilizing circuit 532 may include a resistor R2B, a diode D1B, and a diode D2B. The resistor R2B has a first end and a second end. The first end of the resistor R2B may be coupled to the first end of the voltage stabilizing circuit 532. The diode D1B has a first end and a second end. The first end of the diode D1B may be coupled to the second end of the resistor R2B. The diode D2B has a first end and a second end. The first end of the diode D2B may be coupled to the second end of the diode D1B, and the second end of the diode D2B may be coupled to the second end of the voltage stabilizing circuit 532. The transistor T5B has a first end, a second end, and a control end. The first end of the transistor T5B may be coupled to the operating voltage end VDD2, and the control end of the transistor T5B may be coupled to the second end of the resistor R2B. The resistor R1B has a first end and a second end. The first end of the resistor R1B can be coupled to the second end of the transistor T5B, and the second end of the resistor R1B can be coupled to the bias terminal NB of the amplifier AMP and can be used to output the bias signal Sbias. The capacitor C1B has a first end and a second end. The first end of the capacitor C1B can be coupled to the control terminal of the transistor T5B, and the second end of the capacitor C1B can be coupled to the reference voltage terminal VSS. In some embodiments, when the mirror current Im1 flows through the voltage stabilizing circuit 532, the resistor R2B will generate a voltage drop and can turn on the diodes D1B and D2B. In this case, the voltage VN3 on the node N3 can be regarded as the sum of the voltage drop of the resistor R2B and the turn-on voltage of the diodes D1B and D2B.

[0075] In some embodiments, in order to enable the reference current Iref to be accurately mirrored to generate stable mirrored currents Im2 and Im1, not only the voltage difference between the control terminal and the first terminal of the transistor T1B, the voltage difference between the control terminal and the first terminal of the transistor T2B, and the voltage difference between the control terminal and the first terminal of the transistor T6B need to be designed to be substantially equal, but also the voltage difference between the second terminal and the first terminal of the transistor T1B, the voltage difference between the second terminal and the first terminal of the transistor T2B, and the voltage difference between the second terminal and the first terminal of the transistor T6B need to be designed to be substantially equal. Further, when the mirrored current Im2 flows through the voltage stabilizing circuit 560, the resistor R4B will generate a voltage drop and can turn on the diodes D3B and D4B. In this case, the voltage VN2 on the node N2 can be regarded as the sum of the voltage drop of the resistor R4B and the turn-on voltage of the diodes D3B and D4B. The transistor T1B and the operational amplifier 520 can form a negative feedback loop, so the first input terminal and the second input terminal of the operational amplifier 520 can have a virtual short circuit characteristic. When Figure 5When the first voltage V1 is the voltage VN1 on the node N1 (i.e., the voltage on the reference branch circuit 512), and the second voltage V2 is the voltage VN2 (i.e., the voltage on the mirror branch circuit 516) as an example, the control voltage Vctrl generated by the operational amplifier 520 can be used to make the first voltage V1 follow the change of the second voltage V2, so that when the bias circuit 500 operates in the operation mode, the first voltage V1 and the second voltage V2 can be substantially equal. In some embodiments, the transistor T6B and the transistor T2B can have the same electrical characteristics, and the voltage regulator circuit 532 and the voltage regulator circuit 560 can also have the same electrical characteristics, so the voltages VN3 and VN2 can be substantially equal. In this way, the voltage difference between the second end and the first end of the transistor T1B, the voltage difference between the second end and the first end of the transistor T2B, and the voltage difference between the second end and the first end of the transistor T6B can all be substantially equal, so that the reference current Iref can be accurately mirrored to generate stable mirrored currents Im2 and Im1 respectively, so that the bias signal generating circuit 530 can output a stable bias signal Sbias.

[0076] Since the bias signal generating circuit 530 is coupled to the mirror branch circuit 514 and the second voltage V2 is related to the voltage on the mirror branch circuit 516, the RF signal Srf1 leaked from the input terminal RFIN through the bias signal generating circuit 530 will not affect the stability of the second voltage V2.

[0077] In some embodiments, the bias circuit 500 may further include a capacitor C3B and a capacitor C4B. The capacitor C3B has a first end and a second end. The first end of the capacitor C3B may be coupled to the node N3, and the second end of the capacitor C3B may be coupled to the reference voltage terminal VSS. Figure 5In the embodiment, not only the resistor R2B and the capacitor C1B in the bias signal generating circuit 530 can be used as a low-pass filter, but the resistor R2B can also be used together with the capacitor C3B as another low-pass filter to filter out the undesired RF signal Srf1 and reduce the interference of the RF signal Srf1 on the voltage VN3, thereby maintaining the stability of the voltage VN3. The capacitor C4B has a first end and a second end. The first end of the capacitor C4B can be coupled to the node N2, and the second end of the capacitor C4B can be coupled to the reference voltage terminal VSS. The resistor R4B in the voltage stabilizing circuit 560 can be used together with the capacitor C4B as a low-pass filter to filter out the undesired RF signal Srf1 and reduce the interference of the RF signal Srf1 on the voltage VN2, thereby maintaining the stability of the second voltage V2. Furthermore, the bias circuit 500 can also include a startup circuit 540, a voltage selection circuit 550, a resistor R3B and a capacitor C2B, and the circuit connection relationship and operation principle thereof can be similar to the above, so they are not repeated. In some embodiments, the startup circuit 540 and / or the voltage selection circuit 550 may be selectively configured according to different applications or system requirements. When the bias circuit 500 includes the startup circuit 540 and / or the voltage selection circuit 550, the second voltage V2 may be the regulated voltage on the mirror branch circuit 516 or the voltage on the mirror branch circuit 516.

[0078] In some embodiments, transistors T3A, T4A, T3B and T4B may be N-type metal oxide semiconductor transistors (NMOS), whereby the first terminals of transistors T3A, T4A, T3B and T4B may be drains, the second terminals may be sources, and the control terminals may be gates. Transistors T1A, T2A, T1B and T2B may be P-type metal oxide semiconductor transistors (PMOS), whereby the first terminals of transistors T1A, T2A, T1B and T2B may be sources, the second terminals may be drains, and the control terminals may be gates. Transistors T5A and T5B may be bipolar junction transistors (BJT), whereby the first terminals of transistors T5A and T5B may be collectors, the second terminals may be emitters, and the control terminals may be bases.

[0079] In some embodiments, since the strength of the RF signal is relatively weak, a single amplifier may not be able to amplify the RF signal to a sufficient strength. In this case, a multi-stage amplifier is used to amplify the RF signal. However, the RF signal may leak to the bias circuit of the last amplifier stage, and when the bias circuits of the multi-stage amplifiers are coupled to the same reference voltage terminal, the RF signal may further leak to other amplifier stages through the reference voltage terminal, causing the linearity of each amplifier stage to be affected.

[0080] Figure 6is a schematic diagram of a signal amplifying device 10 according to an embodiment of the present invention. The signal amplifying device 10 may include bias circuits 1001 and 1002, an input terminal RFIN, an output terminal RFOUT, and amplifiers AMP1 and AMP2. In some embodiments, the bias circuits 1001 and 1002 may have the same structure as the bias circuits 100, 200, 300, 400, or 500, and operate according to the same principle. The input terminal RFIN may receive a radio frequency signal Srf1, and the output terminal RFOUT may output an amplified radio frequency signal Srf2. The amplifier AMP1 may receive a bias signal Sbias1 generated by the bias circuit 1001, and the amplifier AMP2 may receive a bias signal Sbias2 generated by the bias circuit 1002. Figure 6 In the embodiment, the amplifiers AMP1 and AMP2 can be coupled between the input terminal RFIN and the output terminal RFOUT of the signal amplifying device 10. Further, the amplifier AMP2 can be coupled between the input terminal RFIN and the amplifier AMP1 of the signal amplifying device 10. That is, the signal amplifying device 10 can include two-stage amplifiers: the amplifiers AMP1 and AMP2, and the two amplifiers can be used to amplify the RF signal Srf1 successively.

[0081] In addition, the bias circuit 1001 can be coupled between the reference voltage terminal Vref1 and the bias terminal NB1 of the amplifier AMP1 to receive the reference voltage VR1. The bias circuit 1002 can be coupled between the reference voltage terminal Vref2 and the bias terminal NB2 of the amplifier AMP2 to receive the reference voltage VR2. The signal amplifying device 10 can also include a low dropout regulator (LDO) 671 and a low dropout regulator 672. The low dropout regulator 671 can be used to generate a reference voltage VR1 to the reference voltage terminal Vref1 according to the supply voltage on the supply voltage terminal VSP, and the low dropout regulator 672 can be used to generate a reference voltage VR2 to the reference voltage terminal Vref2 according to the supply voltage on the supply voltage terminal VSP. In some embodiments, in order to maintain the linearity of the amplifiers AMP1 and AMP2, the capacitor C0 can be set to filter out the undesired RF signal Srf1. Furthermore, the supply voltage terminal VSP can be further coupled to the external pin P1 of the signal amplifying device 10, and the capacitor C0 can be coupled to the external pin P1, that is, the capacitor C0 is disposed outside the signal amplifying device 10. In this way, a capacitor C0 with a larger capacitance value can be selected to effectively filter out the undesired radio frequency signal Srf1 without increasing the area of ​​the signal amplifying device 10, so that the signal amplifying device 10 is more flexible in design.

[0082] In some embodiments, the signal amplifying device 10 may further include an amplifier AMP3, a bias circuit 1003, and a low dropout regulator 673. That is, the signal amplifying device 10 may include more amplifiers, such as a three-stage amplifier: amplifiers AMP1 to AMP3, and may successively amplify the RF signal Srf1. The amplifier AMP3 may be disposed between the input terminal RFIN of the signal amplifying device 10 and the amplifier AMP2, and may receive the bias signal Sbias3 generated by the bias circuit 1003. The bias circuit 1003 may be coupled between the reference voltage terminal Vref3 and the bias terminal NB3 of the amplifier AMP3 to receive the reference voltage VR3. The low dropout regulator 673 is used to generate the reference voltage VR3 to the reference voltage terminal Vref3 according to the supply voltage on the supply voltage terminal VSP. However, the present invention does not limit the number of LDO regulators included in the signal amplifying device 10 . In some embodiments, according to system requirements, the signal amplifying device 10 may include a smaller number of LDO regulators and omit the LDO regulator 672 or 673 .

[0083] Figure 7 1 is a schematic diagram of a signal amplifying device 20 according to another embodiment of the present invention. The signal amplifying device 20 may include bias circuits 2001, 2002 and 2003, an input terminal RFIN, an output terminal RFOUT, amplifiers AMP1 to AMP3 and low dropout regulators 771 and 772. The signal amplifying device 20 has a similar structure and operating principle to 10, and the main difference lies in the bias circuit 2003 and the low dropout regulators 771 and 772 in the signal amplifying device 20.

[0084] exist Figure 7 In the embodiment, the bias circuit 2001 can be coupled between the reference voltage terminal Vref1 and the bias terminal NB1 of the amplifier AMP1 to receive the reference voltage VR1. The bias circuit 2002 can be coupled between the reference voltage terminal Vref2 and the bias terminal NB2 of the amplifier AMP2 to receive the reference voltage VR2. The bias circuit 2003 can be coupled between the reference voltage terminal Vref2 and the bias terminal NB3 of the amplifier AMP3 to receive the reference voltage VR2. The low dropout regulator 771 can be used to generate the reference voltage VR1 to the reference voltage terminal Vref1 according to the supply voltage on the supply voltage terminal VSP, and the low dropout regulator 772 can be used to generate the reference voltage VR2 to the reference voltage terminal Vref2 according to the supply voltage on the supply voltage terminal VSP. That is, the bias circuit 2003 can use the same low dropout regulator as the bias circuit 2002.

[0085] In some embodiments, in order to maintain the linearity of the amplifiers AMP1 to AMP3, the capacitor C0 may be provided to filter out the undesired RF signal Srf1. Further, the supply voltage terminal VSP may be coupled to the external pin P1 of the signal amplifying device 20, and the capacitor C0 may be coupled to the external pin P1, that is, the capacitor C0 is provided outside the signal amplifying device 20. In this way, a capacitor C0 with a larger capacitance value may be selected to effectively filter out the undesired RF signal Srf1 without increasing the area of ​​the signal amplifying device 20, so that the signal amplifying device 20 is more flexible in design.

[0086] In summary, the bias circuit and signal amplification device provided by the embodiments of the present invention can be designed so that the transistors of different branch circuits in the internal current mirror circuit can meet the required operating voltage conditions, thereby providing a stable mirror current, so that the bias signal generating circuit can generate a stable bias signal, thereby maintaining the performance of the amplifier. In addition, when the signal amplification device includes a multi-stage amplifier, it is also possible to reduce the impact of unwanted RF signals on each stage of the amplifier by setting external capacitors. The above is only a preferred embodiment of the present invention, and all equivalent changes and modifications made within the scope of the claims of the present invention should fall within the scope of the present invention.

Claims

1. A bias circuit, characterized in that: Include: A current mirror circuit includes a reference branch circuit for generating a reference current according to a reference current, and at least one mirror branch circuit for generating at least one mirror current according to the reference current; an operational amplifier, coupled to the reference branch circuit and the at least one mirror branch circuit, for receiving a first voltage and a second voltage, and for generating a control voltage according to the second voltage, wherein the control voltage is used to adjust the first voltage; as well as a bias signal generating circuit, coupled to the at least one mirror branch circuit, for generating a bias signal according to the at least one mirror current; The first voltage is a voltage on the reference branch circuit, and the second voltage is a voltage on the at least one mirror branch circuit or an adjusted voltage on the at least one mirror branch circuit; The at least one mirror branch circuit comprises a first mirror branch circuit, and the first mirror branch circuit is used to generate a first mirror current of the at least one mirror current; The bias signal generating circuit is used for generating the bias signal according to the first mirror current; The reference subcircuit contains: a first transistor having a first terminal coupled to a first reference voltage terminal, a second terminal coupled to a first node, and a control terminal; and The first mirror branch circuit comprises: A second transistor has a first terminal coupled to the first reference voltage terminal, a second terminal coupled to a second node, and a control terminal coupled to the control terminal of the first transistor.

2. The bias circuit according to claim 1, wherein: in: The bias signal generating circuit includes a first voltage stabilizing circuit having a first terminal coupled to the second node and a second terminal coupled to a reference voltage terminal. The first voltage stabilizing circuit further includes: a first resistor having a first end coupled to the first end of the first voltage stabilizing circuit and a second end; a first diode having a first end coupled to the second end of the first resistor and a second end; and A second diode has a first end coupled to the second end of the first diode and a second end coupled to the second end of the first voltage stabilizing circuit.

3. The bias circuit according to claim 2, wherein: The second voltage is the sum of the voltage drop of the first resistor and the conduction voltages of the first diode and the second diode.

4. The bias circuit according to claim 1, wherein: The operational amplifier has a first input terminal coupled to the first node, a second input terminal coupled to the second node, and an output terminal coupled to the control terminal of the first transistor and the control terminal of the second transistor.

5. The bias circuit according to claim 4, characterized in that A voltage difference between the control terminal and the first terminal of the first transistor is substantially equal to a voltage difference between the control terminal and the first terminal of the second transistor, and a voltage difference between the second terminal and the first terminal of the first transistor is substantially equal to a voltage difference between the second terminal and the first terminal of the second transistor.

6. The bias circuit according to claim 4, characterized in that: When the bias circuit operates in an operation mode, the first voltage is substantially equal to the second voltage.

7. The bias circuit according to claim 4, characterized in that: A first startup circuit is also included for generating a first startup current to make the second voltage reach a default value when the bias circuit operates in a startup mode, and the first voltage changes from an initial value to follow the default value of the second voltage.

8. The bias circuit according to claim 4, wherein: A voltage selection circuit is also included for setting the second voltage according to a voltage on the second node.

9. The bias circuit according to claim 8, characterized in that When the voltage on the second node is greater than an upper limit voltage, the voltage selection circuit sets the second voltage to a first default voltage that is less than or equal to the upper limit voltage.

10. The bias circuit according to claim 8, characterized in that When the voltage on the second node is less than a lower limit voltage, the voltage selection circuit sets the second voltage to a second default voltage that is greater than or equal to the lower limit voltage.

11. The bias circuit according to claim 8, characterized in that When the voltage on the second node is between an upper limit voltage and a lower limit voltage, the voltage selection circuit sets the second voltage to be equal to the voltage on the second node.

12. A bias circuit, characterized in that: Include: A current mirror circuit includes a reference branch circuit for generating a reference current according to a reference current, and at least one mirror branch circuit for generating at least one mirror current according to the reference current; an operational amplifier, coupled to the reference branch circuit and the at least one mirror branch circuit, for receiving a first voltage and a second voltage, and for generating a control voltage according to the second voltage, wherein the control voltage is used to adjust the first voltage; as well as a bias signal generating circuit, coupled to the at least one mirror branch circuit, for generating a bias signal according to the at least one mirror current; The first voltage is a voltage on the reference branch circuit, and the second voltage is a voltage on the at least one mirror branch circuit or an adjusted voltage on the at least one mirror branch circuit. The at least one mirror branch circuit includes a first mirror branch circuit and a second mirror branch circuit. The first mirror branch circuit is used to generate a first mirror current among the at least one mirror current. and the second mirror branch circuit is used to generate a second mirror current among the at least one mirror current; The bias signal generating circuit is used for generating the bias signal according to the first mirror current; 13. The bias circuit according to claim 12, wherein: in: The reference branch circuit includes a third transistor having a first terminal coupled to a second reference voltage terminal. A second terminal is coupled to a third node and a control terminal; The second mirror branch circuit comprises: a fourth transistor having a first terminal coupled to the second reference voltage terminal, a second terminal coupled to a fourth node, and a control terminal coupled to the control terminal of the third transistor; and A second voltage stabilizing circuit has a first terminal coupled to the fourth node and a second terminal coupled to a reference voltage terminal.

14. The bias circuit according to claim 13, wherein: in: The first mirror branch circuit includes a fifth transistor having a first terminal coupled to the second reference voltage terminal, a second terminal coupled to a fifth node, and a control terminal coupled to the control terminal of the fourth transistor; The bias signal generating circuit includes a third voltage stabilizing circuit having a first terminal coupled to the fifth node, And a second terminal is coupled to the reference voltage terminal.

15. The bias circuit according to claim 14, wherein: The electrical characteristics of the fifth transistor are the same as the electrical characteristics of the fourth transistor, and the electrical characteristics of the third voltage stabilizing circuit are the same as the electrical characteristics of the second voltage stabilizing circuit.

16. The bias circuit according to claim 13, wherein: The operational amplifier has a first input terminal coupled to the third node, a second input terminal coupled to the fourth node, and an output terminal coupled to the control terminal of the third transistor and the control terminal of the fourth transistor.

17. A signal amplification device, characterized in that: Include: A first bias circuit comprising: a first current mirror circuit for receiving a first reference voltage and comprising a first reference branch circuit and at least one first mirror branch circuit, wherein the first reference branch circuit is used to generate a first reference current according to a first reference current, and the at least one first mirror branch circuit is used to generate at least one first mirror current according to the first reference current; a first operational amplifier, coupled to the first reference branch circuit and the at least one first mirror branch circuit, for receiving a first voltage and a second voltage, and for generating a first control voltage according to the second voltage, wherein the first control voltage is used to adjust the first voltage; as well as a first bias signal generating circuit, coupled to the at least one first mirroring branch circuit, for generating a first bias signal according to the at least one first mirroring current; The first voltage is a voltage on the first reference branch circuit, and the second voltage is a voltage on the at least one first mirror branch circuit or the regulated voltage on the at least one first mirror branch circuit; An input terminal for receiving a radio frequency signal; An output terminal, used to output the amplified radio frequency signal; as well as A first amplifier is coupled between the input end of the signal amplifying device and the output end of the signal amplifying device, and is used for receiving the first bias signal and amplifying the radio frequency signal.

18. The signal amplifying device according to claim 17, characterized in that: Also includes: A second bias circuit comprising: a second current mirror circuit for receiving the first reference voltage and comprising a second reference branch circuit and at least one second mirror branch circuit, wherein the second reference branch circuit is used to generate a second reference current according to a second base current, and the at least one second mirror branch circuit is used to generate at least one second mirror current according to the second reference current; a second operational amplifier, coupled to the second reference branch circuit and the at least one second mirror branch circuit, for receiving a third voltage and a fourth voltage, and for generating a second control voltage according to the fourth voltage, wherein the second control voltage is used to adjust the third voltage; as well as a second bias signal generating circuit, coupled to the at least one second mirroring branch circuit, for generating a second bias signal according to the at least one second mirroring current; The third voltage is a voltage on the second reference branch circuit, and the fourth voltage is a voltage on the at least one second mirror branch circuit or the regulated voltage on the at least one second mirror branch circuit; as well as A second amplifier is coupled between the input end of the signal amplifying device and the first amplifier, and is used for receiving the second bias signal and amplifying the radio frequency signal.

19. The signal amplifying device according to claim 17, characterized in that: Also includes: A third bias circuit comprises: a third current mirror circuit for receiving a second reference voltage and comprising a third reference branch circuit and at least one third mirror branch circuit, wherein the third reference branch circuit is used to generate a third reference current according to a third base current, and the at least one third mirror branch circuit is used to generate at least one third mirror current according to the third reference current; a third operational amplifier, coupled to the third reference branch circuit and the at least one third mirror branch circuit, for receiving a fifth voltage and a sixth voltage, and for generating a third control voltage according to the sixth voltage, wherein the third control voltage is used to adjust the fifth voltage; as well as a third bias signal generating circuit, coupled to the at least one third mirroring branch circuit, for generating a third bias signal according to the at least one third mirroring current; The fifth voltage is a voltage on the third reference branch circuit, and the sixth voltage is a voltage on the at least one third mirror branch circuit or an adjusted voltage on the at least one third mirror branch circuit; a third amplifier, coupled between the input terminal of the signal amplifying device and the first amplifier, for receiving the third bias signal and amplifying the radio frequency signal; a first low dropout regulator, for generating the first reference voltage according to a supply voltage; as well as A second low dropout regulator is used to generate the second reference voltage according to the supply voltage.

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