RTL simulation method, device, electronic device and computer-readable storage medium

Abstract

The invention provides an RTL simulation method and a related device. The method comprises: obtaining target RTL code not covered in UVM simulation test, and determining a device under test corresponding to the target RTL code; generating Property data for a formal platform by using a target output signal and a target signal value contained in the target RTL code; establishing a signal connection between the formal platform and an input end and an output end of the device under test and starting a formal verification process, so that the formal platform sends an input signal value to the input end in an exhaustive manner; when the formal platform determines that the Property data can be covered by using the output signal value of the output end, generating a directional excitation sequence by using the target input signal value corresponding to when the Property data is covered; injecting the directional excitation sequence into a UVM environment, so that the UVM environment re-performs a UVM simulation test on the target RTL code by using the directional excitation sequence; and performing coverage verification on the RTL code not covered by conventional simulation by using the formal verification method, thereby improving the simulation analysis efficiency of the RTL code.

Description

Technical Field

[0001] The present invention relates to the field of chip verification, and in particular to an RTL simulation method, device, electronic equipment and computer-readable storage medium. Background Art

[0002] In the chip verification process, analyzing the RTL code (Register Transfer Level) coverage is a common way to analyze the execution of RTL code. In the related art, the verification personnel will perform coverage verification on the RTL code through UVM simulation test (Universal Verification Methodology), and for the RTL code that the conventional UVM simulation test cannot cover, the verification personnel will usually ask the design engineer to assist in the analysis. However, in reality, due to the complex reasons such as overlapping tasks of design engineers, normal changes of personnel and cross-departmental communication, the time cost of asking for help from others is relatively high, which is easy to increase labor costs and reduce efficiency. Summary of the invention

[0003] The purpose of the present invention is to provide an RTL simulation method, device, electronic device and computer-readable storage medium, which can use formal verification to cover RTL code not covered by conventional simulation, thereby improving the simulation analysis efficiency of RTL code.

[0004] In order to solve the above technical problems, the present invention provides an RTL simulation method, comprising:

[0005] Obtain target RTL code not covered in UVM simulation test, and determine the device under test corresponding to the target RTL code;

[0006] Generate Property data for the Formal platform using the target output signal and the target signal value contained in the target RTL code;

[0007] Establishing a signal connection between the formal platform and the input terminal and the output terminal of the device under test and starting a formal verification process, so that the formal platform sends an input signal value to the input terminal in an exhaustive manner;

[0008] When the Formal platform determines that the Property data can be covered by using the output signal value of the output terminal, a directional excitation sequence is generated by using the target input signal value corresponding to when the Property data is covered;

[0009] The directed stimulus sequence is injected into a UVM environment, so that the UVM environment re-performs the UVM simulation test on the target RTL code using the directed stimulus sequence.

[0010] Optionally, after sending the input signal to the input end in an exhaustive manner, the method further includes:

[0011] Generate an fsdb waveform file using the input signal value and the output signal value;

[0012] Correspondingly, the generating of a directional excitation sequence using the target input signal value corresponding to when the Property data is overwritten includes:

[0013] The target input signal value is extracted from the fsdb waveform file using a TCL script, and the directional excitation sequence is generated using the target input signal value.

[0014] Optionally, injecting the directed stimulus sequence into a UVM environment comprises:

[0015] The directional stimulus sequence is saved to a simulation data file, and a driver script is added to a UVM test case;

[0016] Correspondingly, the UVM environment re-performs the UVM simulation test on the target RTL code using the directional stimulus sequence, including:

[0017] The UVM environment reads the drive script from the UVM test case, and uses the drive script to extract the directional stimulus sequence from the simulation data file;

[0018] The device under test is driven by using the driving script and the directed stimulus sequence to re-perform the UVM simulation test on the target RTL code.

[0019] Optionally, before obtaining the target RTL code not covered in the UVM simulation test, the following is further included:

[0020] Obtain preset configuration information, and use the preset configuration information to initialize the Formal platform; the preset configuration information includes the clock signal, reset signal, FPV tool, working mode, instantiation file directory and top-level module name used by the Formal platform.

[0021] Optionally, establishing a signal connection between the formal platform and an input terminal and an output terminal of the device under test includes:

[0022] In the Formal platform, corresponding docking signals are generated for the input end and the output end, and the signal connection is established with the input end and the output end using the docking signals; the docking signals include a clock signal, a reset signal, an input signal and an output signal.

[0023] Optionally, after generating corresponding docking signals for the input end and the output end in the Formal platform, the method further includes:

[0024] generating an input signal constraint range for the input signal in the Formal platform;

[0025] Accordingly, the Formal platform sends the input signal value to the input terminal in an exhaustive manner, including:

[0026] The formal platform sends the input signal value to the input end in the exhaustive manner within the input signal constraint range.

[0027] Optionally, after generating corresponding docking signals for the input end and the output end in the Formal platform, the method further includes:

[0028] Generating basic detection content for the output signal in the Formal platform; the basic detection content is timing detection or sequence detection;

[0029] Correspondingly, after the Formal platform sends the input signal value to the input terminal in an exhaustive manner, it also includes:

[0030] The Formal platform uses the output signal value to determine whether the output signal meets the requirements of the basic detection content;

[0031] If so, the output signal value is used to detect whether the Property data can be overwritten.

[0032] The present invention also provides an RTL simulation device, comprising:

[0033] An acquisition module is used to acquire the target RTL code not covered in the UVM simulation test, and determine the device under test corresponding to the target RTL code;

[0034] A Property data generation module, used to generate Property data for a Formal platform using a target output signal and a target signal value contained in the target RTL code;

[0035] A simulation module, used to establish a signal connection between the formal platform and the input terminal and the output terminal of the device under test and start a formal verification process, so that the formal platform sends an input signal value to the input terminal in an exhaustive manner;

[0036] A directional excitation sequence generating module, used for generating a directional excitation sequence using a target input signal value corresponding to when the Property data is covered, when the Formal platform determines that the Property data can be covered using the output signal value of the output terminal;

[0037] The injection module is used to inject the directed stimulus sequence into the UVM environment, so that the UVM environment uses the directed stimulus sequence to re-perform the UVM simulation test on the target RTL code.

[0038] The present invention also provides an electronic device, comprising:

[0039] Memory for storing computer programs;

[0040] A processor is used to implement the RTL simulation method as described above when executing the computer program.

[0041] The present invention also provides a computer-readable storage medium, in which computer-executable instructions are stored. When the computer-executable instructions are loaded and executed by a processor, the RTL simulation method as described above is implemented.

[0042] The invention provides an RTL simulation method, comprising: obtaining target RTL code not covered in UVM simulation test, and determining a device under test corresponding to the target RTL code; generating Property data for a formal platform by using a target output signal and a target signal value contained in the target RTL code; establishing a signal connection between the formal platform and an input end and an output end of the device under test and starting a formal verification process, so that the formal platform sends an input signal value to the input end in an exhaustive manner; when the formal platform determines that the Property data can be covered by using the output signal value of the output end, generating a directional excitation sequence by using the target input signal value corresponding to when the Property data is covered; and injecting the directional excitation sequence into a UVM environment, so that the UVM environment re-performs the UVM simulation test on the target RTL code by using the directional excitation sequence.

[0043] It can be seen that the present invention can adopt the method of Formal verification to cover and verify the target RTL code that cannot be covered in the UVM simulation test, so as to assist the UVM simulation test. When the target RTL code that cannot be covered in the UVM simulation test is obtained, the present invention will determine the device under test corresponding to the segment code, and generate Property data using the target output signal and the expected target signal value contained in the segment code; Subsequently, the present invention will establish a signal connection between the Formal platform and the input and output ends of the device under test and start Formal verification, so that the Formal platform sends the input signal value to the input end in an exhaustive manner, so as to extract the possible output signal value under various input signal combination conditions from the output end; Finally, the Formal platform can be used to determine whether the Property data can be covered based on the output signal value of the output end, if it can be covered, the corresponding target input signal value when the Property data is covered will be used to generate a directional excitation sequence, and the sequence will be injected into the UVM environment, so that the UVM environment uses this sequence to re-perform the UVM simulation test on the target RTL code, without the need to manually analyze the target RTL code, and can effectively improve the analysis efficiency of the RTL code that cannot be covered by the conventional UVM simulation test. The present invention also provides an RTL simulation device, an electronic device and a computer-readable storage medium, which have the above-mentioned beneficial effects. BRIEF DESCRIPTION OF THE DRAWINGS

[0044] In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the drawings required for use in the embodiments or the description of the prior art will be briefly introduced below. Obviously, the drawings described below are only embodiments of the present invention. For ordinary technicians in this field, other drawings can be obtained based on the provided drawings without paying creative work.

[0045] Figure 1 A flow chart of an RTL simulation method provided by an embodiment of the present invention;

[0046] Figure 2 A structural block diagram of an RTL simulation device provided by an embodiment of the present invention. DETAILED DESCRIPTION

[0047] In order to make the purpose, technical solution and advantages of the embodiments of the present invention clearer, the technical solution in the embodiments of the present invention will be clearly and completely described below in conjunction with the drawings in the embodiments of the present invention. Obviously, the described embodiments are part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of the present invention.

[0048] In the related art, the verifier will perform coverage verification on the RTL code through UVM simulation testing. For the RTL code that cannot be covered by the conventional UVM simulation test, the verifier will usually ask the design engineer to assist in the analysis. However, in reality, due to complex reasons such as overlapping tasks of design engineers, normal personnel changes, and cross-departmental communication, the time cost of seeking help from others is relatively high, which can easily increase labor costs and reduce efficiency. In view of this, the present invention provides an RTL simulation method, which can use Formal verification to perform coverage verification on RTL code that is not covered by conventional simulation, thereby improving the simulation analysis efficiency of RTL code. Please refer to Figure 1 , Figure 1 A flowchart of an RTL simulation method provided by an embodiment of the present invention, the method may include:

[0049] S101, obtaining target RTL code not covered in UVM simulation test, and determining the device under test corresponding to the target RTL code.

[0050] RTL code is covered usually means that this section of code can be triggered to run in UVM simulation test, which means effective. And for the RTL code that is not covered in UVM simulation test, the reason for it not being covered may be that UVM simulation test is not complete enough, or its corresponding logic function is invalid, so it is necessary to extract and analyze the target RTL code that is not covered separately, to correct UVM simulation test, or ignore this section of code in the test link. And the purpose of this method is to cover and verify the above-mentioned RTL code that is not covered in UVM simulation test by Formal verification (formal verification), so as to assist UVM simulation test, wherein Formal verification refers to mathematically completely proving or verifying whether the implementation scheme of the circuit has indeed realized the function described in the circuit design. Specifically, the embodiment of the present invention will adopt Formal platform to perform the above-mentioned Formal verification, wherein the platform is a simulation test platform for formal verification (Formal Property Verification), which includes the environment and tools required for Formal verification. The embodiment of the present invention does not limit the specific Formal platform, and the relevant technology of formal verification can be referred to. It is understandable that the Formal platform should be configured before extracting the target RTL code. The embodiment of the present invention does not limit the specific process of configuration. For example, the clock signal, reset signal, FPV tool, working mode, instantiation file directory and top-level module name used by the Formal platform can be configured, wherein the FPV (Formal Property Verification) tool is a formal verification tool.

[0051] In a possible case, before obtaining the target RTL code not covered in the UVM simulation test, the following may also be included:

[0052] Step 11: Get the preset configuration information and use it to initialize the Formal platform; the preset configuration information includes the clock signal, reset signal, FPV tool, working mode, instantiation file directory and top-level module name used by the Formal tool.

[0053] Further, it should be noted that the embodiment of the present invention does not limit how to obtain the target RTL code not covered in the UVM simulation test, and usually these codes can be separately marked by the simulation test tool, so they can be obtained according to the marked content, and specifically can refer to the related technology of UVM simulation test and UVM simulation test tool. The embodiment of the present invention does not limit how to determine the device under test corresponding to the target RTL code, wherein the device under test (DUT, Design Under Test) is the device module to which the target RTL code belongs, and can refer to the related technology of RTL.

[0054] S102 , generating Property data for the Formal platform using the target output signal and target signal value contained in the target RTL code.

[0055] It is understandable that the RTL code can use the output signal of the device under test to implement the corresponding logic function, that is, when the target output signal corresponding to the RTL code outputs the target signal value, the logic function corresponding to the code segment is triggered. It is also understandable that after different excitation signals are input to the device under test, the device can generate different output signals. Therefore, as long as the excitation signal value that can make the target output signal corresponding to the target RTL code output the target signal value can be found, the static excitation condition that can make the target RTL code covered can be determined, and then the UVM simulation test can be corrected according to the static excitation condition. In an embodiment of the present invention, the Property data is used to determine whether the target output signal can output the target signal value, wherein the data is a special data in the Formal platform, which can be understood as a pre-defined rule, such as a constraint rule for the input signal and a constraint rule for the expected value of the output signal. Since the Property data is generated using the target output signal and the target signal value contained in the target RTL code, it is only necessary to determine whether the Property data can be covered to determine whether the target RTL code can be covered. It should be noted that the embodiment of the present invention does not limit the method for generating Property data, and reference may be made to the relevant technologies of the Formal platform.

[0056] S103 , establishing a signal connection between the formal platform and the input and output terminals of the device under test and starting a formal verification process, so that the formal platform sends an input signal value to the input terminal in an exhaustive manner.

[0057] It can be understood that in order to establish a signal connection with the input and output ends of the device under test, the Formal platform should generate corresponding docking signals according to the signals contained in the input and output ends (such as clock signals, reset signals, input signals and output signals), and then use the docking signals to connect with the device under test.

[0058] In one possible scenario, establishing signal connections between the Formal platform and the input and output terminals of the device under test may include:

[0059] Step 21: Generate corresponding docking signals for the input end and the output end in the Formal platform, and use the docking signals to establish signal connections with the input end and the output end; the docking signals include clock signals, reset signals, input signals, and output signals.

[0060] It should be noted that the embodiments of the present invention do not limit the specific forms of the clock signal, reset signal, input signal and output signal, nor do they limit the specific numbers of the above signals, which can be set according to the specific device under test.

[0061] Further, after establishing a signal connection with the device under test, the Formal platform can start the Formal verification process, that is, send the input signal value to the output end of the device under test in an exhaustive manner, and use all the input signal values ​​that the device under test can receive to test all the output signal values ​​that the device can generate. Of course, considering that the value range of the input signal is large, it is easy to cause the Formal platform to require too much test data, affecting the efficiency of the simulation test. Therefore, a corresponding input signal constraint range can also be generated for each input signal, and the input signal value can be sent to the input end in an exhaustive manner within the input signal constraint range, so as to reduce the amount of test data that the Formal platform needs to process. It should be noted that the embodiment of the present invention does not limit the generation method of the input signal constraint range, for example, it can be generated using the assume statement (constraint statement) in the Formal platform. The embodiment of the present invention also does not limit the specific input signal constraint range, which can be set according to actual application requirements, and the input signal constraint range corresponding to each input signal can be different.

[0062] In a possible case, after generating corresponding docking signals for the input end and the output end in the Formal platform, the following may also be included:

[0063] Step 31: Generate input signal constraint range for the input signal in the Formal platform;

[0064] Accordingly, the Formal platform sends input signal values ​​to the input terminal in an exhaustive manner, which may include:

[0065] Step 32: The Formal platform sends the input signal value to the input terminal in an exhaustive manner within the input signal constraint range.

[0066] Furthermore, when the output signal value of the output terminal is received, the Formal platform can use the output signal value to determine whether the Property data can be covered. Of course, in order to avoid the impact of the fault of the device under test itself on the Property data coverage verification, the Formal platform can also first use the above-mentioned output signal value to perform basic detection on the device under test. Specifically, the corresponding basic detection content can be generated for the output signal in the Formal platform, and the content can be a timing detection or a sequence detection. Furthermore, when the Formal platform receives the output signal value, it can use the preset basic detection content to determine whether the output signal meets the requirements. If it does, the output signal is further used to verify the coverage of the Property data. It should be noted that the embodiment of the present invention does not limit the specific content of the timing detection and sequence detection, and reference can be made to the relevant technology of RTL verification; the embodiment of the present invention does not limit the generation method of the timing detection and sequence detection, for example, it can be generated using the assert statement in the Formal platform. The present invention does not limit the correspondence between the output signal and the basic detection content, which can be one-to-one or many-to-one; the present invention does not limit whether it is necessary to set basic detection content for all output signals. Basic detection content can be set for some output signals or for all output signals, and can be set according to actual application requirements.

[0067] In a possible case, after generating corresponding docking signals for the input end and the output end in the Formal platform, the following may also be included:

[0068] Step 41: Generate basic detection content for the output signal; the basic detection content is timing detection or sequence detection;

[0069] Accordingly, after the Formal platform sends the input signal value to the input terminal in an exhaustive manner, it may also include:

[0070] Step 42: The Formal platform uses the output signal value to determine whether the output signal meets the requirements of the basic detection content; if so, proceed to step 43; if not, exit the detection.

[0071] Step 43: The Formal platform uses the output signal value to detect whether the Property data can be overwritten.

[0072] S104. When the Formal platform determines that the Property data can be covered by using the output signal value of the output terminal, a directional excitation sequence is generated by using the target input signal value corresponding to the Property data being covered.

[0073] It is understandable that when Property data are covered, the corresponding input signal value is the external stimulus condition that can make the target RTL code covered, so the input signal value of all input signals at this time can be written into the directional stimulus sequence, so that the UVM environment utilizes the directional stimulus sequence to re-verify the target RTL code. Of course, the directional stimulus sequence can also further include all input signal values ​​of the preset number of beats before the Property data are covered, so as to promote the verification effect of the UVM environment to the target RTL code.

[0074] Furthermore, the embodiment of the present invention does not limit the method for extracting the target input signal value. For example, the signal value input by the Formal platform can be recorded in real time. Of course, all input signal values ​​and output signal values ​​in the Formal verification can also be recorded in a waveform file to extract the target input signal value from the waveform file. The embodiment of the present invention does not limit the specific waveform file format. For example, it can be in fsdb format (Fast Signal DataBase). The embodiment of the present invention does not limit how to extract the target input signal value from the fsdb waveform file. For example, it can be extracted using a TCL script (Tool Command Language).

[0075] In a possible case, after the Formal platform sends the input signal to the input terminal in an exhaustive manner, the method further includes:

[0076] Step 51: Generate an fsdb waveform file using the input signal value and the output signal value;

[0077] Accordingly, generating a directional excitation sequence using the target input signal value corresponding to when the Property data is overwritten may include:

[0078] Step 52: Use the TCL script to extract the target input signal value from the fsdb waveform file, and use the target input signal value to generate a directional excitation sequence.

[0079] S105, injecting the directed stimulus sequence into the UVM environment, so that the UVM environment utilizes the directed stimulus sequence to re-perform UVM simulation test on the target RTL code.

[0080] Specifically, the directional stimulus sequence can be written into a simulation data file (.dat file), and a preset script can be added to the UVM test case of the UVM environment, so that the UVM environment uses the preset script to read the directional stimulus sequence from the simulation data file, and uses the sequence to re-perform UVM simulation test on the target RTL code.

[0081] In one possible scenario, injecting a directed stimulus sequence into a UVM environment may include:

[0082] Step 61: Save the directional stimulus sequence to a simulation data file and add a driver script to the UVM test case;

[0083] Accordingly, the UVM environment uses the directed stimulus sequence to re-test the target RTL code with UVM simulation, including:

[0084] Step 62: The UVM environment reads a driver script from the UVM test case, and uses the driver script to extract a directional stimulus sequence from the simulation data file;

[0085] Step 63: Use the driver script and the directed stimulus sequence to drive the device under test to re-perform UVM simulation test on the target RTL code.

[0086] Based on the above embodiment, the present invention can use the Formal verification method to cover and verify the target RTL code that cannot be covered in the UVM simulation test, so as to assist the UVM simulation test. When the target RTL code that cannot be covered in the UVM simulation test is obtained, the present invention will determine the device under test corresponding to the segment code, and generate Property data using the target output signal and the expected target signal value contained in the segment code; Subsequently, the present invention will establish a signal connection between the Formal platform and the input and output ends of the device under test, and send the input signal value to the input end in an exhaustive manner to extract the possible output signal value under various input signal combination conditions from the output end; Finally, the Formal platform can be used to determine whether the Property data can be covered based on the output signal value of the output end, and if it can be covered, the corresponding target input signal value when the Property data is covered will be used to generate a directional excitation sequence, and the sequence will be injected into the UVM environment, so that the UVM environment uses this sequence to re-perform the UVM simulation test on the target RTL code, without the need to manually analyze the target RTL code, and can effectively improve the analysis efficiency of the RTL code that cannot be covered by the conventional UVM simulation test.

[0087] The following is an introduction to the RTL simulation device, electronic device and storage medium provided in the embodiments of the present invention. The RTL simulation device, electronic device and computer-readable storage medium described below can be referenced to the RTL simulation method described above.

[0088] Please refer to Figure 2 , Figure 2 A structural block diagram of an RTL simulation device provided by an embodiment of the present invention, the device may include:

[0089] An acquisition module 201 is used to acquire target RTL codes not covered in UVM simulation test, and determine the device under test corresponding to the target RTL codes;

[0090] Property data generating module 202, used to generate Property data for the Formal platform using the target output signal and target signal value contained in the target RTL code;

[0091] The simulation module 203 is used to establish a signal connection between the formal platform and the input and output terminals of the device under test and start the formal verification process, so that the formal platform sends an input signal value to the input terminal in an exhaustive manner;

[0092] A directional excitation sequence generating module 204 is used to generate a directional excitation sequence using a target input signal value corresponding to when the Property data is covered when the Formal platform determines that the Property data can be covered using an output signal value of the output terminal;

[0093] The injection module 205 is used to inject the directed stimulus sequence into the UVM environment, so that the UVM environment uses the directed stimulus sequence to re-perform the UVM simulation test on the target RTL code.

[0094] Optionally, the device may further include:

[0095] A waveform file generation module is used to generate an fsdb waveform file using input signal values ​​and output signal values;

[0096] Accordingly, the directional excitation sequence generating module 204 may include:

[0097] The directional excitation sequence generation submodule is used to extract the target input signal value from the fsdb waveform file using a TCL script, and generate a directional excitation sequence using the target input signal value.

[0098] Optionally, the injection module 205 may include:

[0099] The injection submodule is used to save the directed stimulus sequence to the simulation data file, and add a driver script in the UVM test case, so that the UVM environment reads the driver script from the UVM test case, extracts the directed stimulus sequence from the simulation data file using the driver script, and drives the device under test using the driver script and the directed stimulus sequence to re-perform UVM simulation test on the target RTL code.

[0100] Optionally, the device may further include:

[0101] The configuration module is used to obtain the preset configuration information and use it to initialize the Formal platform; the preset configuration information includes the clock signal, reset signal, FPV tool, working mode, instantiation file directory and top-level module name used by the Formal tool.

[0102] Optionally, the simulation module 203 may include:

[0103] The connection submodule is used to generate corresponding docking signals for the input end and the output end in the Formal platform, and use the docking signals to establish signal connections with the input end and the output end; the docking signals include clock signals, reset signals, input signals and output signals.

[0104] Optionally, the simulation module 203 may further include:

[0105] The constraint range adding submodule is used to generate an input signal constraint range for the input signal in the Formal platform, so that the Formal platform sends the input signal value to the input terminal in an exhaustive manner within the input signal constraint range.

[0106] Optionally, the simulation module 203 may further include:

[0107] The detection content adding submodule is used to generate basic detection content for the output signal in the Formal platform; the basic detection content is timing detection or sequence detection, so that after the Formal platform sends the input signal value to the input end in an exhaustive manner, it uses the output signal value to determine whether the output signal meets the requirements of the basic detection content, and uses the output signal value to detect whether the Property data can be overwritten when the output signal meets the requirements of the basic detection content.

[0108] An embodiment of the present invention further provides an electronic device, including:

[0109] Memory for storing computer programs;

[0110] The processor is used to implement the steps of the RTL simulation method as described above when executing a computer program.

[0111] Since the embodiments of the electronic device part correspond to the embodiments of the RTL simulation method part, please refer to the description of the embodiments of the RTL simulation method part for the embodiments of the electronic device part, which will not be repeated here.

[0112] An embodiment of the present invention further provides a computer-readable storage medium, on which a computer program is stored. When the computer program is executed by a processor, the steps of the RTL simulation method of any of the above embodiments are implemented.

[0113] Since the embodiments of the computer-readable storage medium part correspond to the embodiments of the RTL simulation method part, please refer to the description of the embodiments of the RTL simulation method part for the embodiments of the storage medium part, which will not be repeated here.

[0114] The various embodiments in the specification are described in a progressive manner, and each embodiment focuses on the differences from other embodiments. The same or similar parts between the various embodiments can be referred to each other. For the device disclosed in the embodiment, since it corresponds to the method disclosed in the embodiment, the description is relatively simple, and the relevant parts can be referred to the method part description.

[0115] Professionals may further appreciate that the units and algorithm steps of each example described in conjunction with the embodiments disclosed herein can be implemented in electronic hardware, computer software, or a combination of the two. In order to clearly illustrate the interchangeability of hardware and software, the composition and steps of each example have been generally described in the above description according to function. Whether these functions are performed in hardware or software depends on the specific application and design constraints of the technical solution. Professionals and technicians may use different methods to implement the described functions for each specific application, but such implementation should not be considered to be beyond the scope of the present invention.

[0116] The steps of the method or algorithm described in conjunction with the embodiments disclosed herein may be implemented directly using hardware, a software module executed by a processor, or a combination of the two. The software module may be placed in a random access memory (RAM), a memory, a read-only memory (ROM), an electrically programmable ROM, an electrically erasable programmable ROM, a register, a hard disk, a removable disk, a CD-ROM, or any other form of storage medium known in the art.

[0117] The above is a detailed introduction to an RTL simulation method, device, electronic device and computer-readable storage medium provided by the present invention. Specific examples are used in this article to illustrate the principles and implementation methods of the present invention. The description of the above embodiments is only used to help understand the method of the present invention and its core idea. It should be pointed out that for ordinary technicians in this technical field, without departing from the principles of the present invention, several improvements and modifications can be made to the present invention, and these improvements and modifications also fall within the scope of protection of the claims of the present invention.

Claims

1. An RTL simulation method, characterized in that: include: Obtain target RTL code not covered in UVM simulation test, and determine the device under test corresponding to the target RTL code; Generate Property data for the Formal platform using the target output signal and the target signal value contained in the target RTL code; Establishing a signal connection between the formal platform and the input terminal and the output terminal of the device under test and starting a formal verification process, so that the formal platform sends an input signal value to the input terminal in an exhaustive manner; When the Formal platform determines that the Property data can be covered by using the output signal value of the output terminal, a directional excitation sequence is generated by using the target input signal value corresponding to when the Property data is covered; The directed stimulus sequence is injected into a UVM environment, so that the UVM environment re-performs the UVM simulation test on the target RTL code using the directed stimulus sequence.

2. The RTL simulation method according to claim 1, characterized in that: After sending the input signal to the input terminal in an exhaustive manner, the method further includes: Generate an fsdb waveform file using the input signal value and the output signal value; Correspondingly, the generating of a directional excitation sequence using the target input signal value corresponding to when the Property data is overwritten includes: The target input signal value is extracted from the fsdb waveform file using a TCL script, and the directional excitation sequence is generated using the target input signal value.

3. The RTL simulation method according to claim 1, characterized in that: The step of injecting the directed stimulus sequence into a UVM environment comprises: The directional stimulus sequence is saved to a simulation data file, and a driver script is added to a UVM test case; Correspondingly, the UVM environment re-performs the UVM simulation test on the target RTL code using the directional stimulus sequence, including: The UVM environment reads the drive script from the UVM test case, and uses the drive script to extract the directional stimulus sequence from the simulation data file; The device under test is driven by using the driving script and the directed stimulus sequence to re-perform the UVM simulation test on the target RTL code.

4. The RTL simulation method according to claim 1, characterized in that: Before getting the target RTL code that is not covered in the UVM simulation test, also include: Obtain preset configuration information, and use the preset configuration information to initialize the Formal platform; the preset configuration information includes the clock signal, reset signal, FPV tool, working mode, instantiation file directory and top-level module name used by the Formal platform.

5. The RTL simulation method according to any one of claims 1 to 4, characterized in that: The step of establishing a signal connection between the Formal platform and the input terminal and the output terminal of the device under test includes: In the Formal platform, corresponding docking signals are generated for the input end and the output end, and the signal connection is established with the input end and the output end using the docking signals; the docking signals include a clock signal, a reset signal, an input signal and an output signal.

6. The RTL simulation method according to claim 5, characterized in that: After generating corresponding docking signals for the input end and the output end in the Formal platform, the method further includes: generating an input signal constraint range for the input signal in the Formal platform; Accordingly, the Formal platform sends the input signal value to the input terminal in an exhaustive manner, including: The formal platform sends the input signal value to the input end in the exhaustive manner within the input signal constraint range.

7. The RTL simulation method according to claim 5, characterized in that: After generating corresponding docking signals for the input end and the output end in the Formal platform, the method further includes: Generating basic detection content for the output signal in the Formal platform; the basic detection content is timing detection or sequence detection; Accordingly, after the Formal platform sends the input signal value to the input terminal in an exhaustive manner, it further includes: The Formal platform uses the output signal value to determine whether the output signal meets the requirements of the basic detection content; If so, the Formal platform uses the output signal value to detect whether the Property data can be overwritten.

8. An RTL simulation device, characterized in that: include: An acquisition module is used to acquire the target RTL code not covered in the UVM simulation test, and determine the device under test corresponding to the target RTL code; A Property data generation module, used to generate Property data for a Formal platform using a target output signal and a target signal value contained in the target RTL code; A simulation module, used to establish a signal connection between the formal platform and the input terminal and the output terminal of the device under test and start a formal verification process, so that the formal platform sends an input signal value to the input terminal in an exhaustive manner; A directional excitation sequence generating module, used for generating a directional excitation sequence using a target input signal value corresponding to when the Property data is covered, when the Formal platform determines that the Property data can be covered using the output signal value of the output terminal; The injection module is used to inject the directed stimulus sequence into the UVM environment, so that the UVM environment uses the directed stimulus sequence to re-perform the UVM simulation test on the target RTL code.

9. An electronic device, characterized in that: include: Memory for storing computer programs; A processor, configured to implement the RTL simulation method according to any one of claims 1 to 7 when executing the computer program.

10. A computer-readable storage medium, characterized in that: The computer-readable storage medium stores computer-executable instructions, and when the computer-executable instructions are loaded and executed by a processor, the RTL simulation method according to any one of claims 1 to 7 is implemented.

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