A system on chip, chip and electronic device

Abstract

The application provides a system on chip, a chip and an electronic device. The system on chip comprises: a first central processing unit configured to create a plurality of virtual devices based on physical devices on the system on chip; a second central processing unit configured to control the virtual devices to access system resources; a third central processing unit configured to allocate corresponding system resources for a received service request; and a fourth central processing unit configured to respond to the service request by using the allocated system resources. Through the system on chip, the plurality of central processing units included in the system on chip can be divided according to functions, and the plurality of virtual devices created by the physical devices on the system on chip can be allocated corresponding system resources by the mutual cooperation between the central processing units with different functions, so as to respond to the service request issued by the virtual devices, improve the processing efficiency of the central processing units, and improve the performance stability of the shared system resources.

Description

Technical Field

[0001] This invention relates to the field of System on Chip (SOC) technology, specifically to a system on chip, a chip, and an electronic device. Background Technology

[0002] Data center server rooms house tens of thousands of servers. With the rapid popularization of the NVMe protocol, servers are increasingly being configured with NVMe (Non-Volatile Memory express, also known as the Non-Volatile Memory Host Controller Interface Specification) SSDs (Solid State Drives) as the medium for storing data, thereby enabling tenants (small and medium-sized enterprises) to have a better experience.

[0003] In related technologies, internet companies providing cloud services typically use virtual devices as the hosts for their cloud services. This means that a single server is virtualized into multiple virtual devices based on its hardware configuration for customers to rent. Because the physical resources of a single server are limited, and considering cost and other factors, each tenant cannot exclusively utilize a particular hardware resource. Consequently, in scenarios where virtual devices exist, the native NVMe SSD cannot fully utilize its original performance and latency, thus interfering with the performance of each virtual device. Summary of the Invention

[0004] Therefore, the technical problem to be solved by the present invention is to overcome the defect in the prior art that the central processing unit cannot be used reasonably under the condition of system resource sharing, which leads to the unstable performance of virtual devices when processing business requests, thereby providing a system-on-a-chip, chip and electronic device.

[0005] In a first aspect, the present invention provides a system-on-a-chip, the system-on-a-chip comprising:

[0006] A first central processing unit is configured to create multiple virtual devices based on physical devices on the system-on-a-chip; the multiple virtual devices share the system resources of the system-on-a-chip.

[0007] The second central processing unit is communicatively connected to the first central processing unit and is used to control virtual devices to access the system resources;

[0008] The third central processing unit, which is communicatively connected to the second central processing unit, is used to allocate corresponding system resources for received service requests; the service requests are issued by the virtual device.

[0009] A fourth central processing unit, communicatively connected to the third central processing unit, is used to respond to the service request using allocated system resources.

[0010] In this approach, multiple central processing units (CPUs) included in the on-chip system can be pre-divided according to their functions. Then, through the cooperation between CPUs with different functions, corresponding system resources are allocated to multiple virtual devices created by the physical devices on the on-chip system to respond to the service requests issued by the virtual devices, thereby improving the processing efficiency of the CPUs and achieving the goal of improving the performance stability of shared system resources.

[0011] In conjunction with the first aspect, in a first embodiment of the first aspect, the second central processing unit is configured to allocate a user namespace to the virtual device based on the system resources, and to control the virtual device to access the system resources according to the user namespace.

[0012] In conjunction with the first aspect or the first embodiment of the first aspect, in the second embodiment of the first aspect, the second central processing unit is used to control the virtual device to dynamically apply for or release virtual queue resources and / or virtual interrupt resources;

[0013] The system resources include the virtual queue resources and the virtual interrupt resources.

[0014] In conjunction with the first aspect, in a third embodiment of the first aspect, the second central processing unit is further configured to control the physical device to access the system resources.

[0015] In conjunction with the first aspect, in a fourth embodiment of the first aspect, the second central processing unit is further configured to configure a flow control target value, wherein the flow control target value is the upper limit of system resources allocated by the third central processing unit for service requests.

[0016] In conjunction with the fourth embodiment of the first aspect, in the fifth embodiment of the first aspect, the third central processing unit is used to allocate corresponding system resources based on the traffic control target value of the received service request, so that the traffic of the allocated corresponding system resources is lower than the traffic control target value.

[0017] In conjunction with the first aspect, in the sixth embodiment of the first aspect, the system resources include storage resources, and the service request includes read / write requests;

[0018] The fourth central processing unit is used to respond to the read / write requests using the allocated storage resources.

[0019] In conjunction with the first aspect, in a seventh embodiment of the first aspect, the system-on-chip further includes a fifth central processing unit:

[0020] The fifth central processing unit is used to boot the target firmware;

[0021] The target firmware includes at least one of the firmware of a first central processing unit, a second central processing unit, a third central processing unit, and a fourth central processing unit.

[0022] In a second aspect, the present invention also provides a chip comprising a system-on-a-chip including any of the first aspect and its alternative embodiments.

[0023] In a third aspect, the present invention also provides an electronic device comprising a system-on-a-chip of the first aspect and its alternative embodiments or a chip of the second aspect. Attached Figure Description

[0024] To more clearly illustrate the specific embodiments of the present invention or the technical solutions in the prior art, the drawings used in the description of the specific embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are some embodiments of the present invention. For those skilled in the art, other drawings can be obtained from these drawings without creative effort.

[0025] Figure 1 This is a schematic diagram of a system-on-a-chip proposed according to an exemplary embodiment.

[0026] Figure 2 This is a schematic diagram of another system-on-a-chip proposed according to an exemplary embodiment.

[0027] Figure 3 This is a schematic diagram of the structure of yet another system-on-a-chip proposed according to an exemplary embodiment. Detailed Implementation

[0028] The technical solution of the present invention will now be clearly and completely described with reference to the accompanying drawings. Obviously, the described embodiments are only some, not all, of the embodiments of the present invention. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of the present invention.

[0029] The terms "first," "second," "third," "fourth," etc., used in this invention are used to distinguish different objects, not to describe a specific order. Furthermore, the terms "comprising" and "having," and any variations thereof, are intended to cover non-exclusive inclusion. For example, a process, method, system, product, or apparatus that includes a series of steps or units is not limited to the listed steps or units, but may include steps or units not listed.

[0030] A System on a Chip (SoC) refers to the technology of integrating a complete system onto a single chip, grouping all or part of the necessary electronic circuitry. A complete system typically includes a central processing unit (CPU), memory, and peripheral circuitry. SoC is being developed alongside other technologies, such as silicon-on-insulator (SOI), which can provide enhanced clock frequencies, thereby reducing the power consumption of microchips.

[0031] This invention provides a system-on-a-chip (SoC) for use in a computer device. It should be noted that this SoC can be implemented as part or all of the computer device through software, hardware, or a combination of both. The computer device can be a terminal, client, or server. The server can be a single server or a server cluster consisting of multiple servers. In this embodiment, the terminal can be a smartphone, personal computer, tablet computer, wearable device, or other intelligent hardware device such as an intelligent robot. The following method embodiments all use a computer device as the execution subject for description.

[0032] The computer device in this embodiment of the invention is an input / output (I / O) device capable of supporting Single Root I / O Virtualization (SR-IOV) technology. It provides a virtual environment for creating virtual functions (VFs), thereby enabling system resource sharing within the on-chip system. In this embodiment, the on-chip system used is a system-on-chip comprising multiple central processing units (CPUs), such as a multi-core Advanced Reduced Instruction Set Machine (ARM) SoC.

[0033] The system-on-a-chip provided by this invention can pre-divide the multiple central processing units (CPUs) included in the system-on-a-chip according to their functions, and then allocate corresponding system resources to multiple virtual devices created by the physical devices on the system-on-a-chip through the mutual cooperation between CPUs with different functions, so as to respond to the service requests issued by the virtual devices, thereby improving the processing efficiency of the CPUs and achieving the purpose of improving the performance stability of shared system resources.

[0034] In this invention, the multiple central processing units (CPUs) included in the system-on-a-chip are pre-divided into four types based on their functions, each performing a different function. For ease of explanation, the four CPUs will be referred to as the first CPU, the second CPU, the third CPU, and the fourth CPU, respectively.

[0035] Figure 1 This is a schematic diagram of a system-on-a-chip (SoC) according to an exemplary embodiment. For example... Figure 1 As shown, the system-on-a-chip 100 includes a first central processing unit 110, a second central processing unit 120, a third central processing unit 130, and a fourth central processing unit 140.

[0036] The first central processing unit 110 is used to create multiple virtual devices based on physical devices on the system-on-chip, and the multiple virtual devices created share the system resources of the system-on-chip.

[0037] In this embodiment of the invention, the physical device can be understood as a host machine that provides a virtual environment. The first central processing unit 110 can be understood as a central processing unit used to manage physical devices or physical devices and virtual devices. The virtual devices are created by the physical devices.

[0038] In actual operation, the first central processing unit 110 performs the function of creating multiple virtual devices based on the physical devices on the on-chip system. When a physical device needs to create multiple virtual devices, it can call the first central processing unit 110 to configure space access for the required virtual devices, thereby enabling the creation of multiple virtual devices. Furthermore, to ensure the normal operation of the created virtual devices, the first central processing unit 110 initializes the hosts of the created virtual devices after creation, enabling them to respond to different host requests. These host requests include virtual device host requests or physical device host requests. In one implementation scenario, if the physical device is a Peripheral Component Interconnect Express (PCI-Express or PCIe) device, the created virtual device can also be a PCIe device.

[0039] The second central processing unit 120 is communicatively connected to the first central processing unit and is used to control virtual devices accessing system resources.

[0040] In this embodiment of the invention, the second central processing unit 120 can be understood as a central processing unit for executing management commands, capable of controlling virtual devices to access system resources based on received commands. For example, in one implementation scenario, the second central processing unit 120 can control virtual devices to directly access system resources of a non-volatile memory (NVM) subsystem with multiple controllers included in the physical device. In another implementation scenario, virtual devices can be controlled to access system resources based on the non-volatile memory express (NVMe) technology.

[0041] In one embodiment, within the virtual environment of SR-IOV, it is necessary to ensure that the input / output (I / O) of each virtual device is isolated from each other, independent of each other, and that they cannot directly access each other's data. Therefore, the second central processing unit 120 allocates user namespaces to virtual devices based on system resources and controls virtual devices' access to system resources according to the user namespaces. This enables virtual devices to access system resources in a targeted manner through their corresponding user namespaces, thereby improving the accuracy and security of system resource access.

[0042] In one implementation scenario, when the second central processing unit 120 receives a multi-namespace management command from the physical device, it divides the entire user space within the system resources suitable for user use according to the logical block address (LBA) combination units. The LBA combination units are then mapped and managed using a bitmap, establishing a correspondence between user spaces and virtual devices. Each virtual device is then allocated a user namespace, enabling it to write or read data based on its corresponding user namespace when accessing system resources. In one example, the LBA can be an LBA installed in a solid-state drive (SSD) within the physical device, used to store data written or read by the virtual or physical device. In another example, system resources also include storage resources provided by the SSD.

[0043] In another embodiment, when controlling the virtual device to access system resources, the second central processing unit 120 includes controlling the virtual device to dynamically request or release virtual queue resources and / or virtual interrupt resources. System resources include virtual queue resources and virtual interrupt resources. For example, to balance the I / O throughput and I / O response time of the virtual device, when the virtual device receives an I / O request to be executed, the second central processing unit 120 requests the virtual queue resources corresponding to the virtual device to store the I / O request in the virtual device's I / O queue for scheduling. If the I / O request is responded to, the second central processing unit 120 releases the virtual queue resources occupied by the I / O request. If the I / O request is to read data stored in the virtual device, the second central processing unit 120 first requests the virtual queue resources corresponding to the virtual device to store the I / O request in the virtual device's I / O queue for scheduling. Then, when the I / O request is executed, the second central processing unit 120 controls the virtual device to request virtual interrupt resources for reading. In one implementation scenario, if the virtual queue resources and virtual interrupt resources are managed by the NVMe controller in the SSD, the second central processing unit 120 can control the virtual device to dynamically request virtual queue resources and / or virtual interrupt resources from the NVMe controller.

[0044] In another embodiment, the second central processing unit 120 can also be used to control the network state switching of virtual devices. That is, to control whether the virtual device is in an online or offline state. In one example, the network state of the virtual device can be switched selectively or in batches according to user needs.

[0045] The third central processing unit 130 is communicatively connected to the second central processing unit 120 and is used to allocate corresponding system resources for received service requests, wherein the service requests are issued by virtual devices.

[0046] In this embodiment of the invention, the third central processing unit 130 can be understood as a central processing unit for Flash Translation Layer (FTL), capable of allocating corresponding system resources to the virtual device according to the service request issued by the virtual device, in order to respond to the service request. The service request may include a service request related to data writing or a service request related to data reading. For example, based on the service request issued by the virtual device, data stored in the virtual device host is moved to the virtual hard disk firmware corresponding to the virtual device. Or, based on the service request issued by the virtual device, data stored in the virtual hard disk firmware corresponding to the virtual device is moved to the virtual device host.

[0047] In one implementation scenario, when the third central processing unit 130 receives a service request from the virtual device to move data stored in the virtual device host to the virtual hard disk firmware corresponding to the virtual device, the third central processing unit 130 can map the LBA in the service request to the physical block address (PBA) of the virtual hard disk firmware based on the user namespace allocated to the virtual device by the second central processing unit 120, and then move the data stored in the virtual device host to the virtual hard disk firmware corresponding to the virtual device in response to the service request.

[0048] In another implementation scenario, when the third central processing unit 130 receives a service request from the virtual device to move data stored in the virtual hard disk firmware corresponding to the virtual device to the virtual device host, the third central processing unit 130 can map the LBA in the service request to the physical block address (PBA) of the virtual hard disk firmware based on the user namespace allocated to the virtual device by the second central processing unit 120, and then move the data from the virtual hard disk firmware corresponding to the virtual device to the virtual device host in response to the service request.

[0049] The fourth central processing unit 140 is communicatively connected to the third central processing unit 130 and is used to respond to service requests using allocated system resources.

[0050] In this embodiment of the invention, the fourth central processing unit 140 can be understood as a central processing unit for managing system resources, thereby enabling it to respond to business requests using the allocated system resources.

[0051] In one embodiment, system resources include storage resources, and service requests include read and write requests. A fourth central processing unit 140 is configured to respond to read and write requests using the allocated storage resources.

[0052] In one implementation scenario, when the read / write request issued by the virtual device is to move data stored in the virtual device host to the virtual hard disk firmware corresponding to the virtual device, the fourth central processing unit 140 can schedule the data moved to the virtual hard disk firmware by the third central processing unit 130 to be written to the storage medium of the virtual hard disk firmware to complete the data saving and respond to the read / write request issued by the virtual device. In another implementation scenario, when the read / write request issued by the virtual device is to move data stored in the virtual hard disk firmware corresponding to the virtual device to the virtual device host, the fourth central processing unit 140 can read the data stored in the virtual hard disk firmware corresponding to the virtual device from the storage medium, and then the third central processing unit 130 can move the read data to the virtual device host to respond to the read / write request issued by the virtual device.

[0053] Through the above embodiments, multiple central processing units (CPUs) included in the on-chip system can be pre-divided according to their functions. Then, through the cooperation between CPUs with different functions, corresponding system resources can be allocated to multiple virtual devices created by the physical devices on the on-chip system to respond to the service requests issued by the virtual devices, thereby improving the processing efficiency of the CPU and achieving the goal of improving the performance stability of shared system resources.

[0054] In one embodiment, the second central processing unit 120 is also used to control physical devices' access to system resources to ensure the normal operation of the physical devices. In one example, since virtual devices are created by physical devices, for ease of management, the physical devices can be used as primary controllers, and each virtual device as a secondary controller. Therefore, when the second central processing unit 120 controls physical or virtual devices to access system resources, it can manage them according to their respective levels. In one example, NVMe technology can be used to manage the access to system resources by the primary controllers or the secondary controllers.

[0055] In another embodiment, the second central processing unit 120 is further configured to configure a flow control target value. The flow control target value is the upper limit of system resources allocated by the third central processing unit 130 for service requests, so as to ensure the Quality of Service (QoS) of the virtual device processing read and write services, thereby improving the performance stability of the virtual device processing read and write services. The flow control target value may include the maximum number of input / output operations per second (IOPS) or the maximum bandwidth of the virtual device. In one example, the flow control target values ​​for each virtual device may be the same or different, and may also be configured specifically according to the actual service needs of each virtual device; this is not limited in this invention.

[0056] In another embodiment, the third central processing unit 130 is used to allocate corresponding system resources based on the flow control target value of the received service request, so that the flow of the allocated system resources is lower than the flow control target value, thereby ensuring the QoS of the virtual device in processing read and write services.

[0057] In one implementation scenario, the third central processing unit 130 can employ a token bucket algorithm. Based on the flow control target value configured by the second central processing unit 120, it allocates corresponding system resources to received service requests, thereby controlling the processing progress of the virtual device in handling service requests. This ensures that the flow of allocated system resources is lower than the flow control target value, thus guaranteeing the QoS of the virtual device's read / write services. Specifically, for clarity, a single virtual device is used as an example. If the flow control target value is the maximum IOPS, then in the third central processing unit 130, when allocating corresponding system resources to a service request received using the token bucket algorithm, it allocates a token bucket with a capacity corresponding to the maximum IOPS configured by the second central processing unit 120 for the virtual device, and fills the token bucket with tokens. Whenever the virtual device receives a service request, the number of tokens corresponding to the service request is subtracted from the token bucket corresponding to the virtual device. If the virtual device's token bucket does not have enough tokens to receive the service request or the tokens in the token bucket are exhausted, the virtual device stops processing the service request until its token bucket has enough tokens. The token bucket is continuously filled with tokens at a rate corresponding to the maximum IOPS.

[0058] In another embodiment, the first central processing unit 110, the second central processing unit 120, the third central processing unit 130, and the fourth central processing unit 140 can control the physical device to access system resources in a manner that controls the virtual device to access system resources.

[0059] In one embodiment, the system-on-a-chip 100 also includes a solid-state drive (SSD) that can assist the first central processing unit (CPU) 110, the second CPU 120, the third CPU 130, and the fourth CPU 140 in completing the I / O storage services of each virtual device, exposing each virtual device to its corresponding host, thereby realizing the hardware I / O virtualization technology of the SSD, so as to provide better performance and lower latency for virtual devices or physical devices in the process of realizing system resource sharing.

[0060] Based on the same inventive concept, the present invention also provides another system-on-a-chip.

[0061] Figure 2 This is a schematic diagram of another system-on-a-chip structure proposed according to an exemplary embodiment. For example... Figure 2 As shown, the system-on-a-chip 200 includes the following components.

[0062] First Central Processing Unit 210.

[0063] The second central processing unit 220 is communicatively connected to the first central processing unit 210.

[0064] The third central processing unit 230 is communicatively connected to the second central processing unit 220.

[0065] The fourth central processing unit 240 is communicatively connected to the third central processing unit 230.

[0066] The operating and processing methods of the first central processing unit 210, the second central processing unit 220, the third central processing unit 230 and the fourth central processing unit 240 in the system on-chip 200 are the same as those of the first central processing unit 110, the second central processing unit 120, the third central processing unit 130 and the fourth central processing unit 140 in the system on-chip 100, and will not be described again here.

[0067] The fifth central processing unit 250 is used to boot the target firmware.

[0068] In this embodiment of the invention, the target firmware includes at least one of the firmware of the first central processing unit 210, the firmware of the second central processing unit 220, the firmware of the third central processing unit 230, and the firmware of the fourth central processing unit 240. The fifth central processing unit 250 helps ensure the on-chip system can boot normally, thereby ensuring the normal operation of multiple virtual devices and realizing the sharing of system resources.

[0069] In one implementation scenario, the system-on-a-chip (SoC) can be a multi-core ARM SoC, and in addition to the five central processing units mentioned above, it also includes an NVMe SSD capable of using SR-IOV technology. A schematic diagram of the SoC's structure can be shown below. Figure 3 As shown. Figure 3 This is a schematic diagram of the structure of yet another system-on-a-chip proposed according to an exemplary embodiment.

[0070] A Virtual Machine Monitor (VMM) is installed on the computer device housing the System-on-Chip 300 to monitor the operation of each virtual device. Here, VF represents a virtual device, PF represents a physical device, VM represents the host of the virtual device, and Host represents the host of the physical device. A VF drive represents shared access to system resources provided for a virtual device. A PF drive represents shared access to system resources provided for a physical device. 1, 2…127 represent the numbers of different virtual devices created by the physical device. The host of the virtual device or the host of the physical device communicates with the System-on-Chip 300 via PCIe X4 to issue read and write commands to their respective virtual or physical devices and control them to execute relevant service requests. MSI-X Tabk represents the interrupt mechanism, allowing virtual devices to request virtual interrupt resources in the second central processing unit. SQ represents a service request, and CQ represents a service request response. NS represents the virtual hard disk firmware corresponding to each virtual or physical device in the virtual environment. Flash BlacksArray represents a flash memory array block used to provide storage resources.

[0071] In the first central processing unit, based on SR-IOV technology, physical devices are able to create multiple virtual devices, configure space access for PF and VF, and initialize their respective hosts to respond to different business requests.

[0072] In the second central processing unit (CPU), the SR-IOV NVMe SSD primarily utilizes an NVM subsystem with multiple controllers to provide read / write access for either the virtual device host or the physical device host. The Power Filter (PF) acts as a primary controller, while different Virtual Filters (VFs) are managed as secondary controllers. NVMe technology is used to manage the primary / secondary controllers for dynamic allocation or release of virtual queue resources and / or virtual interrupt resources, as well as network state switching. User namespaces are allocated to virtual devices based on system resources, and these namespaces are used to control virtual device access to system resources. Finally, the CPU allocates flow control target values ​​for service requests to the third CPU.

[0073] In the third central processing unit, the media distribution of read and write data is carried out to complete the read and write business processing under different user command spaces issued by different VFs. At the same time, based on the flow control target value configured in the second central processing unit, the QoS of VF in processing read and write business is guaranteed.

[0074] In the fourth central processing unit, internal read and write data sent from the third central processing unit to the Nand is received and scheduled to be written to the corresponding Nand storage medium.

[0075] The fifth central processing unit is used to manage the system information configuration and firmware boot of the entire SR-IOV system, ensuring that the entire system can start normally.

[0076] Based on the same inventive concept, the present invention also provides a chip, including any of the on-chip systems provided by the present invention.

[0077] Based on the same inventive concept, the present invention also provides an electronic device, which is any of the system-on-a-chip or chips provided by the present invention.

[0078] In the several embodiments provided in this application, it should be understood that the disclosed technical content can be implemented in other ways. The device embodiments described above are merely illustrative; for example, the division of units is only a logical functional division, and in actual implementation, there may be other division methods. For example, multiple units or components may be combined or integrated into another system, or some features may be ignored or not executed. Furthermore, the displayed or discussed mutual coupling, direct coupling, or communication connection may be through some interfaces; the indirect coupling or communication connection between units or modules may be electrical or other forms.

[0079] The units described as separate components may or may not be physically separate. The components shown as units may or may not be physical units; that is, they may be located in one place or distributed across multiple network units. Some or all of the units can be selected to achieve the purpose of this embodiment according to actual needs.

[0080] Furthermore, the functional units in the various embodiments of the present invention can be integrated into one processing unit, or each unit can exist physically separately, or two or more units can be integrated into one unit. The integrated unit can be implemented in hardware or as a software functional unit.

[0081] If the integrated unit is implemented as a software functional unit and sold or used as an independent product, it can be stored in a computer-readable storage medium. Based on this understanding, the technical solution of the present invention, in essence, or the part that contributes to the prior art, or all or part of the technical solution, can be embodied in the form of a software product. This computer software product is stored in a storage medium and includes several instructions to cause a computer device (which may be a personal computer, server, or network device, etc.) to execute all or part of the steps of the methods described in the various embodiments of the present invention. The aforementioned storage medium includes various media capable of storing program code, such as USB flash drives, read-only memory (ROM), random access memory (RAM), portable hard drives, magnetic disks, or optical disks.

[0082] Obviously, the above embodiments are merely illustrative examples for clear explanation and are not intended to limit the implementation. Those skilled in the art will recognize that other variations or modifications can be made based on the above description. It is neither necessary nor possible to exhaustively list all possible implementations here. However, obvious variations or modifications derived therefrom are still within the scope of protection of this invention.

Claims

1. A system-on-a-chip, characterized in that, The on-chip system includes: A first central processing unit is configured to create multiple virtual devices based on physical devices on the system-on-a-chip; the multiple virtual devices share the system resources of the system-on-a-chip. The second central processing unit is communicatively connected to the first central processing unit and is used to control virtual devices to access the system resources; The second central processing unit (CPU) is used to allocate user namespaces to the virtual devices based on the system resources, and to control the virtual devices to access the system resources according to the user namespaces. The allocation of user namespaces by the second CPU to the virtual devices based on the system resources includes: dividing the entire user space in the system resources suitable for user use according to the combination of logical block addresses; managing the set of logical block addresses using a bitmap; establishing a correspondence between user spaces and virtual devices; and allocating a user namespace to each virtual device according to the correspondence. Controlling the virtual devices to access the system resources according to the user namespaces by the second CPU includes: when the third CPU obtains... When a virtual device issues a service request to move data stored in the virtual device host to the virtual hard disk firmware corresponding to the virtual device, the third central processing unit (CPU) maps the logical block address in the service request to the physical block address of the virtual hard disk firmware based on the user namespace, and moves the data stored in the virtual device host to the virtual hard disk firmware corresponding to the virtual device. Similarly, when the third CPU receives a service request from a virtual device to move data stored in the virtual hard disk firmware corresponding to the virtual device to the virtual device host, the third CPU maps the logical block address in the service request to the physical block address of the virtual hard disk firmware based on the user namespace, and moves the data from the virtual hard disk firmware corresponding to the virtual device to the virtual device host. The third central processing unit, which is communicatively connected to the second central processing unit, is used to allocate corresponding system resources for received service requests; the service requests are issued by the virtual device. The second central processing unit is also used to configure a flow control target value, wherein the flow control target value is the upper limit of system resources allocated by the third central processing unit for service requests, and the flow control target value includes the maximum number of read / write operations per second or the maximum bandwidth of the virtual device; The third central processing unit is used to allocate corresponding system resources based on the flow control target value of the received service requests, so that the flow of the allocated corresponding system resources is lower than the flow control target value; A fourth central processing unit, communicatively connected to the third central processing unit, is used to respond to the service request using allocated system resources.

2. The system-on-a-chip according to claim 1, characterized in that, The second central processing unit is used to control the virtual device to dynamically request or release virtual queue resources and / or virtual interrupt resources; The system resources include the virtual queue resources and the virtual interrupt resources.

3. The system-on-a-chip according to claim 1, characterized in that, The second central processing unit is also used to control the physical device's access to the system resources.

4. The system-on-a-chip according to claim 1, characterized in that, The system resources include storage resources, and the service requests include read and write requests; The fourth central processing unit is used to respond to the read / write requests using the allocated storage resources.

5. The system-on-a-chip according to claim 1, characterized in that, The system-on-a-chip also includes a fifth central processing unit: The fifth central processing unit is used to boot the target firmware; The target firmware includes at least one of the firmware of a first central processing unit, a second central processing unit, a third central processing unit, and a fourth central processing unit.

6. A chip, characterized in that, The system-on-chip includes any one of claims 1 to 5.

7. An electronic device, characterized in that, Includes the system-on-a-chip according to any one of claims 1 to 5 or the chip according to claim 6.

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