A Chip Emulation Design Verification Method, Device, Equipment and Medium

Abstract

The present application discloses a method for chip simulation design verification, including: determining verification requirements including the type of the to-be-verified scenario, obtaining a target assertion statement corresponding to the type of the to-be-verified scenario from a preset assertion library, determining the corresponding type of the to-be-verified code according to the type of the to-be-verified scenario, and screening out a simulation design code segment corresponding to the type of the to-be-verified code as the to-be-verified code segment, where the simulation design code segment is obtained by pre-dividing the simulation design code of the target simulation chip based on different code types, inserting the target assertion statement into the to-be-verified code segment, so as to use the target assertion statement to monitor whether the to-be-verified code segment is an abnormal code segment, and determining the abnormal position after detecting the abnormal code segment. Through the above technical solution of the present application, in the case of the increasing complexity of the chip, the verification efficiency can be improved, the speed of locating errors can be effectively increased based on assertion verification, and the accuracy of the simulation result can be improved.

Description

Technical Field

[0001] The present invention relates to the field of computer technology, and particularly to a chip simulation design verification method, device, equipment and medium. Background Art

[0002] With the increasing integration of circuits, many difficulties and challenges have been brought to chip verification work. During the chip design process, simulation verification occupies more than half of the workload. The traditional verification method is to use an incentive generator to generate randomized or directed incentives according to specific constraints, and then apply the generated incentives to the design under verification through a verification environment. After the simulation is completed, the result file and waveform are viewed through automatic comparison or manual means to ensure that the simulation result is consistent with the expected result. However, with the improvement of circuit integration and complexity, the ability to locate errors is getting lower and lower, resulting in a large amount of simulation verification time being consumed.

[0003] In summary, how to increase the speed of error location, improve verification efficiency and the accuracy of simulation results is a problem to be solved at present. Summary of the Invention

[0004] In view of this, the purpose of the present invention is to provide a chip simulation design verification method, device, equipment and medium, which can increase the speed of error location, improve verification efficiency and the accuracy of simulation results. The specific solutions are as follows:

[0005] In the first aspect, the present application discloses a chip simulation design verification method, including:

[0006] Determine the verification requirements including the type of the scenario to be verified;

[0007] Obtain the target assertion statement corresponding to the type of the scenario to be verified from a preset assertion library;

[0008] Determine the corresponding type of code to be verified according to the type of the scenario to be verified, and screen out the simulation design code segment corresponding to the type of code to be verified from all the simulation design code segments of the target simulation chip as the code segment to be verified; the simulation design code segment is obtained by previously dividing the simulation design code of the target simulation chip based on different code types;

[0009] Insert the target assertion statement into the code segment to be verified, so as to use the target assertion statement to monitor whether the code segment to be verified is an abnormal code segment, and determine the corresponding abnormal location based on the monitoring result after detecting the abnormal code segment.

[0010] Optionally, before determining the verification requirements including the type of the scenario to be verified, it further includes:

[0011] Obtain the simulation design code of the target simulation chip, and determine the different code functions corresponding to different scenario types that the simulation design code can implement;

[0012] Based on different code functions, determine different code types, and establish a mapping relationship between the scenario type and the code type;

[0013] Divide the simulation design code based on different code types to obtain all simulation design code segments of the target simulation chip.

[0014] Optionally, determining the verification requirements including the scenario type to be verified includes:

[0015] Determine the scenario type to be verified from different scenario types that the simulation design code can implement, and construct corresponding verification requirements based on the scenario type to be verified; the scenario type to be verified includes any one or a combination of several of the scenarios for verifying the circuit function of the target simulation chip, the scenarios for verifying the interface function of the target simulation chip, and the scenarios for verifying the application program function of the target simulation chip.

[0016] Optionally, inserting the target assertion statement into the code segment to be verified includes:

[0017] Take the target position in the code segment to be verified as the position to be inserted;

[0018] Insert the target assertion statement into the corresponding position in the code segment to be verified according to the position to be inserted.

[0019] Optionally, taking the target position in the code segment to be verified as the position to be inserted includes:

[0020] Use a preset position input interface to obtain the target position in the code segment to be verified, and determine the target position as the position to be inserted;

[0021] Or, randomly determine the target position from the code segment to be verified by a random method, and determine the target position as the position to be inserted;

[0022] Or, according to the code type corresponding to the code segment to be verified, determine the target code statement from all code statements in the code segment to be verified, and determine the position of the target code statement in the code segment to be verified as the position to be inserted.

[0023] Optionally, after detecting the abnormal code segment, determining the corresponding abnormal position includes:

[0024] After detecting the abnormal code snippet, determine the target assertion statement corresponding to the abnormal code snippet;

[0025] Based on the insertion position of the target assertion statement corresponding to the abnormal code snippet, determine the abnormal position of the abnormal code snippet.

[0026] Optionally, before obtaining the target assertion statement corresponding to the to-be-verified scenario type from the preset assertion library, it further includes:

[0027] Obtain an open verification library, and classify each assertion statement in the open verification library according to different scenario types;

[0028] Annotate the open verification library to annotate the corresponding scenario type for each assertion statement in the open verification library;

[0029] Correspondingly, obtaining the target assertion statement corresponding to the to-be-verified scenario type from the preset assertion library includes:

[0030] Use the to-be-verified scenario type to query the annotated open verification library to obtain the target assertion statement corresponding to the to-be-verified scenario type.

[0031] In a second aspect, the present application discloses a chip simulation design verification device, including:

[0032] A requirement determination module, configured to determine a verification requirement including a to-be-verified scenario type;

[0033] A statement acquisition module, configured to obtain a target assertion statement corresponding to the to-be-verified scenario type from a preset assertion library;

[0034] A code snippet determination module, configured to determine a corresponding to-be-verified code type according to the to-be-verified scenario type, and screen out the simulation design code snippet corresponding to the to-be-verified code type from all simulation design code snippets of the target simulation chip as the to-be-verified code snippet; the simulation design code snippet is obtained by pre-dividing the simulation design code of the target simulation chip based on different code types;

[0035] A simulation verification module, configured to insert the target assertion statement into the to-be-verified code snippet, so as to use the target assertion statement to monitor whether the to-be-verified code snippet is an abnormal code snippet, and determine the corresponding abnormal position based on the monitoring result after detecting the abnormal code snippet.

[0036] In a third aspect, the present application discloses an electronic device, including:

[0037] A memory, configured to store a computer program;

[0038] A processor for executing the computer program to implement the foregoing chip simulation design verification method.

[0039] In a fourth aspect, the present application discloses a computer storage medium for storing a computer program; wherein, when the computer program is executed by a processor, the steps of the foregoing disclosed chip simulation design verification method are implemented.

[0040] The present application first determines the verification requirements including the type of the scenario to be verified, obtains the target assertion statement corresponding to the type of the scenario to be verified from a preset assertion library, determines the corresponding type of the code to be verified according to the type of the scenario to be verified, and screens out the simulation design code fragment corresponding to the type of the code to be verified from all the simulation design code fragments of the target simulation chip as the code fragment to be verified; the simulation design code fragment is a code fragment obtained by previously dividing the simulation design code of the target simulation chip based on different code types, inserts the target assertion statement into the code fragment to be verified, so as to use the target assertion statement to monitor whether the code fragment to be verified is an abnormal code fragment, and determines the corresponding abnormal position after detecting the abnormal code fragment. In this way, the present invention determines the code type corresponding to the scenario to be verified in the verification requirements, then determines the corresponding code fragment to be verified, and inserts the target assertion statement obtained from the preset assertion library into the code fragment to implement the process of using the preset assertion library to perform assertion verification in chip simulation design. This verification methodology based on the assertion verification library can effectively solve the problems of inaccurate error location and low efficiency of traditional verification methods, increase the observability of verification, can discover design defects earlier in the chip design cycle, locate the error position more accurately, improve the efficiency of chip verification, and complete the chip simulation verification link more efficiently. Description of the Drawings

[0041] In order to more clearly illustrate the technical solutions in the embodiments of the present invention or the prior art, the following will briefly introduce the drawings required for use in the description of the embodiments or the prior art. Obviously, the drawings in the following description are only the embodiments of the present invention. For those of ordinary skill in the art, other drawings can be obtained according to the provided drawings without creative efforts.

[0042] Figure 1 It is a flowchart of a chip simulation design verification method provided by the present application;

[0043] Figure 2 It is an assertion structure diagram provided by the present application;

[0044] Figure 3 It is a flowchart of a specific chip simulation design verification method provided by the present application;

[0045] Figure 4 Schematic diagram of a specific chip simulation design verification device provided for this application;

[0046] Figure 5 Structural diagram of an electronic device provided for this application. Specific implementation manners

[0047] Next, the technical solutions in the embodiments of the present invention will be clearly and completely described in conjunction with the accompanying drawings in the embodiments of the present invention. Obviously, the described embodiments are only a part of the embodiments of the present invention, rather than all the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those of ordinary skill in the art without creative efforts shall fall within the protection scope of the present invention.

[0048] In the current background, the existing verification method is to use an incentive generator to generate randomized or directed incentives according to specific constraints, and then apply the generated incentives to the design under verification through a verification environment. After the simulation is completed, the result file and waveform are viewed through automatic comparison or manual means to ensure that the simulation result is consistent with the expected result, lacking the accuracy of simulation verification. As can be seen from the above, in the process of chip simulation design verification, how to avoid the situation where the ability to locate errors becomes low, resulting in a decrease in verification efficiency and accuracy, is a problem to be solved in this field.

[0049] See Figure 1 As shown, the embodiments of the present invention disclose a chip simulation design verification method, which may specifically include:

[0050] Step S11: Determine the verification requirements including the type of the scenario to be verified.

[0051] In this embodiment, before determining the verification requirements including the type of the scenario to be verified, it further includes: obtaining the simulation design code of the target simulation chip, and determining the different code functions corresponding to different scenario types that the simulation design code can implement; determining different code types based on different said code functions, and establishing a mapping relationship between the scenario type and the code type; dividing the simulation design code based on different said code types to obtain all simulation design code segments of the target simulation chip.

[0052] In this embodiment, the verification requirements determined to include the to-be-verified scenario type may include: determining the to-be-verified scenario type from different scenario types that can be implemented by the simulation design code, and constructing corresponding verification requirements based on the to-be-verified scenario type; the to-be-verified scenario type includes any one or a combination of several of the scenarios for verifying the circuit function of the target simulation chip, the scenarios for verifying the interface function of the target simulation chip, and the scenarios for verifying the application program function of the target simulation chip. For example, as Figure 2 shown, assertions can be classified into three types according to the application type: structural assertions, interface assertions, and application assertions. The scenarios for verifying the circuit function of the target simulation chip are generally used to check certain function points of the internal circuit design, such as the assertion check for the overflow or empty read of the FIFO (First Input First Output); the scenarios for verifying the interface function of the target simulation chip are mainly used to monitor the interface behavior between modules, such as that the CPU (Central Processing Unit) interface cannot have illegal read and write conditions simultaneously; the scenarios for verifying the application program function of the target simulation chip are generally used to prove the deadlock situation in certain functional structures. For example, when a request is issued, there must be a response signal.

[0053] Step S12: Obtain the target assertion statement corresponding to the to-be-verified scenario type from the preset assertion library.

[0054] In this embodiment, before obtaining the target assertion statement corresponding to the to-be-verified scenario type from the preset assertion library, it further includes: obtaining the Open Verification Library (OVL), and classifying each assertion statement in the Open Verification Library according to different scenario types; annotating the Open Verification Library to annotate each assertion statement in the Open Verification Library with the corresponding scenario type.

[0055] Correspondingly, the obtaining of the target assertion statement corresponding to the to-be-verified scenario type from the preset assertion library includes: querying the annotated Open Verification Library with the to-be-verified scenario type to obtain the target assertion statement corresponding to the to-be-verified scenario type.

[0056] For example, after obtaining the open verification library, group the assertion statements of the functional structure in the open verification library together, group the assertion statements of the bus protocol together, group the assertion statements of the FIFO together, and then label the assertion statements in the open verification library to indicate that the scenario type of each assertion statement is a functional structure or a bus protocol or a FIFO. Then, use the scenario type to be verified, such as a functional structure, to query the assertion statements regarding the functional structure from the above-labeled open verification library, and determine the queried assertion statements as the target assertion statements.

[0057] It can be seen that classifying each assertion statement in the open verification library according to different scenario types and labeling the open verification library can effectively improve the verification efficiency, increase the observability of the verification, and obtain the corresponding assertion statements through the assertion library, effectively reducing the assertion debugging time and increasing the accuracy of the verification.

[0058] Step S13: Determine the corresponding code type to be verified according to the scenario type to be verified, and screen out the simulation design code fragments corresponding to the code type to be verified from all the simulation design code fragments of the target simulation chip as the code fragments to be verified; the simulation design code fragments are the code fragments obtained by pre-dividing the simulation design code of the target simulation chip based on different code types.

[0059] In this embodiment, after obtaining the target assertion statements corresponding to the scenario type to be verified from the preset assertion library, it is necessary to determine the corresponding code type to be verified according to the scenario type to be verified, and then screen out the simulation design code fragments corresponding to the code type to be verified from the code fragments obtained by pre-dividing the simulation design code of the target simulation chip based on different code types as the code fragments to be verified. It can be seen that by screening out the simulation design code fragments corresponding to the code type to be verified from all the simulation design code fragments as the code fragments to be verified, the accuracy of the simulation design verification can be effectively increased, and the chip verification efficiency can be improved.

[0060] Step S14: Insert the target assertion statements into the code fragments to be verified, so as to use the target assertion statements to monitor whether the code fragments to be verified are abnormal code fragments, and determine the corresponding abnormal location based on the monitoring result after detecting the abnormal code fragments.

[0061] In this step, the process of determining the abnormal code segment according to the execution of the assertion statement is completed. Specifically, in actual operation, it can be manifested as: inserting the target assertion statement into the to-be-verified code segment, and executing the target assertion statement to obtain the execution result of the relevant program. If the execution result is consistent with the expected correct result, it indicates that there is no abnormality in the chip function corresponding to the verification requirement; if the execution result is inconsistent with the expected correct result, or abnormal phenomena such as reporting an error or stopping occur, it indicates that the chip function corresponding to the verification requirement has an abnormality. At this time, use the insertion position of the target assertion statement with a running abnormality to determine the abnormal code segment, and then determine the abnormal position in the code abnormal segment. It can be understood that since the actual error position that causes the running abnormality in the code may not be the same as the insertion position of the target assertion statement, the insertion position of the target assertion statement cannot be directly determined as the abnormal position.

[0062] In this embodiment, after determining the corresponding to-be-verified code type according to the to-be-verified scenario type, and screening out the simulation design code segment corresponding to the to-be-verified code type from all the simulation design code segments of the target simulation chip as the to-be-verified code segment, insert the target assertion statement into the to-be-verified code segment, so as to use the target assertion statement to monitor whether the to-be-verified code segment is an abnormal code segment, and determine the corresponding abnormal position based on the monitoring result after detecting the abnormal code segment. Thus, by inserting the target assertion statement into the to-be-verified code segment and using the target assertion statement to monitor the to-be-verified code segment, it is beneficial to increase the chip verification efficiency and effectively improve the verification accuracy.

[0063] In this embodiment, after obtaining the simulation design code of the target simulation chip, different code functions corresponding to different scenario types that the simulation design code can implement are determined. Different code types are determined based on different code functions, and a mapping relationship between the scenario types and the code types is established. The simulation design code is divided based on different code types to obtain all simulation design code segments of the target simulation chip. A target assertion statement corresponding to the scenario type to be verified is obtained from a preset assertion library. The code type to be verified is determined according to the scenario type to be verified, and a simulation design code segment corresponding to the code type to be verified is selected from all simulation design code segments of the target simulation chip as the code segment to be verified. The target assertion statement is inserted into the code segment to be verified, so as to use the target assertion statement to monitor whether the code segment to be verified is an abnormal code segment, and an abnormal position is determined based on the monitoring result after the abnormal code segment is detected. It can be seen that by obtaining the simulation design code to determine different code functions in different scenarios, and determining the code type according to the code function, a mapping relationship between the scenario type and the code type is formed, so as to obtain all simulation design code segments and determine the verification requirements including the scenario type to be verified, which can effectively improve the chip verification efficiency. By obtaining the corresponding assertion statement from the assertion library, the assertion debugging time is effectively reduced. The target assertion statement is inserted into the code segment to be verified, and the code segment to be verified is monitored by the target assertion statement, which can effectively increase the chip verification efficiency and improve the verification accuracy.

[0064] See Figure 3 As shown, an embodiment of the present invention discloses a method for verifying chip simulation design, which may specifically include:

[0065] Step S21: Determine the verification requirements including the scenario type to be verified.

[0066] Step S22: Obtain a target assertion statement corresponding to the scenario type to be verified from a preset assertion library.

[0067] Step S23: Determine the corresponding code type to be verified according to the scenario type to be verified, and select a simulation design code segment corresponding to the code type to be verified from all simulation design code segments of the target simulation chip as the code segment to be verified; the simulation design code segment is a code segment obtained by previously dividing the simulation design code of the target simulation chip based on different code types.

[0068] Step S24: Use the target position in the code segment to be verified as the insertion position, and insert the target assertion statement into the corresponding position in the code segment to be verified according to the insertion position.

[0069] In this embodiment, after determining the corresponding code type to be verified according to the type of the scenario to be verified and screening out the simulation design code segments corresponding to the code type to be verified from all the simulation design code segments of the target simulation chip as the code segments to be verified, it is necessary to use the target position in the code segments to be verified as the position to be inserted, and insert the target assertion statement into the corresponding position in the code segments to be verified according to the position to be inserted. This thus shows that when an abnormal situation occurs in the code segments, the corresponding target assertion statement can be accurately found.

[0070] In the first specific implementation manner, the target position in the code segments to be verified can be obtained by using a preset position input interface, then the target position is determined as the position to be inserted, and the target assertion statement is inserted into the corresponding position in the code segments to be verified according to the position to be inserted. Thus, it can be seen that the position to be inserted can be directly determined by the above method, effectively improving the verification efficiency and reducing the time for chip simulation verification.

[0071] In the second specific implementation manner, the target position can be randomly determined from the code segments to be verified in a random manner, and the target position is determined as the position to be inserted; in this implementation manner, the target position in the code segments to be verified can be directly randomly determined by the background, improving the confirmation speed of the target position and thus improving the verification efficiency.

[0072] In the third specific implementation manner of this embodiment, the target code statement can be determined from all the code statements of the to-be-verified code snippet according to the code type corresponding to the to-be-verified code snippet, and the position of the target code statement in the to-be-verified code snippet is determined as the target position, and the target position is determined as the to-be-inserted position. In this implementation manner, there is a possible manifestation: if the verification requirement is to determine whether a certain parameter A is successfully created in the scenario of the application program function of the target simulation chip, then based on this verification requirement, the code type corresponding to the parameter creation is determined as the code type, and then the to-be-verified code snippet corresponding to the creation of parameter A is determined. The target assertion statement with the corresponding annotation is selected from the preset assertion library. Since the verification requirement is to confirm whether this parameter is successfully created, the first implementable verification method can start from the specific function of parameter A and select the target assertion statement with the annotation of the specific function of parameter A from the preset assertion library. At this time, the target position can be determined at an appropriate position according to the functional characteristics of the specific function of parameter A. For example: the method of verifying whether parameter A is successfully called by verifying the call process of parameter A can be used to verify whether parameter A is successfully created. Then, the line where parameter A is called is determined as the target code statement, and the target insertion position is determined as the line after the line where parameter A is called in the code. If the corresponding function of parameter A can be realized, it means that parameter A is successfully created; the second implementable verification method can be verified by verifying whether the corresponding statement for creating parameter A is successfully implemented. The target assertion statement marked as testing whether the parameter exists is selected from the preset assertion library. The line where parameter A is created in the code is determined as the target code statement, and the line after the line where parameter A is created in the code is determined as the target position in the to-be-verified code snippet, and the target assertion statement is inserted at a certain position after the statement for creating parameter A. If the execution result of the target assertion statement is that parameter A exists, it means that parameter A is successfully created. It can be understood that there are various methods for determining the target position according to the position of the target code statement, including but not limited to the method of taking the line after the target code statement as the target position.

[0073] Step S25: Use the target assertion statement to monitor whether the to-be-verified code snippet is an abnormal code snippet, and after detecting the abnormal code snippet, determine the target assertion statement corresponding to the abnormal code snippet.

[0074] It can be understood that when inserting a target assertion statement, if only one target assertion statement is inserted for a certain verification requirement, and if the monitoring result is abnormal at this time, the abnormal code segment and the abnormal position can be quickly located. Further, when inserting a target assertion statement, it may also occur that multiple statements are inserted simultaneously for monitoring the abnormal code segment. In this case, if you want to accurately locate the error source position in the code, you need to first determine in which abnormal segments the abnormal problem that caused this abnormal verification appears, and determine the target assertion statement in the abnormal segment where the abnormal problem appears, and then combine the verification requirement, the scenario type, and the code function to determine the cause of the abnormality.

[0075] Step S26: Determine the abnormal position of the abnormal code segment based on the insertion position of the target assertion statement corresponding to the abnormal code segment.

[0076] In this embodiment, after determining the verification requirement including the to-be-verified scenario type, obtain the target assertion statement corresponding to the to-be-verified scenario type from the preset assertion library, then determine the corresponding to-be-verified code type according to the to-be-verified scenario type, and screen out the simulation design code segment corresponding to the to-be-verified code type from all the simulation design code segments of the target simulation chip as the to-be-verified code segment. Use the preset position input interface to obtain the target position in the to-be-verified code segment, and determine the target position as the to-be-inserted position, or randomly determine the target position from the to-be-verified code segment by a random method and determine the target position as the to-be-inserted position, or determine the target code statement from all the code statements of the to-be-verified code segment according to the code type corresponding to the to-be-verified code segment, and determine the position of the target code statement in the to-be-verified code segment as the to-be-inserted position. Use the target assertion statement to monitor whether the to-be-verified code segment is an abnormal code segment, and after detecting the abnormal code segment, determine the target assertion statement corresponding to the abnormal code segment, and determine the abnormal position of the abnormal code segment based on the insertion position of the target assertion statement corresponding to the abnormal code segment. Thus, it can be seen that by obtaining the target assertion statement corresponding to the to-be-verified scenario type from the preset assertion library, the observability of verification can be increased and the assertion debugging time can be effectively reduced. Screening out the simulation design code segment corresponding to the to-be-verified code type from all the simulation design code segments of the target simulation chip as the to-be-verified code segment can effectively improve the verification efficiency. Using the preset position input interface or a random method or according to the code type corresponding to the to-be-verified code segment to determine the target code statement from all the code statements of the to-be-verified code segment and determining the position of the target code statement in the to-be-verified code segment as the to-be-inserted position can increase the accuracy of verification and increase the verification efficiency.

[0077] See Figure 4 As shown, an embodiment of the present application discloses a chip simulation design verification device, which may specifically include:

[0078] A requirement determination module 11, configured to determine a verification requirement including a type of scenario to be verified;

[0079] A statement acquisition module 12, configured to acquire a target assertion statement corresponding to the type of scenario to be verified from a preset assertion library;

[0080] A code snippet determination module 13, configured to determine a corresponding type of code to be verified according to the type of scenario to be verified, and screen out a simulation design code snippet corresponding to the type of code to be verified from all simulation design code snippets of the target simulation chip as the code snippet to be verified; the simulation design code snippet is a code snippet obtained by pre-dividing the simulation design code of the target simulation chip based on different code types;

[0081] A simulation verification module 14, configured to insert the target assertion statement into the code snippet to be verified, so as to use the target assertion statement to monitor whether the code snippet to be verified is an abnormal code snippet, and determine a corresponding abnormal position based on the monitoring result after detecting the abnormal code snippet.

[0082] In this embodiment, after determining a verification requirement including a type of scenario to be verified, a target assertion statement corresponding to the type of scenario to be verified is acquired from a preset assertion library, a corresponding type of code to be verified is determined according to the type of scenario to be verified, and a simulation design code snippet corresponding to the type of code to be verified is screened out from all simulation design code snippets of the target simulation chip as the code snippet to be verified; the simulation design code snippet is a code snippet obtained by pre-dividing the simulation design code of the target simulation chip based on different code types, the target assertion statement is inserted into the code snippet to be verified, so as to use the target assertion statement to monitor whether the code snippet to be verified is an abnormal code snippet, and determine a corresponding abnormal position based on the monitoring result after detecting the abnormal code snippet. Thus, by acquiring a target assertion statement corresponding to the type of scenario to be verified from a preset assertion library, the observability of verification can be effectively increased, the assertion debugging time can be reduced, by inserting the target assertion statement into the code snippet to be verified, the accuracy of verification can be effectively increased, and by using the target assertion statement to monitor whether the code snippet to be verified is an abnormal code snippet, the abnormal can be quickly located and the verification efficiency can be improved.

[0083] In some specific embodiments, the requirement determination module 11 may specifically include:

[0084] A code function determination module, configured to obtain the simulation design code of the target simulation chip and determine different code functions corresponding to different scenario types that the simulation design code can implement;

[0085] A code type determination module, configured to determine different code types based on different code functions and establish a mapping relationship between the scenario types and the code types;

[0086] A code snippet determination module, configured to divide the simulation design code based on different code types to obtain all simulation design code snippets of the target simulation chip.

[0087] In some specific embodiments, the requirement determination module 11 may specifically include:

[0088] A scenario type determination module, configured to determine a to-be-verified scenario type from different scenario types that the simulation design code can implement and construct a corresponding verification requirement based on the to-be-verified scenario type; the to-be-verified scenario type includes any one or a combination of several of a scenario for verifying the circuit function of the target simulation chip, a scenario for verifying the interface function of the target simulation chip, and a scenario for verifying the application program function of the target simulation chip.

[0089] In some specific embodiments, the simulation verification module 14 may specifically include:

[0090] An insertion position determination module, configured to use a target position in the to-be-verified code snippet as the to-be-inserted position and insert the target assertion statement into the corresponding position in the to-be-verified code snippet according to the to-be-inserted position;

[0091] In some specific embodiments, the simulation verification module 14 may specifically include:

[0092] A first position determination unit, configured to obtain a target position in the to-be-verified code snippet by using a preset position input interface and determine the target position as the to-be-inserted position;

[0093] A second position determination unit, configured to randomly determine a target position from the to-be-verified code snippet in a random manner and determine the target position as the to-be-inserted position;

[0094] A third position determination unit, configured to determine a target code statement from all code statements of the to-be-verified code snippet according to the code type corresponding to the to-be-verified code snippet and determine the position of the target code statement in the to-be-verified code snippet as the to-be-inserted position.

[0095] In some specific embodiments, the simulation verification module 14 may specifically include:

[0096] An abnormal statement determination module, configured to determine the target assertion statement corresponding to the abnormal code segment after detecting the abnormal code segment;

[0097] An abnormal position determination module, configured to determine the abnormal position of the abnormal code segment based on the insertion position of the target assertion statement corresponding to the abnormal code segment.

[0098] Figure 5 The figure is a schematic structural diagram of an electronic device provided in an embodiment of the present application. The chip simulation design verification device 20 may specifically include: at least one processor 21, at least one memory 22, a power supply 23, a communication interface 24, a sensor 25, and a communication bus 26. Among them, the memory 22 is used to store a computer program, and the computer program is loaded and executed by the processor 21 to implement the relevant steps in the chip simulation design verification method executed by the chip simulation design verification device disclosed in any of the foregoing embodiments.

[0099] In this embodiment, the power supply 23 is used to provide a working voltage for each hardware device on the chip simulation design verification device 20; the communication interface 24 can create a data transmission channel between the chip simulation design verification device 20 and external devices, and the communication protocol it follows is any communication protocol applicable to the technical solution of the present application, and specific limitations are not imposed here; the sensor 25 is used to obtain sensor data, and its specific sensor types include but are not limited to a speed sensor, a temperature sensor, an infrared sensor, a sound sensor, an image sensor, etc.

[0100] In addition, as a carrier for resource storage, the memory 22 may be a read-only memory, a random access memory, a magnetic disk, or an optical disc, etc., and the resources stored thereon include an operating system 221, a computer program 222, and data 223, etc., and the storage method may be short-term storage or permanent storage.

[0101] Among them, the operating system 221 is used to manage and control each hardware device on the chip simulation design verification device 20 and the computer program 222 to implement the operation and processing of a large amount of data 223 in the memory 22 by the processor 21, and it may be Windows, Unix, Linux, etc. The computer program 222 may further include a computer program capable of completing other specific tasks in addition to the computer program capable of implementing the chip simulation design verification method executed by the chip simulation design verification device 20 disclosed in any of the foregoing embodiments. The data 223 may include not only the data transmitted by external devices received by the chip simulation design verification device, but also the data collected by its own sensor 25, etc.

[0102] The steps of the methods or algorithms described in combination with the embodiments disclosed in this article can be implemented directly by hardware, software modules executed by a processor, or a combination of both. The software modules can be placed in a random access memory (RAM), internal memory, read-only memory (ROM), electrically programmable ROM, electrically erasable programmable ROM, registers, hard disk, removable disk, CD-ROM, or any other form of storage medium well-known in the technical field.

[0103] Finally, it should also be noted that in this article, relational terms such as first and second are only used to distinguish one entity or operation from another entity or operation, and do not necessarily require or imply any such actual relationship or order between these entities or operations. Moreover, the term "comprising", "including" or any other variant thereof is intended to cover non-exclusive inclusion, so that a process, method, article or device comprising a series of elements includes not only those elements but also other elements not expressly listed, or elements inherent to such process, method, article or device. Without further limitation, an element defined by the statement "comprising an..." does not exclude the presence of additional identical elements in the process, method, article or device comprising the element.

[0104] The above has introduced in detail a chip simulation design verification method, device, equipment and storage medium provided by the present invention. Specific examples are used in this article to elaborate on the principle and implementation manner of the present invention. The description of the above embodiments is only used to help understand the method and its core idea of the present invention; at the same time, for those of ordinary skill in the art, according to the idea of the present invention, there will be changes in the specific implementation manner and application scope. In summary, the content of this specification should not be construed as a limitation to the present invention.

Claims

1. A method for chip simulation design verification, characterized in that, Including: Determine the verification requirements including the type of the scenario to be verified; Obtain the target assertion statement corresponding to the type of the scenario to be verified from a preset assertion library; Determine the corresponding type of code to be verified according to the type of the scenario to be verified, and screen out the simulation design code fragment corresponding to the type of code to be verified from all simulation design code fragments of the target simulation chip as the code fragment to be verified; The simulation design code fragment is a code fragment obtained by previously dividing the simulation design code of the target simulation chip based on different code types; Insert the target assertion statement into the code fragment to be verified, so as to use the target assertion statement to monitor whether the code fragment to be verified is an abnormal code fragment, and determine the corresponding abnormal position based on the monitoring result after detecting the abnormal code fragment; The determination of the verification requirements including the type of the scenario to be verified includes: Determine the type of the scenario to be verified from different scenario types that the simulation design code can implement, and construct the corresponding verification requirements based on the type of the scenario to be verified; The type of the scenario to be verified includes any one or a combination of several of the scenario for verifying the circuit function of the target simulation chip, the scenario for verifying the interface function of the target simulation chip, and the scenario for verifying the application program function of the target simulation chip.

2. The chip simulation design verification method according to claim 1, wherein Before the determination of the verification requirements including the type of the scenario to be verified, it further includes: Obtain the simulation design code of the target simulation chip, and determine the different code functions corresponding to different scenario types that the simulation design code can implement; Determine different code types based on different code functions, and establish a mapping relationship between the scenario type and the code type; Divide the simulation design code based on different code types to obtain all simulation design code fragments of the target simulation chip.

3. The chip simulation design verification method according to claim 1, wherein The insertion of the target assertion statement into the code fragment to be verified includes: Take the target position in the code fragment to be verified as the position to be inserted; Insert the target assertion statement into the corresponding position in the code fragment to be verified according to the position to be inserted.

4. The chip simulation design verification method according to claim 3, wherein The taking the target position in the code fragment to be verified as the position to be inserted includes: Obtain the target position in the code fragment to be verified by using a preset position input interface, and determine the target position as the position to be inserted; Or, randomly determine the target position from the code fragment to be verified by a random method, and determine the target position as the position to be inserted; Or, according to the code type corresponding to the code fragment to be verified, determine the target code statement from all code statements of the code fragment to be verified, and determine the position of the target code statement in the code fragment to be verified as the position to be inserted.

5. The chip simulation design verification method according to claim 3, wherein The determination of the corresponding abnormal position after detecting the abnormal code fragment includes: After detecting the abnormal code fragment, determine the target assertion statement corresponding to the abnormal code fragment; Determine the abnormal position of the abnormal code segment based on the insertion position of the target assertion statement corresponding to the abnormal code segment.

6. The chip simulation design verification method according to any one of claims 1 to 5, characterized in that Before obtaining the target assertion statement corresponding to the to-be-verified scenario type from the preset assertion library, it further includes: Obtain an open verification library, and classify each assertion statement in the open verification library according to different scenario types; Annotate the open verification library to annotate each assertion statement in the open verification library with the corresponding scenario type; Correspondingly, obtaining the target assertion statement corresponding to the to-be-verified scenario type from the preset assertion library includes: Query the annotated open verification library using the to-be-verified scenario type to obtain the target assertion statement corresponding to the to-be-verified scenario type.

7. A chip simulation design verification device, characterized in that, It includes: A requirement determination module, configured to determine the verification requirements including the to-be-verified scenario type; A statement acquisition module, configured to obtain the target assertion statement corresponding to the to-be-verified scenario type from the preset assertion library; A code segment determination module, configured to determine the corresponding to-be-verified code type according to the to-be-verified scenario type, and screen out the simulation design code segment corresponding to the to-be-verified code type from all simulation design code segments of the target simulation chip as the to-be-verified code segment; The simulation design code segment is a code segment obtained by previously dividing the simulation design code of the target simulation chip based on different code types; A simulation verification module, configured to insert the target assertion statement into the to-be-verified code segment, so as to use the target assertion statement to monitor whether the to-be-verified code segment is an abnormal code segment, and determine the corresponding abnormal position based on the monitoring result after detecting the abnormal code segment; The requirement determination module is specifically configured to: Determine the to-be-verified scenario type from different scenario types that the simulation design code can implement, and construct corresponding verification requirements based on the to-be-verified scenario type; the to-be-verified scenario type includes any one or a combination of several of the scenarios of verifying the circuit function of the target simulation chip, verifying the interface function of the target simulation chip, and verifying the application program function of the target simulation chip.

8. A chip simulation design verification device, characterized in that, It includes: A memory, configured to store a computer program; A processor, configured to execute the computer program to implement the chip simulation design verification method according to any one of claims 1 to 6.

9. A computer-readable storage medium, characterized in that, For storing a computer program; wherein, when the computer program is executed by the processor, it implements the chip simulation design verification method according to any one of claims 1 to 6.

Images