Semiconductor device and method for manufacturing semiconductor device

Abstract

The present invention relates to a semiconductor device and a method for manufacturing a semiconductor device. A semiconductor device with improved energy loss is provided. The semiconductor device includes a semiconductor substrate, a first semiconductor layer of a first conductivity type, a second semiconductor layer of a second conductivity type, a diode trench gate, and an electrode layer. The first semiconductor layer is provided as a surface layer on the upper surface side of the semiconductor substrate. The second semiconductor layer is provided below the first semiconductor layer. The diode trench insulating film of the diode trench gate is formed along the lower side wall and bottom of the inner wall of the trench, which is located below the upper side wall, and the upper side wall is located on the upper end side of the trench. The diode trench electrode of the diode trench gate is provided inside the trench. The electrode layer covers the upper side wall of the trench. The first semiconductor layer contacts the electrode layer at the upper side wall of the trench.

Description

Technical Field

[0001] The present invention relates to a semiconductor device and a method for manufacturing the semiconductor device. Background Art

[0002] A reverse conducting IGBT (RC-IGBT) is a semiconductor device having an IGBT region and a diode region within a semiconductor substrate. A freewheeling diode is formed in the diode region. The freewheeling diode comprises a trench formed in the semiconductor substrate, a diode trench insulating film formed on the inner wall of the trench, and a diode trench electrode disposed within the trench via the diode trench insulating film. The diode in the RC-IGBT described in Patent Document 1 comprises a trench gate (diode trench electrode) and a gate oxide film (diode trench insulating film) in contact with the trench gate. The side surfaces of the anode layer and the trench gate are separated by the gate oxide film and do not contact each other.

[0003] Patent Document 1: Japanese Patent Application Laid-Open No. 2016-96222

[0004] When the side of the anode layer is separated from the diode trench electrode by the diode trench insulating film, the carrier concentration near the anode layer increases due to the IE (Injection Enhanced) effect, reducing the forward voltage drop. On the other hand, the recovery current increases, increasing energy loss. Summary of the Invention

[0005] The present invention has been made to solve the above-mentioned problems and provides a semiconductor device with improved energy loss.

[0006] The semiconductor device according to the present invention includes a semiconductor substrate, a first semiconductor layer of a first conductivity type, a second semiconductor layer of a second conductivity type, a diode trench gate, and an electrode layer. The first semiconductor layer of the first conductivity type is provided as a surface layer on the upper surface side of the semiconductor substrate. The second semiconductor layer of the second conductivity type is provided below the first semiconductor layer. The diode trench gate includes a diode trench insulating film and a diode trench electrode. The diode trench insulating film is formed on the inner wall of a trench that penetrates the first semiconductor layer from the upper surface of the semiconductor substrate and reaches the second semiconductor layer. The diode trench electrode is provided inside the trench. The electrode layer covers the surface layer of the semiconductor substrate. The diode trench insulating film is formed along the lower sidewall and bottom of the inner wall of the trench, located below the upper sidewall, and the upper sidewall is located on the upper end side of the trench. The electrode layer further covers the upper sidewall of the trench. The first semiconductor layer contacts the electrode layer at the upper sidewall of the trench.

[0007] Effects of the Invention

[0008] According to the semiconductor device of the present invention, energy loss can be improved.

[0009] The objects, features, aspects and advantages of the present invention will become more apparent from the following detailed description and accompanying drawings. BRIEF DESCRIPTION OF THE DRAWINGS

[0010] Figure 1 This is a plan view showing an example of the structure of the semiconductor device in the first embodiment.

[0011] Figure 2 This is a plan view showing an example of the structure of the semiconductor device in the first embodiment.

[0012] Figure 3 This is a partially enlarged plan view showing the structure of the IGBT region of the semiconductor device in the first embodiment.

[0013] Figure 4 This is a cross-sectional view showing the structure of the IGBT region of the semiconductor device in the first embodiment.

[0014] Figure 5 This is a cross-sectional view showing the structure of the IGBT region of the semiconductor device in the first embodiment.

[0015] Figure 6 This is a partially enlarged plan view showing the structure of a diode region of the semiconductor device in the first embodiment.

[0016] Figure 7 This is a cross-sectional view showing the structure of a diode region of the semiconductor device in the first embodiment.

[0017] Figure 8 It will Figure 7 An enlarged cross-sectional view of the area shown.

[0018] Figure 9 This is a cross-sectional view showing the structure of a diode region of the semiconductor device in the first embodiment.

[0019] Figure 10 It is a cross-sectional view showing the structure of the boundary portion between the IGBT region and the diode region.

[0020] Figure 11 It is a cross-sectional view showing the structure of the boundary portion between the IGBT region and the termination region.

[0021] Figure 12 It is a cross-sectional view showing the structure of the boundary portion between the diode region and the termination region.

[0022] Figure 13 It is a diagram showing the process of preparing a semiconductor substrate.

[0023] Figure 14 It is a diagram showing the steps of forming an n-type carrier storage layer, a p-type base layer, and a p-type anode layer.

[0024] Figure 15 Is to form n + Type source layer, p + Type contact layer and p + Diagram of the process of forming the type contact layer.

[0025] Figure 16 It is a diagram showing the process of forming a groove.

[0026] Figure 17 It is a diagram showing the process of forming an oxide film.

[0027] Figure 18 It is a diagram showing the process of forming a gate trench electrode, a dummy trench electrode, and a diode trench electrode.

[0028] Figure 19 It is a diagram showing the process of forming an insulating material film.

[0029] Figure 20 A diagram showing a step of forming a contact hole in the IGBT region.

[0030] Figure 21 A diagram showing a step of forming a contact hole in a diode region.

[0031] Figure 22 It is a diagram showing the process of forming a barrier metal and an emitter electrode.

[0032] Figure 23 It is a diagram showing the process of thinning the semiconductor substrate.

[0033] Figure 24 It is a diagram showing the steps of forming an n-type buffer layer and a p-type collector layer.

[0034] Figure 25 Is to form n + Figure 2 shows the process of forming a cathode layer.

[0035] Figure 26 It is a diagram showing the process of forming a collector electrode.

[0036] Figure 27 This is a diagram showing the relationship between the position of the upper end of the diode trench insulating film and the forward voltage drop of the diode.

[0037] Figure 28 This is a diagram showing the relationship between the position of the upper end of the diode trench insulating film and the recovery current.

[0038] Figure 29 This is a diagram showing the relationship between the position of the upper end of the diode trench insulating film and the recovery loss.

[0039] Figure 30 It is a diagram showing the step of exposing the upper sidewall of the trench.

[0040] Figure 31 It is a diagram showing the process of forming an insulating material film.

[0041] Figure 32 It is a diagram showing the process of forming a contact hole.

[0042] Figure 33 It is a diagram showing the process of forming a barrier metal and an emitter electrode.

[0043] Figure 34 It is a diagram showing the process of forming an insulating material film.

[0044] Figure 35 It is a diagram showing the process of forming a contact hole.

[0045] Figure 36 It is a diagram showing the process of forming a barrier metal and an emitter electrode.

[0046] Figure 37 This is a partially enlarged plan view showing the structure of the diode region in the second embodiment.

[0047] Figure 38 This is a cross-sectional view showing the structure of the diode region in the second embodiment.

[0048] Figure 39 This is a cross-sectional view showing the structure of the diode region in the third embodiment.

[0049] Figure 40 This is a cross-sectional view showing the structure of the diode region in the fourth embodiment. DETAILED DESCRIPTION

[0050] <Implementation Method 1>

[0051] In the following description, n and p represent the conductivity type of the semiconductor. - Indicates that the impurity concentration is lower than n. + Indicates that the impurity concentration is higher than n. Similarly, p - Indicates that the impurity concentration is lower than p. + Indicates an impurity concentration higher than p. The p-type and n-type layers shown below may be interchanged.

[0052] (1) Overall planar structure of semiconductor device

[0053] Figure 1This is a top view showing an example of the structure of the semiconductor device 100 in embodiment 1. The semiconductor device 100 has an IGBT (Insulated Gate Bipolar Transistor) region 10 and a diode region 20 in one semiconductor substrate. The diode region 20 is adjacent to the IGBT region 10. A unit structure of multiple IGBTs (IGBT cells) is formed in the IGBT region 10, and a unit structure of multiple freewheeling diodes (diode cells) is formed in the diode region 20. The unit structure is a structure corresponding to the smallest unit of the element. The region including the IGBT region 10 and the diode region 20 is called a unit region. The semiconductor device 100 in embodiment 1 is an RC-IGBT (Reverse Conducting IGBT). The semiconductor substrate is formed of, for example, a semiconductor such as Si, or a so-called wide bandgap semiconductor such as SiC or GaN.

[0054] The IGBT region 10 and the diode region 20 have a stripe-like planar shape. The IGBT region 10 and the diode region 20 extend in one direction within the plane of the semiconductor substrate. The IGBT region 10 and the diode region 20 are alternately arranged side by side in a direction perpendicular to their extending directions. This type of semiconductor device 100 is referred to as a "stripe-type" device.

[0055] Figure 2 1 is a plan view showing an example of the structure of a semiconductor device 101 in Embodiment 1. Similar to the semiconductor device 100 , the semiconductor device 101 is an RC-IGBT including an IGBT region 10 and a diode region 20 within a single semiconductor substrate.

[0056] The diode region 20 has an island-like planar shape. Here, multiple diode regions 20 are arranged side by side in the vertical and horizontal directions within the plane of the semiconductor substrate. The IGBT region 10 surrounds each of the multiple diode regions 20. Such a semiconductor device 101 is called an "island type."

[0057] The semiconductor devices 100 and 101 include a pad region 40 and a termination region 30 in addition to the IGBT region 10 and the diode region 20 .

[0058] Pad region 40 is provided outside the cell region, that is, outside IGBT region 10 and diode region 20. Pad region 40 is provided adjacent to IGBT region 10. Pad region 40 is an area where control pads 41 for controlling the semiconductor device are provided. Control pads 41 include, for example, current sensing pad 41a, Kelvin emitter pad 41b, gate pad 41c, and temperature sensing diode pads 41d and 41e.

[0059] The current sensing pad 41a is a control pad for detecting the current flowing in the cell region and is electrically connected to some IGBT cells or diode cells in the cell region so that a current of a fraction to tens of thousands of the current flowing in the entire cell region flows.

[0060] The Kelvin emitter pad 41b and the gate pad 41c are control pads for applying a gate drive voltage for on / off control of the semiconductor device. The Kelvin emitter pad 41b is connected to the p-type base layer and n-type base layer of the IGBT cell. + The Kelvin emitter pad 41b and the p-type base layer can also be electrically connected via p + The gate pad 41c is electrically connected to a gate trench electrode (not shown) of the IGBT cell.

[0061] Temperature sensing diode pads 41d and 41e are control pads electrically connected to the anode and cathode of a temperature sensing diode (not shown) provided in the cell region. The voltage between the anode and cathode of the temperature sensing diodes in temperature sensing diode pads 41d and 41e is measured to measure the temperature of the semiconductor device.

[0062] The terminal region 30 is configured to surround the combined area of the cell region and the pad region 40. The terminal region 30 has a structure for maintaining the withstand voltage of the semiconductor device. Various structures can be appropriately selected for the withstand voltage maintenance structure. Examples of the withstand voltage maintenance structure include an FLR (Field Limiting Ring) and a VLD (Variation of Lateral Doping) formed on the surface layer of the first main surface side (upper surface side) of the semiconductor device. The FLR has a p-type terminal well layer (not shown) that is configured to surround the cell region. The VLD has a p-type well layer (not shown) that is configured to surround the cell region and has a concentration gradient. Depending on the withstand voltage design of the semiconductor device, the number of annular p-type terminal well layers 31 that constitute the FLR and the concentration distribution of the p-type well layer that constitutes the VLD are appropriately selected. In addition, a p-type terminal well layer can also be provided over substantially the entire pad region 40. Alternatively, an IGBT cell or a diode cell can also be provided in the pad region 40.

[0063] exist Figure 1 , three IGBT regions 10 and two diode regions 20 are shown. However, the number of IGBT regions 10 and diode regions 20 is not limited thereto. The number of IGBT regions 10 may be greater than or equal to four, or less than or equal to two. The number of diode regions 20 may be greater than or equal to three, or one. Figure 1The diode region 20 shown in FIG. 1 is sandwiched between two IGBT regions 10. However, the arrangement of the IGBT region 10 and the diode region 20 is not limited to this. The semiconductor device 100 may also have Figure 1 The configuration shown is a structure in which the arrangement of the IGBT region 10 and the diode region 20 is reversed. That is, one IGBT region 10 may be sandwiched between two diode regions 20. Alternatively, the same number of IGBT regions 10 and diode regions 20 may be provided adjacent to each other.

[0064] exist Figure 2 In the embodiment, multiple diode regions 20 are arranged in a matrix with four columns in the horizontal direction and two rows in the vertical direction. However, the number and arrangement of diode regions 20 are not limited to this. Semiconductor device 101 may also have a structure in which at least one diode region 20 is interspersed within IGBT region 10. The diode regions 20 may be arranged in any manner as long as they are surrounded by IGBT region 10.

[0065] (2) Structure of IGBT Region 10

[0066] Figure 3 This is a partially enlarged plan view showing the structure of the IGBT region 10 of the semiconductor device in the first embodiment. Figure 3 Enlarged view Figure 1 The semiconductor device 100 shown, or Figure 2 Region 82 in semiconductor device 101 is shown.

[0067] The semiconductor devices 100 and 101 include an active trench gate 11 and a dummy trench gate 12 provided in the IGBT region 10 .

[0068] In the semiconductor device 100, the active trench gate 11 and the dummy trench gate 12 extend in the length direction of the IGBT region 10. In other words, the lengths of the active trench gate 11 and the dummy trench gate 12 of the semiconductor device 100 are located in the extending direction of the IGBT region 10. Figure 3 The left and right directions correspond to .

[0069] In the semiconductor device 101, the active trench gate 11 and the dummy trench gate 12 extend in one direction of the IGBT region 10. For example, the active trench gate 11 and the dummy trench gate 12 are located at Figure 2 Extends in any direction of the up and down directions and the left and right directions.

[0070] The active trench gate 11 includes a gate trench insulating film 11b and a gate trench electrode 11a. The cross-sectional structure of the active trench gate 11 will be described in detail later. The gate trench insulating film 11b is formed along the inner wall of a trench formed in the depth direction from the first main surface (top surface) of the semiconductor substrate. The gate trench electrode 11a is formed within the trench through the gate trench insulating film 11b. The gate trench electrode 11a is electrically connected to the gate pad 41c (not shown).

[0071] The dummy trench gate 12 includes a dummy trench insulating film 12b and a dummy trench electrode 12a. The cross-sectional structure of the dummy trench gate 12 will be described in detail later. The dummy trench insulating film 12b is formed along the inner wall of the trench formed in the depth direction from the first main surface of the semiconductor substrate. The dummy trench electrode 12a is formed inside the trench through the dummy trench insulating film 12b. The dummy trench electrode 12a is connected to the emitter electrode 6 (on the first main surface of the semiconductor device 100 or the semiconductor device 101) provided above the first main surface. Figure 3 Not shown in the figure, refer to Figure 4 ) electrical connection.

[0072] In the region where the active trench gate 11 is provided in the IGBT region 10, n is selectively provided as a surface layer on the first main surface side of the semiconductor substrate. + Type source layer 13 and p + Type contact layer 14. In embodiment 1, n + Type source layer 13 and p + The n type contact layers 14 are alternately arranged along the extending direction (length direction) of the active trench gate 11. The active trench gate 11 is arranged to cross the above n type contact layers 14. + Type source layer 13 and p + Type contact layer 14. On both sides of the active trench gate 11 (in the direction perpendicular to the extension direction), n + The type source layer 13 is in contact with the gate trench insulating film 11b. + Type source layer 13 and p + The details of the type contact layer 14 are described below.

[0073] In the region where the dummy trench gate 12 is provided in the IGBT region 10, a p-type semiconductor substrate is provided as a surface layer on the first main surface side. + A p-type contact layer 14 is provided between two adjacent dummy trench gates 12. + Type contact layer 14.

[0074] exist Figure 3In the embodiment, three dummy trench gates 12 are arranged next to the three active trench gates 11. Furthermore, another three active trench gates 11 are arranged next to these three dummy trench gates 12. That is, active trench gate groups consisting of three active trench gates 11 and dummy trench gate groups consisting of three dummy trench gates 12 are arranged alternately. The number of active trench gates 11 included in one active trench gate group is not limited to three, and may be greater than or equal to one. In addition, the number of dummy trench gates 12 included in one dummy trench gate group is not limited to three, and may be greater than or equal to one. However, the dummy trench gates 12 are not essential for the semiconductor device 100 and the semiconductor device 101. That is, all the trench gates provided in the IGBT region 10 may also be active trench gates 11.

[0075] Figure 4 This is a cross-sectional view showing the structure of the IGBT region 10 of the semiconductor device in the first embodiment. Figure 4 Show Figure 3 The cross section is shown along line segment AA.

[0076] The semiconductor device 100 and the semiconductor device 101 include n in the IGBT region 10 + Type source layer 13, p + type contact layer 14, p-type base layer 15, n-type carrier storage layer 2, n - The IGBT cell corresponds to the region divided by the active trench gate 11. In this case, one IGBT cell includes n-type drift layer 1, n-type buffer layer 3, p-type collector layer 16, interlayer insulating film 4, barrier metal 5, emitter electrode 6 and collector electrode 7. + type source layer 13, p-type base layer 15, n-type carrier storage layer 2, n - type drift layer 1 , n-type buffer layer 3 , p-type collector layer 16 , interlayer insulating film 4 , barrier metal 5 , emitter electrode 6 and collector electrode 7 .

[0077] n - The drift layer 1 is formed as an inner layer of the semiconductor substrate. - The drift layer 1 is provided between the first main surface and the second main surface of the semiconductor substrate. The first main surface is the upper surface of the semiconductor substrate. The second main surface is the surface opposite to the first main surface and is the lower surface of the semiconductor substrate. + Type source layer 13 and p + The second main surface of the IGBT region 10 corresponds to the surface (upper surface) of the p-type contact layer 14. The second main surface of the IGBT region 10 corresponds to the surface (lower surface) of the p-type collector layer 16. Figure 4 In the AA cross section shown, the semiconductor substrate and the + Type source layer 13 and p+ The region corresponds to the range from the upper surface of the p-type contact layer 14 to the lower surface of the p-type collector layer 16. - The type drift layer 1 originates from the structure of the substrate before each structure of the semiconductor device is formed on the first main surface side and the second main surface side of the semiconductor substrate. - The drift layer 1 is a semiconductor layer containing, for example, arsenic (As) or phosphorus (P) as an n-type impurity. The concentration of the n-type impurity is preferably greater than or equal to 1.0E+12 / cm 3 and less than or equal to 1.0E+15 / cm 3 .

[0078] The n-type carrier storage layer 2 has a - The n-type drift layer 1 is provided on the first main surface side of the semiconductor substrate. The n-type carrier storage layer 2 is a semiconductor layer containing, for example, arsenic or phosphorus as an n-type impurity. The concentration of the n-type impurity in the n-type carrier storage layer 2 is greater than that of the n-type impurity. - The n-type drift layer 1 is high. Preferably, the concentration of the n-type impurity is greater than or equal to 1.0E+13 / cm 3 and less than or equal to 1.0E+17 / cm 3 The n-type carrier storage layer 2 reduces conduction loss when current flows through the IGBT region 10 .

[0079] The p-type base layer 15 is provided on the first main surface side of the semiconductor substrate relative to the n-type carrier storage layer 2. The p-type base layer 15 is a semiconductor layer containing, for example, boron (B) or aluminum (Al) as a p-type impurity. The concentration of the p-type impurity is preferably greater than or equal to 1.0E+12 / cm 3 and less than or equal to 1.0E+19 / cm 3 The p-type base layer 15 is in contact with the gate trench insulating film 11 b of the active trench gate 11 . When a gate driving voltage is applied to the gate trench electrode 11 a , a channel is formed in the p-type base layer 15 .

[0080] n + The n-type source layer 13 is provided on the first main surface side of the semiconductor substrate relative to the p-type base layer 15. As the surface layer of the semiconductor substrate, the n-type source layer 13 is provided on the first main surface side of the semiconductor substrate. + The p-type source layer 13 is selectively provided on the upper surface side of the p-type base layer 15. + The surface (upper surface) of the type source layer 13 constitutes the first main surface of the semiconductor substrate of the IGBT region 10. + The n-type source layer 13 is a semiconductor layer containing, for example, arsenic or phosphorus as an n-type impurity. The concentration of the n-type impurity is preferably greater than or equal to 1.0E+17 / cm 3 and less than or equal to 1.0E+20 / cm 3 In addition, sometimes n +The type source layer 13 is called n + type emitter layer.

[0081] p + The p-type contact layer 14 is provided on the first main surface side of the semiconductor substrate relative to the p-type base layer 15. As the surface layer of the semiconductor substrate, the p-type base layer 14 is provided on the first main surface side of the semiconductor substrate. + The p-type contact layer 14 is selectively provided on the upper surface side of the p-type base layer 15. + The p-type contact layer 14 is provided on the upper surface side of the p-type base layer 15 where no n-type base layer is provided. + The region of the type source layer 13. + The surface (upper surface) of the p-type contact layer 14 constitutes the first main surface of the semiconductor substrate of the IGBT region 10. + The p-type contact layer 14 is a semiconductor layer containing, for example, boron or aluminum as a p-type impurity. + The concentration of the p-type impurity in the p-type contact layer 14 is higher than the concentration of the p-type impurity in the p-type base layer 15. Preferably, the concentration of the p-type impurity is greater than or equal to 1.0E+15 / cm 3 and less than or equal to 1.0E+20 / cm 3 .

[0082] The n-type buffer layer 3 is relatively - The n-type drift layer 1 is provided on the second main surface side of the semiconductor substrate. The n-type buffer layer 3 contains, for example, phosphorus or protons (H + ) etc. The concentration of n-type impurities in the n-type buffer layer 3 is higher than that in the n-type buffer layer 3. - The n-type drift layer 1 is high. Preferably, the concentration of the n-type impurity is greater than or equal to 1.0E+12 / cm 3 and less than or equal to 1.0E+18 / cm 3 When the semiconductor device 100 is in the off state, the n-type buffer layer 3 reduces the depletion layer extending from the p-type base layer 15 to the second main surface side, thereby causing punch-through.

[0083] The p-type collector layer 16 is provided on the second main surface side of the semiconductor substrate relative to the n-type buffer layer 3. The surface (lower surface) of the p-type collector layer 16 constitutes the second main surface of the semiconductor substrate. The p-type collector layer 16 is a semiconductor layer containing, for example, boron or aluminum as a p-type impurity. The concentration of the p-type impurity is preferably greater than or equal to 1.0E+16 / cm 3 and less than or equal to 1.0E+20 / cm 3 .

[0084] The active trench gate 11 extends from the first main surface of the semiconductor substrate to the n + The p-type source layer 13, the p-type base layer 15 and the n-type carrier storage layer 2 penetrate and reach the n-type carrier storage layer 2. - Type drift layer 1.

[0085] The gate trench insulating film 11b is formed along the inner wall of a trench formed in the depth direction from the first main surface of the semiconductor substrate. The gate trench insulating film 11b is, for example, an oxide film.

[0086] The gate trench electrode 11a is formed inside the trench via the gate trench insulating film 11b. The bottom of the gate trench electrode 11a is connected to the n - The gate trench insulating film 11b is opposite to the n-type drift layer 1. + The gate trench electrode 11a is formed of, for example, conductive polysilicon. When a gate drive voltage is applied to the gate trench electrode 11a, a channel is formed in the p-type base layer 15 in contact with the gate trench insulating film 11b.

[0087] The dummy trench gate 12 extends the p + The p-type contact layer 14, the p-type base layer 15 and the n-type carrier storage layer 2 penetrate and reach the n-type - Type drift layer 1.

[0088] The dummy trench insulating film 12b is formed along the inner wall of the trench formed in the depth direction from the first main surface of the semiconductor substrate. The dummy trench insulating film 12b is, for example, an oxide film.

[0089] The dummy trench electrode 12a is formed inside the trench via the dummy trench insulating film 12b. - The dummy trench insulating film 12b on at least one side of the dummy trench insulating film 12b on both sides of the dummy trench electrode 12a is not in contact with the n type drift layer 1. + The dummy trench electrode 12a is in contact with the source layer 13. The dummy trench electrode 12a is formed of, for example, conductive polysilicon.

[0090] The interlayer insulating film 4 is provided on the gate trench electrode 11 a of the active trench gate 11 .

[0091] The barrier metal 5 is formed on the first main surface of the semiconductor substrate in the region where the interlayer insulating film 4 is not provided and on the interlayer insulating film 4. The barrier metal 5 is formed of a metal containing titanium, such as Ti, TiN, or TiSi. TiSi is an alloy of titanium and silicon (Si). + Type source layer 13, p + The barrier metal 5 and the n type contact layer 14 and the dummy trench electrode 12a make ohmic contact. + Type source layer 13, p + The type contact layer 14 and the dummy trench electrode 12a are electrically connected.

[0092] The emitter electrode 6 is provided on the barrier metal 5. The emitter electrode 6 is preferably formed of, for example, an aluminum alloy (Al-Si alloy) containing aluminum and silicon. + Type source layer 13, p + The type contact layer 14 and the dummy trench electrode 12a are electrically connected.

[0093] The collector electrode 7 is provided on the p-type collector layer 16 . The collector electrode 7 is preferably formed of an aluminum alloy, similarly to the emitter electrode 6 . The collector electrode 7 is in ohmic contact with the p-type collector layer 16 and is electrically connected to the p-type collector layer 16 .

[0094] Figure 5 This is a cross-sectional view showing the structure of the IGBT region 10 of the semiconductor device in the first embodiment. Figure 5 Show Figure 3 The cross section at line segment BB is shown.

[0095] Figure 5 The cross section at line segment BB shown is the same as Figure 4 The cross section at the line segment AA shown is different in that n is provided on the first main surface side of the semiconductor substrate without a surface layer. + Type source layer 13. That is, Figure 3 As shown, n + The p-type source layer 13 is selectively provided on the upper surface side of the p-type base layer 15 .

[0096] The structure of the IGBT region 10 has been described above, but the structure of the IGBT region 10 is not limited to the above structure. + The p-type contact layer 14 and the p-type base layer 15 are combined to define one p-type base layer.

[0097] It is also possible to form the n-type carrier accumulation layer 2 and the n-type carrier accumulation layer 2. - The n-type drift layer 1 is merged to form an n-type drift layer. The n-type carrier accumulation layer 2 is not essential, and an n-type carrier accumulation layer 2 may be provided at the position of the n-type carrier accumulation layer 2. - Type drift layer 1.

[0098] The n-type buffer layer 3 and n - The n-type drift layer 1 is combined to form an n-type drift layer. - The n-type drift layer 1 is merged to form an n-type drift layer. In addition, the n-type buffer layer 3 is not essential, and an n-type buffer layer 3 can also be provided at the position of the n-type buffer layer 3. - Type drift layer 1.

[0099] The barrier metal 5 is not essential. In the absence of the barrier metal 5, the emitter electrode 6 is provided at n + On the p-type source layer 13, + The barrier metal 5 may be provided only on the n-type contact layer 14 and on the dummy trench electrode 12a, and make ohmic contact with them. + The emitter electrode 6 is formed on an n-type semiconductor layer such as an n-type source layer 13. Alternatively, the barrier metal 5 and the emitter electrode 6 may be combined to form a single emitter electrode. Alternatively, an interlayer insulating film 4 may be provided partially above the dummy trench electrode 12 a. In this case, the emitter electrode 6 is electrically connected to the dummy trench electrode 12 a at a certain region above the dummy trench electrode 12 a.

[0100] The emitter electrode 6 may also be composed of multiple metal films, each of which may be composed of an aluminum alloy film or other metal films. For example, the emitter electrode 6 may be composed of an aluminum alloy film and a plated film. The plated film is formed, for example, by chemical plating or electroplating. The plated film is, for example, a nickel (Ni) film. A tungsten film may also be formed in a small area, such as between adjacent interlayer insulating films 4. The emitter electrode 6 is formed so as to cover the tungsten film. Since the tungsten film has better filling properties than the plated film, a good emitter electrode 6 is formed.

[0101] The collector electrode 7 may be made of an aluminum alloy and a plating film. The collector electrode 7 may have a structure different from that of the emitter electrode 6 .

[0102] (3) Structure of the diode region 20

[0103] Figure 6 This is a partially enlarged plan view showing the structure of the diode region 20 of the semiconductor device in the first embodiment. Figure 6 Enlarged view Figure 1 The semiconductor device 100 shown, or Figure 2 Region 83 in semiconductor device 101 is shown.

[0104] The semiconductor device 100 and the semiconductor device 101 include a diode trench gate 21 provided in the diode region 20 .

[0105] The diode trench gate 21 extends in one direction of the diode region 20. The diode trench gate 21 in the first embodiment extends in the same direction as the active trench gate 11 and the dummy trench gate 12.

[0106] The diode trench gate 21 includes a diode trench insulating film 21b and a diode trench electrode 21a. The cross-sectional structure of the diode trench gate 21 will be described in detail later. The diode trench insulating film 21b is formed along the inner wall of a trench formed in the depth direction from the first main surface of the semiconductor substrate. The diode trench electrode 21a is formed within the trench via the diode trench insulating film 21b.

[0107] In the diode region 20, p is selectively provided as a surface layer on the first main surface side of the semiconductor substrate. + type contact layer 24 and p-type anode layer 25. In embodiment 1, p + The p-type contact layer 24 and the p-type anode layer 25 are alternately arranged along the extending direction (length direction) of the diode trench gate 21. The diode trench gate 21 is arranged to cross the p-type anode layer 25. + Type contact layer 24 and p-type anode layer 25. + The p-type contact layer 24 and the p-type anode layer 25 are provided between two adjacent diode trench gates 21. + The details of the p-type contact layer 24 and the p-type anode layer 25 will be described below.

[0108] Figure 7 1 is a cross-sectional view showing the structure of the diode region 20 of the semiconductor device in the first embodiment. Figure 7 Show Figure 6 The cross section is shown at line CC. Figure 8 It will Figure 7 An enlarged cross-sectional view of area 200 is shown.

[0109] The semiconductor device 100 and the semiconductor device 101 include a p-type diode region 20. + type contact layer 24, p-type anode layer 25, n-type carrier storage layer 2, n - Type drift layer 1, n-type buffer layer 3, n + The p-type cathode layer 26, the barrier metal 5, the emitter electrode 6 and the collector electrode 7. The diode unit corresponds to the region divided by the diode trench gate 21. In this case, one diode unit includes p-type cathode layer 26, the barrier metal 5, the emitter electrode 6 and the collector electrode 7. + type contact layer 24, p-type anode layer 25, n-type carrier storage layer 2, n - Type drift layer 1, n-type buffer layer 3, n + type cathode layer 26, barrier metal 5, emitter electrode 6 and collector electrode 7.

[0110] n - The n-type drift layer 1 is formed as an inner layer of the semiconductor substrate. - n type drift layer 1 and IGBT region 10 -The type drift layer 1 is similarly provided between the first and second main surfaces of the semiconductor substrate. The diode region 20 is provided with a p + The region of the type contact layer 24, the first main surface of the semiconductor substrate and the p + The first main surface of the diode region 20 is continuous with the first main surface of the IGBT region 10. The second main surface of the diode region 20 is continuous with the n-type contact layer 24. + The second main surface of the diode region 20 is continuous with the second main surface of the IGBT region 10. Figure 7 In the cross section shown, the semiconductor substrate and the + The upper surface of the n-type contact layer 24 is + The n of the diode region 20 corresponds to the range from the lower surface of the cathode layer 26. - n type drift layer 1 and IGBT region 10 - Similarly, the n-type drift layer 1 is derived from the structure of the substrate before each structure is formed on the first main surface side and the second main surface side of the semiconductor substrate. - In other words, the n-type drift layer 1 is continuously and integrally formed in the diode region 20 and the IGBT region 10. - The type drift layer 1 is formed on the same semiconductor substrate.

[0111] The n-type carrier storage layer 2 has a - The n-type drift layer 1 is provided on the first main surface side of the semiconductor substrate. The n-type carrier accumulating layer 2 provided in the diode region 20 extends in the same plane as the n-type carrier accumulating layer 2 provided in the IGBT region 10. For example, the thickness and impurity concentration of the n-type carrier accumulating layer 2 in the diode region 20 are the same as those of the n-type carrier accumulating layer 2 in the IGBT region 10.

[0112] The p-type anode layer 25 is provided on the first main surface side of the semiconductor substrate relative to the n-type carrier storage layer 2. The p-type anode layer 25 is a semiconductor layer containing, for example, boron or aluminum as a p-type impurity. The concentration of the p-type impurity is preferably greater than or equal to 1.0E+12 / cm 3 and less than or equal to 1.0E+19 / cm 3The p-type impurity concentration of the p-type anode layer 25 is, for example, the same as the p-type impurity concentration of the p-type base layer 15 of the IGBT region 10. When the p-type impurity concentrations are the same, the p-type anode layer 25 is formed simultaneously with the p-type base layer 15. Alternatively, for example, the p-type impurity concentration of the p-type anode layer 25 may be lower than the p-type impurity concentration of the p-type base layer 15 of the IGBT region 10. When the p-type impurity concentration of the p-type anode layer 25 is low, the amount of holes injected into the diode region 20 during diode operation is reduced. Therefore, the recovery loss during diode operation is reduced.

[0113] p + The p-type contact layer 24 is provided on the first main surface side of the semiconductor substrate relative to the p-type anode layer 25. Figure 7 In the CC section shown, p + The p-type contact layer 24 covers the entire surface of the p-type anode layer 25. Figure 6 As shown, p + The p-type contact layer 24 is selectively provided on the upper surface side of the p-type anode layer 25. In other words, in the diode region 20, the p + The p-type contact layer 24 is selectively provided on the upper surface side of the p-type anode layer 25 as a surface layer on the first main surface side of the semiconductor substrate. + The p-type contact layer 24 is a semiconductor layer containing, for example, boron or aluminum as a p-type impurity. + The concentration of the p-type impurity in the p-type contact layer 24 is higher than the concentration of the p-type impurity in the p-type anode layer 25. Preferably, the concentration of the p-type impurity is greater than or equal to 1.0E+15 / cm 3 and less than or equal to 1.0E+20 / cm 3 .

[0114] The n-type buffer layer 3 is relatively - The n-type drift layer 1 is provided on the second main surface side of the semiconductor substrate. The n-type buffer layer 3 provided in the diode region 20 extends in the same plane as the n-type buffer layer 3 provided in the IGBT region 10. For example, the thickness and impurity concentration of the n-type buffer layer 3 in the diode region 20 are the same as those of the n-type buffer layer 3 in the IGBT region 10.

[0115] n + The n-type cathode layer 26 is provided on the second main surface side of the semiconductor substrate relative to the n-type buffer layer 3. + The surface (lower surface) of the cathode layer 26 constitutes the second main surface of the semiconductor substrate. + The cathode layer 26 is a semiconductor layer containing, for example, arsenic or phosphorus as an n-type impurity. The concentration of the n-type impurity is preferably greater than or equal to 1.0E+16 / cm 3 and less than or equal to 1.0E+21 / cm 3.

[0116] The diode trench gate 21 extends p from the first main surface of the semiconductor substrate. + The p-type contact layer 24, the p-type anode layer 25 and the n-type carrier storage layer 2 penetrate and reach the n-type carrier storage layer 2. - Type drift layer 1.

[0117] The diode trench insulating film 21b is formed along the inner wall of the trench 8 formed in the depth direction from the first main surface of the semiconductor substrate. The diode trench insulating film 21b is, for example, an oxide film.

[0118] The diode trench electrode 21a is formed in the interior of the trench 8 via the diode trench insulating film 21b. The bottom of the diode trench electrode 21a is connected to the n-type diode trench insulating film 21b via the diode trench insulating film 21b. - The diode trench electrode 21a is opposite to the type drift layer 1. The diode trench electrode 21a is formed of, for example, conductive polysilicon.

[0119] The diode trench insulating film 21b is formed along the lower sidewall 8b and bottom 8c of the trench 8 among the inner walls of the trench 8. The lower sidewall 8b is located below the upper sidewall 8a located at the upper end of the trench 8. The upper sidewall 8a of the trench 8 is not covered by the diode trench insulating film 21b.

[0120] The upper end 21c of the diode trench insulating film 21b is located below the upper surface of the diode trench electrode 21a and above the n-type carrier storage layer 2. More preferably, the upper end 21c of the diode trench insulating film 21b is located above the n-type carrier storage layer 2. + The p-type contact layer 24 is located below the p-type contact layer 24. The upper end 21c of the diode trench insulating film 21b corresponds to the lower end of the upper sidewall 8a and the upper end of the lower sidewall 8b of the trench 8. A portion of the side surface of the p-type anode layer 25 is not covered by the diode trench insulating film 21b. On the other hand, the side surface of the n-type carrier storage layer 2 is covered by the diode trench insulating film 21b. The depth D from the first main surface of the semiconductor substrate to the upper end 21c of the diode trench insulating film 21b is preferably greater than or equal to 0.5 μm.

[0121] The barrier metal 5 not only + The barrier metal 5 is formed of a metal containing titanium, such as Ti, TiN, TiSi, etc., similar to the barrier metal 5 of the IGBT region 10. The barrier metal 5 and the p-type contact layer 24 and the diode trench electrode 21a are covered. The upper sidewall 8a of the trench 8 and the side of the diode trench electrode 21a are also covered. + The barrier metal 5 makes ohmic contact with the p-type anode layer 25 and the p-type contact layer 24 and the diode trench electrode 21a. + Ohmic contact is made with the side surface of the type contact layer 24.

[0122] The emitter electrode 6 is provided on the barrier metal 5. It is preferable that the emitter electrode 6 is formed of, for example, an aluminum alloy (Al-Si alloy) similar to the emitter electrode 6 of the IGBT region 10. The emitter electrode 6 is connected to the diode trench electrodes 21a and p through the barrier metal 5. + The p-type contact layer 24 and the p-type anode layer 25 are electrically connected.

[0123] The collector electrode 7 is provided at n + The collector electrode 7 is preferably formed of an aluminum alloy, similar to the collector electrode 7 of the IGBT region 10. + The cathode layer 26 makes ohmic contact.

[0124] Figure 9 1 is a cross-sectional view showing the structure of the diode region 20 of the semiconductor device in the first embodiment. Figure 9 Show Figure 6 The cross section at line segment DD is shown.

[0125] Figure 9 The cross section at line segment DD shown is the same as Figure 7 The cross section at line segment CC shown is different in that the p-type semiconductor substrate is not provided on the first main surface side. + Type contact layer 24. That is, Figure 6 As shown, p + The p-type contact layer 24 is selectively provided on the upper surface side of the p-type anode layer 25. + In the region of the p-type contact layer 24, the first main surface of the semiconductor substrate corresponds to the surface (upper surface) of the p-type anode layer 25. Figure 9 In the cross section shown, one diode unit includes a p-type anode layer 25, an n-type carrier storage layer 2, and an n-type carrier storage layer 2. - Type drift layer 1, n-type buffer layer 3, n + type cathode layer 26, barrier metal 5, emitter electrode 6 and collector electrode 7.

[0126] In the DD cross section, the barrier metal 5 also makes ohmic contact with the side surface of the p-type anode layer 25 exposed at the upper side wall 8 a of the trench 8 .

[0127] The structure of the diode region 20 has been described above, but the structure of the diode region 20 is not limited to the above structure. + The p-type contact layer 24 and the p-type anode layer 25 are combined to form one p-type anode layer. + The concentration of the p-type impurities in the p-type contact layer 24 can be equal to that of the p-type impurities in the IGBT region 10. +The p-type impurities of the p-type contact layer 14 may be the same or different.

[0128] It is also possible to form the n-type carrier accumulation layer 2 and the n-type carrier accumulation layer 2. - The n-type drift layer 1 is merged to form an n-type drift layer. The n-type carrier accumulation layer 2 of the diode region 20 is not essential. An n-type carrier accumulation layer 2 may be provided at the position of the n-type carrier accumulation layer 2. - Even if the n-type carrier accumulating layer 2 is provided in the IGBT region 10 , it is not necessary to provide the n-type carrier accumulating layer 2 in the diode region 20 .

[0129] The n-type buffer layer 3 and n - The n-type drift layer 1 is combined to form an n-type drift layer. - The n-type drift layer 1 is merged to form an n-type drift layer. In addition, the n-type buffer layer 3 is not essential, and an n-type buffer layer 3 can also be provided at the position of the n-type buffer layer 3. - Type drift layer 1.

[0130] n + The n-type cathode layer 26 may be provided in the entire diode region 20 or in a part thereof. Although not shown in the figure, the semiconductor device 100 and the semiconductor device 101 may also include n-type cathode layers alternately arranged. + Type cathode layer 26 and p + The semiconductor layer of the type cathode layer is used as the semiconductor layer of the second main surface of the semiconductor substrate constituting the diode region 20. Such a structure is achieved by forming an n + The p-type cathode layer 26 is formed by selectively implanting p-type impurities into a portion of the region. + Type cathode layer 26 and p + A diode with a semiconductor layer in the cathode layer is called an RFC (Relaxed Field of Cathode) diode.

[0131] The barrier metal 5 is not essential. In the absence of the barrier metal 5, the emitter electrode 6 not only + The emitter electrode 6 is connected to the p-type anode layer 25 and the p-type contact layer 24 and the diode trench electrode 21a, and also covers the upper sidewall 8a of the trench 8 and the side of the diode trench electrode 21a. + An ohmic contact (not shown) is made to the side of the diode trench electrode 21a. An interlayer insulating film 4 may be provided on a portion of the diode trench electrode 21a. In this case, the emitter electrode 6 is electrically connected to the diode trench electrode 21a in a certain region on the diode trench electrode 21a.

[0132] (4) Structure of the Boundary Portion between the IGBT Region 10 and the Diode Region 20

[0133] Figure 10 It is a cross-sectional view showing the structure of the boundary portion between the IGBT region 10 and the diode region 20 . Figure 10 Show Figure 1 or Figure 2 The cross section at line segment EE is shown.

[0134] The p-type collector layer 16 provided on the second main surface side of the IGBT region 10 is provided so as to extend from the boundary between the IGBT region 10 and the diode region 20 to the diode region 20 at a distance U1. Compared with the structure in which the p-type collector layer 16 does not extend to the diode region 20, n + The distance between the cathode layer 26 and the active trench gate 11 is increased. In such a structure, when the freewheeling diode is in operation, when a gate drive voltage is applied to the gate trench electrode 11a, current flows from the channel formed adjacent to the active trench gate 11 to the n-type cathode layer 26. + The current of the cathode layer 26 is reduced. The distance U1 is, for example, 100 μm. However, depending on the application of the semiconductor device 100 or the semiconductor device 101, the distance U1 may be 0 μm or a distance smaller than 100 μm.

[0135] (5) Structure of the terminal region 30

[0136] Figure 11 It is a cross-sectional view showing the structure of the boundary portion between the IGBT region 10 and the termination region 30 . Figure 11 Show Figure 1 or Figure 2 The cross section is shown at line segment FF. Figure 12 3 is a cross-sectional view showing the structure of the boundary portion between the diode region 20 and the termination region 30 . Figure 12 Show Figure 1 The cross section at line segment GG is shown.

[0137] The semiconductor device 100 and the semiconductor device 101 include n in the terminal region 30. - type drift layer 1, p-type end well layer 31, n + type channel stopper layer 32 , n-type buffer layer 3 , p-type terminal collector layer 16 a , interlayer insulating film 4 , barrier metal 5 , emitter electrode 6 , terminal electrode 6 a , semi-insulating film 33 , terminal protection film 34 and collector electrode 7 .

[0138] n of the terminal region 30 - n type drift layer 1 and IGBT region 10 and diode region 20 -The n type drift layer 1 is similarly provided between the first main surface and the second main surface of the semiconductor substrate. - A portion of the n type drift layer 1 is exposed to the first main surface as the surface layer of the semiconductor substrate. - type drift layer 1, p-type end well layer 31 and n + The first main surface of the termination region 30 corresponds to the surface of the channel stopper layer 32. Figure 11 n in - type drift layer 1, p-type end well layer 31 and n + The first main surface of the termination region 30 is continuous with the first main surface of the IGBT region 10 or the diode region 20. The second main surface of the termination region 30 is continuous with the surface of the p-type termination collector layer 16a. Figure 11 The second main surface of the termination region 30 is continuous with the second main surface of the IGBT region 10 or the diode region 20. - n type drift layer 1 and IGBT region 10 and diode region 20 - Similarly, the n type drift layer 1 is derived from the structure of the substrate before each structure is formed on the first main surface side or the second main surface side of the semiconductor substrate. That is, the n type drift layer 1 is derived from the structure of the substrate before each structure is formed on the first main surface side or the second main surface side of the semiconductor substrate. - In other words, the n-type drift layer 1 is continuously and integrally formed in the terminal region 30, the IGBT region 10 and the diode region 20. - The type drift layer 1 is formed on the same semiconductor substrate.

[0139] The p-type end well layer 31 is relatively close to the n - The p-type drift layer 1 is provided on the first main surface side of the semiconductor substrate. The p-type end well layer 31 is provided to surround the cell region when viewed from above. In the first embodiment, the three p-type end well layers 31 form a triple ring when viewed from above and surround the cell region. The three p-type end well layers 31 form an FLR. The number of p-type end well layers 31 is not limited to three. The number of p-type end well layers 31 is appropriately selected based on the withstand voltage design of the semiconductor device 100 or the semiconductor device 101. The p-type end well layer 31 is a semiconductor layer having, for example, boron or aluminum as a p-type impurity. The concentration of the p-type impurity is greater than or equal to 1.0E+14 / cm 3 and less than or equal to 1.0E+19 / cm 3 .

[0140] n + The channel stopper layer 32 has a - The type drift layer 1 is provided on the first main surface side of the semiconductor substrate.+ The p-type channel stopper layer 32 is provided outside the p-type end well layer 31 in a plan view. + The p-type channel stopper layer 32 is provided to surround the p-type termination well layer 31 .

[0141] The n-type buffer layer 3 is relatively - The n-type drift layer 1 is provided on the second main surface side of the semiconductor substrate. The n-type buffer layer 3 provided in the terminal region 30 has the same structure as the n-type buffer layer 3 provided in the IGBT region 10 or the diode region 20. The n-type buffer layer 3 provided in the terminal region 30 is formed continuously and integrally with the n-type buffer layer 3 provided in the IGBT region 10 or the diode region 20. The n-type buffer layer 3 and the n-type buffer layer 3 may also be formed in a continuous and integral manner. - The n-type drift layer 1 is merged to form an n-type drift layer. In addition, the n-type buffer layer 3 is not necessary. An n-type buffer layer 3 can also be provided at the position of the n-type buffer layer 3. - Type drift layer 1.

[0142] P-type terminal collector layer 16a is provided on the second main surface side of the semiconductor substrate relative to n-type buffer layer 3. P-type terminal collector layer 16a has the same structure as p-type collector layer 16 provided in IGBT region 10. P-type terminal collector layer 16a is formed continuously and integrally with p-type collector layer 16 provided in IGBT region 10. Alternatively, p-type terminal collector layer 16a of terminal region 30 and p-type collector layer 16 of IGBT region 10 may be combined to define a single p-type collector layer.

[0143] like Figure 12 As shown, the p-type terminal collector layer 16a is arranged to extend from the boundary between the diode region 20 and the terminal region 30 to the diode region 20 at a distance U2. Compared with the structure in which the p-type terminal collector layer 16a does not extend to the diode region 20, the n + The distance between the p-type cathode layer 26 and the p-type end well layer 31 is increased. This structure prevents the p-type end well layer 31 from functioning as the anode of the freewheeling diode. The distance U2 is, for example, 100 μm.

[0144] The interlayer insulating film 4 is provided on the first main surface of the semiconductor substrate. The interlayer insulating film 4 has a contact hole. The contact hole is connected to the p-type terminal well layer 31 and the n-type terminal well layer 31. + The position of the p-type channel stopper layer 32 is correspondingly arranged. + The surface of the channel stopper layer 32 is exposed from the contact hole.

[0145] The barrier metal 5 is disposed on the p-type terminal well layer 31 and the n-type terminal well layer 31. + Type channel stopper layer 32.

[0146] Emitter electrode 6 is provided to be electrically connected to p-type termination well layer 31 close to IGBT region 10 or diode region 20 via barrier metal 5. Emitter electrode 6 of termination region 30 is formed integrally and continuously with emitter electrode 6 of IGBT region 10 or diode region 20.

[0147] The terminal electrode 6a is separated from the emitter electrode 6 and is provided outside the emitter electrode 6. The terminal electrode 6a is connected to the p-type terminal well layer 31 and the n-type terminal well layer 31 via the barrier metal 5 in the contact hole. + The channel stopper layer 32 is electrically connected to the substrate.

[0148] The semi-insulating film 33 is provided to electrically connect the emitter electrode 6 and the terminal electrode 6a. The semi-insulating film 33 is, for example, a semi-insulating silicon nitride film (sin SiN).

[0149] The terminal protection film 34 covers the emitter electrode 6, the terminal electrode 6a, and the semi-insulating film 33. The terminal protection film 34 is formed of, for example, polyimide.

[0150] The collector electrode 7 is provided on the p-type terminal collector layer 16a, that is, on the second main surface of the semiconductor substrate. The collector electrode 7 of the terminal region 30 is formed continuously and integrally with the collector electrodes 7 of the IGBT region 10 and the diode region 20.

[0151] (6) Method for manufacturing a semiconductor device

[0152] Figures 13 to 25 It is a diagram showing a method for manufacturing a semiconductor device in the first embodiment. Figures 13 to 19 The steps of forming the structure on the first main surface side of the semiconductor device are shown. Figures 22 to 25 The figures show the cross section of the boundary portion between the IGBT region 10 and the diode region 20. Figure 1 or Figure 2 The cross section at line segment EE is shown.

[0153] Figure 13 FIG is a diagram showing a process for preparing a semiconductor substrate. In Embodiment 1, an n-type wafer containing n-type impurities is prepared as a semiconductor substrate. In this process, the entire semiconductor substrate is connected to an n-type wafer. - The concentration of the n-type impurity is appropriately selected according to the withstand voltage specification of the semiconductor device 100 or the semiconductor device 101. For example, when the withstand voltage specification of the semiconductor device is 1200V, the concentration of the n-type impurity is adjusted to n - The resistivity of the drift layer 1 is about 40 to 120Ω·cm. Figure 13In the figure, the whole semiconductor substrate is prepared as n - The process of preparing an n-type wafer of the type drift layer 1 is not limited to this process. For example, the process of ion implanting n-type impurities from the first main surface or the second main surface of the semiconductor substrate and the process of diffusing the n-type impurities by heat treatment can be used to prepare an n-type wafer. - The semiconductor substrate may be a so-called FZ wafer produced by the FZ (Floating Zone) method, or a so-called MCZ wafer produced by the MCZ (Magnetic Field Applied Zochralki) method. Alternatively, the semiconductor substrate may be a wafer produced by sublimation or CVD (Chemical Vapor Deposition).

[0154] In the semiconductor substrate, an IGBT region 10 where an IGBT cell is to be arranged and a diode region 20 where a diode cell is to be arranged are predefined according to the structure of the semiconductor device 100 or the semiconductor device 101. Figure 13 Although not shown, a terminal region 30 in which a withstand voltage maintaining structure is to be formed is predefined around the IGBT region 10 and the diode region 20. Hereinafter, a method for manufacturing each structure of the IGBT region 10 and the diode region 20 will be mainly described.

[0155] Figure 14 The figure shows the process of forming the n-type carrier storage layer 2, the p-type base layer 15 and the p-type anode layer 25. The n-type impurities for forming the n-type carrier storage layer 2 are ion-implanted into the n-type carrier storage layer 2 from the first main surface side of the semiconductor substrate. - The surface layer of the n-type drift layer 1 is formed by ion implantation of the p-type impurity. For example, the n-type impurity is phosphorus. P-type impurities for forming the p-type base layer 15 and the p-type anode layer 25 are ion implanted into the first main surface of the semiconductor substrate. For example, the p-type impurity is boron. After the ion implantation, a heat treatment is performed. This heat treatment diffuses the n-type and p-type impurities, forming the n-type carrier storage layer 2, the p-type base layer 15, and the p-type anode layer 25.

[0156] During the above-mentioned ion implantation, a mask having openings in predetermined areas is formed on the first main surface of the semiconductor substrate. N-type impurities and p-type impurities are implanted into areas corresponding to the openings of the mask. The mask is formed by applying a resist to the first main surface of the semiconductor substrate and forming openings in predetermined areas of the resist using photolithography (photoengraving) technology. Hereinafter, the process of forming such a mask having openings in predetermined areas is referred to as masking. N-type impurities and p-type impurities are implanted into predetermined areas through masking. As a result, an n-type carrier storage layer 2, a p-type base layer 15, and a p-type anode layer 25 are selectively formed within the surface of the first main surface of the semiconductor substrate.

[0157] When the p-type base layer 15 and the p-type anode layer 25 have the same structure, that is, when their depths and p-type impurity concentrations are the same, the p-type impurity is ion-implanted simultaneously. On the other hand, when the p-type base layer 15 and the p-type anode layer 25 have different structures, that is, when their depths or p-type impurity concentrations are different, the p-type impurity for the p-type base layer 15 and the p-type impurity for the p-type anode layer 25 are ion-implanted separately using masking. For example, the p-type impurity for the p-type base layer 15 is ion-implanted through an opening provided in the IGBT region 10. The p-type impurity for the p-type anode layer 25 is ion-implanted through an opening provided in the diode region 20.

[0158] Although not shown in the figure, the process of forming the FLR having the p-type termination well layer 31 as the withstand voltage maintenance structure of the termination region 30 can be performed before processing the IGBT region 10 and the diode region 20, or can be performed simultaneously with the ion implantation of the p-type impurity into the IGBT region 10 or the diode region 20. For example, if the structure of the p-type termination well layer 31 in the termination region 30 is the same as that of the p-type anode layer 25, the p-type impurity for the p-type termination well layer 31 and the p-type impurity for the p-type anode layer 25 are ion implanted simultaneously. This results in the formation of the p-type termination well layer 31 and the p-type anode layer 25 having the same depth and p-type impurity concentration. If the p-type termination well layer 31 and the p-type anode layer 25 have different depths or p-type impurity concentrations, the p-type impurity for the p-type termination well layer 31 and the p-type impurity for the p-type anode layer 25 are ion implanted separately using a mask process. When the structures of the p-type terminal well layer 31 and the p-type anode layer 25 differ, the p-type impurities for the p-type terminal well layer 31 and the p-type impurities for the p-type anode layer 25 can similarly be ion-implanted simultaneously. However, the mask openings in at least one of the regions where the p-type terminal well layer 31 is formed and the regions where the p-type anode layer 25 is formed form a grid pattern. This grid pattern reduces the aperture ratio, thereby controlling the amount of p-type impurities implanted into the semiconductor substrate. While the formation relationship between the p-type terminal well layer 31 and the p-type anode layer 25 has been described here, the formation relationship between the p-type terminal well layer 31 and the p-type base layer 15 is also similar. Furthermore, the p-type impurities for forming the p-type terminal well layer 31, the p-type base layer 15, and the p-type anode layer 25 can also be ion-implanted simultaneously. The n-type carrier storage layer 2 and the p-type base layer 15 are formed in the IGBT region 10 and connected to the p-type terminal well layer 31 in the terminal region 30. The n-type carrier storage layer 2 and the p-type anode layer 25 are formed in the diode region 20 and are connected to the p-type terminal well layer 31 in the terminal region 30 .

[0159] Figure 15 Is to form n + Type source layer 13, p + Type contact layer 14 and p + Figure 24 is a process diagram for forming an n-type contact layer. + The n-type impurities of the p-type source layer 13 are ion-implanted into the surface layer of the p-type base layer 15 from the first main surface side of the semiconductor substrate. The n-type impurities are, for example, arsenic or phosphorus. At this time, the openings of the mask are arranged so that the n-type impurities are injected only into the predetermined area within the IGBT region 10. By this masking process, n + The p-type source layer 13 is selectively formed on the surface layer of the p-type base layer 15 in the IGBT region 10 .

[0160] Similarly, the substrate for forming the p+ Type contact layer 14 and p + The p-type impurities are ion-implanted into the contact layer 24. The p-type impurities are, for example, boron or aluminum. At this time, the mask opening is configured so that the p-type impurities are injected only into the specified area in the IGBT area 10 and the specified area in the diode area 20. By this masking process, the p-type impurities are ion-implanted into the contact layer 24. The p-type impurities are, for example, boron or aluminum. + Type contact layer 14 and p + The p-type contact layer 24 is selectively formed on the surface layers of the p-type base layer 15 in the IGBT region 10 and the diode region 20 .

[0161] Figure 16 This diagram illustrates the process of forming trench 8. Trench 8 is formed by depositing a hard mask material on the first main surface of the semiconductor substrate, forming a hard mask including an opening corresponding to trench 8 by photolithography, and etching the semiconductor substrate through the hard mask. The hard mask is, for example, a thin film such as SiO2.

[0162] The trench 8 of the IGBT region 10 penetrates the p-type base layer 15 and the n-type carrier storage layer 2 from the first main surface of the semiconductor substrate and reaches the n-type carrier storage layer 2. - Type drift layer 1. A portion of the plurality of trenches 8 formed in the IGBT region 10 further forms n + The type source layer 13 penetrates, and another portion of the trench further connects the p + The trench 8 of the diode region 20 penetrates the p-type anode layer 25 and the n-type carrier storage layer 2 from the first main surface of the semiconductor substrate to reach the n-type contact layer 14. - Type drift layer 1. As the surface layer of the semiconductor substrate, a p + The region of the p-type contact layer 24 is further formed by the trench 8. + The contact layer 24 penetrates through the substrate.

[0163] exist Figure 16 In the embodiment, the pitch of the trenches 8 in the IGBT region 10 is the same as the pitch of the trenches 8 in the diode region 20. However, the pitch of the trenches 8 in the IGBT region 10 may be different from the pitch of the trenches 8 in the diode region 20. The pitch of the trenches 8 may be appropriately changed according to the mask pattern in the masking process.

[0164] Figure 17 1 is a diagram showing the process of forming the oxide film 9. The semiconductor substrate is heated in an atmosphere containing oxygen. The oxide film 9 is formed on the inner wall of the trench 8 and the first main surface of the semiconductor substrate. In the IGBT region 10, the n + The oxide film 9 formed on the inner wall of the trench 8 through which the type source layer 13 penetrates corresponds to the gate trench insulating film 11b. Similarly, in the IGBT region 10, when the p +The oxide film 9 formed on the inner wall of the trench 8 through which the type contact layer 14 penetrates corresponds to the dummy trench insulating film 12b. The oxide film 9 formed on the first main surface of the semiconductor substrate is removed in a subsequent step.

[0165] Figure 18 This diagram illustrates the steps for forming the gate trench electrode 11a, the dummy trench electrode 12a, and the diode trench electrode 21a. Polycrystalline silicon doped with n-type or p-type impurities is deposited within the trench 8 by CVD (chemical vapor deposition) or other methods. As a result, the gate trench electrode 11a is formed within the trench 8 via the gate trench insulating film 11b. The dummy trench electrode 12a is formed within the trench 8 via the dummy trench insulating film 12b. The diode trench electrode 21a is formed within the trench 8 via the diode trench insulating film 21b.

[0166] Figure 19 1 is a diagram showing a step of forming an insulating material film 4a. The insulating material film 4a is formed on the first main surface of the semiconductor substrate. The insulating material film 4a contains, for example, SiO2.

[0167] Figure 20 This figure shows the process of forming a contact hole in the IGBT region 10. After masking the insulating material film 4a, the insulating material film 4a and the oxide film 9 are etched. The etching is performed by dry etching. The dry etching is performed in a gas atmosphere containing a fluorocarbon. The gas includes, for example, C5F8, C4F8, CHF3, CF4, C4F6, C3F8, C2F6, etc. The contact hole is formed in the n of the IGBT region 10. + Type source layer 13, p + The position of the type contact layer 14 and the dummy trench gate 12 is not formed in the diode region 20. Through this process, n + Type source layer 13, p + The type contact layer 14 and the dummy trench electrode 12a are exposed. In the region covered by the mask, that is, on the active trench gate 11 of the IGBT region 10, the insulating material film 4a remains, forming the interlayer insulating film 4.

[0168] Figure 21 2 is a diagram showing a process of forming a contact hole in the diode region 20. More specifically, Figure 21 The process of exposing the upper sidewall 8a of the trench 8 in the diode region 20 is shown. After masking the insulating material film 4a, the insulating material film 4a and the oxide film 9 are etched. At this point, the entire surface of the IGBT region 10, where the interlayer insulating film 4 has been formed, is covered by the mask. The etching is performed by dry etching. The dry etching is performed in a gas atmosphere containing a fluorocarbon. The contact hole is formed in the p +The type contact layer 24 and the diode trench gate 21 are located therein.

[0169] When etching the insulating material film 4a of the diode region 20, the upper portion of the diode trench insulating film 21b of the dummy trench gate 12, which is not covered by the mask, is also etched. As a result, the upper sidewall 8a of the trench 8 is exposed. A gap is formed between the upper sidewall 8a of the trench 8 and the diode trench electrode 21a. The diode trench insulating film 21b remains on the lower sidewall 8b and bottom 8c of the trench 8.

[0170] Figure 22 : This is a diagram showing the process of forming the barrier metal 5 and the emitter electrode 6. The barrier metal 5 is formed on the first main surface of the semiconductor substrate and the interlayer insulating film 4. In addition, the barrier metal 5 is also deposited in the gap between the upper side wall 8a of the trench 8 and the diode trench electrode 21a. The barrier metal 5 is, for example, a metal containing titanium such as Ti, TiN, or TiSi. The barrier metal 5 is formed by PVD (physical vapor deposition) or CVD. The barrier metal 5 is in contact with the p-type anode layer 25 and the p-type anode layer exposed at the upper side wall 8a of the trench 8. + The barrier metal 5 is in contact with the side surfaces of the diode trench electrode 21a.

[0171] Moreover, the emitter electrode 6 is formed on the barrier metal 5. The emitter electrode 6 includes, for example, an aluminum silicon alloy (Al-Si alloy). The emitter electrode 6 is formed by PVD such as sputtering and evaporation. In addition, as the emitter electrode 6, a nickel alloy (Ni alloy) can also be formed on the aluminum silicon alloy by chemical plating or electroplating. The electroplating method can easily form a thick metal film. Since the heat capacity of the thick film emitter electrode 6 increases, the heat resistance of the emitter electrode 6 is improved. In addition, when a nickel alloy is further formed on the aluminum silicon alloy by plating, the plating process can also be implemented after the second main surface side of the semiconductor substrate is processed.

[0172] Figure 23 This diagram illustrates the process of thinning a semiconductor substrate. The second main surface of the semiconductor substrate is polished to a thickness specified according to the design of the semiconductor device. The thickness of the polished semiconductor substrate is, for example, greater than or equal to 80 μm and less than or equal to 200 μm.

[0173] Figure 24 The figure shows the process of forming the n-type buffer layer 3 and the p-type collector layer 16. The n-type impurities for forming the n-type buffer layer 3 are ion-implanted into the n-type buffer layer 3 from the second main surface side of the semiconductor substrate. -The surface layer of the n-type drift layer 1. As the n-type impurity, for example, phosphorus may be implanted, or protons may be implanted. Alternatively, for example, both phosphorus and protons may be implanted.

[0174] Protons can be implanted from the second main surface of the semiconductor substrate to a deep location at relatively low acceleration energy. By varying the acceleration energy, the proton implantation depth can be easily controlled. Therefore, by performing multiple proton ion implantations while varying the acceleration energy, an n-type buffer layer 3 having a wider width in the thickness direction of the semiconductor substrate is formed compared to an n-type buffer layer 3 containing phosphorus.

[0175] Phosphorus has a higher activation rate as an n-type impurity than protons. Even with a thinned semiconductor substrate, an n-type buffer layer 3 containing phosphorus more reliably reduces the occurrence of punch-through caused by the expansion of the depletion layer. To further thin the semiconductor substrate, it is preferable to form an n-type buffer layer 3 containing both protons and phosphorus. In this case, protons are implanted deeper into the second main surface of the semiconductor substrate than phosphorus.

[0176] Then, p-type impurities for forming p-type collector layer 16 are ion implanted from the second main surface of the semiconductor substrate. For example, boron is implanted as the p-type impurity. After the ion implantation, the second main surface of the semiconductor substrate is irradiated with laser light. This laser annealing activates the implanted boron, forming p-type collector layer 16.

[0177] During this laser annealing, phosphorus implanted from the second main surface of the semiconductor substrate into the relatively shallow n-type buffer layer 3 is also activated. On the other hand, protons are activated at relatively low annealing temperatures of approximately 380°C to 420°C. Therefore, after proton implantation, it is preferable not to heat the semiconductor substrate to a temperature higher than 380°C to 420°C, except for the proton activation step. Laser annealing only heats the area near the second main surface of the semiconductor substrate to a high temperature. Therefore, laser annealing is effective for activating n-type or p-type impurities following proton implantation.

[0178] The n-type buffer layer 3 may be formed in the IGBT region 10, the diode region 20, and the termination region 30, or may be formed only in the IGBT region 10 or the diode region 20. The p-type collector layer 16 is also formed in the termination region 30. Here, the p-type collector layer 16 in the termination region 30 corresponds to the p-type termination collector layer 16a.

[0179] Figure 25 Is to form n + Figure 2 is a process diagram for forming an n-type cathode layer 26. + The n-type impurities of the cathode layer 26 are ion-implanted into the second main surface of the semiconductor substrate in the diode region 20. Phosphorus is implanted as the n-type impurity.+ N-type impurities are selectively implanted by masking so that the boundary of the cathode layer 26 is located at a position away from the boundary between the IGBT region 10 and the diode region 20 by a distance U1 toward the diode region 20 .

[0180] To form n + The amount of n-type impurities injected into the p-type cathode layer 26 is greater than the amount of p-type impurities injected into the p-type collector layer 16. + The n-type impurities of the cathode layer 26 are injected into the region where the p-type collector layer 16 is formed. That is, it is necessary to change the p-type semiconductor into an n-type semiconductor by injecting the n-type impurities. + N-type impurities are implanted into the entire region of the cathode layer 26 so that the concentration of the n-type impurities is higher than the concentration of the p-type impurities.

[0181] exist Figure 25 The depth of the p-type collector layer 16 from the second main surface and the n + The depth of the p-type cathode layer 26 is the same as that of the p-type collector layer 16 and the n-type cathode layer 26. + The relationship of the depth of the cathode layer 26 is not limited to this. + The depth of the p-type cathode layer 26 is greater than or equal to the depth of the p-type collector layer 16 .

[0182] Figure 26 : This is a diagram showing the process of forming the collector electrode 7. The collector electrode 7 is formed on the second main surface of the IGBT region 10, the diode region 20, and the termination region 30. The collector electrode 7 may be formed over the entire second main surface of the semiconductor substrate.

[0183] Collector electrode 7 includes aluminum-silicon alloy, titanium, or the like. Collector electrode 7 is formed by PVD (photovoltaic deposition) such as sputtering or vapor deposition. Collector electrode 7 may also have a structure comprising a stack of multiple metal layers, such as aluminum-silicon alloy, titanium, nickel, or gold. Alternatively, collector electrode 7 may be formed by further forming a metal film by chemical plating or electroplating on a metal film formed by PVD.

[0184] In the first embodiment, through the above-described manufacturing process, multiple semiconductor devices 100 or 101 are fabricated in a matrix on a single semiconductor substrate. The multiple semiconductor devices are then separated into individual semiconductor devices by laser dicing or blade dicing. Thus, semiconductor devices 100 or 101 are completed.

[0185] (7) The role of the upper sidewall of the groove

[0186] Figure 27 2 is a diagram showing the relationship between the position of the upper end 21c of the diode trench insulating film 21b and the forward voltage drop (VF) of the diode. Figure 27 The relationship between the depth D from the first main surface of the semiconductor substrate to the upper end 21c of the diode trench insulating film 21b and the forward voltage drop (VF) is shown. The forward voltage drop (VF) is represented by a normalized value.

[0187] Figure 28 : is a diagram showing the relationship between the position of the upper end 21c of the diode trench insulating film 21b and the recovery current (Irr). Figure 28 The relationship between the depth D and the recovery current (Irr) is shown. The recovery current (Irr) is represented by a standardized value.

[0188] Figure 29 : is a diagram showing the relationship between the position of the upper end 21c of the diode trench insulating film 21b and the recovery loss (Err). Figure 29 The relationship between the depth D and the recovery loss (Err) is shown. The recovery loss (Err) is represented by a normalized value.

[0189] As the depth D increases, the forward voltage drop (VF) increases, while the recovery current (Irr) and recovery loss (Err) decrease. For example, the forward voltage drop (VF) when D = 0.5 μm increases by 6% compared to the forward voltage drop (VF) when D = 0 μm. On the other hand, the recovery current (Irr) and recovery loss (Err) decrease by 19%. When D ≥ 0.5 μm, the recovery current (Irr) and recovery loss (Err) decrease.

[0190] In summary, the semiconductor device in the first embodiment includes a semiconductor substrate, a first semiconductor layer of the first conductivity type, a second semiconductor layer of the second conductivity type, a diode trench gate 21, and an electrode layer. In the first embodiment, the first semiconductor layer of the first conductivity type is a p-type anode layer 25, and the second semiconductor layer of the second conductivity type is an n-type carrier storage layer 2 and an n-type carrier storage layer 2. - The n-type semiconductor layer of the n-type drift layer 1. The electrode layer in the first embodiment is the barrier metal 5. The p-type anode layer 25 is provided as a surface layer on the first main surface side of the semiconductor substrate. - The p-type drift layer 1 is provided below the p-type anode layer 25. The diode trench gate 21 includes a diode trench insulating film 21b and a diode trench electrode 21a. The diode trench insulating film 21b is formed from the first main surface of the semiconductor substrate through the p-type anode layer 25 to the n-type semiconductor layer (n -type drift layer 1). The diode trench electrode 21a is arranged inside the trench 8. The barrier metal 5 covers the surface of the semiconductor substrate. The diode trench insulating film 21b is formed along the lower side wall 8b and the bottom 8c located below the upper side wall 8a in the inner wall of the trench 8, and the upper side wall 8a is located on the upper end side of the trench 8. The barrier metal 5 further covers the upper side wall 8a of the trench 8. The p-type anode layer 25 contacts the barrier metal 5 at the upper side wall 8a of the trench 8. The electrode layer can also be an emitter electrode 6 instead of the barrier metal 5. The electrode layer is not limited to the barrier metal 5 and the emitter electrode 6, but is a metal layer that makes ohmic contact with the p-type anode layer 25 at the upper side wall 8a.

[0191] In such a structure, since the contact area between the p-type anode layer 25 and the barrier metal 5 increases, the number of carriers flowing into the emitter electrode 6 increases. Since the carrier concentration near the p-type anode layer 25 decreases, the IE effect is suppressed. As a result, the recovery current (Irr) and the recovery loss (Err) are reduced. In high-speed applications such as transistor on-off loss, power loss, that is, energy loss, is also reduced. In embodiment 1, a semiconductor device in which the first conductivity type is p-type and the second conductivity type is n-type is shown, but the first conductivity type may also be n-type and the second conductivity type may be p-type. In this case, the first semiconductor layer of the first conductivity type is an n-type cathode layer.

[0192] Furthermore, in the first embodiment, the depth D from the first main surface of the semiconductor substrate to the upper end 21 c of the diode trench insulating film 21 b is greater than or equal to 0.5 μm.

[0193] With such a structure, the carrier concentration near the p-type anode layer 25 is further reduced, and the effect of reducing the recovery current (Irr) is significantly exhibited.

[0194] In addition, in the first embodiment, the barrier metal 5 is formed by the CVD method.

[0195] In such a manufacturing method, the barrier metal 5 satisfactorily fills the gap between the upper sidewall 8 a of the trench 8 and the diode trench electrode 21 a .

[0196] (Variation 1 of Implementation Example 1)

[0197] Figure 30 This is a diagram showing a method for manufacturing a semiconductor device in Modification 1 of Embodiment 1, and illustrates a step of exposing the upper sidewall 8 a of the trench 8 .

[0198] When etching the insulating material film 4a and the oxide film 9 of the interlayer insulating film 4, a groove (recess) corresponding to the position of the contact hole is formed on the first main surface of the semiconductor substrate. The contact hole is formed by dry etching. The groove is formed by overetching at this time.

[0199] Dry etching is performed in a gas environment containing fluorocarbons, such as C5F8, C4F8, CHF3, CF4, C4F6, C3F8, and C2F6.

[0200] In order to expose the upper sidewall 8a of the trench 8 and realize a predetermined recess depth DR, it is necessary to make the etching rate of the oxide film 9 faster than that of the p-type anode layer 25 and the p-type anode layer 25. + The etching rate of the type contact layer 24 is high.

[0201] In particular, in order to form the upper end 21c of the diode trench insulating film 21b at a position deeper than the groove, it is preferable that the etching rate of the oxide film 9 is the same as that of the p-type anode layer 25 or the p-type anode layer 25. + The selectivity between the etching rates of the type contact layer 24 is greater than or equal to 11.0. The etching conditions with a selectivity greater than or equal to 11.0 can achieve a structure with RD=50 nm and D≥0.5 μm.

[0202] Then, a barrier metal 5 is formed in the groove. The groove reduces the contact resistance between the barrier metal 5 and the p-type anode layer 25, and the contact resistance between the barrier metal 5 and the p-type anode layer 25. + The contact resistance of the type contact layer 24 is reduced. Even when the emitter electrode 6 is formed instead of the barrier metal 5, the same effect as described above is obtained.

[0203] (Variation 2 of Implementation 1)

[0204] Figures 31 to 33 A diagram showing a method for manufacturing a semiconductor device in Modification 2 of Embodiment 1.

[0205] Figure 31 The step of forming the insulating material film 4a is shown. The step of forming the insulating material film 4a is the same as that of the first embodiment.

[0206] Figure 32 1 shows the process of forming the contact hole. In more detail, Figure 32 The process of forming the interlayer insulating film 4 and exposing the upper sidewall 8a of the trench 8 in the diode region 20 is shown. After masking the insulating material film 4a, the insulating material film 4a and the oxide film 9 are etched. The contact hole is formed in n + Type source layer 13, p + Type contact layer 14, p + The position of the type contact layer 24 and the diode trench gate 21. Through this process, n +Type source layer 13, p + Type contact layer 14, p + The type contact layer 24 and the diode trench electrode 21a are exposed. An interlayer insulating film 4 is formed in the region covered by the mask, that is, on the active trench gate 11 and the dummy trench gate 12 of the IGBT region 10.

[0207] When etching insulating material film 4a, the upper portion of diode trench insulating film 21b of diode trench gate 21, which is not covered by the mask, is also etched. As a result, upper sidewall 8a of trench 8 is exposed. A gap is formed between upper sidewall 8a of trench 8 and diode trench electrode 21a. Diode trench insulating film 21b remains on lower sidewall 8b and bottom 8c of trench 8.

[0208] Figure 33 FIG2 shows the process of forming the barrier metal 5 and the emitter electrode 6. The barrier metal 5 is formed on the first main surface of the semiconductor substrate and the interlayer insulating film 4. In addition, the barrier metal 5 is also deposited in the gap between the upper sidewall 8a of the trench 8 and the diode trench electrode 21a. The barrier metal 5 and the p-type anode layer 25 and the p-type anode layer 25 exposed at the upper sidewall 8a of the trench 8 are connected. + The diode trench electrode 21a is in contact with the side surface of the type contact layer 24. In addition, the barrier metal 5 is also in contact with the upper surface and side surface of the diode trench electrode 21a. Moreover, the emitter electrode 6 is formed on the barrier metal 5.

[0209] Such a semiconductor device also achieves the same effects as those of the first embodiment.

[0210] (Variation 3 of Implementation 1)

[0211] Figures 34 to 36 It is a diagram showing a method for manufacturing a semiconductor device in Modification 3 of Embodiment 1.

[0212] Figure 34 The step of forming the insulating material film 4a is shown. The step of forming the insulating material film 4a is the same as that of the first embodiment.

[0213] Figure 35 1 shows the process of forming the contact hole. In more detail, Figure 35 The process of forming the interlayer insulating film 4 and exposing the upper sidewall 8a of the trench 8 in the diode region 20 is shown. After masking the insulating material film 4a, the insulating material film 4a and the oxide film 9 are etched. The contact hole is formed in n + Type source layer 13, p + Type contact layer 14, p + The positions of the type contact layer 24, the dummy trench gate 12 and the diode trench gate 21. Through this process, n + Type source layer 13, p +Type contact layer 14, p + The type contact layer 24, the dummy trench electrode 12a and the diode trench electrode 21a are exposed. An interlayer insulating film 4 is formed on the region covered by the mask, that is, on the active trench gate 11 of the IGBT region 10.

[0214] When etching the insulating material film 4a, the upper portion of the diode trench insulating film 21b and the upper portion of the dummy trench insulating film 12b not covered by the mask are also etched. As a result, a gap is formed not only between the upper sidewall 8a of the trench 8 and the diode trench electrode 21a, but also between the upper sidewall 8a and the dummy trench electrode 12a.

[0215] Figure 36 FIG4 shows the process of forming the barrier metal 5 and the emitter electrode 6. The barrier metal 5 is formed on the first main surface of the semiconductor substrate and the interlayer insulating film 4. The barrier metal 5 is deposited not only in the gap between the upper sidewall 8a of the trench 8 and the diode trench electrode 21a, but also in the gap between the upper sidewall 8a and the dummy trench electrode 12a. The barrier metal 5 is in contact with the p-type anode layer 25 and the p-type anode layer 25 exposed at the upper sidewall 8a of the trench 8. + The diode trench electrode 21a is in contact with the side surface of the type contact layer 24. In addition, the barrier metal 5 is also in contact with the upper surface and side surface of the diode trench electrode 21a. Moreover, the emitter electrode 6 is formed on the barrier metal 5.

[0216] Such a semiconductor device also achieves the same effects as those of the first embodiment.

[0217] <Implementation Method 2>

[0218] A semiconductor device and a method for manufacturing the semiconductor device in Embodiment 2 will be described. Embodiment 2 is a subordinate concept of Embodiment 1. In Embodiment 2, the same components as those in Embodiment 1 are denoted by the same reference numerals, and detailed description thereof will be omitted.

[0219] Figure 37 It is a partially enlarged plan view showing the structure of the diode region 20 of the semiconductor device in the second embodiment. Figure 37 Enlarged view Figure 1 The semiconductor device 100 shown, or Figure 2 Region 83 in semiconductor device 101 is shown.

[0220] p + The p-type contact layer 24 is selectively provided on the upper surface side of the p-type anode layer 25 as in the first embodiment. However, when viewed from above, the p-type contact layer 24 is provided. + A plurality of contact regions of the p-type contact layer 24 are surrounded by the p-type anode layer 25 .

[0221] Figure 38This is a cross-sectional view showing the structure of the diode region 20 of the semiconductor device in the second embodiment. Figure 38 Show Figure 37 The cross section at line segment CA-CA is shown.

[0222] The diode trench gate 21 is arranged between the plurality of contact regions in a plan view. The upper sidewall 8a of the trench 8 is arranged so as not to + That is, the trench 8 is provided so as to penetrate the p-type anode layer 25 on the first main surface of the semiconductor substrate. + The p-type contact layer 24 is not exposed at the upper side wall 8 a , and only the p-type anode layer 25 is exposed at the upper side wall 8 a .

[0223] The impurity concentration of the p-type anode layer 25 is higher than that of the p-type anode layer 25. + The p-type contact layer 24 is not in contact with the barrier metal 5 (or emitter electrode 6) at the upper sidewall 8a of the trench 8. + The amount of holes injected into the contact layer 24 is reduced. As a result, the recovery current (Irr) and the recovery loss (Err) are reduced.

[0224] <Implementation Method 3>

[0225] A semiconductor device and a method for manufacturing the semiconductor device in Embodiment 3 will be described. Embodiment 3 is a subordinate concept of Embodiment 1. In Embodiment 3, the same components as those in Embodiment 1 or 2 are denoted by the same reference numerals, and detailed description thereof will be omitted.

[0226] Figure 39 1 is a cross-sectional view showing the structure of the diode region 20 of the semiconductor device in the third embodiment. Figure 39 Show Figure 6 The cross section is shown at line CC.

[0227] The upper sidewall 8a of the trench 8 has an inclination that widens toward the outside of the trench 8. In other words, the mesa portion sandwiched between two adjacent diode trench gates 21 has an inclined surface. The inclined surface of the mesa portion is formed by etching the trench 8.

[0228] The barrier metal 5 also covers the inclined surface. Since the upper sidewall 8a is inclined, the barrier metal 5 is easily deposited on the upper sidewall 8a. The same is true when the emitter electrode 6 is formed directly on the upper sidewall 8a instead of the barrier metal 5.

[0229] Such a structure can also achieve the same effect as that of the first embodiment.

[0230] <Implementation Method 4>

[0231] A semiconductor device and a method for manufacturing the semiconductor device in Embodiment 4 will be described. Embodiment 4 is a subordinate concept of Embodiment 1. In Embodiment 4, the same components as those in Embodiments 1 to 3 are denoted by the same reference numerals, and detailed description thereof will be omitted.

[0232] Figure 40 1 is a cross-sectional view showing the structure of the diode region 20 of the semiconductor device in the fourth embodiment. Figure 40 Show Figure 6 The cross section is shown at line CC.

[0233] In the diode region 20, the barrier metal 5 is provided on the p + type contact layer 24 and the upper surface of the diode trench electrode 21a.

[0234] The emitter electrode 6 is provided above the barrier metal 5 and in the gap between the upper sidewall 8a of the trench 8 and the side surface of the diode trench electrode 21a. Specifically, the p-type anode layer 25 exposed at the upper sidewall 8a is in direct ohmic contact with the emitter electrode 6. Furthermore, the emitter electrode 6 is also in contact with the side surface of the diode trench electrode 21a. In other words, the barrier metal 5 is not provided in the gap between the upper sidewall 8a of the trench 8 and the side surface of the diode trench electrode 21a.

[0235] When the emitter electrode 6 is formed of an aluminum alloy such as AlSi, and the barrier metal 5 is formed of a metal containing titanium, the contact resistance between the emitter electrode 6 and the p-type anode layer 25 is smaller than the contact resistance between the barrier metal 5 and the p-type anode layer 25. In other words, good ohmic contact is achieved between the emitter electrode 6 and the p-type anode layer 25.

[0236] In such a structure, in addition to the effects of the first embodiment, the contact resistance at the upper side wall 8 a of the trench 8 is reduced.

[0237] Furthermore, the present invention can freely combine the various embodiments, and can appropriately modify or omit the various embodiments.

[0238] Description of the label

[0239] 1n - drift layer, 2n-type carrier accumulation layer, 3n-type buffer layer, 4 interlayer insulating film, 4a insulating material film, 5 barrier metal, 6 emitter electrode, 6a terminal electrode, 7 collector electrode, 8 trench, 8a upper sidewall, 8b lower sidewall, 8c bottom, 9 oxide film, 10 IGBT region, 11 active trench gate, 11a gate trench electrode, 11b gate trench insulating film, 12 dummy trench gate, 12a dummy trench electrode, 12b dummy trench insulating film, 13n + Type source layer, 14p +type contact layer, 15p type base layer, 16p type collector layer, 16a p type end collector layer, 20 diode region, 21 diode trench gate, 21a diode trench electrode, 21b diode trench insulating film, 21c upper end, 24p + Type contact layer, 25p type anode layer, 26n + type cathode layer, 30 terminal region, 31p type terminal well layer, 32n + type channel stop layer, 33 semi-insulating film, 34 terminal protection film, 40 pad area, 41 control pad, 41a current sensing pad, 41b Kelvin emitter pad, 41c gate pad, 41d temperature sensing diode pad, 41e temperature sensing diode pad, 100 semiconductor device, 101 semiconductor device.

Claims

1. A semiconductor device comprising: semiconductor substrates; a first semiconductor layer of a first conductivity type provided as a surface layer on the upper surface side of the semiconductor substrate; a second semiconductor layer of a second conductivity type, disposed below the first semiconductor layer; a diode trench gate, comprising a diode trench insulating film and a diode trench electrode, wherein the diode trench insulating film is formed on an inner wall of a trench penetrating from the upper surface of the semiconductor substrate through the first semiconductor layer to the second semiconductor layer, and the diode trench electrode is provided inside the trench; as well as an electrode layer covering the surface layer of the semiconductor substrate, The diode trench insulating film is formed along the lower sidewall and the bottom of the inner wall of the trench, which is located below the upper sidewall. The upper sidewall is located on the upper end side of the trench. The electrode layer further covers the upper sidewall of the trench, The first semiconductor layer is in contact with the electrode layer at the upper sidewall of the trench.

2. The semiconductor device according to claim 1, wherein An upper end of the diode trench insulating film corresponding to a lower end of the upper sidewall of the trench is located above the second semiconductor layer.

3. The semiconductor device according to claim 2, wherein A depth from the upper surface of the semiconductor substrate to the upper end of the diode trench insulating film is greater than or equal to 0.5 μm.

4. The semiconductor device according to claim 2 or 3, wherein further comprising a first conductive type contact layer provided on the surface side of the first semiconductor layer as the surface layer on the upper surface side of the semiconductor substrate, The trench of the diode trench gate penetrates the contact layer. The upper end of the diode trench insulating film is located below the contact layer.

5. The semiconductor device according to any one of claims 1 to 3, wherein further comprising a first conductive type contact layer, the first conductive type contact layer being selectively provided on the surface side of the first semiconductor layer as the surface layer on the upper surface side of the semiconductor substrate, The plurality of contact regions provided with the contact layer are surrounded by the first semiconductor layer in a plan view. The diode trench gate is arranged between the plurality of contact regions such that the upper sidewall of the trench penetrates the first semiconductor layer located around the plurality of contact regions in a plan view.

6. The semiconductor device according to any one of claims 1 to 3, wherein The upper sidewall of the trench has an inclination that expands toward an outer side of the trench.

7. The semiconductor device according to any one of claims 1 to 3, wherein The electrode layer is formed of an aluminum alloy.

8. The semiconductor device according to any one of claims 1 to 3, further comprising: a diode region disposed in the semiconductor substrate and forming a diode; and A transistor region is provided in the semiconductor substrate adjacent to the diode region and forms an insulated gate bipolar transistor. The diode includes the first semiconductor layer, the second semiconductor layer, and the diode trench gate. The diode and the insulated gate bipolar transistor form a reverse conducting IGBT, namely, an RC-IGBT.

9. A method for manufacturing a semiconductor device, comprising: a step of preparing a semiconductor substrate including a first semiconductor layer of a first conductivity type provided as a surface layer on an upper surface side and a second semiconductor layer of a second conductivity type provided below the first semiconductor layer; forming a diode trench gate, the diode trench gate comprising a diode trench insulating film and a diode trench electrode, the diode trench insulating film being formed on an inner wall of a trench penetrating the first semiconductor layer from the upper surface of the semiconductor substrate to the second semiconductor layer, and the diode trench electrode being provided inside the trench; as well as forming an electrode layer covering the surface layer of the semiconductor substrate; The diode trench insulating film is formed along the lower sidewall and the bottom of the inner wall of the trench, which is located below the upper sidewall. The upper sidewall is located on the upper end side of the trench. The electrode layer further covers the upper sidewall of the trench, The first semiconductor layer is in contact with the electrode layer at the upper sidewall of the trench.

10. The method for manufacturing a semiconductor device according to claim 9, wherein: The process of forming the diode trench gate includes: forming an insulating film on the inner wall of the trench; forming the diode trench electrode inside the trench via the insulating film; and After forming the diode trench electrode, the insulating film is etched from the upper surface side of the semiconductor substrate to expose the upper sidewall of the trench.

11. The method for manufacturing a semiconductor device according to claim 10, wherein: The step of forming the electrode layer includes the step of depositing a material for the electrode layer in a gap between the upper sidewall of the trench formed by etching the insulating film and the diode trench electrode.

12. The method for manufacturing a semiconductor device according to claim 10 or 11, wherein: The electrode layer is formed by a CVD method.

13. The method for manufacturing a semiconductor device according to claim 10 or 11, wherein: In the step of forming the diode trench insulating film, a selectivity ratio between an etching rate of the insulating film and an etching rate of the first semiconductor layer is greater than or equal to 11.

0.

14. The method for manufacturing a semiconductor device according to claim 10 or 11, wherein: The insulating film is formed by dry etching, The dry etching is performed in a gas environment containing fluorocarbons.

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