Semiconductor device

Abstract

Provided is a semiconductor device that has improved damage tolerance during recovery operation. A semiconductor device (100) according to the present invention has an insulated-gate bipolar transistor region (1) and a diode region (2) arranged side by side in a first direction along a first main surface of a semiconductor substrate, and includes: a base layer (9) of a second conductivity type, provided on a surface layer on the first main surface side of the semiconductor substrate; an emitter layer (8) of a first conductivity type, selectively provided on a surface layer on the first main surface side of the base layer (9), having a higher impurity concentration than a drift layer; a plurality of gate electrodes (7a) arranged side by side in the first direction, facing the emitter layer, the base layer, and the drift layer with a gate insulating film (6a) interposed therebetween; an anti-doping layer (10) provided on a surface layer of the base layer, having a higher impurity concentration of the second conductivity type than the base layer and a higher impurity concentration of the first conductivity type than the drift layer; and a collector layer of the second conductivity type provided on a surface layer on the second main surface side of the semiconductor substrate.

Description

TECHNICAL FIELD

[0001] The present application relates to a semiconductor device. BACKGROUND

[0002] From the viewpoint of energy saving, inverter devices are widely used in the fields of home electric appliances, electric vehicles, railways, etc. The inverter devices are mostly configured using an Insulated Gate Bipolar Transistor (IGBT) and a diode for freewheeling. The IGBT and the diode are connected by wiring such as a wire inside the inverter device.

[0003] Insulated Gate Bipolar Transistor) and a diode for freewheeling. The IGBT and the diode are connected by wiring such as a wire inside the inverter device.

[0004] In order to miniaturize the inverter device, a semiconductor device in which the IGBT and the diode are formed on one semiconductor substrate is proposed (for example, Patent Document 1).

[0005] Patent Document 1: Japanese Patent Application Publication No. 2008-103590

[0006] However, in the semiconductor device in which the IGBT and the diode are formed on one semiconductor substrate as described above, since minority carriers, i.e., holes, flow from the IGBT region to the diode region, the recovery current at the time of recovery operation becomes large, and the breakdown resistance of the diode decreases, as compared with the case where the IGBT and the diode as separate components are connected in parallel and used. A semiconductor device having a diode region with high breakdown resistance at the time of recovery operation is sought. SUMMARY

[0007] The present application is proposed in order to solve the above-described problems, and has an object to provide a semiconductor device with improved breakdown resistance at the time of recovery operation.

[0008] The semiconductor device according to the present application includes a semiconductor substrate having a drift layer of a first conductivity type between a first main surface and a second main surface opposite to the first main surface; a diode region having an anode layer of a second conductivity type disposed at a surface layer on the first main surface side of the semiconductor substrate and a cathode layer of the first conductivity type disposed at a surface layer on the second main surface side of the semiconductor substrate; and an insulated gate bipolar transistor region disposed in parallel with the diode region in a first direction along the first main surface of the semiconductor substrate, the insulated gate bipolar transistor region having a base layer of the second conductivity type disposed at a surface layer on the first main surface side of the semiconductor substrate; an emitter layer of the first conductivity type selectively disposed at a surface layer on the first main surface side of the base layer, the impurity concentration of which is higher than that of the drift layer; a gate electrode disposed in parallel with a plurality of gate insulating films facing the emitter layer, the base layer and the drift layer in the first direction; a counter-doped layer disposed at a surface layer of the base layer, the impurity concentration of which is higher than that of the base layer and the impurity concentration of the first conductivity type is higher than that of the drift layer; and a collector layer of the second conductivity type disposed at a surface layer on the second main surface side of the semiconductor substrate.

[0009] Effects of the Invention

[0010] According to the present application, by disposing the counter-doped layer in the insulated gate bipolar transistor region, the inflow of holes to the diode region can be suppressed, and the breakdown resistance at the time of recovery operation can be improved. BRIEF DESCRIPTION OF DRAWINGS

[0011] Figure 1 is a plan view showing a semiconductor device according to Embodiment 1.

[0012] Figure 2 is a plan view showing a semiconductor device according to Embodiment 1.

[0013] Figure 3 is a sectional view showing a semiconductor device according to Embodiment 1.

[0014] Figure 4 is a sectional view showing a semiconductor device according to Embodiment 1.

[0015] Figure 5 is a sectional view showing a semiconductor device according to Embodiment 1.

[0016] Figure 6 is a flowchart showing a manufacturing process of a semiconductor device according to Embodiment 1.

[0017] Figure 7 is a flowchart showing a manufacturing process of a semiconductor device according to Embodiment 1.

[0018] Figure 8 is a flowchart showing a manufacturing process of a semiconductor device according to Embodiment 1.

[0019] Figure 9 is a view showing a manufacturing process of the semiconductor device according to Embodiment 1.

[0020] Figure 10 is a view showing a manufacturing process of the semiconductor device according to Embodiment 1.

[0021] Figure 11 is a view schematically showing a hole action at the time of diode action of the semiconductor device according to Embodiment 1.

[0022] Figure 12 is a view schematically showing a hole action at the time of recovery action of the semiconductor device according to Embodiment 1.

[0023] Figure 13 is a plan view of the semiconductor device according to Embodiment 2.

[0024] Figure 14 is a plan view of the semiconductor device according to Embodiment 2.

[0025] Figure 15 is a plan view of the semiconductor device according to Embodiment 3.

[0026] Figure 16 is a plan view of the semiconductor device according to Embodiment 3.

[0027] Figure 17 is a plan view of the semiconductor device according to Embodiment 4.

[0028] Figure 18 is a plan view of the semiconductor device according to Embodiment 4. DETAILED DESCRIPTION

[0029] Hereinafter, the embodiments will be described with reference to the drawings. Since the drawings are merely schematic, the mutual relationship of the dimensions and the positions can be changed. In the following description, the same or corresponding structural elements are denoted by the same reference numerals, and the repeated description will be omitted.

[0030] In the following description, terms such as "upper", "lower", "side", and the like indicating specific positions and directions are sometimes used, but these terms are used for the sake of convenience in order to easily understand the contents of the embodiments, and do not limit the positions and directions at the time of implementation.

[0031] The first conductive type is set to n-type and the second conductive type is set to p-type, but they can be reversed, and the first conductive type can be set to p-type and the second conductive type can be set to n-type. +The meaning of p-type is that the concentration of acceptors is higher than that of p - The meaning of p-type is that the concentration of acceptors is lower than that of p + The meaning of p-type is that the concentration of acceptors is higher than that of p - The meaning of p-type is that the concentration of acceptors is lower than that of p

[0032] <Embodiment 1>

[0033] Use Figures 1 to 5 The structure of the semiconductor device according to Embodiment 1 will be described. Figure 1 and Figure 2 is a plan view of the semiconductor device according to Embodiment 1. Figure 2 is a plan view of the semiconductor device according to Embodiment 1. Figure 1 is a plan view of the semiconductor substrate on the side of the first main surface. In Figure 2 the description of the electrodes and the like provided on the upper side than the first main surface of the semiconductor substrate is omitted. Figures 3 to 5 is a sectional view of the semiconductor device according to Embodiment 1. Figure 3 is Figure 2 a sectional view at the B-B line described in Figure 4 is Figure 2 a sectional view at the C-C line described in Figure 5 is Figure 2 a sectional view at the D-D line described in Figures 1 to 5 In

[0034] As shown in Figure 1 , the semiconductor device 100 has an insulated gate bipolar transistor region 1 in which an insulated gate bipolar transistor is formed and a diode region 2 in which a diode is formed provided adjacently in one semiconductor substrate. The insulated gate bipolar transistor region 1 and the diode region 2 are strip-shaped regions whose length direction is the Y direction of the semiconductor device 100, and the insulated gate bipolar transistor region 1 and the diode region 2 are provided in parallel in the X direction of the semiconductor device 100. The insulated gate bipolar transistor region 1 and the diode region 2 are active regions of the semiconductor device 100, and the insulated gate bipolar transistor region 1 and the diode region 2 are disposed in the center of the semiconductor device 100 when viewed in plan.

[0035] A gate signal receiving region 3 is provided in the semiconductor device 100. The gate signal receiving region 3 is a region for receiving electrical signals from the outside. The insulated-gate bipolar transistor (IGBT) region 1 switches between an on-state and an off-state in response to the electrical signals received through the gate signal receiving region 3. The gate signal receiving region 3 is disposed near the IGBT region 1. By distributing the gate signal receiving region 3 near the IGBT region 1, noise interference into the electrical signal can be suppressed, preventing malfunction of the IGBT region 1. Wiring for receiving electrical signals from the outside is connected to the gate signal receiving region 3. Wiring can be, for example, wires, leads, etc.

[0036] exist Figure 1 In this design, the gate signal receiving region 3 is rectangular, arranged with its three sides adjacent to the insulated-gate bipolar transistor region 1 and the diode region 2. However, the arrangement of the gate signal receiving region 3 is not limited to this. The gate signal receiving region 3 can be located near the active region, i.e., near the insulated-gate bipolar transistor region 1 and the diode region 2. Alternatively, it can be located in the center of the active region with all four sides adjacent to the insulated-gate bipolar transistor region 1 and the diode region 2, or it can be located at the corner of the active region with only two of its four sides adjacent to the insulated-gate bipolar transistor region 1 and the diode region 2. Furthermore, the arrangement of the gate signal receiving region 3 is not limited to these specific arrangements; it can be located within the area surrounded by the end region 4 of the active region when viewed from above. The shape of the gate signal receiving region 3 also does not have to be rectangular.

[0037] When viewed from above, the end region 4 is configured to surround the insulated gate bipolar transistor region 1, the diode region 2, and the gate signal receiving region 3. In order to maintain the withstand voltage of the semiconductor device 100, the end region 4 is provided with withstand voltage maintenance structures such as FLR (Field Limiting Ring) and RESURF (Reduced SURface Field).

[0038] like Figure 2As shown, a plurality of trenches 5a are provided on the surface side of the insulated-gate bipolar transistor region 1, one trench 5c is provided on the boundary between the insulated-gate bipolar transistor region 1 and the diode region 2, and a plurality of trenches 5b are provided on the surface side of the diode region 2. The trenches 5a, 5b, 5c are grooves formed on the first main surface side of the semiconductor substrate by an etching technique or the like. The trenches 5a, 5b, 5c are arranged in parallel in the first direction, that is, the X direction, and the length direction is the second direction, that is, the Y direction, which is orthogonal to the first direction. A gate insulating film 6a is provided on the side wall of the trench 5a. A gate insulating film 6b is provided on the side wall of the trench 5b and the trench 5c. An electrically conductive gate electrode 7a is provided at the inner side of the gate insulating film 6a in the trench 5a, and an electrically conductive gate electrode 7b is provided at the inner side of the gate insulating film 6b in the trench 5b and the trench 5c. The length direction of the gate electrode 7a and the gate electrode 7b is the Y direction, and a plurality of the gate electrode 7a and the gate electrode 7b are arranged in parallel in the X direction.

[0039] The surface layer of the semiconductor substrate between adjacent trenches 5a at the insulated-gate bipolar transistor region 1 and the surface layer of the semiconductor substrate between the adjacent trench 5a and the trench 5c have an n-type emitter layer 8 having a higher donor concentration than the donor concentration of the drift layer (not shown in the drawing) in the insulated-gate bipolar transistor region 1, a p-type base layer 9 having an acceptor, a p-type base contact layer 16 having a higher acceptor concentration than the acceptor concentration of the base layer 9, and a counter-doped layer 10 having a higher donor concentration than the drift layer and a higher acceptor concentration than the base layer 9. Figure 2 The surface layer of the semiconductor substrate between adjacent trenches 5a at the insulated-gate bipolar transistor region 1 and the surface layer of the semiconductor substrate between the adjacent trench 5a and the trench 5c have an n-type emitter layer 8 having a higher donor concentration than the donor concentration of the drift layer (not shown in the drawing) in the insulated-gate bipolar transistor region 1, a p-type base layer 9 having an acceptor, a p-type base contact layer 16 having a higher acceptor concentration than the acceptor concentration of the base layer 9, and a counter-doped layer 10 having a higher donor concentration than the drift layer and a higher acceptor concentration than the base layer 9.

[0040] The emitter layer 8 is in contact with the gate insulating film 6a in the X direction. On the other hand, the counter-doped layer 10 is sandwiched by the base layer 9 in the X direction between adjacent gate electrodes 7a and between the gate electrode 7a and the gate electrode 7b adjacent to each other, and is also sandwiched by the base contact layer 16, and is not in contact with the gate insulating film 6a. The length direction of the emitter layer 8 is the X direction, and the width direction is the Y direction. The length direction of the counter-doped layer 10 is the Y direction, and the width direction is the X direction. In addition, the counter-doped layer 10 is arranged in a manner of being sandwiched by the emitter layer 8 in the Y direction.

[0041] Preferably, when viewed from above, the width W2 of the anti-doped layer 10 in the X direction is less than or equal to the width W1 of the emitter layer 8 in the Y direction. By providing the anti-doped layer 10, there is a concern that latch-up may occur directly below the anti-doped layer 10 when the insulated gate bipolar transistor region 1 changes from an on-state to a non-on-state, thus reducing the current interruption capability. However, by setting the widths of the anti-doped layer 10 and the emitter layer 8 in the width direction to satisfy the above relationship, the risk of latch-up directly below the anti-doped layer 10 can be suppressed to below the risk of latch-up directly below the emitter layer 8.

[0042] A p-type anode layer 11 is provided on the surface layer of the semiconductor substrate between adjacent trenches 5c and 5b in diode region 2 and on the surface layer of the semiconductor substrate between adjacent trenches 5b.

[0043] like Figure 3 As shown, an insulated-gate bipolar transistor (IGBT) region 1 and a diode region 2 are disposed on a common semiconductor substrate. The semiconductor substrate is, for example, a substrate made of silicon. The semiconductor substrate has a first main surface S1 on the positive side in the Z direction, and a second main surface S2 opposite to the first main surface S1 on the negative side in the Z direction. The X and Y directions are along the first main surface S1, and the Z direction is orthogonal to the first main surface S1. A drift layer 12 is provided between the first main surface S1 and the second main surface S2. The drift layer 12 is disposed across both the IGBT region 1 and the diode region 2. The drift layer 12 is a semiconductor layer containing, for example, arsenic or phosphorus as a donor, with a donor concentration of 1.0E+12 / cm³. 3 ~1.0E+16 / cm 3 .

[0044] In an insulated-gate bipolar transistor region 1, a base layer 9 is provided on the first main surface S1 side of the semiconductor substrate. An emitter layer 8 is provided on the surface of the base layer 9. The emitter layer 8 is a semiconductor layer having, for example, arsenic or phosphorus as a donor, with a donor concentration of 1.0E+17 / cm³. 3 ~1.0E+20 / cm 3 The base layer 9 is a semiconductor layer having, for example, boron or aluminum as an acceptor, with an acceptor concentration of 1.0E+15 / cm³. 3 ~1.0E+18 / cm 3 .

[0045] On the side of the first main surface S1 of the IGBT region 1, the trench 5a is provided so as to reach the drift layer 12 by penetrating the emitter layer 8 and the base layer 9. The gate electrode 7a faces the emitter layer 8, the base layer 9, and the drift layer 12 with the gate insulating film 6a interposed therebetween. The first electrode 18 is provided on the Z-direction positive side of the gate electrode 7a with the interlayer insulating film 17 interposed therebetween. The gate electrode 7a is electrically insulated from the first electrode 18 by the interlayer insulating film 17. The gate electrode 7a is electrically connected to the gate signal receiving region 3 shown in FIG. 1, receives an electric signal via the gate signal receiving region 3, and controls the rise and fall of the voltage by the electric signal. The gate electrode 7a is an electrode also called a so-called active gate electrode, and the like. Figure 1

[0046] In a case where a positive voltage is applied to the gate electrode 7a, an n-type channel (not shown) is formed at a position of the base layer 9 in contact with the gate insulating film 6a. Since the emitter layer 8 is in contact with the gate insulating film 6a, the emitter layer 8 and the drift layer 12 are connected by the n-type channel, and the IGBT region 1 is switched to an energized state. In a case where no positive voltage is applied to the gate electrode 7a, since no n-type channel is formed in the base layer 9, the IGBT region 1 is switched to a non-energized state. As for the electrical connection of the gate electrode 7a and the gate signal receiving region 3, in other cross sections, for example, a wiring (not shown) of aluminum or the like is provided on the side of the first main surface S1 to make the connection.

[0047] The first electrode 18 is composed of, for example, aluminum or an aluminum alloy. The first electrode 18 is provided on the Z-direction positive side of the emitter layer 8 and is electrically connected to the emitter layer 8. Aluminum and an aluminum alloy are metals in which the contact resistance with a p-type semiconductor layer is low and the contact resistance with an n-type semiconductor layer is high. Therefore, in a case where the first electrode 18 is composed of aluminum or an aluminum alloy, the first electrode 18 can not be directly connected to the n-type emitter layer 8, but titanium, in which the contact resistance with an n-type semiconductor layer is low, can be brought into contact with the emitter layer 8, and the emitter layer 8 and the first electrode 18 can be electrically connected via the titanium.

[0048] The IGBT region 1 is provided with a p-type collector layer 13 having a higher concentration of acceptors than the base layer 9 on the side of the second main surface S2 of the semiconductor substrate. The collector layer 13 is a semiconductor layer having, for example, boron or aluminum as an acceptor, and the concentration of acceptors is 1.0E+16 / cm 3 ~ 1.0E+20 / cm 3 The second electrode 19 is provided on the Z-direction negative side of the collector layer 13, and the collector layer 13 and the second electrode 19 are electrically connected.

[0049] ​Diode region 2 has an anode layer 11 disposed on the first main surface S1 side of the semiconductor substrate. The anode layer 11 is a semiconductor layer having, for example, boron or aluminum as an acceptor, and the acceptor concentration is 1.0E+15 / cm³. 3 ~1.0E+18 / cm 3 .

[0050] A trench 5b is provided on the first main surface S1 side of diode region 2. The trench 5b is provided in such a way that it penetrates the anode layer 11 and reaches the drift layer 12. The gate electrode 7b faces the anode layer 11 and the drift layer 12 through the gate insulating film 6b. A first electrode 18 is provided on the positive side of the gate electrode 7b in the Z direction. The gate electrode 7b and the first electrode 18 are electrically connected. Unlike the gate electrode 7a, the voltage of the gate electrode 7b does not rise or fall according to the gate signal receiving region 3. The first electrode 18 is provided on the positive side of the anode layer 11 in the Z direction and is electrically connected to the anode layer 11. The gate electrode 7b is an electrode that is also called a so-called dumb gate electrode, etc.

[0051] In diode region 2, an n-type cathode layer 15 is disposed on the second main surface S2 side of the semiconductor substrate, wherein the donor concentration is higher than that of the drift layer 12. The cathode layer 15 is a semiconductor layer having, for example, arsenic or phosphorus as a donor, and the donor concentration is 1.0E+16 / cm³. 3 ~1.0E+20 / cm 3 A second electrode 19 is disposed on the negative side of the cathode layer 15 in the Z direction. The second electrode 19 is electrically connected to the cathode layer 15.

[0052] A trench 5c is provided on the first main surface S1 side of the boundary between the insulated gate bipolar transistor region 1 and the diode region 2. The trench 5c is provided in such a way that it penetrates the emitter layer 8, the anode layer 11, and the base layer 9 to reach the drift layer 12. The gate electrode 7b faces the emitter layer 8, the base layer 9, and the drift layer 12 through the gate insulating film 6b. A first electrode 18 is provided on the positive side of the gate electrode 7b in the Z direction, and the gate electrode 7b and the first electrode 18 are electrically connected.

[0053] like Figure 4 As shown, in region 1 of the insulated gate bipolar transistor, an anti-doped layer 10 and a base contact layer 16 are disposed on the surface of the base layer 9. The anti-doped layer 10 is a semiconductor layer having, for example, arsenic or phosphorus as a donor, with a donor concentration of 1.0E+17 / cm³. 3 ~1.0E+20 / cm 3 Furthermore, the anti-doped layer 10 is a semiconductor layer having, for example, boron or aluminum as an acceptor, with an acceptor concentration of 1.0E+15 / cm³. 3 ~1.0E+20 / cm 3The base contact layer 16 is a semiconductor layer having, for example, boron or aluminum as an acceptor, with an acceptor concentration of 1.0E+15 / cm³. 3 ~1.0E+20 / cm 3 .

[0054] The anti-doped layer 10 is arranged in the X direction between adjacent gate electrodes 7a and between adjacent gate electrodes 7a and gate electrodes 7b, sandwiched by the base layer 9, and does not contact the gate insulating film 6a. Therefore, even when a positive voltage is applied to the gate electrode 7a, the anti-doped layer 10 and the drift layer 12 are not connected through an n-type channel. That is, the anti-doped layer 10 is a semiconductor layer that does not participate in the switching between the on-state and off-state of the insulated-gate bipolar transistor region 1.

[0055] like Figure 5 As shown, in the region 1 of the insulated gate bipolar transistor, the emitter layer 8, the anti-doped layer 10, and the base contact layer 16 are each selectively disposed on the surface of the base layer 9.

[0056] Next, the method for manufacturing the semiconductor device according to Embodiment 1 will be described. Figure 6 This is a manufacturing flow chart of the semiconductor device according to Embodiment 1. The manufacturing method will be described in the order of the manufacturing flow chart. In the following description of the manufacturing method, the manufacturing method of the active region is described, and the manufacturing methods of the terminal region 4 and the gate signal receiving region 3, which are formed by arbitrary structure, are omitted.

[0057] like Figure 6 As shown, the semiconductor device according to Embodiment 1 is manufactured through the following steps: a first main surface semiconductor layer formation step (S100), a gate electrode formation step (S200), a first electrode formation step (S300), a second main surface semiconductor layer formation step (S400), and a second electrode formation step (S500). The first main surface semiconductor layer formation step (S100) is divided into a semiconductor substrate preparation step, a first main surface p-type semiconductor layer formation step, and a first main surface n-type semiconductor layer formation step. The gate electrode formation step (S200) is divided into a trench formation step, a gate electrode deposition step, and an interlayer insulating film deposition step. The second main surface semiconductor layer formation step (S400) is divided into a second main surface p-type semiconductor layer formation step and a second main surface n-type semiconductor layer formation step.

[0058] Figures 7 to 10 This is a diagram illustrating the manufacturing process of the semiconductor device according to Embodiment 1. Figures 7 to 10 It means Figure 2 A diagram of the manufacturing process in the cross-section at the CC line.

[0059] Figure 7is a view showing a manufacturing process of the step of forming the semiconductor layer on the first main surface side. Figure 7 (a) is a view showing a state after the semiconductor substrate preparation step is completed. The semiconductor substrate preparation step is a step of preparing a donor of a low-concentration n-type semiconductor substrate. Since the donor concentration of the drift layer 12 becomes the donor concentration of the semiconductor substrate itself, the semiconductor substrate is prepared to match the donor concentration of the drift layer 12. At the time when the semiconductor substrate preparation step is completed, the insulated-gate bipolar transistor region 1 and the diode region 2 have only the drift layer 12.

[0060] Figure 7 (b) is a view showing a manufacturing process of the step of forming the p-type semiconductor layer on the first main surface side. The step of forming the p-type semiconductor layer on the first main surface side is a step of forming the base layer 9, the base contact layer 16, and the anode layer 11. The base layer 9 is formed by implanting an acceptor Al from the first main surface S1 side to the insulated-gate bipolar transistor region 1. The base contact layer 16 is formed by implanting an acceptor A3 from the first main surface S1 side to the insulated-gate bipolar transistor region 1. The anode layer 11 is formed by implanting an acceptor A2 from the first main surface S1 side to the diode region 2. The acceptors Al, A2, and A3 use, for example, boron or aluminum, or the like. The acceptors Al, A2, and A3 can be the same, and in the case where the acceptors Al, A2, and A3 are the same, switching of the acceptors is not needed.

[0061] In the case where the acceptors Al and A2 are the same and the acceptors Al and A2 are set to the same implantation amount, the acceptors Al and A2 can be simultaneously implanted. The acceptor A3 is selectively implanted. In order to selectively implant, the acceptor A3 can be implanted in a state where a mask that hinders implantation is arranged at a site where implantation is not intended. The mask can use, for example, a resist mask. In the case where the acceptors Al and A2 are separately implanted, similarly, implantation can be selectively performed using a mask. The implanted acceptors Al, A2, and A3 are diffused by heating, and the base layer 9, the anode layer 11, and the base contact layer 16 are formed.

[0062] Figure 7 (c) is a view showing a manufacturing process of the step of forming the n-type semiconductor layer on the first main surface side. The step of forming the n-type semiconductor layer on the first main surface side is a step of forming the counter-doped layer 10. The counter-doped layer 10 is formed by implanting a donor Dl from the first main surface S1 side to the base contact layer 16 of the insulated-gate bipolar transistor region 1. As the donor Dl, arsenic or phosphorus, or the like is used.

[0063] The counter-doped layer 10 is formed by selectively implanting the donor Dl into the base contact layer 16. That is, the base contact layer 16 and the counter-doped layer 10 have the same acceptor, and the region of the base contact layer 16 into which the donor Dl is implanted becomes the counter-doped layer 10, and the region of the base contact layer 16 into which the donor Dl is not implanted becomes the base contact layer 16.

[0064] In order to selectively form the counter-doped layer 10, implantation of the donor Dl is selectively performed using the first main surface side donor implantation mask Ml. The first main surface side donor implantation mask Ml is, for example, a resist mask formed by applying resist on the first main surface S l and preventing the passage of the donor. The first main surface side donor implantation mask Ml is provided at a position where the donor Dl is not implanted, and is removed after implantation of the donor Dl.

[0065] The implanted donor Dl diffuses by heating to form the counter-doped layer 10. The base layer 9, the anode layer 11, the base contact layer 16, and the counter-doped layer 10 are formed by implanting the donor Dl after diffusing the acceptor Al, the acceptor A2, and the acceptor A3, and diffusing the donor Dl after implantation, but the method of forming each semiconductor layer is not limited thereto. For example, the acceptor Al, the acceptor A2, and the acceptor A3 can be implanted after implantation of the donor Dl, and the donor Dl can be implanted after implantation of the acceptor Al and the acceptor A2, and the acceptor A3 can be implanted simultaneously with heating to diffuse. The heating after implantation can be performed separately after each implantation, or can be performed simultaneously after implantation of a plurality of acceptors and donors.

[0066] In the first main surface side semiconductor layer forming step, the emitter layer 8 shown in FIG. 6 is formed in a cross section different from the cross section of the semiconductor layer. Figure 7 The emitter layer 8 shown in FIG. 6 is formed in a cross section different from the cross section of the semiconductor layer. Figure 5 The emitter layer 8 is formed by selectively implanting a donor into the base layer 9, like the counter-doped layer 10. In the case where the donor used for forming the emitter layer 8 and the donor Dl used for forming the counter-doped layer 10 are the same, and the concentration of the donor is the same, the donor of the emitter layer 8 and the donor Dl of the counter-doped layer 10 can be implanted simultaneously using one first main surface side donor implantation mask, and the manufacturing process can be simplified.

[0067] In the case where the emitter layer 8 and the counter-doped layer 10 use different donors, or in the case where the concentration of the donor is desired to be different, the implantation of the donor of the emitter layer 8 and the implantation of the donor Dl of the counter-doped layer 10 are performed separately. In this case, two first main surface side donor implantation masks are formed, and the donor is selectively implanted at a position corresponding to each semiconductor layer.

[0068] Figure 8 is a view showing the manufacturing process of the gate electrode forming step.

[0069] Figure 8 (a) is a diagram showing the manufacturing process of the trench forming step. The trench forming step is a step of forming trenches 5a, 5b, 5c on the first main surface Sl side by etching. In portions where the trenches 5a, 5b, 5c are not to be formed, a trench mask M2 is formed in advance before etching is performed. The trench mask M2 is, for example, a mask formed of an oxide film formed by heating on the first main surface Sl, and is removed after the trenches are formed.

[0070] Figure 8 (b) is a diagram showing the manufacturing process of the gate electrode depositing step. The gate electrode depositing step is a step of depositing a gate electrode 7a in the trench 5a, and depositing gate electrodes 7b in the trenches 5b and 5c. First, an oxide film is formed on the surface of the semiconductor substrate including the side walls of the trenches 5a, 5b, 5c by heating. After the oxide film is formed, the gate electrode 7a and the gate electrodes 7b are deposited from the first main surface Sl side. The gate electrode 7a and the gate electrodes 7b are formed of the same conductive material deposited. The gate electrode 7a and the gate electrodes 7b are, for example, formed of polysilicon deposited. After polysilicon is deposited on the entire surface of the first main surface Sl, the unnecessary polysilicon is removed by etching. The polysilicon remaining inside the trench 5a becomes the gate electrode 7a, and the polysilicon remaining inside the trenches 5b and 5c becomes the gate electrodes 7b. In addition, the unnecessary oxide film is removed, and the oxide film remaining inside the trench 5a becomes the gate insulating film 6a, and the oxide film remaining inside the trenches 5b and 5c becomes the gate insulating films 6b.

[0071] Figure 8 (c) is a diagram showing the state after the interlayer insulating film depositing step is completed. The interlayer insulating film forming step is a step of forming an insulating material, i.e., an interlayer insulating film 17, on the gate electrode 7a. The interlayer insulating film 17 is, for example, an oxide film formed by a CVD (Chemical Vapor Deposition) method. The oxide film formed on the first main surface Sl other than the gate electrode 7a is removed, for example, by etching.

[0072] Figure 9 is a diagram showing the state after the first electrode forming step is completed. The first electrode forming step is a step of forming a first electrode 18. The first electrode 18 is, for example, formed by sputtering a metal from the first main surface Sl side. The metal is, for example, aluminum. The first electrode 18 covering the interlayer insulating film 17 and the first main surface Sl is formed by sputtering.

[0073] Figure 10 is a diagram showing the manufacturing process of the second main surface side semiconductor layer forming step.

[0074] Figure 10(a) is a view showing a manufacturing process of a step of forming a p-type semiconductor layer on the second main surface side. The step of forming a p-type semiconductor layer on the second main surface side is a step of forming the collector layer 13. The collector layer 13 is formed by implanting an acceptor A4 from the second main surface S2 side. As the acceptor A4, boron or aluminum, or the like is used, for example. The acceptor A4 of the collector layer 13 can be made the same as one or more of the acceptor Al of the base layer 9, the acceptor A2 of the anode layer 11, and the acceptor A3 of the base contact layer 16. In the case where the acceptors are made the same, the switching work of the acceptors can be reduced. A second main surface side acceptor implantation mask M3 can be used on the second main surface S2 of the diode region 2 where the acceptor A4 is not implanted. The second main surface side acceptor implantation mask M3 is formed by applying a resist on the second main surface S2, for example, and is removed after the acceptor A4 is implanted. The implanted acceptor A4 is diffused by heating, and the collector layer 13 is formed.

[0075] Figure 10 (b) is a view showing a manufacturing process of a step of forming an n-type semiconductor layer on the second main surface side. The step of forming an n-type semiconductor layer on the second main surface side is a step of forming the cathode layer 15. The cathode layer 15 is formed by implanting a donor D2 from the second main surface S2 side. As the donor D2, arsenic or phosphorus, or the like is used, for example. The donor D2 of the cathode layer 15 can be made the same as one or both of the donor of the emitter layer 8 and the donor of the counter-doped layer 10. In the case where the donors are made the same, the switching work of the donors can be reduced.

[0076] A second main surface side donor implantation mask M4 can be used on the second main surface S2 of the insulated gate bipolar transistor region 1 where the donor D2 is not implanted. The second main surface side donor implantation mask M4 is formed by applying a resist on the second main surface S2, for example, and is removed after the donor D2 is implanted. The implanted donor D2 is diffused by heating, and the cathode layer 15 is formed. The cathode layer 15 is formed after the collector layer 13 is formed, but the order of formation is not limited thereto. For example, the cathode layer 15 can be formed after the collector layer 13 is formed. Alternatively, the acceptor A3 and the donor D2 can be diffused at the same time.

[0077] The second electrode formation step (not shown) is a step of forming the second electrode 19. The second electrode 19 is formed by sputtering a metal from the second main surface S2 side, for example. The metal is aluminum, for example. The second electrode 19 that covers the second main surface S2 is formed by sputtering. Through the above steps, the semiconductor device 100 shown in FIG. 1 is obtained. Figure 1

[0078] The diode operation of the semiconductor device related to Embodiment 1 is described. Figure 11 is a view schematically showing the operation of holes at the time of diode operation of the semiconductor device related to Embodiment 1. Figure 11 is a view schematically showing​Figure 2 is a diagram schematically showing the action of holes at the time of diode action in the sectional view at the C-C line in FIG. 8. At the time of diode action, a positive voltage is applied to the first electrode 18 compared to the second electrode 19. Holes h are injected from the anode layer 11, the base layer 9, and the base contact layer 16, which are p-type semiconductor layers, to the drift layer 12 by the application of the positive voltage, and the injected holes h move toward the cathode layer 15. The diode region 2 near the boundary of the insulated-gate bipolar transistor region 1 flows holes h from the insulated-gate bipolar transistor region 1 in addition to the holes h from the anode layer 11, and thus is in a state in which the density of holes h is higher than the diode region 2 farther from the insulated-gate bipolar transistor region 1. At the time of diode action, a continuous current flows in the direction from the first electrode 18 to the second electrode 19.

[0079] The recovery action of the semiconductor device according to Embodiment 1 is described. Figure 12 is a diagram schematically showing the action of holes at the time of recovery action of the semiconductor device according to Embodiment 1. Figure 12 is a diagram schematically showing Figure 2 is a diagram schematically showing the action of holes at the time of recovery action in the sectional view at the C-C line in FIG. 8. At the time of recovery action, a negative voltage is applied to the first electrode 18 compared to the second electrode 19. The holes h that moved toward the cathode layer 15 at the time of diode action move with the direction of movement changed to the direction toward the anode layer 11. At the time of recovery action, the holes h flow out to the outside of the semiconductor device via the anode layer 11 and the first electrode 18.

[0080] The anode layer 11 of the diode region 2 near the boundary between the insulated-gate bipolar transistor region 1 in which the density of holes h is high at the time of diode action flows more holes h than the anode layer 11 of the diode region 2 farther from the insulated-gate bipolar transistor region 1. In addition, a part of the holes h present in the insulated-gate bipolar transistor region 1 flow out to the outside of the semiconductor device via the base layer 9, the base contact layer 16, and the first electrode 18. At the time of recovery action, a recovery current flows in the direction from the second electrode 19 to the first electrode 18.

[0081] Using Figure 11 The hole injection suppression effect of the semiconductor device according to Embodiment 1 is described.

[0082] The semiconductor device according to Embodiment 1 suppresses the holes h flowing from the insulated-gate bipolar transistor region 1 to the diode region 2. As described above, the hole injection suppression effect is obtained by the provision of the base layer 9 and the base contact layer 16. Figure 11As shown, during diode operation, holes h are injected from the p-type base layer 9 and base contact layer 16 into the drift layer 12 of diode region 2. On the other hand, no holes h are injected from the n-type anti-doped layer 10 into the drift layer 12 of diode region 2. Therefore, by providing the anti-doped layer 10, compared to the case where the anti-doped layer 10 is not provided, the injection of holes h from the insulated-gate bipolar transistor region 1 into diode region 2 during diode operation can be suppressed.

[0083] Therefore, by selectively providing an anti-doped layer 10 on the surface of the base layer 9, the recovery current can be suppressed, thereby increasing the damage tolerance during recovery operation. Furthermore, the concentration of acceptor impurities on the surface of the anti-doped layer 10 is higher than that of the anode layer 9. Consequently, the electrical contact resistance between the first electrode 18 and the anti-doped layer 10 can be lower than that between the first electrode 18 and the anode layer 9.

[0084] Furthermore, regarding the semiconductor device according to Embodiment 1, such as Figure 2 As shown, the width W2 of the anti-doped layer 10 in the X direction is narrower than the width W1 of the emitter layer 8 in the Y direction. By setting the width W2 of the anti-doped layer 10 to such a width, the voltage drop generated at the interface between the anti-doped layer 10 and the base layer 9 can be set to be less than or equal to the voltage drop generated at the interface between the emitter layer 8 and the base layer 9, and the latch-up tolerance at the junction between the anti-doped layer 10 and the base layer 9 can be set to be higher than the latch-up tolerance at the junction between the emitter layer 8 and the base layer 9.

[0085] In Embodiment 1, a structure is shown in which gate electrodes 7a are provided in all trenches 5a. However, if the heat generated per unit area of ​​the insulated gate bipolar transistor region 1 is large when energized, it is not necessary to provide gate electrodes 7a in all trenches 5a of the insulated gate bipolar transistor region 1. Instead, a structure known as the so-called interval rejection structure can be provided, in which gate electrodes 7b electrically connected to the first electrode 18 are provided in a number of trenches in the plurality of trenches provided in the insulated gate bipolar transistor region 1.

[0086] In addition, although a structure is shown in which a gate electrode 7b is configured in a trench 5c located at the boundary between the insulated gate bipolar transistor region 1 and the diode region 2, it is also possible to configure a structure in which a gate electrode 7a is electrically connected to the gate signal receiving region 3 in the trench 5c.

[0087] <Implementation Method 2>

[0088] use Figure 13 and Figure 14 The structure of the semiconductor device according to Embodiment 2 will be described. Figure 13 and Figure 14is a plan view showing the semiconductor device according to Embodiment 2. Figure 14 is a plan view showing the semiconductor substrate. Figure 13 is a plan view showing the semiconductor substrate. Figure 14 is a plan view showing the semiconductor substrate. Figure 13 is a plan view showing the semiconductor substrate. Figure 14 In Embodiment 2, XYZ orthogonal coordinate axes showing directions are also shown for convenience of explanation. Further, in Embodiment 2, the same reference numerals are assigned to the same structural elements as those explained in Embodiment 1, and the explanation thereof is omitted.

[0089] As shown in Figure 13 , in the semiconductor device 200 according to Embodiment 2, the insulated-gate bipolar transistor region 20 and the diode region 2 are repeatedly provided in the X direction of the semiconductor device 200.

[0090] As shown in Figure 14 , the semiconductor device according to Embodiment 2 is configured such that, in terms of a ratio of an area in which the counter-doped layer 21 is provided between mutually adjacent gate electrodes 7a or between a mutually adjacent gate electrode 7a and a gate electrode 7b, when viewed in plan, the closer to the diode region 2, the larger the ratio is. Further, it is a configuration in which the base contact layer 16 is provided in a surface layer of the semiconductor substrate and the base layer is not exposed.

[0091] In Figure 14 , the areas of the respective counter-doped layers 21 provided in plurality are all the same. In terms of a ratio of an area in which the counter-doped layer 21 is provided between mutually adjacent gate electrodes 7a or between a mutually adjacent gate electrode 7a and a gate electrode 7b of the insulated-gate bipolar transistor region 20, when viewed in plan, the ratio of the area of the counter-doped layer 21 between the gate electrode 7b closest to the diode region 2 and the adjacent gate electrode 7a is twice the ratio of the areas of the counter-doped layers 21 between mutually adjacent gate electrodes 7a.

[0092] Generally, in terms of holes flowing from the insulated-gate bipolar transistor region to the diode region at the time of recovery operation, the closer to the diode region, the more the holes are.

[0093] As for the semiconductor device according to Embodiment 2, by setting the ratio of the area in which the counter-doped layer 21 is arranged between the gate electrodes 7a adjacent to each other or between the gate electrode 7a and the gate electrode 7b to be larger as closer to the diode region 2, the inflow of holes from the insulated-gate bipolar transistor region 20 to the diode region 2 can be more efficiently suppressed, and the breakdown tolerance at the time of the recovery operation can be improved. On the other hand, in the insulated-gate bipolar transistor region 20 distant from the diode region 2, the risk of latch-up occurring right below the counter-doped layer 21 at the time of non-energization can be suppressed.

[0094] Further, the counter-doped layer 21 is sandwiched by the base contact layer 16 and does not contact the gate insulating film 6a. The counter-doped layer 21 is a semiconductor layer that does not participate in the switching between the energized state and the non-energized state of the insulated-gate bipolar transistor region 20. Therefore, in the case of the configuration in which the ratio of the area in which the counter-doped layer 21 is arranged between the gate electrodes 7a adjacent to each other or between the gate electrode 7a and the gate electrode 7b is set to be larger as closer to the diode region 2, the imbalance of the current at the insulated-gate bipolar transistor region 20 is also suppressed.

[0095] In Embodiment 2, the following example is shown, in which the area of each of the plurality of counter-doped layers 21 is set to be all the same, the number of the counter-doped layers 21 arranged between the gate electrodes 7a adjacent to each other or between the gate electrode 7a and the gate electrode 7b is set to be larger as closer to the diode region 2, and the ratio of the area in which the counter-doped layer 21 is arranged between the gate electrodes 7a adjacent to each other or between the gate electrode 7a and the gate electrode 7b is set to be larger as closer to the diode region 2. However, the ratio of the area in which the counter-doped layer 21 is arranged between the gate electrodes 7a adjacent to each other or between the gate electrode 7a and the gate electrode 7b can be set to be larger as closer to the diode region 2 by setting the number of the counter-doped layers 21 arranged between the gate electrodes 7a adjacent to each other or between the gate electrode 7a and the gate electrode 7b to be the same and increasing the area of the counter-doped layer 21 as closer to the diode region 2.

[0096] Further, in Embodiment 2, the base contact layer 16 is arranged in the surface layer of the semiconductor substrate and the base layer is not exposed. In order to set such a configuration, the base contact layer 16 can be provided by implanting acceptors into the portion of the base layer exposed. The base contact layer 16 is a semiconductor layer in which the concentration of acceptors is higher than that of the base layer and the injection of holes into the diode region 2 is more, but on the other hand, is a semiconductor layer in which the electrical contact resistance with the emitter electrode is lower than that of the base layer. Since both the counter-doped layer 21 and the base contact layer 16 are semiconductor layers in which the electrical contact resistance with the emitter electrode is low, the semiconductor device of Embodiment 2 is a semiconductor device in which the electrical contact resistance between the emitter electrode of the insulated-gate bipolar transistor region and the semiconductor substrate is reduced as compared with the semiconductor device of Embodiment 1.

[0097] <Implementation Method 3>

[0098] use Figure 15 and Figure 16 The structure of the semiconductor device according to Embodiment 3 will be described. Figure 15 and Figure 16 This is a top view of the semiconductor device involved in Embodiment 3. Figure 16 It is Figure 15 The enlarged view of part F described herein is a top view showing the structure of the first main surface of the semiconductor substrate. Figure 16 Descriptions of electrodes, etc., positioned above the first main surface of the semiconductor substrate are omitted. Figure 15 and Figure 16 For ease of explanation, the XYZ orthogonal coordinate axes representing directions are also shown. Furthermore, in Embodiment 3, structural elements identical to those described in Embodiments 1 and 2 are labeled with the same reference numerals and their descriptions are omitted.

[0099] like Figure 15 As shown, in the semiconductor device 300 according to Embodiment 3, the insulated gate bipolar transistor region 30 and the diode region 2 are repeatedly arranged in the X direction of the semiconductor device 300.

[0100] like Figure 16 As shown, the semiconductor device involved in Embodiment 3 is a semiconductor layer with a net doping concentration of p-type on the surface layer of the anti-doped layer 31. In order to set the net doping concentration of the surface layer of the anti-doped layer 31 to p-type, impurities are implanted in such a way that the acceptor impurity concentration on the surface layer of the anti-doped layer 31 is higher than the donor impurity concentration.

[0101] In the semiconductor device according to Embodiment 3, the risk of latch-up in the insulated gate bipolar transistor region 30 can be suppressed.

[0102] Furthermore, the anti-doped layer 31 is p-type, but its net doping concentration is lower than that of the p-type base contact layer 16. Therefore, the anti-doped layer 31 injects fewer holes into the diode region 2 compared to the base contact layer 16.

[0103] In embodiment 3, by setting the ratio of the areas of the anti-doped layer 31 between adjacent gate electrodes 7a, or between gate electrodes 7a and gate electrodes 7b, to be larger the closer to the diode region 2, the inflow of holes from the insulated gate bipolar transistor region 30 to the diode region 2 can be suppressed more efficiently, thereby improving the latch-up failure tolerance of the insulated gate bipolar transistor region.

[0104] <Implementation Method 4>

[0105] useFigure 17 and Figure 18 The structure of the semiconductor device according to Embodiment 3 will be described. Figure 17 and Figure 18 is a plan view showing the semiconductor device according to Embodiment 4. Figure 18 is a plan view showing the structure of the first main surface side of the semiconductor substrate. Figure 17 is a plan view showing the structure of the first main surface side of the semiconductor substrate. Figure 18 In Figure 17 and Figure 18 are shown for the convenience of explanation. Further, in Embodiment 4, the same reference numerals are given to the same structural elements as those described in Embodiments 1 to 3, and the description thereof is omitted.

[0106] As shown in Figure 17 , in the semiconductor device 400 according to Embodiment 4, the insulated-gate bipolar transistor region 40 and the diode region 2 are repeatedly provided in the X direction of the semiconductor device 400.

[0107] As shown in Figure 18 , the semiconductor device 400 according to Embodiment 4 has the insulated-gate bipolar transistor region 40. The insulated-gate bipolar transistor region 40 has a first region 40a in which the counter-doped layer 41 is provided between the gate electrodes 7a or 7b adjacent to each other, and a second region 40b in which the counter-doped layer 41 is not provided between the gate electrodes 7a or 7b adjacent to each other. The first region 40a is disposed closer to the diode region 2 than the second region 40b.

[0108] In the semiconductor device according to Embodiment 4, by disposing the first region 40a in which the counter-doped layer 41 is provided closer to the diode region 2 than the second region 40b in which the counter-doped layer 41 is not provided, the inflow of holes from the insulated-gate bipolar transistor region 40 to the diode region 2 can be efficiently suppressed, and the withstand voltage at the time of the recovery operation can be improved. On the other hand, since the second region 40b is disposed in the insulated-gate bipolar transistor region 40 farther from the diode region 2 than the first region 40a, and the counter-doped layer 41 is not provided in the second region 40b, the risk of the occurrence of latch-up at the time when the insulated-gate bipolar transistor region 40 is changed to the non-energized state can be suppressed.

[0109] Further, the counter-doped layer 41 contacts the emitter layer 8 in the Y direction. By providing such a structure, the area of the counter-doped layer 41 can be increased, the inflow of holes to the diode region 2 can be suppressed, and the withstand voltage at the time of the recovery operation can be improved.

[0110] Unlike the semiconductor device of Embodiments 1 to 3, the semiconductor device of Embodiment 4 is a configuration in which the base contact layer is not provided in the surface layer on the first main surface side of the semiconductor substrate. In order to provide such a configuration, the injection region of the donor layer forming the antidoping layer is made larger than the injection region of the acceptor forming the base contact layer, or each impurity is injected into the same region. In the case where the injection region of the donor layer forming the antidoping layer is made larger than the injection region of the acceptor forming the base contact layer, a configuration is obtained in which the n-type semiconductor layer covers the antidoping layer in plan view. By providing a configuration in which the n-type semiconductor layer does not contact the gate insulating film of the active gate electrode, it is possible to suppress the imbalance of the current at the insulated gate bipolar transistor region. If a configuration is provided in which the base contact layer is not provided in the surface layer on the first main surface side of the semiconductor substrate, it is possible to further suppress the inflow of holes to the diode region.

[0111] In Embodiments 1 to 4, a configuration is shown in which the anode layer is a single layer, but it is not limited thereto, and the anode layer can also be a two-layer configuration formed of the same conductivity type. For example, in the case where the contact resistance of the contact portion of the anode layer and the first electrode is large, by providing a two-layer configuration having a high-concentration anode layer having a high impurity concentration on the first main surface side of the anode layer, and a low-concentration anode layer having a lower impurity concentration than the high-concentration anode layer on the second main surface side than the high-concentration anode layer, it is possible to reduce the contact resistance of the contact portion of the anode layer and the first electrode.

[0112] The embodiments of the present application have been described, but these embodiments are disclosed only as examples. Various omissions, substitutions, and changes can be made without departing from the spirit of the present application. In addition, the embodiments can be combined.

[0113] Explanation of Reference Signs

[0114] 1 Insulated gate bipolar transistor region

[0115] 2 Diode region

[0116] 6a Gate insulating film

[0117] 7a Gate electrode

[0118] 8 Emitter layer

[0119] 9 Base layer

[0120] 10 Antidoping layer

[0121] 11 Anode layer

[0122] 12 Drift layer

[0123] 13 Collector layer

[0124] 15 cathode layer

[0125] 20 insulated gate bipolar transistor region

[0126] 21 counter-doped layer

[0127] 30 insulated gate bipolar transistor region

[0128] 31 counter-doped layer

[0129] 40 insulated gate bipolar transistor region

[0130] 40a first region

[0131] 40b second region

[0132] 41 counter-doped layer

[0133] 100 semiconductor device

[0134] 200 semiconductor device

[0135] 300 semiconductor device

[0136] 400 semiconductor device

[0137] S1 first main surface

[0138] S2 second main surface

[0139] W1 width of the emitter layer

[0140] W2 width of the counter-doped layer

Claims

1. A semiconductor device, comprising: a semiconductor substrate having a drift layer of a first conductivity type between a first main surface and a second main surface opposite to the first main surface; a diode region having an anode layer of a second conductivity type disposed at a surface layer on the first main surface side of the semiconductor substrate and a cathode layer of the first conductivity type disposed at a surface layer on the second main surface side of the semiconductor substrate; and an insulated gate bipolar transistor region disposed in parallel with the diode region in a first direction along the first main surface of the semiconductor substrate, the insulated gate bipolar transistor region having: a base layer of the second conductivity type disposed at a surface layer on the first main surface side of the semiconductor substrate; an emitter layer of the first conductivity type selectively disposed at a surface layer on the first main surface side of the base layer, the impurity concentration of which is higher than that of the drift layer; gate electrodes disposed in parallel with each other in the first direction, facing the emitter layer, the base layer and the drift layer through a gate insulating film; an anti-doping layer disposed at a surface layer of the base layer, the impurity concentration of which is higher than that of the base layer of the second conductivity type and higher than that of the drift layer of the first conductivity type, and the thickness of which is smaller than that of the base layer in a direction from the first main surface toward the second main surface; and a collector layer of the second conductivity type disposed at a surface layer on the second main surface side of the semiconductor substrate, the base layer being only one layer in a direction from the first main surface toward the second main surface.

2. The semiconductor device according to claim 1, wherein the anti-doping layer is disposed so as to be sandwiched by the base layer in the first direction between the gate electrodes adjacent to each other.

3. The semiconductor device according to claim 1 or 2, wherein a base contact layer of the second conductivity type having an impurity concentration higher than that of the base layer is further provided at a surface layer of the base layer, and the anti-doping layer is disposed so as to be sandwiched by the base contact layer in the first direction between the gate electrodes adjacent to each other.

4. The semiconductor device according to claim 3, wherein the impurity of the second conductivity type of the anti-doping layer is the same as that of the base contact layer.

5. The semiconductor device according to claim 1 or 2, wherein the impurity of the first conductivity type of the anti-doping layer is the same as that of the emitter layer.

6. The semiconductor device according to claim 1 or 2, wherein the impurity concentration of the first conductivity type within the anti-doping layer is higher than that of the second conductivity type within the anti-doping layer.

7. The semiconductor device according to claim 1 or 2, wherein the anti-doping layer is in contact with the emitter layer in a second direction orthogonal to the first direction and along the first main surface.

8. The semiconductor device according to claim 1 or 2, wherein the diode region has: a high-impurity-concentration anode layer at a surface layer on the first main surface side; and a low-impurity-concentration anode layer disposed on the second main surface side as compared with the high-impurity-concentration anode layer, the impurity concentration of which is lower than that of the high-impurity-concentration anode layer. ​ ​ ​ ​ ​ ​ ​ ​ ​ ​ ​ ​ ​ ​ ​ ​ ​ ​ ​ ​ ​ ​ 9. A semiconductor device, comprising: a semiconductor substrate having a drift layer of a first conductivity type between a first main surface and a second main surface opposite to the first main surface; a diode region having an anode layer of a second conductivity type disposed at a surface layer on the first main surface side of the semiconductor substrate and a cathode layer of the first conductivity type disposed at a surface layer on the second main surface side of the semiconductor substrate; and an insulated gate bipolar transistor region disposed in parallel with the diode region in a first direction along the first main surface of the semiconductor substrate, the insulated gate bipolar transistor region having: a base layer of the second conductivity type disposed at a surface layer on the first main surface side of the semiconductor substrate; an emitter layer of the first conductivity type selectively disposed at a surface layer on the first main surface side of the base layer with a higher impurity concentration than the drift layer; gate electrodes disposed in parallel with each other in the first direction, facing the emitter layer, the base layer and the drift layer through a gate insulating film; an anti-doping layer disposed at a surface layer of the base layer, having a higher impurity concentration of the second conductivity type than the base layer and a higher impurity concentration of the first conductivity type than the drift layer; and a collector layer of the second conductivity type disposed at a surface layer on the second main surface side of the semiconductor substrate, the anti-doping layer having a lower impurity concentration of the first conductivity type than the anti-doping layer has of the second conductivity type.

10. A semiconductor device, comprising: a semiconductor substrate having a drift layer of a first conductivity type between a first main surface and a second main surface opposite to the first main surface; a diode region having an anode layer of a second conductivity type disposed at a surface layer on the first main surface side of the semiconductor substrate and a cathode layer of the first conductivity type disposed at a surface layer on the second main surface side of the semiconductor substrate; and an insulated gate bipolar transistor region disposed in parallel with the diode region in a first direction along the first main surface of the semiconductor substrate, the insulated gate bipolar transistor region having: a base layer of the second conductivity type disposed at a surface layer on the first main surface side of the semiconductor substrate; an emitter layer of the first conductivity type selectively disposed at a surface layer on the first main surface side of the base layer with a higher impurity concentration than the drift layer; gate electrodes disposed in parallel with each other in the first direction, facing the emitter layer, the base layer and the drift layer through a gate insulating film; an anti-doping layer disposed at a surface layer of the base layer, having a higher impurity concentration of the second conductivity type than the base layer and a higher impurity concentration of the first conductivity type than the drift layer; and a collector layer of the second conductivity type disposed at a surface layer on the second main surface side of the semiconductor substrate, the anti-doping layer and the emitter layer each having a length direction and a width direction in a direction orthogonal to the length direction when viewed in plan, the anti-doping layer having a narrower width in the width direction than the emitter layer has in the width direction.

11. A semiconductor device, comprising: ​ ​ ​ ​ A semiconductor substrate having a drift layer of a first conductivity type between a first main surface and a second main surface opposite to the first main surface; A diode region having an anode layer of a second conductivity type disposed at a surface layer on the first main surface side of the semiconductor substrate and a cathode layer of the first conductivity type disposed at a surface layer on the second main surface side of the semiconductor substrate; and An insulated gate bipolar transistor region disposed in parallel with the diode region in a first direction along the first main surface of the semiconductor substrate, the insulated gate bipolar transistor region having: a base layer of the second conductivity type disposed at a surface layer on the first main surface side of the semiconductor substrate; an emitter layer of the first conductivity type selectively disposed at a surface layer on the first main surface side of the base layer with a higher impurity concentration than the drift layer; gate electrodes disposed in parallel with each other in the first direction, facing the emitter layer, the base layer, and the drift layer through a gate insulating film; an anti-doping layer disposed at a surface layer of the base layer, having a higher impurity concentration of the second conductivity type than the base layer and a higher impurity concentration of the first conductivity type than the drift layer; and a collector layer of the second conductivity type disposed at a surface layer on the second main surface side of the semiconductor substrate, the insulated gate bipolar transistor region having: a first region in which the anti-doping layer is disposed between the gate electrodes adjacent to each other; and a second region adjacent to the first region, in which the anti-doping layer is disposed between the gate electrodes adjacent to each other at a larger area ratio than the first region, the second region being closer to the diode region than the first region.

12. A semiconductor device having: a semiconductor substrate having a drift layer of a first conductivity type between a first main surface and a second main surface opposite to the first main surface; a diode region having an anode layer of a second conductivity type disposed at a surface layer on the first main surface side of the semiconductor substrate and a cathode layer of the first conductivity type disposed at a surface layer on the second main surface side of the semiconductor substrate; and an insulated gate bipolar transistor region disposed in parallel with the diode region in a first direction along the first main surface of the semiconductor substrate, the insulated gate bipolar transistor region having: a base layer of the second conductivity type disposed at a surface layer on the first main surface side of the semiconductor substrate; an emitter layer of the first conductivity type selectively disposed at a surface layer on the first main surface side of the base layer with a higher impurity concentration than the drift layer; gate electrodes disposed in parallel with each other in the first direction, facing the emitter layer, the base layer, and the drift layer through a gate insulating film; an anti-doping layer disposed at a surface layer of the base layer, having a higher impurity concentration of the second conductivity type than the base layer and a higher impurity concentration of the first conductivity type than the drift layer; and a collector layer of the second conductivity type disposed at a surface layer on the second main surface side of the semiconductor substrate, the insulated gate bipolar transistor region having: a third region in which the anti-doping layer is disposed between the gate electrodes adjacent to each other; and ​ ​ ​ ​ a fourth region without the counter-doped layer between the gate electrodes adjacent to each other, the third region is closer to the diode region than the fourth region.

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