A low-leakage startup circuit for self-powered chip systems

Abstract

This invention discloses a low-leakage startup circuit for a self-powered chip system, comprising a diode series circuit, an on-chip capacitor, an inverter, and a level shifter. The startup circuit detects the voltage signal of the energy storage capacitor in the self-powered chip system. Before this voltage signal falls below a set threshold, all other circuit modules in the self-powered chip system are shut down. This prevents the entire energy harvesting network from operating abnormally due to continuous leakage current from other circuit modules exceeding the energy collected by the energy harvesting module during energy harvesting. The startup circuit ensures that the chip starts operating when the energy storage capacitor voltage is higher than the minimum operating voltage of the self-powered chip system, ensuring normal energy harvesting and power supply to the self-powered chip system.

Description

Technical Field

[0001] This invention belongs to the field of integrated circuit design technology, specifically relating to a low leakage current startup circuit for self-powered chip systems. Background Technology

[0002] In the current construction of smart cities, the Internet of Things (IoT) has fully penetrated all aspects of urban life, continuously expanding the scope of smart city facilities such as buildings, bridges, roads, pipelines, light poles, and parking spaces, automatically sensing their operational status. Simultaneously, farms are also beginning to adopt IoT, low-cost cloud applications, low-power wide-area networks (LPWANs), sensing technologies, and data analysis platforms. These systems can be applied to all stages of agricultural production to improve agricultural efficiency. The essence of the Internet of Everything lies in sensors that perceive information from the physical world. Currently, sensors are mainly powered by traditional batteries or power supplies. This power supply method greatly limits the widespread adoption of the Internet of Everything due to short battery life, inconvenient replacement, and environmental pollution. To address this, researchers have proposed a miniaturized, long-life, and pollution-free self-powered chip system that can liberate sensor systems from the constraints of external power sources, achieving energy self-sufficiency and thus driving the leapfrog development of the IoT.

[0003] Self-powered chips typically include an energy harvesting module, a power management module, and a signal acquisition, processing, and transmission module. The energy harvesting module is responsible for collecting and converting environmental vibration energy, light energy, electromagnetic energy, and thermal energy into electrical energy and storing it in an energy storage capacitor. The power management module includes a startup circuit, a bandgap reference, a low-dropout regulator, and a DC-DC converter. The startup circuit is used to determine the voltage value in the energy storage capacitor, the bandgap reference is used to provide bias voltage for subsequent circuits, and the low-dropout regulator and DC-DC converter are used to provide stable voltage for the signal acquisition, processing, and transmission circuits.

[0004] In the design of self-powered chips, the design of the startup circuit is crucial, as it determines the turn-on time of other circuit modules on the chip, ensuring that the energy storage capacitor can continuously collect energy.

[0005] Many studies have investigated leakage current issues in self-powered chip systems during startup. For example, BHStark et al.'s 2011 paper, "Start-up circuit with low minimum operating power for microwatt energy harvesters," published in IET Circuit Dev.Syst., summarized the significant leakage current problem in self-powered chips during startup and proposed a startup circuit operating in the subthreshold region to address leakage current during energy harvesting. This startup circuit monitors the energy storage capacitor voltage in real time and activates the energy storage capacitor and subsequent voltage management circuit after reaching the threshold. The energy storage capacitor consumes 3.5 μW. However, this startup circuit still cannot meet the requirements of self-powered chip systems with energy harvesting capabilities only in the μA range.

[0006] Subsequently, D. Alghisi et al., in their 2017 paper "A new nano-power trigger circuit for battery-less power management electronics in energy harvesting systems" published in Sensors and Actuators A: Physical, further discussed under what conditions this leakage current would cause a self-powered system to malfunction. They also designed a startup circuit with a capacity of tens of nA. This startup circuit uses latch-up-based control logic to form a hysteresis comparator to determine the voltage of the energy storage capacitor and decide whether to turn on the energy storage capacitor and subsequent circuits. However, this startup circuit still cannot meet the requirements of current self-powered chip systems with energy harvesting capacity only in the nA range. Summary of the Invention

[0007] In view of the above, the present invention provides a low leakage current startup circuit for self-powered chip systems, which has the characteristics of ultra-low power consumption and meets the operating requirements of self-powered chip systems with lower energy harvesters.

[0008] A low-leakage startup circuit for a self-powered chip system includes: a diode series circuit, an on-chip capacitor, an inverter, and a level shifter, wherein:

[0009] One end of the diode series circuit is connected to the system external energy storage capacitor voltage VDD, and the other end is connected to one end of the on-chip capacitor and the input terminal of the inverter. The other end of the on-chip capacitor is grounded. This circuit is used to determine the voltage difference between VDD and one end of the on-chip capacitor, and thus decide whether to charge the on-chip capacitor.

[0010] The level converter uses the input and output of the inverter as a pair of complementary drive signals to switch the on-chip capacitor voltage between GND (ground) and VDD states, so as to ensure that the output start signal can be directly used to turn on and off other circuit modules in the system.

[0011] Furthermore, the diode series circuit is composed of multiple NMOS transistors connected in series, with the gate and drain of each NMOS transistor connected together, and the substrate grounded. Since the NMOS substrates are all grounded, the threshold voltage of the nth NMOS is higher than that of the (n-1)th NMOS. This threshold voltage only increases when the voltage difference across the diode series circuit exceeds n*V. THN (V THN When the voltage is the NMOS threshold voltage, the entire diode series circuit will be turned on; otherwise, it will remain in the subthreshold region.

[0012] Furthermore, the number of NMOS transistors in the diode series circuit is at least two or more.

[0013] Furthermore, the on-chip capacitor is constructed using MOM capacitors, MIM capacitors, or MOS capacitors supported by the manufacturing process. Before the diode series circuit is turned on, the voltage of the on-chip capacitor is close to ground. When the diode series circuit is turned on, the voltage of the on-chip capacitor will gradually accumulate and turn on the level shifter.

[0014] Furthermore, the power supply voltage of the inverter is provided by the voltage of the on-chip capacitor. When the voltage of the on-chip capacitor accumulates to exceed the threshold voltage, the inverter outputs a low level and shuts off another set of drives in the level converter, causing the output of the level converter to invert.

[0015] Furthermore, the level converter consists of two sets of driving transistors, a driving load, and an inverting circuit, specifically including three NMOS transistors M n1 ~M n3 And five PMOS transistors M p1 ~M p5 Among them, PMOS transistor M p3 The source and PMOS transistor M p4 The source and PMOS transistor M p5 The source of the PMOS transistor is connected to VDD. p3 The drain of the PMOS transistor M p4 The gate and PMOS transistor M p1 The source of the PMOS transistor is connected to the source. p4 The drain of the PMOS transistor M p3 The gate and PMOS transistor M p2 The source of the PMOS transistor is connected to the source. p1 The gate of the NMOS transistor M n1 The gate of the PMOS transistor is connected to the input of the inverter.p1 The drain of the NMOS transistor M n1 The drain of the PMOS transistor M p5 The gate and NMOS transistor M n3 The gate of the NMOS transistor is connected to the gate of the transistor. n1 The source is grounded, and the PMOS transistor M p2 The gate of the NMOS transistor M n2 The gate of the PMOS transistor is connected to the output of the inverter. p2 The drain of the NMOS transistor M n2 The drains of the NMOS transistor M are connected. n2 The source is grounded, and the PMOS transistor M p5 The drain of the NMOS transistor M n3 The drain of the NMOS transistor M is connected to generate a start signal. n3 The source is grounded. When the on-chip capacitor voltage accumulates to exceed the threshold voltage, the output of the level converter is reversed, and the output voltage is conditioned by the subsequent inverting circuit to the voltage of the off-chip energy storage capacitor.

[0016] Furthermore, the PMOS transistor M p1 With NMOS transistor M n1 The connection forms a set of driving transistors, PMOS transistor M p2 With NMOS transistor M n2 The connection forms another set of driving transistors. The driving transistors abandon the traditional NMOS pair form and adopt the PMOS and NMOS cascade method, which can greatly reduce the transient current during the level reversal process, ensure the normal charging process of the energy harvesting module to the energy storage capacitor, and avoid the instantaneous voltage drop on the energy storage capacitor.

[0017] Furthermore, the PMOS transistor M p3 With PMOS transistor M p4 The cross-coupled connection serves as the driving load, ensuring that the level shifter remains stationary and consumes extremely low power (100pA).

[0018] Furthermore, the PMOS transistor M p5 With NMOS transistor M n3 The circuit is connected to form an inverting circuit. The output signal generated by the driving transistor connected to the on-chip capacitor voltage (i.e., the inverter input) is conditioned by the inverting circuit to generate a start signal, which is used to turn on other circuit modules of the system.

[0019] The working principle of the circuit of this invention is as follows: when the voltage of the external energy storage capacitor is lower than the threshold, the diode series circuit is in the subthreshold region, and the voltage of the on-chip capacitor is close to ground; only when the voltage of the energy storage capacitor is greater than the threshold, the diode series circuit leaves the subthreshold region, accelerates the charging of the on-chip capacitor, and the voltage of the on-chip capacitor will gradually accumulate to exceed the threshold voltage. The inverter outputs a low level and shuts off one of the driving paths of the level converter, causing the output of the level converter to reverse. After being conditioned by the next stage inverter circuit, the final output start signal voltage is the energy storage capacitor voltage VDD.

[0020] The startup circuit of this invention detects the voltage signal of the energy storage capacitor in the self-powered chip system. Before this voltage signal falls below a threshold set by the startup circuit, all other circuit modules in the self-powered chip system are shut down. This prevents the entire energy harvesting network from operating abnormally due to continuous leakage current from other circuit modules exceeding the energy collected by the energy harvesting module during energy harvesting. The startup circuit of this invention ensures that the chip starts operating when the energy storage capacitor voltage is higher than the minimum operating voltage of the self-powered chip system, ensuring normal energy harvesting and power supply to the self-powered chip system. Attached Figure Description

[0021] Figure 1 This is a schematic diagram of the low leakage current start-up circuit in an embodiment of the present invention. Detailed Implementation

[0022] To describe the present invention in more detail, the technical solution of the present invention will be described in detail below with reference to the accompanying drawings and specific embodiments.

[0023] This invention relates to a low-leakage startup circuit for a self-powered chip system, comprising a diode series circuit, an on-chip capacitor, an inverter, and a level shifter, wherein:

[0024] A diode series circuit includes n (two or more) NMOS transistors, which form a series diode. The gates and drains of these diodes are connected, and the substrates are grounded. Because the NMOS substrates are all grounded, the threshold voltage of the nth NMOS is higher than that of the (n-1)th NMOS. This threshold voltage only increases when the voltage difference across the series diode exceeds n*V. THN When the diode is in the subthreshold region, the entire diode series circuit will be turned on; otherwise, it will remain in the subthreshold region.

[0025] The on-chip capacitor consists of MOM capacitors, MIM capacitors, or MOS capacitors supported by the process. One end of the on-chip capacitor is grounded, and the other end is connected to the source of the NMOS series diode. Before the series diode is turned on, the voltage of the on-chip capacitor is close to ground. When the series diode is turned on, the voltage of the on-chip capacitor will gradually accumulate and turn on the level shifter.

[0026] The inverter's power supply and input are provided by the on-chip capacitor voltage. When the on-chip capacitor voltage accumulates to exceed the threshold voltage, the inverter outputs a low level and shuts off another driver of the level converter, causing the level converter's output to invert.

[0027] The inputs of the two complementary drivers of the level converter are connected to the on-chip capacitor voltage and the inverter output voltage, respectively. The driver output connected to the on-chip capacitor voltage, after passing through an inverter circuit, becomes the start signal. The load of the complementary drivers is a cross-coupled PMOS. When the on-chip capacitor voltage accumulates to exceed the threshold voltage, the level converter output inverts, and the subsequent inverter circuit conditions its output voltage to the off-chip energy storage capacitor voltage. The level converter abandons the traditional NMOS pair in favor of a cascaded PMOS and NMOS configuration, which significantly reduces transient current during level inversion, ensuring continuous charging of the energy storage capacitor.

[0028] The startup circuit of this invention embodiment is as follows: Figure 1 As shown, n NMOS transistors form a diode series circuit. This embodiment uses three NMOS transistors as an example, and then connects them with the on-chip capacitor C. L Connected, the three NMOS transistors are M nd1 M nd2 M nd3 M nd1 ~M nd3 The gates are connected to the drains, and the substrate is grounded; M nd3 The drain is connected to VDD, M nd1 The source terminal capacitor C L When the energy storage capacitor voltage VDD is below 3V THN When (NMOS threshold voltage) is reached, M nd1 ~M nd3 In the subthreshold region, the leakage current is on the order of fA-pA relative to the on-chip capacitor C. L Charging begins, but because the charging rate is lower than the charging rate of the energy harvesting module for the energy storage capacitor, charging continues until VDD reaches 3V. THN Previously, on-chip capacitor C L The voltage on the inverter is close to ground. Since the inverter's supply voltage is close to ground, the inverter's output is also close to ground.

[0029] Meanwhile, the level shifter is driven by complementary M p1 -M n1 and M p2 -M n2 Since the input voltage is close to ground, it is only necessary to include M in the design. n1 and M n2 The channel length is increased to make its voltage drop greater than that of the PMOS transistor M. p1 M p2 and M p3 M p4Therefore, drive M p1 -M n1 and M p2 -M n2 The outputs are all high level, close to VDD, and are then transmitted through the next stage inverting circuit M. p5 -M n3 After conditioning, the final output start signal voltage is ground.

[0030] When VDD is greater than 3V THN At that time, NMOS transistor M nd1 ~M nd3 Leaving the subthreshold region, for the on-chip capacitor C L Accelerate charging until V DDL Charging exceeds V THN At the same time, complementary drive M p1 -M n1 and M p2 -M n2 The balance between them was broken, driving M p1 -M n1 The output is gradually pulled closer to ground by the inverting circuit M of the next stage. p5 -M n3 After conditioning, the final output start signal voltage is VDD. At this point, the level conversion circuit has completed its inversion and cross-coupled M. p3 -M p4 The transistor acts as a load, ensuring that the level shifting circuit remains in a static state and consumes extremely low power (100pA).

[0031] Furthermore, the complementary driving M introduced in this invention p1 -M n1 and M p2 -M n2 Unlike traditional NMOS transistor drives, this method effectively reduces the demand for transient current during level transitions, ensuring the energy harvester can charge the energy storage capacitor normally and avoiding instantaneous voltage drops on the energy storage capacitor.

[0032] As can be seen from the above embodiments, the present invention uses a method of charging the on-chip capacitor with a series NMOS diode and cascading level conversion circuits to detect changes in the voltage on the energy storage capacitor. After reaching a threshold, a start signal is given to start the subsequent circuit. This method has the advantages of low power consumption, small area, and high reliability.

[0033] The above description of the embodiments is provided to enable those skilled in the art to understand and apply the present invention. Those skilled in the art can readily make various modifications to the above embodiments and apply the general principles described herein to other embodiments without creative effort. Therefore, the present invention is not limited to the above embodiments, and any improvements and modifications made to the present invention by those skilled in the art based on the disclosure thereof should be within the scope of protection of the present invention.

Claims

1. A low-leakage startup circuit for a self-powered chip system, characterized in that, include: The circuit consists of a series diode circuit, an on-chip capacitor, an inverter, and a level shifter, among which: One end of the diode series circuit is connected to the system external energy storage capacitor voltage VDD, and the other end is connected to one end of the on-chip capacitor and the input terminal of the inverter. The other end of the on-chip capacitor is grounded. This circuit is used to determine the voltage difference between VDD and one end of the on-chip capacitor, and thus decide whether to charge the on-chip capacitor. The level converter uses the input and output of the inverter as a pair of complementary drive signals to switch the on-chip capacitor voltage between GND and VDD states, so as to ensure that the output start signal can be directly used to turn on and off other circuit modules in the system. The level converter consists of two sets of driver transistors, a driver load, and an inverting circuit, specifically including three NMOS transistors M n1 ~M n3 And five PMOS transistors M p1 ~M p5 Among them, PMOS transistor M p3 The source and PMOS transistor M p4 The source and PMOS transistor M p5 The source of the PMOS transistor is connected to VDD. p3 The drain of the PMOS transistor M p4 The gate and PMOS transistor M p1 The source of the PMOS transistor is connected to the source. p4 The drain of the PMOS transistor M p3 The gate and PMOS transistor M p2 The source of the PMOS transistor is connected to the source. p1 The gate of the NMOS transistor M n1 The gate of the PMOS transistor is connected to the input of the inverter. p1 The drain of the NMOS transistor M n1 The drain of the PMOS transistor M p5 The gate and NMOS transistor M n3 The gate of the NMOS transistor is connected to the gate of the transistor. n1 The source is grounded, and the PMOS transistor M p2 The gate of the NMOS transistor M n2 The gate of the PMOS transistor is connected to the output of the inverter. p2 The drain of the NMOS transistor M n2 The drains of the NMOS transistor M are connected. n2 The source is grounded, and the PMOS transistor M p5 The drain of the NMOS transistor M n3 The drain of the NMOS transistor M is connected to generate a start signal. n3 The source electrode is grounded.

2. The low leakage current start-up circuit according to claim 1, characterized in that: The diode series circuit is composed of multiple NMOS transistors connected in series, with the gate and drain of each NMOS transistor connected together and the substrate grounded.

3. The low leakage current start-up circuit according to claim 2, characterized in that: The number of NMOS transistors in the diode series circuit is at least two or more.

4. The low leakage current start-up circuit according to claim 1, characterized in that: The on-chip capacitors are constructed using MOM capacitors, MIM capacitors, or MOS capacitors supported by the manufacturing process.

5. The low leakage current start-up circuit according to claim 1, characterized in that: The inverter's power supply voltage is provided by the voltage of the on-chip capacitor.

6. The low leakage current start-up circuit according to claim 1, characterized in that: The PMOS transistor M p1 With NMOS transistor M n1 The connection forms a set of driving transistors, PMOS transistor M p2 With NMOS transistor M n2 The connection forms another set of drive transistors.

7. The low leakage current start-up circuit according to claim 1, characterized in that: The PMOS transistor M p3 With PMOS transistor M p4 Cross-coupled connections serve as driving loads.

8. The low leakage current start-up circuit according to claim 1, characterized in that: The PMOS transistor M p5 With NMOS transistor M n3 The connection forms an inverting circuit. The output signal generated by the driving transistor connected to the on-chip capacitor voltage is conditioned by this inverting circuit to generate a start signal, which is used to turn on other circuit modules of the system.

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