Switched capacitor sampling circuit and analog-to-digital converter

Abstract

A switched capacitor sampling circuit and an analog-to-digital converter belong to the field of electronic technology. The invention relates to a switched capacitor sampling circuit and an analog-to-digital converter. The switched capacitor sampling circuit and an analog-to-digital converter belong to the field of electronic technology. The switched capacitor sampling circuit and an analog-to-digital converter include an operational amplifier and a configurable capacitor network. The configurable capacitor network includes a first switching circuit to a fourth switching circuit, a first offset capacitor, a second offset capacitor, four sampling capacitors, a first output capacitor, a second output capacitor, a first conversion capacitor, and a second conversion capacitor. The configurable capacitor network receives an external control signal to control the switch circuit and configure the switched capacitor sampling circuit to be in a first state or a second state. Since the sampling voltage is always applied in the two states, the gain of the switched capacitor sampling circuit is doubled and the equivalent bandwidth is increased. The invention also has an offset elimination effect and can eliminate the influence of the operational amplifier offset and the switch charge injection in the circuit.

Description

Technical Field

[0001] The present application belongs to the field of electronic technology, and in particular relates to a switched capacitor sampling circuit and an analog-to-digital converter. Background Art

[0002] In the application of modern electronic systems, with the continuous increase in the application market of high-speed digital signal processing, the analog-to-digital converter, as a bridge between analog signals and digital signal processing, has great potential in the application market. As one of the core modules of the analog-to-digital converter, the sample-and-hold circuit is located at the front end of the analog-to-digital converter. Its main function is to convert the continuously changing analog signal from the outside into a discrete signal and keep it for a sufficient time for the subsequent circuit to perform quantization encoding. The sampling accuracy and sampling speed of the sample-and-hold circuit determine the highest conversion accuracy and fastest sampling speed that the entire analog-to-digital converter can achieve.

[0003] The operational amplifier in the related switched capacitor sampling circuit has an offset error, which may affect the sampling accuracy of the switched capacitor sampling circuit. At the same time, the field effect tube switch in the circuit has a charge injection effect during the on and off process, which will also affect the accuracy of the switched capacitor sampling circuit. At the same time, the switched capacitor sampling circuit usually has a low gain.

[0004] In summary, the related switched capacitor sampling circuit has non-negligible offset and low gain problems. Summary of the invention

[0005] The purpose of the present application is to provide a switched capacitor sampling circuit and an analog-to-digital converter, aiming to solve the problem that the related switched capacitor sampling circuit has non-negligible offset and low gain.

[0006] The embodiment of the present application provides a switched capacitor sampling circuit, including an operational amplifier, a first offset capacitor, a second offset capacitor, four sampling capacitors, a first output capacitor, a second output capacitor, a first conversion capacitor, and a second conversion capacitor;

[0007] The positive input terminal of the operational amplifier is connected to the first end of the first offset capacitor, the second end of the first offset capacitor is connected to the first node, the negative input terminal of the operational amplifier is connected to the first end of the second offset capacitor, the second end of the second offset capacitor is connected to the second node, and the positive output terminal of the operational amplifier and the negative output terminal of the operational amplifier are used together as the output terminal of the switch capacitor sampling circuit;

[0008] The switch capacitor sampling circuit has a first state and a second state; wherein, in the first state, the first node and the second node are connected to a common mode voltage, and in the second state, the first node and the second node are disconnected; the switch capacitor sampling circuit further includes:

[0009] A first switch circuit is connected to the four sampling capacitors and is configured to connect a first reference voltage, a second reference voltage, a positive sampling voltage and a negative sampling voltage to the first node and the second node through the four sampling capacitors in a first state, and connect a second reference voltage and a positive sampling voltage to the first node through two sampling capacitors in a second state, and connect the first reference voltage and the negative sampling voltage to the second node through another two sampling capacitors;

[0010] a second switch circuit connected to the operational amplifier, the first node and the first output capacitor, configured to short-circuit the first output capacitor and transfer the common mode voltage to the first node in a first state, and connect the first output capacitor between the inverting output terminal of the operational amplifier and the first node in a second state;

[0011] a third switch circuit, connected to the operational amplifier and the first conversion capacitor, configured to connect the first conversion capacitor between the inverting output terminal of the operational amplifier and the non-inverting input terminal of the operational amplifier in a first state, and to connect the first conversion capacitor to a common mode voltage at the inverting output terminal of the operational amplifier in a second state;

[0012] a fourth switch circuit connected to the operational amplifier, the second node and the second output capacitor, configured to short-circuit the second output capacitor and transfer the common mode voltage to the second node in a first state, and connect the second output capacitor between the non-inverting output terminal of the operational amplifier and the second node in a second state;

[0013] A fifth switching circuit is connected to the operational amplifier and the second conversion capacitor, and is configured to connect the second conversion capacitor between the positive phase output terminal of the operational amplifier and the inverting input terminal of the operational amplifier in a first state, and to connect the second conversion capacitor to the common mode voltage to the positive phase output terminal of the operational amplifier in a second state.

[0014] An embodiment of the present invention further provides an analog-to-digital converter, which includes the above-mentioned switched capacitor sampling circuit.

[0015] Compared with the prior art, the embodiments of the present invention have the following beneficial effects: since the positive sampling voltage and the negative sampling voltage are always in effect in the first state and the second state (during the sampling and conversion process), the gain of the switched capacitor sampling circuit is doubled. Furthermore, since the offset voltage in the circuit is equivalent to the charge stored in the offset capacitor during the sampling and conversion process, there is no charge change in the offset capacitor before and after the conversion process, and the offset voltage is eliminated; thereby improving the sampling accuracy and gain. BRIEF DESCRIPTION OF THE DRAWINGS

[0016] In order to more clearly illustrate the technical invention in the embodiments of the present invention, the drawings required for use in the description of the embodiments will be briefly introduced below. Obviously, the drawings in the following description are only some embodiments of the present invention. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying creative work.

[0017] Figure 1 A schematic diagram of a switched capacitor sampling circuit provided in an embodiment of the present application;

[0018] Figure 2 Another structural schematic diagram of a switched capacitor sampling circuit provided in an embodiment of the present application;

[0019] Figure 3 Another structural schematic diagram of a switched capacitor sampling circuit provided in an embodiment of the present application;

[0020] Figure 4 An exemplary circuit schematic diagram of a switched capacitor sampling circuit provided in an embodiment of the present application;

[0021] Figure 5 An exemplary circuit schematic diagram of a switched capacitor sampling circuit in a first state provided by an embodiment of the present application;

[0022] Figure 6 An exemplary circuit schematic diagram of a switched capacitor sampling circuit in a second state provided by an embodiment of the present application. DETAILED DESCRIPTION

[0023] In order to make the technical problems, technical solutions and beneficial effects to be solved by the present application more clearly understood, the present application is further described in detail below in conjunction with the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are only used to explain the present application and are not used to limit the present application.

[0024] It should be noted that when an element is referred to as being "fixed to" or "disposed on" another element, it can be directly on the other element or indirectly on the other element. When an element is referred to as being "connected to" another element, it can be directly connected to the other element or indirectly connected to the other element.

[0025] It should be understood that the orientation or position relationship indicated by terms such as "length", "width", "up", "down", "front", "back", "left", "right", "vertical", "horizontal", "top", "bottom", "inside" and "outside" are based on the orientation or position relationship shown in the drawings, and are only for the convenience of describing the present application and simplifying the description, and do not indicate or imply that the device or element referred to must have a specific orientation, be constructed and operated in a specific orientation, and therefore should not be understood as a limitation on the present application.

[0026] In addition, the terms "first" and "second" are used for descriptive purposes only and should not be understood as indicating or implying relative importance or implicitly indicating the number of the indicated technical features. Thus, a feature defined as "first" or "second" may explicitly or implicitly include one or more of the features. In the description of this application, the meaning of "plurality" is two or more, unless otherwise clearly and specifically defined.

[0027] Figure 1 The structure diagram of the switch capacitor sampling circuit provided by the preferred embodiment of the present application is shown. For the convenience of explanation, only the part related to the present embodiment is shown, which is described in detail as follows:

[0028] The switched capacitor sampling circuit includes an operational amplifier U1, a first offset capacitor Cca1, a second offset capacitor Cca2, four sampling capacitors, a first output capacitor Cb1, a second output capacitor Cb2, a first conversion capacitor Cc1 and a second conversion capacitor Cc2.

[0029] The positive input terminal of the operational amplifier U1 is connected to the first end of the first offset capacitor Cca1, the second end of the first offset capacitor Cca1 is connected to the first node A, the negative input terminal of the operational amplifier U1 is connected to the first end of the second offset capacitor Cca2, the second end of the second offset capacitor Cca2 is connected to the second node B, and the positive output terminal of the operational amplifier U1 and the negative output terminal of the operational amplifier U1 are used together as the output terminal of the switched capacitor sampling circuit.

[0030] The switched capacitor sampling circuit has a first state and a second state; wherein, in the first state, the first node A and the second node B are connected to a common mode voltage together, and in the second state, the first node A and the second node B are disconnected; the switched capacitor sampling circuit also includes a first switch circuit 11, a second switch circuit 12, a third switch circuit 13, a fourth switch circuit 14 and a fifth switch circuit 15.

[0031] The first switch circuit 11 is connected to four sampling capacitors and is configured to connect the first reference voltage, the second reference voltage, the positive sampling voltage and the negative sampling voltage to the first node A and the second node B through the four sampling capacitors in the first state, and connect the second reference voltage and the positive sampling voltage to the first node A through two sampling capacitors in the second state, and connect the first reference voltage and the negative sampling voltage to the second node B through the other two sampling capacitors.

[0032] The second switch circuit 12 is connected to the operational amplifier, the first node A and the first output capacitor Cb1, and is configured to short-circuit the first output capacitor Cb1 and transfer the common mode voltage to the first node A in a first state, and connect the first output capacitor Cb1 between the inverting output terminal of the operational amplifier and the first node A in a second state.

[0033] The third switch circuit 13 is connected to the operational amplifier and the first conversion capacitor Cc1, and is configured to connect the first conversion capacitor Cc1 between the inverting output terminal of the operational amplifier and the non-inverting input terminal of the operational amplifier in a first state, and to connect the first conversion capacitor Cc1 to the common mode voltage to the inverting output terminal of the operational amplifier in a second state.

[0034] The fourth switch circuit 14 is connected to the operational amplifier, the second node B and the second output capacitor Cb2, and is configured to short-circuit the second output capacitor Cb2 and transfer the common mode voltage to the second node B in a first state, and to connect the second output capacitor Cb2 between the positive phase output terminal of the operational amplifier and the second node B in a second state.

[0035] The fifth switching circuit 15 is connected to the operational amplifier and the second conversion capacitor Cc2, and is configured to connect the second conversion capacitor Cc2 between the positive phase output terminal of the operational amplifier and the inverting input terminal of the operational amplifier in the first state, and to connect the second conversion capacitor Cc2 to the common mode voltage to the positive phase output terminal of the operational amplifier in the second state.

[0036] like Figure 2 As shown, the four sampling capacitors are connected in parallel to the first gain adjustment circuit 16 , and the first gain adjustment circuit 16 includes a first selection switch Sx1 and a first adjustment capacitor Ct1 .

[0037] A first end of the first selection switch Sx1 is connected to a first end of the sampling capacitor, a second end of the first selection switch Sx1 is connected to a first end of the first adjustment capacitor Ct1, and a second end of the first adjustment capacitor Ct1 is connected to a second end of the sampling capacitor.

[0038] By connecting the first adjustment capacitor Ct1 in parallel at both ends of the sampling capacitor through the first gain adjustment circuit 16, gain adjustment of the switched capacitor sampling circuit is achieved.

[0039] like Figure 3 As shown, a second gain adjustment circuit 17 is set between the first node A and the inverting input terminal of the operational amplifier, and between the second node B and the non-inverting input terminal of the operational amplifier. The second gain adjustment circuit 17 includes a second selection switch Sx2, a second adjustment capacitor Ct2 and a ninth conversion switch Sc9.

[0040] The first end of the ninth conversion switch Sc9 is connected to the first node A or the second node B, the second end of the ninth conversion switch Sc9 is connected to the first end of the second selection switch Sx2, the second end of the second selection switch Sx2 is connected to the first end of the second adjustment capacitor Ct2, and the second end of the second adjustment capacitor Ct2 is connected to the non-inverting input terminal of the operational amplifier or the inverting input terminal of the operational amplifier.

[0041] By connecting the second adjustment capacitor Ct2 in parallel at both ends of the output capacitor through the second gain adjustment circuit 17, gain adjustment of the switched capacitor sampling circuit is achieved.

[0042] Figure 4 An exemplary circuit structure of a switched capacitor sampling circuit provided by an embodiment of the present invention is shown. For ease of description, only the part related to the embodiment of the present invention is shown, which is described in detail as follows:

[0043] The four sampling capacitors are a first sampling capacitor Ca1, a second sampling capacitor Ca2, a third sampling capacitor Ca3, and a fourth sampling capacitor Ca4; a first end of the first sampling capacitor Ca1 and a first end of the second sampling capacitor Ca2 are connected to a first node A, and a first end of the third sampling capacitor Ca3 and a first end of the fourth sampling capacitor Ca4 are connected to a second node B.

[0044] The first switch circuit 11 includes a first sampling switch Ss1 , a second sampling switch Ss2 , a third sampling switch Ss3 , a fourth sampling switch Ss4 , a first conversion switch Sc1 , a second conversion switch Sc2 , a third conversion switch Sc3 , and a fourth conversion switch Sc4 .

[0045] The first end of the first sampling switch Ss1 and the first end of the first conversion switch Sc1 serve together as the positive sampling voltage input end of the first switch circuit 11, the second end of the first conversion switch Sc1 and the first end of the second sampling switch Ss2 serve together as the first output end of the first switch circuit 11, and are connected to the second end of the first sampling capacitor Ca1, the second end of the second sampling switch Ss2 and the first end of the second conversion switch Sc2 serve together as the first reference voltage input end of the first switch circuit 11, the second end of the first sampling switch Ss1 and the second end of the second conversion switch Sc2 serve together as the third output end of the first switch circuit 11, and are connected to the second end of the third sampling capacitor Ca3.

[0046] The first end of the third sampling switch Ss3 and the first end of the fourth conversion switch Sc4 serve together as the negative sampling voltage input end of the first switch circuit 11, the second end of the third sampling switch Ss3 and the first end of the third conversion switch Sc3 serve together as the second output end of the first switch circuit 11, and are connected to the second end of the second sampling capacitor Ca2, the second end of the third conversion switch Sc3 and the first end of the fourth sampling switch Ss4 serve together as the second reference voltage input end of the first switch circuit 11, the second end of the fourth sampling switch Ss4 and the second end of the fourth conversion switch Sc4 serve together as the fourth output end of the first switch circuit 11, and are connected to the second end of the fourth sampling capacitor Ca4.

[0047] The second switch circuit 12 includes a fifth sampling switch Ss5 , a sixth sampling switch Ss6 , and a fifth conversion switch Sc5 .

[0048] The first end of the fifth sampling switch Ss5 and the first end of the sixth sampling switch Ss6 serve together as the common-mode voltage input end of the second switch circuit 12, the second end of the fifth sampling switch Ss5 serves as the common-mode voltage output end of the second switch circuit 12 and is connected to the first end of the first output capacitor Cb1, the second end of the sixth sampling switch Ss6 and the first end of the fifth conversion switch Sc5 are commonly connected to the second end of the first output capacitor Cb1, and the second end of the fifth conversion switch Sc5 is connected to the inverting output end of the operational amplifier.

[0049] The third switch circuit 13 includes a seventh sampling switch Ss7 and a sixth conversion switch Sc6;

[0050] The first end of the seventh sampling switch Ss7 is connected to the non-inverting input end of the operational amplifier, the second end of the seventh sampling switch Ss7 and the first end of the sixth conversion switch Sc6 are commonly connected to the first end of the first conversion capacitor Cc1, and the second end of the sixth conversion switch Sc6 is connected to the common mode voltage.

[0051] The fourth switch circuit 14 includes an eighth sampling switch Ss8 , a ninth sampling switch Ss9 , and a seventh conversion switch Sc7 .

[0052] The first end of the eighth sampling switch Ss8 and the first end of the ninth sampling switch Ss9 serve together as the common-mode voltage input end of the fourth switch circuit 14, the second end of the eighth sampling switch Ss8 serves as the common-mode voltage output end of the fourth switch circuit 14 and is connected to the first end of the second output capacitor Cb2, the second end of the ninth sampling switch Ss9 and the first end of the seventh conversion switch Sc7 are commonly connected to the second end of the second output capacitor Cb2, and the second end of the seventh conversion switch Sc7 is connected to the non-inverting output end of the operational amplifier.

[0053] The fifth switch circuit 15 includes a tenth sampling switch Ss10 and an eighth conversion switch Sc8 .

[0054] The first end of the tenth sampling switch Ss10 is connected to the inverting input end of the operational amplifier, the second end of the tenth sampling switch Ss10 and the first end of the eighth conversion switch Sc8 are commonly connected to the first end of the second conversion capacitor Cc2, and the second end of the eighth conversion switch Sc8 is connected to the common mode voltage.

[0055] The following is a combination of working principles Figure 4 As shown for further explanation:

[0056] The switched capacitor sampling circuit has a first state and a second state; in the first state, Figure 4 The sampling switches in are all closed and the conversion switches are all open; in the second state, Figure 4 The sampling switches in the switch capacitor sampling circuit are all disconnected, and the conversion switches are all closed; wherein, in the first state, the first node A and the second node B are connected to the common mode voltage together, and in the second state, the first node A and the second node B are disconnected. Therefore, an exemplary circuit structure of the switch capacitor sampling circuit in the first state is obtained, as shown in FIG. Figure 5 As shown. And an example circuit structure of the switched capacitor sampling circuit in the second state is obtained, as shown Figure 6 shown.

[0057] Figure 5 and Figure 6 In, V 02 is the positive output voltage of the switched capacitor sampling circuit, V 01 is the negative output voltage of the switched capacitor sampling circuit, V REF The first reference voltage for external input, V OP4 The second reference voltage is input externally, V EAN is the negative sampling voltage of the external input, V ENP It is the positive sampling voltage of the external input. CM is the determined common mode voltage. S is the input voltage of the operational amplifier with built-in clamp in the first state (sampling state). V C is the input voltage of the operational amplifier with built-in clamp in the second state (conversion state). V CM_C is the voltage at the first node A and the second node B in the conversion state. a1 , C a2 , C a3 and C a4 is the capacitance of the sampling capacitor, C b1 and C b2 is the output capacitor value, C ca1 and C ca2 is the capacitance of the offset capacitor. According to the charge conservation at the first node A and the second node B, we can get:

[0058] (VREF -V CM )C a1 +(V EAN -V CM )C a2 +(V S -V CM )C a1 =(V EAP -V CM_C )C a2 +(V 0p4 -V CM_C )C a1 +(V C -V CM_C )C a1 +(V 01 -V CM_C )C b1 (1)

[0059] (V EAP -V CM )C a3 +(V OP4 -V CM )C a4 +(V S -V CM )C a2 =(V REF -V CM_C )C a3 +(V EAN -V CM_C )C a4 +(V C -V CM_C )C a2 +(V 02 -V CM_C )C b2 (2)

[0060] According to the circuit requirements, define C a1 =C a2 =C a3 =C a4 =C a , C b1 =C b2 =C b , C ca1 =C ca2 =C ca Before and after the conversion of the switched capacitor sampling circuit, the input voltages of the operational amplifier with built-in clamp are Vs and Vc respectively.

[0061] From equation (1) + equation (2), we can get:

[0062] -4V CM Ca +2(V S -V CM )C ca =-4V CM_C C a +2(V C -V CM_C )C ca +(V 01 -V 02 )C b -2V CM_C C b Since the offset cancellation capacitor C ca There is no charge transfer, so:

[0063] V S -V CM =V C -V CM_C

[0064] -4V CM C a =-4V CM_C C a +(V 01 -V 02 )C b -2V CM_C C b

[0065] Let V CMO is the common-mode level of the output voltage.

[0066] -4V CM C a =-4V CM_C +2V CMO C b -2V CM_C C b

[0067] V CM_C (2C a -C b )=2V CM C a +V CMO C b

[0068] get

[0069] V CM_C =V CM =V CMO

[0070] From this we can get

[0071] V S =V C

[0072] During the sampling-conversion process, the voltage at the input of the op amp with built-in clamp remains constant.

[0073] (2)-(1) gives the differential mode gain:

[0074]

[0075] Since the sampling input terminals EAN and EAP are always in effect during the sampling and conversion process, the loop gain of the switched capacitor sampling circuit is doubled, the closed-loop gain is halved, and the equivalent bandwidth is increased.

[0076] Assuming that there is an offset voltage Vos at the positive input of the op amp, the charge conservation at the first node A and the second node B yields:

[0077] (V EAP -V CM )C a3 +(V OP4 -V CM )C a4 +(V S +V OS -V CM )C ca2 =(V REF -V CM_C )C a3 +(V EAN -V CM_C )C a4 +(V C -V CM_C )C ca2 +(V 02 -V CM_C )C b2

[0078] (V REF -V CM )C a1 +(V EAN -V CM )C a2 +(V S +V OS -V CM )C ca1 =(V EAP -V CM_C )C a2 +(V OP4 -V CM_C )C a1 +(V C -V CM_C )C ca1 +(V 01 -V CM_C )Cb1

[0079] It can be seen that the offset voltage Vos can be eliminated on both sides of the equation, and the differential output voltage (V 02 -V 01 ) has nothing to do with the offset voltage. During the sampling and conversion process, the offset voltage is equivalent to the charge stored in the offset cancellation capacitor. There is no charge change in the offset cancellation capacitor before and after the conversion process, and the offset voltage is eliminated.

[0080] An embodiment of the present invention further provides an analog-to-digital converter, which includes the above-mentioned switched capacitor sampling circuit.

[0081] The embodiment of the present invention includes an operational amplifier and a configurable capacitor network, wherein the configurable capacitor network includes a first switch circuit to a fourth switch circuit, a first offset capacitor, a second offset capacitor, four sampling capacitors, a first output capacitor, a second output capacitor, a first conversion capacitor, and a second conversion capacitor; the configurable capacitor network receives an external control signal to control the switch circuit, and configures the switch capacitor sampling circuit to be in a first state or a second state. Since the sampling voltage is always applied in the two states, the gain of the switch capacitor sampling circuit is doubled and the equivalent bandwidth is increased; at the same time, the offset elimination effect can be achieved, and the influence of the operational amplifier offset and the switch charge injection in the circuit can be eliminated.

[0082] It should be understood that the size of the serial numbers of the steps in the above embodiments does not mean the order of execution. The execution order of each process should be determined by its function and internal logic, and should not constitute any limitation on the implementation process of the embodiments of the present application.

[0083] The embodiments described above are only used to illustrate the technical solutions of the present application, rather than to limit them. Although the present application has been described in detail with reference to the aforementioned embodiments, a person skilled in the art should understand that the technical solutions described in the aforementioned embodiments may still be modified, or some of the technical features may be replaced by equivalents. Such modifications or replacements do not deviate the essence of the corresponding technical solutions from the spirit and scope of the technical solutions of the embodiments of the present application, and should all be included in the protection scope of the present application.

Claims

1. A switched capacitor sampling circuit, characterized in that: It includes an operational amplifier, a first offset capacitor, a second offset capacitor, four sampling capacitors, a first output capacitor, a second output capacitor, a first conversion capacitor and a second conversion capacitor; The positive input terminal of the operational amplifier is connected to the first end of the first offset capacitor, the second end of the first offset capacitor is connected to the first node, the negative input terminal of the operational amplifier is connected to the first end of the second offset capacitor, the second end of the second offset capacitor is connected to the second node, and the positive output terminal of the operational amplifier and the negative output terminal of the operational amplifier are used together as the output terminal of the switch capacitor sampling circuit; The switch capacitor sampling circuit has a first state and a second state; wherein, in the first state, the first node and the second node are connected to a common mode voltage, and in the second state, the first node and the second node are disconnected; the switch capacitor sampling circuit further includes: A first switch circuit is connected to the four sampling capacitors and is configured to connect a first reference voltage, a second reference voltage, a positive sampling voltage and a negative sampling voltage to the first node and the second node through the four sampling capacitors in a first state, and connect a second reference voltage and a positive sampling voltage to the first node through two sampling capacitors in a second state, and connect the first reference voltage and the negative sampling voltage to the second node through another two sampling capacitors; a second switch circuit connected to the operational amplifier, the first node and the first output capacitor, configured to short-circuit the first output capacitor and transfer the common mode voltage to the first node in a first state, and connect the first output capacitor between the inverting output terminal of the operational amplifier and the first node in a second state; a third switch circuit, connected to the operational amplifier and the first conversion capacitor, configured to connect the first conversion capacitor between the inverting output terminal of the operational amplifier and the non-inverting input terminal of the operational amplifier in a first state, and to connect the first conversion capacitor to a common mode voltage at the inverting output terminal of the operational amplifier in a second state; a fourth switch circuit connected to the operational amplifier, the second node and the second output capacitor, configured to short-circuit the second output capacitor and transfer the common mode voltage to the second node in a first state, and connect the second output capacitor between the non-inverting output terminal of the operational amplifier and the second node in a second state; A fifth switching circuit is connected to the operational amplifier and the second conversion capacitor, and is configured to connect the second conversion capacitor between the positive phase output terminal of the operational amplifier and the inverting input terminal of the operational amplifier in a first state, and to connect the second conversion capacitor to the common mode voltage to the positive phase output terminal of the operational amplifier in a second state.

2. The switched capacitor sampling circuit according to claim 1, characterized in that: The four sampling capacitors are a first sampling capacitor, a second sampling capacitor, a third sampling capacitor, and a fourth sampling capacitor; a first end of the first sampling capacitor and a first end of the second sampling capacitor are connected to the first node, and a first end of the third sampling capacitor and a first end of the fourth sampling capacitor are connected to the second node; The first switch circuit includes a first sampling switch, a second sampling switch, a third sampling switch, a fourth sampling switch, a first conversion switch, a second conversion switch, a third conversion switch, and a fourth conversion switch; The first end of the first sampling switch and the first end of the first conversion switch are used together as the positive sampling voltage input end of the first switch circuit, the second end of the first conversion switch and the first end of the second sampling switch are used together as the first output end of the first switch circuit, and are connected to the second end of the first sampling capacitor, the second end of the second sampling switch and the first end of the second conversion switch are used together as the first reference voltage input end of the first switch circuit, the second end of the first sampling switch and the second end of the second conversion switch are used together as the third output end of the first switch circuit, and are connected to the second end of the third sampling capacitor, The first end of the third sampling switch and the first end of the fourth conversion switch serve together as a negative sampling voltage input end of the first switch circuit, the second end of the third sampling switch and the first end of the third conversion switch serve together as a second output end of the first switch circuit, and are connected to the second end of the second sampling capacitor, the second end of the third conversion switch and the first end of the fourth sampling switch serve together as a second reference voltage input end of the first switch circuit, the second end of the fourth sampling switch and the second end of the fourth conversion switch serve together as a fourth output end of the first switch circuit, and are connected to the second end of the fourth sampling capacitor.

3. The switched capacitor sampling circuit according to claim 1, wherein: The second switch circuit includes a fifth sampling switch, a sixth sampling switch and a fifth conversion switch; The first end of the fifth sampling switch and the first end of the sixth sampling switch serve together as the common mode voltage input end of the second switch circuit; the second end of the fifth sampling switch serves as the common mode voltage output end of the second switch circuit and is connected to the first end of the first output capacitor; the second end of the sixth sampling switch and the first end of the fifth conversion switch are commonly connected to the second end of the first output capacitor; and the second end of the fifth conversion switch is connected to the inverting output end of the operational amplifier.

4. The switched capacitor sampling circuit according to claim 1, wherein: The third switch circuit includes a seventh sampling switch and a sixth conversion switch; The first end of the seventh sampling switch is connected to the non-inverting input end of the operational amplifier, the second end of the seventh sampling switch and the first end of the sixth conversion switch are commonly connected to the first end of the first conversion capacitor, and the second end of the sixth conversion switch is connected to the common mode voltage.

5. The switched capacitor sampling circuit according to claim 1, wherein: The fourth switch circuit includes an eighth sampling switch, a ninth sampling switch and a seventh conversion switch; The first end of the eighth sampling switch and the first end of the ninth sampling switch serve together as the common-mode voltage input end of the fourth switch circuit; the second end of the eighth sampling switch serves as the common-mode voltage output end of the fourth switch circuit and is connected to the first end of the second output capacitor; the second end of the ninth sampling switch and the first end of the seventh conversion switch are commonly connected to the second end of the second output capacitor; and the second end of the seventh conversion switch is connected to the non-inverting output end of the operational amplifier.

6. The switched capacitor sampling circuit according to claim 1, wherein: The fifth switch circuit includes a tenth sampling switch and an eighth conversion switch; The first end of the tenth sampling switch is connected to the inverting input end of the operational amplifier, the second end of the tenth sampling switch and the first end of the eighth conversion switch are commonly connected to the first end of the second conversion capacitor, and the second end of the eighth conversion switch is connected to the common mode voltage.

7. The switched capacitor sampling circuit according to claim 1, characterized in that: The four sampling capacitors are all connected in parallel to a first gain adjustment circuit, wherein the first gain adjustment circuit includes a first selection switch and a first adjustment capacitor; The first end of the first selection switch is connected to the first end of the sampling capacitor, the second end of the first selection switch Sx1 is connected to the first end of the first adjustment capacitor, and the second end of the first adjustment capacitor is connected to the second end of the sampling capacitor.

8. The switched capacitor sampling circuit according to claim 1, wherein: A second gain adjustment circuit is provided between the first node and the inverting input terminal of the operational amplifier, and between the second node and the non-inverting input terminal of the operational amplifier, wherein the second gain adjustment circuit includes a second selection switch, a second adjustment capacitor and a ninth conversion switch; The first end of the ninth conversion switch is connected to the first node or the second node, the second end of the ninth conversion switch is connected to the first end of the second selection switch, the second end of the second selection switch is connected to the first end of the second adjustment capacitor, and the second end of the second adjustment capacitor is connected to the non-inverting input terminal of the operational amplifier or the inverting input terminal of the operational amplifier.

9. An analog-to-digital converter, characterized in that: The analog-to-digital converter comprises a switched capacitor sampling circuit as claimed in any one of claims 1 to 8.

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