Low-voltage operational amplifier for reducing system offset voltage

Abstract

The invention relates to a low-voltage operational amplifier for reducing system offset voltage, which comprises a folded cascode input module (101), a CLASSAB output-stage control circuit (102) and an output-stage module (103), and solves the problems of large system offset voltage, inaccurate output-stage quiescent current control, waste of dynamic power consumption and the like in the existing low-voltage CLASSAB operational amplifier. An output stage quiescent current error caused by a channel length modulation effect is improved, meanwhile, a second stage common-gate tube is added, the current matching of the first stage common-source common-gate tube is improved, the input offset voltage of the operational amplifier system is effectively reduced, and when large pull-sink current exists outside, current limiting is carried out on the CLASSAB output stage control circuit (102), so that the output stage quiescent current error caused by the channel length modulation effect is reduced. Compared with the prior art, the CLASSAB output-stage operational amplifier has the advantages that the internal maximum power consumption is limited, the heating value is reduced, the useless power consumption is reduced, and the application range of the CLASSAB output-stage operational amplifier in a low-voltage and high-precision circuit system is widened.

Description

Technical Field

[0001] The present invention relates to a low-voltage operational amplifier for reducing system offset voltage, and belongs to the technical field of analog integrated circuits. Background Technology

[0002] Common output stage circuits in operational amplifiers mainly include CLASS-A, CLASS-B, and CLASS-AB. Among them, CLASS-AB is widely used because it shows excellent performance when driving large capacitors and small resistors. The working state of the CLASS-AB output stage is between CLASS-A and CLASS-B, which overcomes the disadvantage of low efficiency of the CLASS-A output stage circuit, and also avoids the disadvantage of crossover distortion of the CLASS_B output stage. Therefore, the CLASS_AB output stage has the advantages of low distortion, high efficiency, and moderate power consumption, but its control structure is complex.

[0003] Theoretically, the output resistance of the MOS tube in the saturation region is infinite, but in fact, due to the existence of the channel length modulation effect, the output resistance is not a constant value, but changes with the change of the drain voltage. When the matching MOS tube has the channel length modulation effect, due to the difference in the drain terminal potential, there will be a certain error in the mirror current, which will cause mismatch problems in the internal devices of the op amp, making it difficult to accurately control the static current of the op amp output stage, causing distortion of the op amp output.

[0004] In low voltage CLASS_AB output stage circuits, feedback control bias circuits are often used to control the output tubes of operational amplifiers to determine the quiescent current of the output stage of the operational amplifiers. The prior art CLASS_AB output stage operational amplifier circuits using feedback control bias circuits are as follows Figure 1 As shown, it mainly includes a rail-to-rail input stage circuit, a CLASS_AB control circuit, and an output stage circuit. The rail-to-rail input stage circuit can provide a larger output swing and a higher output impedance. PMOS tubes M1 and M2 are input tubes, and current source I1 provides bias for them; NMOS tubes M3 and M4 are input tubes, and current source I2 provides bias for them. PMOS tubes M10 and M11 are input pairs of tubes of the CLASS_AB bias circuit. PMOS tubes M17, M18, M19, NMOS tubes M8, and NMOS tubes M20 are minimum current selection circuits. NMOS transistor M8 in diode connection mode provides bias for NMOS transistor M11. The current source I5 flows through the NMOS tube M7, and the generated bias voltage provides bias for the NMOS tubes M9 and M10. The output stage circuit includes the PMOS tube M22 and the NMOS tube M21. The capacitors C1 and C2 and the resistors R1 and R2 form a Miller compensation structure to provide frequency compensation for the operational amplifier.

[0005] The quiescent current control accuracy of the output stage circuit is related to the matching between M20 / M21. Since the source-drain voltage VDS of M20 and M21 is different and the VGS is the same, under the effect of the channel length modulation effect, M20 cannot accurately copy the quiescent current of M21, making the quiescent current of the output tube M21 deviate greatly from the theoretical value. When the op amp is working dynamically, if a large current flows through the output tube M21, M20 samples the current of the M21 tube proportionally, which will cause unnecessary power waste and increase the heat generation of the chip.

[0006] On the other hand, channel length modulation will increase the offset voltage of the op amp system. Since the drain voltage of M9 is not equal to the drain voltage of M10 and not equal to the drain voltage of M11, the current flowing through M10 is not equal to the current flowing through M11, and the current flowing through M9 is not equal to the current flowing through M10 + the current flowing through M11, resulting in the drain voltage of M5 not being equal to the drain voltage of M6. In order to make the current flowing through M5 as close as possible to the current flowing through M6, the input will generate an offset voltage.

[0007] In the above CLASS-AB output stage op amp, a feedback-controlled bias circuit is used to control the quiescent current of the output stage. However, due to the channel length modulation effect and the fact that the drain voltage of the sampling tube M20 for sampling the quiescent current of the output stage is not equal to the drain voltage of the output tube M21, the output stage current changes significantly. At the same time, the difference in the VDS voltage of the folded common source and common gate tube will increase the system offset voltage of the op amp. SUMMARY OF THE INVENTION

[0008] The technical problem to be solved by the present invention is to provide a low-voltage operational amplifier with reduced system offset voltage, solve the problems of large system offset voltage, inaccurate output stage quiescent current control, and waste of dynamic power consumption in the existing low-voltage CLASS_AB operational amplifier, and broaden the application of CLASS_AB output stage operational amplifiers in low-voltage, high-precision circuit systems.

[0009] In order to solve the above technical problems, the present invention adopts the following technical scheme: the present invention designs a low-voltage operational amplifier for reducing system offset voltage, including a folded common-source common-gate input module, a CLASS_AB output stage control circuit, and an output stage module, wherein the signal output end of the folded common-source common-gate input module, the signal input end of the CLASS_AB output stage control circuit, and the signal input end of the output stage module are connected; the signal output end of the CLASS_AB output stage control circuit is connected to the feedback input end of the folded common-source common-gate input module, and the signal output end of the output stage module is connected to the feedback input end of the CLASS_AB output stage control circuit and the feedback input end of the folded common-source common-gate input module respectively while outputting; The folded cascode input module performs amplification processing on the input signal received at its signal input end according to the signal received at its feedback input end, generates a control signal and transmits it to the CLASS_AB output stage control circuit and the output stage module respectively. The output stage module receives the control signal from the folded cascode input module and performs processing to obtain the output signal for output, and simultaneously transmits it to the feedback input end of the CLASS_AB output stage control circuit and the feedback input end of the folded cascode input module. The CLASS_AB output stage control circuit performs processing on the control signal received from the folded cascode input module according to the signal received at its feedback input end to obtain the result signal, and transmits it to the feedback input end of the folded cascode input module.

[0010] As a preferred technical solution of the present invention: the CLASS_AB output stage control circuit includes NMOS tube M8, NMOS tube M20, NMOS tube M33, NMOS tube M34, PMOS tube M17, PMOS tube M18, PMOS tube M19, PMOS tube M30, PMOS tube M31, PMOS tube M32, and a sixth current source I6; wherein the source of the PMOS tube M30, the source of the PMOS tube M31, the source of the PMOS tube M32, and the sixth current source I6 are The source of PMOS tube M32 is connected to the external power supply VCC, the gate of PMOS tube M30, the gate of PMOS tube M31, the gate of PMOS tube M32, the drain of PMOS tube M30, and the positive electrode of the sixth current source I6 are connected, the negative electrode of the sixth current source I6 is grounded, the drain of PMOS tube M31 is connected to the source of PMOS tube M17, the drain of PMOS tube M32 is connected to the source of PMOS tube M18, the drain of PMOS tube M17 is connected to the source of PMOS tube M19, and PMOS The gate of S tube M19 constitutes the first signal input terminal of CLASS_AB output stage control circuit, the drain of PMOS tube M19, the gate of NMOS tube M8 and the drain of NMOS tube M8 are connected to constitute the signal output terminal of CLASS_AB output stage control circuit, the source of NMOS tube M8 is grounded, the gate of PMOS tube M17, the gate of PMOS tube M18, the drain of PMOS tube M18, the drain of NMOS tube M33 and the drain of NMOS tube M34 are connected, the gate of NMOS tube M33 constitutes the second signal input terminal of CLASS_AB output stage control circuit, the source of NMOS tube M33, the source of NMOS tube M34 and the drain of NMOS tube M20 are connected, the gate of NMOS tube M20 constitutes the third signal input terminal of CLASS_AB output stage control circuit, the source of NMOS tube M20 is grounded, and the gate of NMOS tube M34 constitutes the feedback input terminal of CLASS_AB output stage control circuit.

[0011] As a preferred technical solution of the present invention: in the structure of the folded cascode input module, the positive electrode of the first current source I1 is connected to an external power supply VCC, the negative electrode of the first current source I1, the source electrode of the PMOS tube M1, and the source electrode of the PMOS tube M2 are connected, the gate electrode of the PMOS tube M2 is connected to the gate electrode of the NMOS tube M3 to form a first feedback input end of the folded cascode input module, which is used to connect the signal output end of the output stage module, the source electrode of the NMOS tube M3, the source electrode of the NMOS tube M4, and the positive electrode of the second current source I2 are connected, the negative electrode of the second current source I2 is grounded, the gate electrode of the PMOS tube M1 is connected to the gate electrode of the NMOS tube M4 to form the signal input end of the folded cascode input module, and the PMOS The source of the transistor M29 is connected to the external power supply VCC, the drain of the PMOS transistor M29, the source of the PMOS transistor M26, and the gate of the PMOS transistor M29 are connected, the gate of the PMOS transistor M26, the gate of the PMOS transistor M27, the gate of the PMOS transistor M28, the drain of the PMOS transistor M26, and the positive electrode of the third current source I3 are connected, the negative electrode of the third current source I3 is grounded, the positive electrode of the fourth current source I4 is connected to the external power supply VCC, the negative electrode of the fourth current source I4, the drain of the NMOS transistor M24, the gate of the NMOS transistor M24, and the gate of the NMOS transistor M25 are connected to form the second signal output end of the folded common source and common gate input module, which is used to connect the second signal of the CLASS_AB output stage control circuit. The input end, the source of the NMOS tube M24, the drain of the NMOS tube M23, and the gate of the NMOS tube M23 are connected, the source of the NMOS tube M23 is grounded, the positive electrode of the fifth current source I5 is externally connected to the power supply VCC, the negative electrode of the fifth current source I5, the drain of the NMOS tube M7, the gate of the NMOS tube M7, the gate of the NMOS tube M9, and the gate of the NMOS tube M10 are connected, the source of the NMOS tube M7 is grounded, the source of the PMOS tube M15 and the source of the PMOS tube M16 are both externally connected to the power supply VCC, the gate of the PMOS tube M15 and the gate of the PMOS tube M16 are connected and externally connected to the first bias voltage VB1, the drain of the PMOS tube M15, the drain of the NMOS tube M3, and the PMOS tube M10 are connected. The sources of the S tube M12 are connected, the drain of the PMOS tube M16, the drain of the NMOS tube M4, the source of the PMOS tube M13, and the source of the PMOS tube M14 are connected, the gate of the PMOS tube M12, the gate of the PMOS tube M13, and the gate of the PMOS tube M14 are connected and externally connected to the second bias voltage VB2, the drain of the PMOS tube M12 is connected to the source of the PMOS tube M27, the drain of the PMOS tube M27, the drain of the NMOS tube M9, the gate of the NMOS tube M5, and the gate of the NMOS tube M6 are connected, the source of the NMOS tube M9, the drain of the PMOS tube M2, and the drain of the NMOS tube M5 are connected, and the source of the NMOS tube M5 is grounded.The drain of the PMOS tube M13 is connected to the drain of the NMOS tube M25 to form the first signal output end of the folded cascode input module, which is used to connect the first signal input end of the CLASS_AB output stage control circuit. The source of the NMOS tube M25 is connected to the drain of the NMOS tube M10. The drain of the PMOS tube M14 is connected to the source of the PMOS tube M28. The drain of the PMOS tube M28 is connected to the drain of the NMOS tube M11 to form the third signal output end of the folded cascode input module, which is used to connect the third signal input end of the CLASS_AB output stage control circuit. The gate of the NMOS tube M11 constitutes the second feedback input end of the folded cascode input module, which is used to connect the signal output end of the CLASS_AB output stage control circuit. The source of the NMOS tube M10, the source of the NMOS tube M11, the drain of the PMOS tube M1, and the drain of the NMOS tube M6 are connected, and the source of the NMOS tube M6 is grounded. ,

[0012] As a preferred technical solution of the present invention: the width-to-length ratio of the PMOS tube M14 is equal to that of the PMOS tube M13, and is half of the width-to-length ratio of the PMOS tube M12; the width-to-length ratio of the NMOS tube M10 is equal to that of the NMOS tube M11, and is half of the width-to-length ratio of the NMOS tube M9.

[0013] As a preferred technical solution of the present invention: the current generated by the first bias voltage VB1 acting on the NMOS tube M15 is K1 times the current at the position set by the fourth current source I4, and the width-to-length ratio of the PMOS tube M27 is twice the width-to-length ratio of the PMOS tube M28.

[0014] As a preferred technical solution of the present invention: the width-to-length ratio of the PMOS tube M29 is adjusted to the width-to-length ratio of the PMOS tube M26, so that the drain voltage of the PMOS tube M13, the drain voltage of the PMOS tube M12, and the drain voltage of the PMOS tube M14 are equal; the width-to-length ratio of the NMOS tube M23 and the width-to-length ratio of the NMOS tube M24 are adjusted to make the drain voltage of the PMOS tube M10 equal to the drain voltage of the NMOS tube M11.

[0015] As a preferred technical solution of the present invention: the output stage module includes an NMOS tube M21, a PMOS tube M22, a Miller capacitor C1, a Miller capacitor C2, a zero adjustment resistor R1, and a zero adjustment resistor R2, wherein the source of the PMOS tube M22 is externally connected to a power supply VCC, the gate of the PMOS tube M22 is connected to one end of the Miller capacitor C1 to form a first signal input end of the output stage module, and is used to be connected to the first signal input end of the CLASS_AB output stage control circuit, the other end of the Miller capacitor C1 is connected to one end of the zero adjustment resistor R1, the other end of the zero adjustment resistor R1, the drain of the PMOS tube M22 , one end of the zero adjustment resistor R2, and the drain of the NMOS tube M21 are connected to form the signal output end of the output stage module. While the signal output end of the output stage module is outputting, it is respectively connected to the feedback input end of the CLASS_AB output stage control circuit and the feedback input end of the folded common source and common gate input module. The other end of the zero adjustment resistor R2 is connected to one end of the Miller capacitor C2, and the other end of the Miller capacitor C2 is connected to the gate of the NMOS tube M21 to form the second signal input end of the output stage module, which is used to be connected to the third signal input end of the CLASS_AB output stage control circuit. The source of the NMOS tube M21 is grounded.

[0016] As a preferred technical solution of the present invention: the width-to-length ratio of the PMOS tube M19, the width-to-length ratio of the PMOS tube M17, and the width-to-length ratio of the PMOS tube M18 are consistent, and are 1 / K3 times the width-to-length ratio of the PMOS output tube M22, the width-to-length ratio of the NMOS output tube M21 is K1 times the width-to-length ratio of the NMOS tube M20, and K3=K1.

[0017] As a preferred technical solution of the present invention: the width-to-length ratio of the PMOS tube M31 and the width-to-length ratio of the PMOS tube M32 are both K2 times the width-to-length ratio of the PMOS tube M30.

[0018] The low-voltage operational amplifier for reducing system offset voltage described in the present invention adopts the above technical solution and has the following technical effects compared with the prior art: The present invention designs a low-voltage operational amplifier for reducing system offset voltage, including a folded common-source common-gate input module, a CLASS_AB output stage control circuit, and an output stage module, which solves the problems of large system offset voltage, inaccurate output stage static current control, and waste of dynamic power consumption in existing low-voltage CLASS_AB operational amplifiers, improves the output stage static current error caused by the channel length modulation effect, and at the same time, by adding a second-stage common-gate tube, the current matching of the first-stage common-source common-gate tube is improved, and the input offset voltage of the operational amplifier system is effectively reduced. When there is a large external pull-in current, the CLASS_AB output stage control circuit is current-limited to limit the internal maximum power consumption, that is, the heat generation is reduced, and the useless power consumption is reduced, which broadens the application of the CLASS_AB output stage operational amplifier in low-voltage, high-precision circuit systems. Brief Description of the Figures

[0019] Figure 1 is the schematic diagram of the existing CLASS_AB output stage operational amplifier circuit; Figure 2 This is a schematic diagram of the low-voltage CLASS_AB output stage control circuit designed by the present invention.

[0020] Among them, 101. Folded common source and common gate input module, 102. CLASS_AB output stage control circuit, 103. Output stage module. Specific implementation method

[0021] The following is a further detailed description of the specific implementation of the present invention in conjunction with the accompanying drawings.

[0022] The present invention designs a low voltage operational amplifier for reducing the system offset voltage, such as Figure 2 As shown, the design includes a folded cascode input module 101, a CLASS_AB output stage control circuit 102, and an output stage module 103, wherein the signal output end of the folded cascode input module 101, the signal input end of the CLASS_AB output stage control circuit 102, and the signal input end of the output stage module 103 are connected; the signal output end of the CLASS_AB output stage control circuit 102 is connected to the feedback input end of the folded cascode input module 101, and the signal output end of the output stage module 103 is connected to the feedback input end of the CLASS_AB output stage control circuit 102 and the feedback input end of the folded cascode input module 101 respectively while outputting.

[0023] The folded cascode input module 101 performs amplification processing on the input signal received at its signal input end according to the signal received at its feedback input end, generates a control signal and transmits it to the CLASS_AB output stage control circuit 102 and the output stage module 103 respectively. The output stage module 103 receives the control signal from the folded cascode input module 101 and performs processing to obtain the output signal to output and drive the external load, and simultaneously transmits it to the feedback input end of the CLASS_AB output stage control circuit 102 and the feedback input end of the folded cascode input module 101. The CLASS_AB output stage control circuit 102 performs processing on the control signal received from the folded cascode input module 101 according to the signal received at its feedback input end to obtain the result signal, and transmits it to the feedback input end of the folded cascode input module 101.

[0024] According to the above design, in actual application, the folded common source and common gate input module 101, the CLASS_AB output stage control circuit 102, and the output stage module 103 are specifically designed, wherein Figure 2As shown, the folded common source and common gate input module 101 receives the feedback signal from the CLASS_AB output stage control circuit 102 and generates a bias voltage of the output transistor to control the output stage static current. The design includes NMOS tube M8, NMOS tube M20, NMOS tube M33, NMOS tube M34, PMOS tube M17, PMOS tube M18, PMOS tube M19, PMOS tube M30, PMOS tube M31, PMOS tube M32, and a sixth current source I6; wherein, the PMOS tube M3 The source of the PMOS tube M0, the source of the PMOS tube M31, and the source of the PMOS tube M32 are all connected to the external power supply VCC, the gate of the PMOS tube M30, the gate of the PMOS tube M31, the gate of the PMOS tube M32, the drain of the PMOS tube M30, and the positive electrode of the sixth current source I6 are connected, the negative electrode of the sixth current source I6 is grounded, the drain of the PMOS tube M31 is connected to the source of the PMOS tube M17, the drain of the PMOS tube M32 is connected to the source of the PMOS tube M18, and the drain of the PMOS tube M17 is connected to the positive electrode of the PMOS tube M19. The source of the PMOS tube M19 and the gate of the PMOS tube M19 constitute the first signal input terminal of the CLASS_AB output stage control circuit 102. The drain of the PMOS tube M19, the gate of the NMOS tube M8, and the drain of the NMOS tube M8 are connected to form the signal output terminal of the CLASS_AB output stage control circuit 102. The source of the NMOS tube M8 is grounded. The gate of the PMOS tube M17, the gate of the PMOS tube M18, the drain of the PMOS tube M18, the drain of the NMOS tube M33, and the drain of the NMOS tube M34 are connected to each other. The drains of the five transistors are connected, the gate of the NMOS transistor M33 constitutes the second signal input terminal of the CLASS_AB output stage control circuit 102, the source of the NMOS transistor M33, the source of the NMOS transistor M34, and the drain of the NMOS transistor M20 are connected, the gate of the NMOS transistor M20 constitutes the third signal input terminal of the CLASS_AB output stage control circuit 102, the source of the NMOS transistor M20 is grounded, and the gate of the NMOS transistor M34 constitutes the feedback input terminal of the CLASS_AB output stage control circuit 102.

[0025] Based on the above specific design structure of the CLASS_AB output stage control circuit 102, the structure of the folded common source and common gate input module 101 is further designed, as shown in Figure 2As shown, the positive electrode of the first current source I1 is connected to the external power supply VCC, the negative electrode of the first current source I1, the source of the PMOS tube M1, and the source of the PMOS tube M2 are connected, the gate of the PMOS tube M2 is connected to the gate of the NMOS tube M3 to form the first feedback input end of the folded common source and common gate input module 101, which is used to connect the signal output end of the output stage module 103, the source of the NMOS tube M3, the source of the NMOS tube M4, and the positive electrode of the second current source I2 are connected, the negative electrode of the second current source I2 is grounded, the gate of the PMOS tube M1 is connected to the gate of the NMOS tube M4 to form the signal input end of the folded common source and common gate input module 101, and the source of the PMOS tube M29 is connected to the external power supply VCC , the drain of the PMOS tube M29, the source of the PMOS tube M26, and the gate of the PMOS tube M29 are connected, the gate of the PMOS tube M26, the gate of the PMOS tube M27, the gate of the PMOS tube M28, the drain of the PMOS tube M26, and the positive electrode of the third current source I3 are connected, the negative electrode of the third current source I3 is grounded, the positive electrode of the fourth current source I4 is connected to the external power supply VCC, the negative electrode of the fourth current source I4, the drain of the NMOS tube M24, the gate of the NMOS tube M24, and the gate of the NMOS tube M25 are connected to form the second signal output end of the folded common source and common gate input module 101, which is used to connect the second signal input end of the CLASS_AB output stage control circuit 102, N The source of the MOS tube M24, the drain of the NMOS tube M23, and the gate of the NMOS tube M23 are connected, the source of the NMOS tube M23 is grounded, the positive electrode of the fifth current source I5 is externally connected to the power supply VCC, the negative electrode of the fifth current source I5, the drain of the NMOS tube M7, the gate of the NMOS tube M7, the gate of the NMOS tube M9, and the gate of the NMOS tube M10 are connected, the source of the NMOS tube M7 is grounded, the source of the PMOS tube M15 and the source of the PMOS tube M16 are both externally connected to the power supply VCC, the gate of the PMOS tube M15 and the gate of the PMOS tube M16 are connected and externally connected to the first bias voltage VB1, the drain of the PMOS tube M15, the drain of the NMOS tube M3, and the PMOS tube M10 are connected. The sources of the PMOS tube M12 are connected, the drain of the PMOS tube M16, the drain of the NMOS tube M4, the source of the PMOS tube M13, and the source of the PMOS tube M14 are connected, the gate of the PMOS tube M12, the gate of the PMOS tube M13, and the gate of the PMOS tube M14 are connected and externally connected to the second bias voltage VB2, the drain of the PMOS tube M12 is connected to the source of the PMOS tube M27, the drain of the PMOS tube M27, the drain of the NMOS tube M9, the gate of the NMOS tube M5, and the gate of the NMOS tube M6 are connected, the source of the NMOS tube M9, the drain of the PMOS tube M2, and the drain of the NMOS tube M5 are connected, and the source of the NMOS tube M5 is grounded.The drain of the PMOS tube M13 is connected to the drain of the NMOS tube M25 to form the first signal output terminal of the folded common source and common gate input module 101, which is used to connect the first signal input terminal of the CLASS_AB output stage control circuit 102. The source of the NMOS tube M25 is connected to the drain of the NMOS tube M10, the drain of the PMOS tube M14 is connected to the source of the PMOS tube M28, and the drain of the PMOS tube M28 is connected to the drain of the NMOS tube M11 to form the folded common source and common gate input module. The third signal output terminal of the block 101 is used to connect the third signal input terminal of the CLASS_AB output stage control circuit 102. The gate of the NMOS tube M11 constitutes the second feedback input terminal of the folded common source and common gate input module 101, which is used to connect the signal output terminal of the CLASS_AB output stage control circuit 102. The source of the NMOS tube M10, the source of the NMOS tube M11, the drain of the PMOS tube M1, and the drain of the NMOS tube M6 are connected, and the source of the NMOS tube M6 is grounded. ,

[0026] In the application of the folded common source and common gate input module 101, the NMOS tube M7 cooperates with the current source I5 to provide bias for the NMOS tubes M9 and NMOSM10 of the common gate connection structure, the NMOS tubes M23 and M24 are diode-connected, and cooperate with the current source I4 to provide bias for the NMOS tube M25 of the second common gate structure, and the PMOS tubes M12, M13, and M14 are also common gate structures. The PMOS tubes M29 and M26 are diode-connected, and cooperate with the current source I3 to provide bias for the PMOS tubes M27 and M28 of the second common gate structure.

[0027] Regarding the output stage module 103, in practical applications, such as Figure 2As shown, the design includes an NMOS tube M21, a PMOS tube M22, a Miller capacitor C1, a Miller capacitor C2, a zeroing resistor R1, and a zeroing resistor R2, wherein the source of the PMOS tube M22 is externally connected to a power supply VCC, the gate of the PMOS tube M22 is connected to one end of the Miller capacitor C1 to form a first signal input end of the output stage module 103, and is used to be connected to the first signal input end of the CLASS_AB output stage control circuit 102, the other end of the Miller capacitor C1 is connected to one end of the zeroing resistor R1, the other end of the zeroing resistor R1, the drain of the PMOS tube M22, one end of the zeroing resistor R2, and the NMOS tube M22 are connected to the output stage module 103. The drains of the OS tube M21 are connected to form the signal output end of the output stage module 103. When the signal output end of the output stage module 103 is output, it is connected to the feedback input end of the CLASS_AB output stage control circuit 102 and the feedback input end of the folded common source and common gate input module 101 respectively. The other end of the zero adjustment resistor R2 is connected to one end of the Miller capacitor C2. The other end of the Miller capacitor C2 is connected to the gate of the NMOS tube M21 to form the second signal input end of the output stage module 103, which is used to connect to the third signal input end of the CLASS_AB output stage control circuit 102. The source of the NMOS tube M21 is grounded. In the application, the output stage module 103 is used to drive the external load, and the frequency response characteristics of the operational amplifier are compensated by the Miller capacitor and the zero adjustment resistor.

[0028] The above design is applied in practice, and the width-to-length ratio of the PMOS tube M14 is further specifically designed to be equal to that of the PMOS tube M13, and half of that of the PMOS tube M12; the width-to-length ratio of the NMOS tube M10 is equal to that of the NMOS tube M11, and half of that of the NMOS tube M9; the current generated by the first bias voltage VB1 acting on the NMOS tube M15 is K1 times the current at the position set by the fourth current source I4, and the width-to-length ratio of the PMOS tube M27 is The width-to-length ratio of the PMOS tube M28 is twice that of the PMOS tube M28; the width-to-length ratios of the PMOS tube M19, the PMOS tube M17, and the PMOS tube M18 are consistent and are 1 / K3 times the width-to-length ratio of the PMOS output tube M22; the width-to-length ratio of the NMOS output tube M21 is K1 times the width-to-length ratio of the NMOS tube M20, and K3=K1; the width-to-length ratios of the PMOS tube M31 and the PMOS tube M32 are both K2 times the width-to-length ratio of the PMOS tube M30. In the application, the width-to-length ratio of the PMOS tube M29 is adjusted to the width-to-length ratio of the PMOS tube M26, so that the drain voltage of the PMOS tube M13, the drain voltage of the PMOS tube M12, and the drain voltage of the PMOS tube M14 are equal; the width-to-length ratio of the NMOS tube M23 and the width-to-length ratio of the NMOS tube M24 are adjusted to make the drain voltage of the PMOS tube M10 equal to the drain voltage of the NMOS tube M11.

[0029] In the specific implementation and application of the above-mentioned design circuit, for the folded common source and common gate input module 101, the NMOS tube M10 and the NMOS tube M11 are used as differential input ports, and the NMOS tube M7 in the diode connection mode generates a reference voltage V3 under the action of the current source I5. The function of the CLASS_AB output stage control circuit 102 is to proportionally mirror the current of the NMOS output tube M21 through the NMOS tube M20, and this current flows through the PMOS tube M18 in the diode connection mode. Since the gate terminal voltages of the PMOS tube M17 and the PMOS tube M19 are similar, the PMOS tube M17 and the PMOS tube M19 can be equivalent to a PMOS tube with a gate length of 2L, where L represents the length of the MOS tube, so the current flowing through the PMOS tube M17 and the PMOS tube M19 is the current flowing through the NMOS tube M20. Half of the current of the MOS tube M20 flows through the NMOS tube M8 in the diode connection mode, that is, the voltage V4 output by the NMOS tube M8 to the NMOS tube M11 is generated. Under the feedback control of the loop in the folded common source and common gate input module 101 and the CLASS_AB output stage control circuit 102, the current output by the PMOS tube M19 is equal to the current at the position set by the current source I5, so that the voltage V4 output by the NMOS tube M8 is equal to the voltage V3 output by the NMOS tube M7, that is, Figure 2In the figure, V3=V4, the static current of the PMOS tube M21 and the NMOS tube M22 in the output stage module 103 is confirmed to be 2*K3*the position current set by the current source I5. The accuracy of this current is determined by the matching of the NMOS tube M20 and the NMOS output tube M21. In order to reduce the influence of the channel length modulation effect on the mirror current accuracy, the NMOS tube M33 and the NMOS tube M34 are further designed to reduce the influence of the channel length modulation effect. Define the sum of the gate-source voltage of NMOS tube M23 and the gate-source voltage of NMOS tube M24 as V2. When the Vout of the signal output end of the output stage module 103 is less than the result of V2 minus the gate-source voltage of NMOS tube M33, the drain voltage difference between NMOS tube M20 and NMOS output tube M21 is controlled by NMOS tube M33. When the Vout of the signal output end of the output stage module 103 is greater than the result of V2 minus the gate-source voltage of NMOS tube M33, the drain voltage difference between NMOS tube M20 and NMOS output tube M21 is controlled by NMOS tube M33. In the application, the current at the set position of current source I1 is equal to the current at the set position of current source I2, and the current at the set position of current source I3 is equal to the current at the set position of current source I4.

[0030] Regarding the design of the NMOS tube M25, PMOS tube M27, and PMOS tube M28 in the present invention with the second common-gate structure, if the power supply voltage is high before the addition, then at this time, due to the channel length modulation effect, the sum of the current flowing through the NMOS tube M10 and the current flowing through the NMOS tube M11 is greater than the current flowing through the NMOS tube M9. Since the gate of the NMOS tube M5 is connected to the gate of the NMOS tube M6, the difference in the drain terminal voltage is very small, so the current flowing through the NMOS tube M5 is equal to the current flowing through the NMOS tube M6. Then the current relationship of the input tube is: , the system input offset voltage is , among which, represents the current flowing through the PMOS tube M2, represents the current flowing through the PMOS tube M1, represents the current flowing through NMOS tube M10, indicates the current flowing through NMOS tube M11, represents the current flowing through NMOS tube M9, represents the transconductance of the PMOS tube M1; after adding the NMOS tube M25, PMOS tube M27, and PMOS tube M28 of the second common-gate tube structure, the channel length modulation effect is improved, Approaching zero, greatly reducing the system input offset voltage.

[0031] Regarding the design of adding PMOS tube M30, PMOS tube M31, PMOS tube M32, and current source I6 to the present invention, if before adding, if an external load injects a large current into the output stage NMOS tube M21, since NMOS tube M20 is a proportional mirror image of the current of the output stage NMOS tube M21, a large current will also flow through NMOS tube M20 at this time, and this current is provided by the external power supply of the system, and the power consumption of the operational amplifier increases greatly at this time. After adding PMOS tube M30, PMOS tube M31, PMOS tube M32, and current source I6, the external load injects a large current into the output stage NMOS tube M21, and the drain voltage of PMOS tube M31 and PMOS tube M32 drops and enters the saturation region. At this time, the current flowing through them is determined by the ratio of current source I6, PMOS tube M30, PMOS tube M31, and PMOS tube M32, and the power consumption of the system is controlled.

[0032] Using the above structure to control the output stage transistors, the drain-source voltage difference of the matched transistors is controlled, which solves the problem of increased input offset voltage of the system caused by the channel length modulation effect and inaccurate static current control of the output stage transistors. It also solves the problem that the system dynamic power consumption cannot be effectively controlled.

[0033] The low-voltage operational amplifier designed by the above technical solution to reduce the system offset voltage includes a folded common-source common-gate input module 101, a CLASS_AB output stage control circuit 102, and an output stage module 103, which solves the problems of large system offset voltage, inaccurate output stage static current control, and waste of dynamic power consumption in the existing low-voltage CLASS_AB operational amplifier, improves the output stage static current error caused by the channel length modulation effect, and at the same time, by adding a second-stage common-gate tube, the current matching of the first-stage common-source common-gate tube is improved, and the input offset voltage of the operational amplifier system is effectively reduced. When there is a large external pull-in current, the CLASS_AB output stage control circuit 102 is current-limited to limit the internal maximum power consumption, which reduces both the heat generation and the useless power consumption, and broadens the application of the CLASS_AB output stage operational amplifier in low-voltage, high-precision circuit systems.

[0034] The embodiments of the present invention are described in detail above in conjunction with the accompanying drawings, but the present invention is not limited to the above embodiments, and various changes can be made within the knowledge scope of ordinary technicians in the field without departing from the purpose of the present invention.

Claims

1. A low voltage operational amplifier for reducing system offset voltage, characterized in that: It comprises a folded cascode input module (101), a CLASS_AB output stage control circuit (102), and an output stage module (103), wherein the signal output end of the folded cascode input module (101), the signal input end of the CLASS_AB output stage control circuit (102), and the signal input end of the output stage module (103) are connected; the signal output end of the CLASS_AB output stage control circuit (102) is connected to the feedback input end of the folded cascode input module (101), and the signal output end of the output stage module (103) is connected to the feedback input end of the CLASS_AB output stage control circuit (102) and the feedback input end of the folded cascode input module (101) respectively while outputting; The folded cascode input module (101) performs amplification processing on the input signal received at its signal input end according to the signal received at its feedback input end, generates a control signal, and transmits it to the CLASS_AB output stage control circuit (102) and the output stage module (103) respectively; the output stage module (103) receives the control signal from the folded cascode input module (101), performs processing, obtains an output signal, outputs it, and transmits it to the feedback input end of the CLASS_AB output stage control circuit (102) and the feedback input end of the folded cascode input module (101) at the same time; the CLASS_AB output stage control circuit (102) performs processing on the control signal received from the folded cascode input module (101) according to the signal received at its feedback input end, obtains a result signal, and transmits it to the feedback input end of the folded cascode input module (101).

2. A low voltage operational amplifier for reducing system offset voltage according to claim 1, characterized in that: The CLASS_AB output stage control circuit (102) comprises an NMOS tube M8, an NMOS tube M20, an NMOS tube M33, an NMOS tube M34, a PMOS tube M17, a PMOS tube M18, a PMOS tube M19, a PMOS tube M30, a PMOS tube M31, a PMOS tube M32, and a sixth current source I6; wherein the source of the PMOS tube M30, the source of the PMOS tube M31, and the source of the PMOS tube M32 are all externally connected to a power supply VCC, and the PMOS tube M17 is connected to a power supply VCC. The gate of the S tube M30, the gate of the PMOS tube M31, the gate of the PMOS tube M32, the drain of the PMOS tube M30, and the positive electrode of the sixth current source I6 are connected. The negative electrode of the sixth current source I6 is grounded. The drain of the PMOS tube M31 is connected to the source of the PMOS tube M17. The drain of the PMOS tube M32 is connected to the source of the PMOS tube M18. The drain of the PMOS tube M17 is connected to the source of the PMOS tube M19. The gate of the PMOS tube M19 constitutes the CLASS_AB output. The first signal input terminal of the class control circuit (102), the drain of the PMOS tube M19, the gate of the NMOS tube M8, and the drain of the NMOS tube M8 are connected to form a signal output terminal of the CLASS_AB output class control circuit (102), the source of the NMOS tube M8 is grounded, the gate of the PMOS tube M17, the gate of the PMOS tube M18, the drain of the PMOS tube M18, the drain of the NMOS tube M33, and the drain of the NMOS tube M34 are connected, and the NMOS tube M33 is connected to the ground. The gate of the NMOS tube M33 constitutes a second signal input terminal of the CLASS_AB output stage control circuit (102); the source of the NMOS tube M33, the source of the NMOS tube M34 and the drain of the NMOS tube M20 are connected; the gate of the NMOS tube M20 constitutes a third signal input terminal of the CLASS_AB output stage control circuit (102); the source of the NMOS tube M20 is grounded; and the gate of the NMOS tube M34 constitutes a feedback input terminal of the CLASS_AB output stage control circuit (102).

3. A low voltage operational amplifier for reducing system offset voltage according to claim 2, characterized in that: In the structure of the folded cascode input module (101), the positive electrode of the first current source I1 is connected to an external power supply VCC, the negative electrode of the first current source I1, the source electrode of the PMOS tube M1, and the source electrode of the PMOS tube M2 are connected, the gate electrode of the PMOS tube M2 is connected to the gate electrode of the NMOS tube M3 to form a first feedback input end of the folded cascode input module (101), which is used to connect to the signal output end of the output stage module (103), the source electrode of the NMOS tube M3, the source electrode of the NMOS tube M4, and the positive electrode of the second current source I2 are connected, the negative electrode of the second current source I2 is grounded, and the gate electrode of the PMOS tube M1 is connected to the gate electrode of the NMOS tube M4 to form a signal input end of the folded cascode input module (101). The source of the PMOS tube M29 is connected to an external power supply VCC, the drain of the PMOS tube M29, the source of the PMOS tube M26, and the gate of the PMOS tube M29 are connected, the gate of the PMOS tube M26, the gate of the PMOS tube M27, the gate of the PMOS tube M28, the drain of the PMOS tube M26, and the positive electrode of the third current source I3 are connected, the negative electrode of the third current source I3 is grounded, the positive electrode of the fourth current source I4 is connected to an external power supply VCC, the negative electrode of the fourth current source I4, the drain of the NMOS tube M24, the gate of the NMOS tube M24, and the gate of the NMOS tube M25 are connected to form a second signal output end of the folded common source and common gate input module (101), which is used to connect the CLASS_AB output stage At a second signal input terminal of the control circuit (102), the source of the NMOS tube M24, the drain of the NMOS tube M23, and the gate of the NMOS tube M23 are connected, the source of the NMOS tube M23 is grounded, the positive electrode of the fifth current source I5 is externally connected to the power supply VCC, the negative electrode of the fifth current source I5, the drain of the NMOS tube M7, the gate of the NMOS tube M7, the gate of the NMOS tube M9, and the gate of the NMOS tube M10 are connected, the source of the NMOS tube M7 is grounded, the source of the PMOS tube M15 and the source of the PMOS tube M16 are both externally connected to the power supply VCC, the gate of the PMOS tube M15 and the gate of the PMOS tube M16 are connected and externally connected to the first bias voltage VB1, the drain of the PMOS tube M15, The drain of the NMOS tube M3 and the source of the PMOS tube M12 are connected, the drain of the PMOS tube M16, the drain of the NMOS tube M4, the source of the PMOS tube M13, and the source of the PMOS tube M14 are connected, the gate of the PMOS tube M12, the gate of the PMOS tube M13, and the gate of the PMOS tube M14 are connected and externally connected to the second bias voltage VB2, the drain of the PMOS tube M12 is connected to the source of the PMOS tube M27, the drain of the PMOS tube M27, the drain of the NMOS tube M9, the gate of the NMOS tube M5, and the gate of the NMOS tube M6 are connected, the source of the NMOS tube M9, the drain of the PMOS tube M2, and the drain of the NMOS tube M5 are connected,The source of the NMOS tube M5 is grounded, the drain of the PMOS tube M13 is connected to the drain of the NMOS tube M25 to form a first signal output end of the folded common source and common gate input module (101), which is used to connect to the first signal input end of the CLASS_AB output stage control circuit (102), the source of the NMOS tube M25 is connected to the drain of the NMOS tube M10, the drain of the PMOS tube M14 is connected to the source of the PMOS tube M28, and the drain of the PMOS tube M28 is connected to the drain of the NMOS tube M11 to form a folded common source. The third signal output terminal of the common-gate input module (101) is used to connect to the third signal input terminal of the CLASS_AB output stage control circuit (102); the gate of the NMOS tube M11 constitutes the second feedback input terminal of the folded common-source common-gate input module (101) and is used to connect to the signal output terminal of the CLASS_AB output stage control circuit (102); the source of the NMOS tube M10, the source of the NMOS tube M11, the drain of the PMOS tube M1, and the drain of the NMOS tube M6 are connected; the source of the NMOS tube M6 is grounded.

4. A low voltage operational amplifier for reducing system offset voltage according to claim 3, characterized in that: The width-to-length ratio of the PMOS tube M14 is equal to that of the PMOS tube M13 and is half of that of the PMOS tube M12; the width-to-length ratio of the NMOS tube M10 is equal to that of the NMOS tube M11 and is half of that of the NMOS tube M9.

5. A low voltage operational amplifier for reducing system offset voltage according to claim 3, characterized in that: The current generated by the first bias voltage VB1 acting on the NMOS tube M15 is K1 times the current set by the fourth current source I4, and the width-to-length ratio of the PMOS tube M27 is twice the width-to-length ratio of the PMOS tube M28.

6. A low voltage operational amplifier for reducing system offset voltage according to claim 3, characterized in that: The width-to-length ratio of the PMOS tube M29 and the width-to-length ratio of the PMOS tube M26 are adjusted to make the drain voltage of the PMOS tube M13, the drain voltage of the PMOS tube M12, and the drain voltage of the PMOS tube M14 equal; the width-to-length ratio of the NMOS tube M23 and the width-to-length ratio of the NMOS tube M24 are adjusted to make the drain voltage of the PMOS tube M10 equal to the drain voltage of the NMOS tube M11.

7. A low voltage operational amplifier for reducing system offset voltage according to claim 2, characterized in that: The output stage module (103) comprises an NMOS tube M21, a PMOS tube M22, a Miller capacitor C1, a Miller capacitor C2, a zero adjustment resistor R1, and a zero adjustment resistor R2, wherein the source of the PMOS tube M22 is externally connected to a power supply VCC, the gate of the PMOS tube M22 is connected to one end of the Miller capacitor C1 to form a first signal input end of the output stage module (103), and is used to be connected to the first signal input end of the CLASS_AB output stage control circuit (102), the other end of the Miller capacitor C1 is connected to one end of the zero adjustment resistor R1, the other end of the zero adjustment resistor R1, the drain of the PMOS tube M22, one end of the zero adjustment resistor R2, the NMOS tube M22, and the gate of the PMOS tube M22 are connected to one end of the Miller capacitor C1 to form a first signal input end of the output stage module (103), and is used to be connected to the first signal input end of the CLASS_AB output stage control circuit (102), the other end of the Miller capacitor C1 is connected to one end of the zero adjustment resistor R1, and the other end of the zero adjustment resistor R1, the drain of the PMOS tube M22, one end of the zero adjustment resistor R2, and the NMOS tube M22 are connected to one end of the zero adjustment resistor R2. The drains of the OS transistor M21 are connected to form a signal output end of the output stage module (103). When the signal output end of the output stage module (103) outputs, the drains are connected to the feedback input end of the CLASS_AB output stage control circuit (102) and the feedback input end of the folded common source and common gate input module (101) respectively. The other end of the zero adjustment resistor R2 is connected to one end of the Miller capacitor C2. The other end of the Miller capacitor C2 is connected to the gate of the NMOS transistor M21 to form a second signal input end of the output stage module (103), which is used to be connected to the third signal input end of the CLASS_AB output stage control circuit (102). The source of the NMOS transistor M21 is grounded.

8. A low voltage operational amplifier for reducing system offset voltage according to claim 7, characterized in that: The width-to-length ratios of the PMOS tube M19, the PMOS tube M17, and the PMOS tube M18 are consistent and are 1 / K3 times the width-to-length ratio of the PMOS output tube M22. The width-to-length ratio of the NMOS output tube M21 is K1 times the width-to-length ratio of the NMOS tube M20, and K3=K1.

9. A low voltage operational amplifier for reducing system offset voltage according to claim 2, characterized in that: The width-to-length ratio of the PMOS tube M31 and the width-to-length ratio of the PMOS tube M32 are both K2 times the width-to-length ratio of the PMOS tube M30.

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