A six-fold quasi-periodic photonic crystal all-optical logic gate capable of realizing seven logical states

Abstract

The present invention provides a six-fold quasi-periodic photonic crystal all-optical logic gate capable of realizing seven logical states. The gate comprises a plurality of dielectric pillars arranged in a six-fold quasi-periodic pattern to form a plurality of concentric rings. Four waveguides are constructed by deleting one row of dielectric pillars counterclockwise from the center of the logic gate in the directions of 0°, 180°, 240°, and 300°, two of which serve as input ports and the other two as output ports. The logical states of the input ports are controlled using BPSK technology. Without changing the photonic crystal structure, the present invention generates seven different logical states by changing the initial phases of the two input ports, causing signal light of different phases to interfere within the photonic crystal.

Description

Technical Field

[0001] The present invention relates to the technical field of photonic crystal logic gates, and in particular to a quasi-periodic photonic crystal all-optical logic gate capable of realizing seven logic states. Background Art

[0002] Since the third scientific and technological revolution, continuous advancements in integrated process technology have dramatically increased the information storage capacity and processing speed of semiconductor electronic chips. However, in recent decades, people have placed higher demands on the ability of devices to receive, transmit, and process information, and the heat generation and transmission losses of semiconductor electronic chips have long impacted their performance. Photonic crystals, artificial microstructures with a periodic arrangement of refractive indices, have attracted the attention of researchers due to their low power consumption, stable performance, and low heat generation.

[0003] In future all-optical networks, optical switching, optical computing, and optical transmission will be the core elements of all-optical signal processing, all of which rely on all-optical logic gates. Therefore, designing compact, low-latency all-optical logic structures is crucial. Current all-optical logic gates require changes to the basic photonic crystal structure and optical power during logic conversion, making them difficult to implement in practical applications. Furthermore, most structures can only implement two or three of the seven basic logic gates, resulting in limited functionality. Summary of the Invention

[0004] In view of the shortcomings of the prior art, the present invention provides a quasi-periodic photonic crystal all-optical logic gate that can realize seven logical states, which can generate seven different logical states without changing the photonic crystal structure.

[0005] The present invention achieves the above technical objectives through the following technical means.

[0006] A six-fold quasi-periodic photonic crystal all-optical logic gate capable of realizing seven logical states comprises a plurality of dielectric pillars arranged in a six-fold quasi-periodic pattern to form a plurality of concentric rings. Four waveguides are constructed by deleting one row of dielectric pillars counterclockwise from the center of the logic gate in the directions of 0°, 180°, 240°, and 300°, two of which serve as input ports and the other two as output ports. The logical states of the input ports are controlled using BPSK technology.

[0007] Furthermore, two phase modulators are included, and the two input ports correspond to one phase modulator respectively, and the phase of the input port signal is controlled by the phase modulator.

[0008] Furthermore, the material of the dielectric column is silicon, and the background medium is air.

[0009] Furthermore, the refractive index of the dielectric column is 3.48, and the refractive index of air is 1.

[0010] Furthermore, the radial distance between two adjacent concentric rings is a, and the radius of the dielectric column r=0.11*a.

[0011] Furthermore, two waveguides at 240° and 300° counterclockwise from the center of the logic gate are two input ports.

[0012] Furthermore, for the first input port, the input light phase of π is regarded as logic 0, and the input light phase of 0 is regarded as logic 1. For the second input port, the input light phase of -π / 2 is regarded as logic 0, and the input light phase of π / 2 is regarded as logic 1, realizing the XOR and XNOR logic gates.

[0013] Furthermore, for the first input port, an input light phase of π / 2 is considered as a logic 1, and an input light phase of 0 is considered as a logic 0; for the second input port, an input light phase of π is considered as a logic 1, and an input light phase of -π / 2 is considered as a logic 0, realizing two logic gates, NOR and AND.

[0014] Furthermore, for the first input port, an input light phase of π / 2 is regarded as a logic 1, and an input light phase of 0 is regarded as a logic 0; for the second input port, an input light phase of π is regarded as a logic 1, and an input light phase of -π / 2 is regarded as a logic 0, thereby realizing two logic gates, OR and NAND.

[0015] Furthermore, for the first input port that continuously emits light with a phase of π, for the second input port, the input light with a phase of π / 2 is regarded as logic 1, and the input light with a phase of -π / 2 is regarded as logic 0, thereby realizing a NOT logic gate.

[0016] Beneficial effects of the present invention:

[0017] 1) The quasi-periodic photonic crystal all-optical logic gate of this invention does not require changing the structure of the photonic crystal when performing logic conversion. The control method is simple and fast, and can achieve real-time and effective control.

[0018] 2) The quasi-periodic photonic crystal all-optical logic gate of the present invention can realize all seven basic logic gates, with a short response time and a small footprint. BRIEF DESCRIPTION OF THE DRAWINGS

[0019] Figure 1 This is a schematic diagram of the Sunflower-type six-fold quasi-periodic photonic crystal structure;

[0020] Figure 2 2 is a schematic structural diagram of a quasi-periodic photonic crystal all-optical logic gate capable of realizing seven logic states according to an embodiment of the present invention;

[0021] Figure 3 This is the BPSK principle according to an embodiment of the present invention.

[0022] Figure 4 These are XOR and XNOR logic gates. (a) is the electric field distribution diagram for X=Y=0, (b) is the electric field distribution diagram for X=0, Y=1, (c) is the electric field distribution diagram for X=1, Y=0, and (d) is the electric field distribution diagram for X=Y=1.

[0023] Figure 5 These are NOR and AND logic gates. (a) is the electric field distribution diagram for X=Y=0, (b) is the electric field distribution diagram for X=0, Y=1, (c) is the electric field distribution diagram for X=1, Y=0, and (d) is the electric field distribution diagram for X=Y=1.

[0024] Figure 6 These are OR and NAND logic gates. (a) is the electric field distribution diagram for X=Y=0, (b) is the electric field distribution diagram for X=0, Y=1, (c) is the electric field distribution diagram for X=1, Y=0, and (d) is the electric field distribution diagram for X=Y=1.

[0025] Figure 7 It is a NOT logic gate, (a) is the electric field distribution diagram when X=Y=0, (b) is the electric field distribution diagram when X=0, Y=1;

[0026] Figure 8 The normalized power response curves of XOR and XNOR logic gates are (a) X=Y=0, (b) X=0, Y=1, (c) X=1, Y=0, and (d) X=Y=1.

[0027] Figure 9 The normalized power response curves of NOR and AND logic gates are (a) X=Y=0, (b) X=0, Y=1, (c) X=1, Y=0, and (d) X=Y=1.

[0028] Figure 10 These are the normalized power response curves of the OR and NAND logic gates, with (a) X=Y=0, (b) X=0, Y=1, (c) X=1, Y=0, and (d) X=Y=1.

[0029] Figure 11 It is a NOT logic gate, (a) is the normalized power response curve over time when X=Y=0, and (b) is the normalized power response curve when X=0, Y=1. DETAILED DESCRIPTION

[0030] The following describes embodiments of the present invention in detail, examples of which are shown in the accompanying drawings, wherein the same or similar reference numerals throughout represent the same or similar elements or elements having the same or similar functions. The embodiments described below with reference to the accompanying drawings are exemplary and are intended to be used to explain the present invention, and are not to be construed as limiting the present invention.

[0031] In the description of the present invention, it should be understood that the terms "center," "longitudinal," "lateral," "length," "width," "thickness," "upper," "lower," "axial," "radial," "vertical," "horizontal," "inner," "outer," and the like, indicating orientations or positional relationships, are based on the orientations or positional relationships shown in the accompanying drawings and are intended only to facilitate the description of the present invention and simplify the description. They do not indicate or imply that the devices or elements referred to must have a specific orientation, be constructed, or operate in a specific orientation. Therefore, they should not be construed as limiting the present invention. In the description of the present invention, "plurality" means two or more, unless otherwise expressly and specifically defined.

[0032] First, a quasi-periodic photonic crystal all-optical logic gate capable of realizing seven logic states according to an embodiment of the present invention will be described in detail below with reference to the accompanying drawings.

[0033] Please refer to Figure 1 and Figure 2 According to an embodiment of the present invention, a quasi-periodic photonic crystal all-optical logic gate capable of realizing seven logical states includes a plurality of dielectric pillars and two phase modulators. The plurality of dielectric pillars are arranged in a six-fold quasi-periodic arrangement in a Sunflower pattern to form a plurality of concentric rings. Four waveguides are constructed by deleting a row of dielectric pillars counterclockwise from the center of the logic gate along the directions of 0°, 180°, 240°, and 300°. The two waveguides along the directions of 240° and 300° serve as input ports, and the other two waveguides serve as output ports. Each of the two input ports corresponds to one of the phase modulators, and the phase of the input port signal is controlled by the phase modulator using BPSK technology.

[0034] Furthermore, in this embodiment, the dielectric column is made of silicon, and the background medium is air, with a refractive index of 3.48, while the refractive index of air is 1.

[0035] The sunflower-type structure is a non-periodic crystal structure. This type of quasicrystal structure has a unified coordinate formula that can be expressed as:

[0036]

[0037] Where a represents the distance between two adjacent rings, M represents the number of dielectric pillars in the first ring, N represents the ordinal number of the ring, and n represents the ordinal number of a dielectric pillar in the Nth ring. In this embodiment, a = 661 nm, the dielectric pillar radius is r = 0.11 * a, M = 6, and N = 12.

[0038] The following describes the principle of BPSK control:

[0039] Assume that light is input at the first input port 1, such as Figure 3 As shown in (a), both output ports have the same output. Assuming that light is input into the second input port 2, both output ports also have light output, as shown in Figure 3 As shown in (b). Assuming that the first input ports 1 and 2 input light with a phase difference of 0 or π respectively, both output ports have light output, as shown in Figure 3 As shown in (c). Assuming that the first input ports 1 and 2 input light with a phase difference of π / 2, the light is output from only one output port, as shown in Figure 3 The present invention utilizes BPSK technology to design a logic gate whose output port logic state is determined by the light intensity of the output port, with the normalized intensity of the output port being set to logic 1 when it is greater than 60% and to logic 0 when it is less than 40%.

[0040] The quasi-periodic photonic crystal all-optical logic gate of the embodiment of the present invention, without changing the photonic crystal structure, can generate seven different logic states by changing the initial phase of the two input ports, causing signal light of different phases to interfere within the photonic crystal. The two output ports can respectively implement two different logic gates. The seven achievable logic states are described below:

[0041] If you want to implement the XOR and XNOR logic gates, for the first input port 1, the input light phase of π is regarded as logic 0, and the input light phase of 0 is regarded as logic 1. For the second input port 2, the input light phase of -π / 2 is regarded as logic 0, and the input light phase of π / 2 is regarded as logic 1. According to the above regulations, the logic gate depends on the following phase conditions: When the input logic state is "00", the electric field distribution diagram is shown in Figure 4a. According to Figure 8 a. The normalized intensities of ports O1 and O2 are 1% and 210% respectively, so the logic value of port O1 is 0 and the logic value of port O2 is 1. When the input logic state is "01", the electric field distribution diagram is as follows: Figure 4 As shown in b. Figure 8 b. The normalized intensities of ports O1 and O2 are 150% and 1% respectively, so the logic value of port O1 is 1 and the logic value of port O2 is 0. When the input logic state is "10", the electric field distribution diagram is as follows: Figure 4 c. According to Figure 8c. The normalized intensities of ports O1 and O2 are 150% and 1% respectively, so the logic value of port O1 is 1 and the logic value of port O2 is 0. When the input logic state is "11", the electric field distribution diagram is as follows: Figure 4 d. According to Figure 8 d. The normalized intensities of ports O1 and O2 are 1% and 210%, respectively, so the logic value of port O1 is 0 and the logic value of port O2 is 1.

[0042] Table 1 Logical values ​​of XOR and XNOR functions BPSK signals

[0043]

[0044] If we want to implement two logic gates, NOR and AND, for the first input port 1, the input light phase of π / 2 is considered as logic 1, and the input light phase of 0 is considered as logic 0. For the second input port 2, the input light phase of 0 is considered as logic 1, and the input light phase of π / 2 is considered as logic 0. According to the above regulations, the logic gate depends on the following phase conditions: When the input logic state is "00", the electric field distribution diagram is as follows Figure 5 As shown in a. Figure 9 a. The normalized intensities of ports O1 and O2 are 150% and 1% respectively, so the logic value of port O1 is 1 and the logic value of port O2 is 0. When the input logic state is "01", the electric field distribution diagram is as follows: Figure 5 As shown in b. Figure 9 b. The normalized intensities of ports O1 and O2 are 30% and 30% respectively, so the logic value of port O1 is 0 and the logic value of port O2 is 0. When the input logic state is "10", the electric field distribution diagram is as follows: Figure 5 c. According to Figure 9 c. The normalized intensities of ports O1 and O2 are 30% and 30% respectively, so the logic value of port O1 is 0 and the logic value of port O2 is 0. When the input logic state is "11", the electric field distribution diagram is as follows: Figure 5 d. According to Figure 9 d. The normalized intensities of ports O1 and O2 are 1% and 210%, respectively, so the logic value of port O1 is 0 and the logic value of port O2 is 1.

[0045] Table 2 Logical values ​​of NOR and AND functions BPSK signals

[0046]

[0047] If we want to implement two logic gates, OR and NAND, for the first input port 1, the input light phase of π / 2 is considered as logic 1, and the input light phase of 0 is considered as logic 0. For the second input port 2, the input light phase of π is considered as logic 1, and the input light phase of -π / 2 is considered as logic 0. According to the above regulations, the logic gate depends on the following phase conditions: When the input logic state is "00", the electric field distribution diagram is as follows Figure 6 As shown in a. Figure 10 a. The normalized intensities of ports O1 and O2 are 1% and 210% respectively, so the logic value of port O1 is 0 and the logic value of port O2 is 1. When the input logic state is "01", the electric field distribution diagram is as follows: Figure 6 As shown in b. Figure 10 b. The normalized intensities of ports O1 and O2 are 260% and 260% respectively, so the logic value of port O1 is 1 and the logic value of port O2 is 1. When the input logic state is "10", the electric field distribution diagram is as follows: Figure 6 c. According to Figure 10 c. The normalized intensities of ports O1 and O2 are 260% and 260% respectively, so the logic value of port O1 is 1 and the logic value of port O2 is 1. When the input logic state is "11", the electric field distribution diagram is as follows: Figure 6 d. According to Figure 10 d. The normalized intensities of ports O1 and O2 are 150% and 1% respectively, so the logic value of port O1 is 1 and the logic value of port O2 is 0.

[0048] Table 3 Logic values ​​of BPSK signals using NAND and OR functions

[0049]

[0050] To implement a NOT logic gate, the first input port 1 continuously emits light with a phase of π. For the second input port 2, the input light with a phase of π / 2 is considered a logic 1, and the input light with a phase of -π / 2 is considered a logic 0. According to the above regulations, the logic gate depends on the following phase conditions: When the input logic state is "0", the electric field distribution diagram is as follows Figure 7 As shown in a. Figure 11 a. The normalized intensity of the O2 port is 210%, and the logic value of the O2 port is 1. When the input logic state is "1", the electric field distribution diagram is as follows: Figure 7 As shown in b. Figure 11 b, The normalized intensity of the O2 port is 1%, and the logic value of the O2 port is 0.

[0051] Table 4 Logical values ​​of NOT function BPSK signal

[0052]

[0053] Throughout this specification, reference to terms such as "one embodiment," "some embodiments," "examples," "specific examples," or "some examples" means that a specific feature, structure, material, or characteristic described in conjunction with that embodiment or example is included in at least one embodiment or example of the present invention. In this specification, schematic representations of the above terms do not necessarily refer to the same embodiment or example. Furthermore, the specific features, structures, materials, or characteristics described may be combined in any suitable manner in any one or more embodiments or examples.

[0054] Although the embodiments of the present invention have been shown and described above, it will be understood that the above embodiments are illustrative and are not to be construed as limitations on the present invention. A person skilled in the art may change, modify, replace and modify the above embodiments within the scope of the present invention without departing from the principles and purpose of the present invention.

Claims

1. A six-fold quasi-periodic photonic crystal all-optical logic gate capable of realizing seven logical states, characterized in that: The invention comprises a plurality of dielectric columns, which are arranged in a sextuple quasi-periodic pattern to form a plurality of concentric rings. A row of dielectric columns is deleted counterclockwise from the center of the logic gate along the directions of 0°, 180°, 240° and 300° to construct four waveguides, two of which serve as input ports and the other two as output ports. The logic states of the input ports are controlled by BPSK technology.

2. The six-fold quasi-periodic photonic crystal all-optical logic gate capable of realizing seven logical states according to claim 1, characterized in that: It also includes two phase modulators, and the two input ports correspond to one phase modulator respectively, and the phase of the input port signal is controlled by the phase modulator.

3. The six-fold quasi-periodic photonic crystal all-optical logic gate capable of realizing seven logical states according to claim 1, characterized in that: The material of the dielectric column is silicon, and the background medium is air.

4. The six-fold quasi-periodic photonic crystal all-optical logic gate capable of realizing seven logical states according to claim 1, characterized in that: The refractive index of the dielectric column is 3.48, and the refractive index of air is 1.

5. The six-fold quasi-periodic photonic crystal all-optical logic gate capable of realizing seven logical states according to claim 1, characterized in that: The radial distance between two adjacent concentric rings is a, and the radius of the dielectric column is r=0.11*a.

6. The six-fold quasi-periodic photonic crystal all-optical logic gate capable of realizing seven logical states according to claim 1, characterized in that: The two waveguides at 240° and 300° counterclockwise from the center of the logic gate are two input ports.

7. The six-fold quasi-periodic photonic crystal all-optical logic gate capable of realizing seven logical states according to claim 1, characterized in that: The logic state of the output port is determined by the light intensity of the output port. A normalized intensity of the output port greater than 60% is set to logic 1, and less than 40% is set to logic 0. For the first input port, an input light phase of π is considered to be logic 0, and an input light phase of 0 is considered to be logic 1. For the second input port, an input light phase of -π / 2 is considered to be logic 0, and an input light phase of π / 2 is considered to be logic 1, realizing two types of logic gates: XOR and XNOR.

8. The six-fold quasi-periodic photonic crystal all-optical logic gate capable of realizing seven logical states according to claim 1, characterized in that: The logic state of the output port is determined by the light intensity of the output port. A normalized intensity of the output port greater than 60% is set to logic 1, and less than 40% is set to logic 0. For the first input port, an input light phase of π / 2 is considered to be logic 1, and an input light phase of 0 is considered to be logic 0. For the second input port, an input light phase of π is considered to be logic 1, and an input light phase of -π / 2 is considered to be logic 0, realizing two logic gates, NOR and AND.

9. The six-fold quasi-periodic photonic crystal all-optical logic gate capable of realizing seven logical states according to claim 1, characterized in that: The logic state of the output port is determined by the light intensity of the output port. A normalized intensity of the output port greater than 60% is set to logic 1, and less than 40% is set to logic 0. For the first input port, an input light phase of π / 2 is considered to be logic 1, and an input light phase of 0 is considered to be logic 0. For the second input port, an input light phase of 0 is considered to be logic 1, and an input light phase of π / 2 is considered to be logic 0, realizing two logic gates, OR and NAND.

10. The six-fold quasi-periodic photonic crystal all-optical logic gate capable of realizing seven logical states according to claim 1, characterized in that: The logic state of the output port is determined by the light intensity at the output port. A normalized intensity greater than 60% is set as logic 1, and less than 40% is set as logic 0. For the first input port, which continuously emits light with a phase of π, for the second input port, an input light with a phase of π / 2 is considered as logic 1, and an input light with a phase of -π / 2 is considered as logic 0, thus realizing a NOT logic gate.

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