Wafer exposure layout calculation method and device, electronic equipment and storage medium

Abstract

This application provides a method, apparatus, electronic device, and storage medium for calculating wafer exposure layout. The calculation method includes: moving an exposure grid area according to a preset step offset, and calculating the number of exposed dies in the target exposure area of ​​the wafer to be exposed; determining whether the total offset of the exposure grid area movement exceeds a preset threshold based on the number of times the exposure grid area is moved; if it exceeds the threshold, then using the exposure grid area corresponding to the exposed die with the largest number as the target exposure layout for the wafer to be exposed, and exposing the wafer to be exposed according to the target exposure layout. The technical solution provided in this application simplifies the operation steps and improves wafer product yield while increasing the efficiency of the wafer exposure process by moving the exposure grid area multiple times with a set step offset to use the exposure grid area corresponding to the exposed die with the largest number as the target exposure layout for the wafer to be exposed.

Description

Technical Field

[0001] This application relates to the field of semiconductor technology, and in particular to a method, apparatus, electronic device, and storage medium for calculating wafer exposure layout. Background Technology

[0002] During wafer exposure, because the area that an exposure system can expose at one time is limited, a wafer needs to be divided into multiple exposure units for imaging. These exposure units include incomplete exposure units and complete exposure units. Complete exposure units fall entirely within the wafer's surface area, while incomplete exposure units partially fall outside the wafer's surface area. Furthermore, each exposure unit may contain multiple small exposure dies.

[0003] Currently, wafer exposure layout primarily involves performing exposure on equipment and measuring the center offset of the overlay marks between complete and incomplete exposure cells to obtain the exposure layout with the maximum number of complete exposure cells. However, this method requires on-equipment operation, is complex, and impacts work efficiency. Therefore, providing a simple and quick way to determine the wafer exposure field layout and exposure path, thereby maximizing the number of complete exposure dies in the wafer to be exposed and improving wafer product yield, has become an urgent problem to be solved. Summary of the Invention

[0004] In view of this, the purpose of this application is to provide a method, apparatus, electronic device and storage medium for calculating wafer exposure layout, which can move the exposure grid area multiple times by setting a step offset, calculate the number of exposed dies in the target exposure area each time, and take the exposure grid area corresponding to the exposed die with the largest number as the target exposure layout of the wafer to be exposed, so as to expose the wafer to be exposed according to the target exposure layout, simplify the actual operation steps, maximize the number of fully exposed dies, and improve the working efficiency of the wafer exposure process while improving the wafer product yield.

[0005] This application mainly includes the following aspects:

[0006] In a first aspect, embodiments of this application provide a method for calculating wafer exposure layout, the calculation method comprising:

[0007] The wafer to be exposed is placed in a pre-established exposure grid area, and the exposure grid area is moved according to a pre-set step offset; wherein, the exposure grid area includes the target exposure area and the clearing area;

[0008] Based on the moved exposure grid area, calculate the number of exposure dies in the target exposure area of ​​the wafer to be exposed;

[0009] Based on the number of times the exposure grid area moves, determine whether the total offset of the exposure grid area movement exceeds a preset threshold. If it does, then take the exposure grid area corresponding to the largest number of exposure dies as the target exposure layout of the wafer to be exposed, and expose the wafer to be exposed according to the target exposure layout.

[0010] Furthermore, the exposure grid area is established through the following steps:

[0011] The size of each exposure grid unit is determined based on the exposure requirements;

[0012] Using the center position of the wafer to be exposed as the origin of the coordinate system, the position of each exposure grid unit in the coordinate system is determined.

[0013] The edge removal amount of the wafer to be exposed is set according to historical data, the removal area is determined, and the internal area of ​​the wafer to be exposed after removing the removal area is determined as the target exposure area.

[0014] The exposure grid area is established based on the clearing area, the target exposure area, the size of each exposure grid unit, and its position in the coordinate system.

[0015] Furthermore, the step offset includes a horizontal step offset and a vertical step offset; the horizontal step offset is 1 / N of the horizontal dimension of the exposed die, and the vertical step offset is 1 / M of the vertical dimension of the exposed die; N and M are integers.

[0016] Furthermore, the step of calculating the number of exposure grains in the target exposure area of ​​the wafer to be exposed based on the moved exposure grid area includes:

[0017] Based on the moved exposure grid area, determine the center position of all exposed grains in the wafer to be exposed;

[0018] The positions of the four corners of the exposed die are determined based on the center position of each exposed die;

[0019] Based on the positions of the four corners of the exposed die, determine whether the exposed die is within the target exposure area;

[0020] If it is, then increment the number of exposed chips in the target exposure area by one, and execute the step of determining whether the next exposed chip is in the target exposure area, until all exposed chips in the wafer to be exposed have been traversed, and calculate the number of exposed chips in the target exposure area.

[0021] If not, proceed to the step of determining whether the next exposed die is within the target exposure area, until all exposed dies in the wafer to be exposed have been traversed, and the number of exposed dies in the target exposure area is calculated.

[0022] Furthermore, the step of determining whether the exposed die is within the target exposure area based on the positions of its four corners includes:

[0023] Based on the positions of the four corners of the exposed die, determine the positional distance between the exposed die and the center of the wafer to be exposed;

[0024] The radius of the wafer to be exposed and the edge removal amount of the removal area are obtained, and the difference between the radius of the wafer to be exposed and the edge removal amount is determined as the target detection value.

[0025] Detect whether the distance to the location is less than the target detection value;

[0026] If it is smaller than the target exposure area, then the exposed grain is determined to be within the target exposure area;

[0027] If it is not smaller than, then the exposed die is determined to be outside the target exposure area.

[0028] Furthermore, the calculation method also includes:

[0029] The target exposure layout is divided into an inner field and an outer field according to the exposure grid units; wherein, the inner field is where all the exposure grid units are within the target exposure layout area; and the outer field is where the exposure grid units span both the target exposure layout area and the clearing area.

[0030] In the inner field, the shortest adjacent distance is used as the target path, and a preset type path is used to number each exposure grid unit from smallest to largest;

[0031] In the outer field, each exposure grid cell is numbered according to polar coordinates, following the order of the inner field numbers.

[0032] The path determined by connecting each exposure grid unit in the order of the inner field number and the outer field number is used to determine the target exposure path.

[0033] Secondly, embodiments of this application also provide a computing device for wafer exposure layout, the computing device comprising:

[0034] The moving module is used to place the wafer to be exposed into a pre-established exposure grid area and move the exposure grid area according to a pre-set step offset; wherein, the exposure grid area includes a target exposure area and a clearing area;

[0035] The calculation module is used to calculate the number of exposure dies in the target exposure area of ​​the wafer to be exposed, based on the moved exposure grid area;

[0036] The determination module is used to determine whether the total offset of the exposure grid area movement exceeds a preset threshold based on the number of times the exposure grid area moves. If it does, the exposure grid area corresponding to the largest number of exposure dies is taken as the target exposure layout of the wafer to be exposed, so as to expose the wafer to be exposed according to the target exposure layout.

[0037] Furthermore, the computing device also includes a setup module; the setup module is used for:

[0038] The size of each exposure grid unit is determined based on the exposure requirements;

[0039] Using the center position of the wafer to be exposed as the origin of the coordinate system, the position of each exposure grid unit in the coordinate system is determined.

[0040] The edge removal amount of the wafer to be exposed is set according to historical data, the removal area is determined, and the internal area of ​​the wafer to be exposed after removing the removal area is determined as the target exposure area.

[0041] The exposure grid area is established based on the clearing area, the target exposure area, the size of each exposure grid unit, and its position in the coordinate system.

[0042] Thirdly, embodiments of this application also provide an electronic device, including: a processor, a memory, and a bus. The memory stores machine-readable instructions executable by the processor. When the electronic device is running, the processor communicates with the memory via the bus. When the machine-readable instructions are executed by the processor, the steps of the wafer exposure layout calculation method described above are performed.

[0043] Fourthly, embodiments of this application also provide a computer-readable storage medium storing a computer program, which, when executed by a processor, performs the wafer exposure layout calculation steps as described above.

[0044] This application provides a method, apparatus, electronic device, and storage medium for calculating wafer exposure layout. The calculation method includes: placing the wafer to be exposed in a pre-established exposure grid area; moving the exposure grid area according to a pre-set step offset; wherein the exposure grid area includes a target exposure area and a clearing area; calculating the number of exposure dies in the wafer to be exposed in the target exposure area based on the moved exposure grid area; determining whether the total offset of the exposure grid area movement exceeds a preset threshold based on the number of times the exposure grid area is moved; if it exceeds the threshold, then taking the exposure grid area corresponding to the exposure die with the largest number as the target exposure layout of the wafer to be exposed, and exposing the wafer to be exposed according to the target exposure layout.

[0045] In this way, the technical solution provided in this application can move the exposure grid area multiple times by setting the step offset. Each time it moves, the number of exposed dies in the target exposure area is calculated. The exposure grid area corresponding to the dies with the largest number of exposed dies is taken as the target exposure layout of the wafer to be exposed. The wafer to be exposed is then exposed according to the target exposure layout, which simplifies the actual operation steps and maximizes the number of dies exposed. This improves the wafer product yield and the working efficiency of the wafer exposure process.

[0046] To make the above-mentioned objectives, features and advantages of this application more apparent and understandable, preferred embodiments are described below in detail with reference to the accompanying drawings. Attached Figure Description

[0047] To more clearly illustrate the technical solutions of the embodiments of this application, the accompanying drawings used in the embodiments will be briefly introduced below. It should be understood that the following drawings only show some embodiments of this application and should not be regarded as a limitation of the scope. For those skilled in the art, other related drawings can be obtained based on these drawings without creative effort.

[0048] Figure 1 A flowchart illustrating a method for calculating wafer exposure layout provided in an embodiment of this application is shown;

[0049] Figure 2 A flowchart illustrating another method for calculating wafer exposure layout provided in an embodiment of this application is shown;

[0050] Figure 3 A schematic diagram of the target exposure path provided in an embodiment of this application is shown;

[0051] Figure 4 This illustration shows one of the structural schematic diagrams of a computing device for wafer exposure layout provided in an embodiment of this application;

[0052] Figure 5 This is a second schematic diagram of the structure of a computing device for wafer exposure layout provided in an embodiment of this application;

[0053] Figure 6 A schematic diagram of the structure of an electronic device provided in an embodiment of this application is shown. Detailed Implementation

[0054] To make the objectives, technical solutions, and advantages of the embodiments of this application clearer, the technical solutions of the embodiments of this application will be clearly and completely described below with reference to the accompanying drawings. It should be understood that the drawings in this application are for illustrative and descriptive purposes only and are not intended to limit the scope of protection of this application. Furthermore, it should be understood that the schematic drawings are not drawn to scale. The flowcharts used in this application illustrate operations implemented according to some embodiments of this application. It should be understood that the operations in the flowcharts may not be implemented in sequence, and steps without logical contextual relationships may be reversed or implemented simultaneously. In addition, those skilled in the art, guided by the content of this application, may add one or more other operations to the flowcharts, or remove one or more operations from the flowcharts.

[0055] Furthermore, the described embodiments are merely some, not all, of the embodiments of this application. The components of the embodiments of this application described and illustrated herein can typically be arranged and designed in various different configurations. Therefore, the following detailed description of the embodiments of this application provided in the accompanying drawings is not intended to limit the scope of the claimed application, but merely to illustrate selected embodiments of the application. All other embodiments obtained by those skilled in the art based on the embodiments of this application without inventive effort are within the scope of protection of this application.

[0056] To enable those skilled in the art to use the content of this application and in conjunction with the specific application scenario of "calculating the exposure layout of a wafer", the following implementation methods are provided. For those skilled in the art, the general principles defined herein can be applied to other embodiments and application scenarios without departing from the spirit and scope of this application.

[0057] The methods, apparatus, electronic devices, or computer-readable storage media described in this application can be applied to any scenario that requires calculating wafer exposure layout. This application does not limit the specific application scenario. Any scheme that uses a wafer exposure layout calculation method, apparatus, electronic device, and storage medium provided in this application is within the protection scope of this application.

[0058] It is worth noting that during wafer exposure, since the area that an exposure system can expose at one time is limited, a wafer needs to be divided into multiple exposure units for separate exposure imaging. These exposure units include incomplete exposure units and complete exposure units. Complete exposure units fall entirely within the wafer's surface area, while incomplete exposure units partially fall outside the wafer's surface area. Furthermore, each exposure unit may contain multiple small exposure dies.

[0059] Currently, wafer exposure layout primarily involves performing exposure on equipment and measuring the center offset of the overlay marks between complete and incomplete exposure cells to obtain the exposure layout with the maximum number of complete exposure cells. However, this method requires on-equipment operation, is complex, and impacts work efficiency. Therefore, providing a simple and quick way to determine the wafer exposure field layout and exposure path, thereby maximizing the number of complete exposure dies in the wafer to be exposed and improving wafer product yield, has become an urgent problem to be solved.

[0060] Based on this, this application proposes a method, apparatus, electronic device, and storage medium for calculating wafer exposure layout. The calculation method includes: placing the wafer to be exposed in a pre-established exposure grid area, and moving the exposure grid area according to a pre-set step offset; wherein the exposure grid area includes a target exposure area and a clearing area; calculating the number of exposure dies in the wafer to be exposed in the target exposure area based on the moved exposure grid area; determining whether the total offset of the exposure grid area movement exceeds a preset threshold based on the number of times the exposure grid area is moved; if it exceeds the threshold, then taking the exposure grid area corresponding to the exposure die with the largest number as the target exposure layout of the wafer to be exposed, and exposing the wafer to be exposed according to the target exposure layout.

[0061] In this way, the technical solution provided in this application can move the exposure grid area multiple times by setting the step offset. Each time it moves, the number of exposed dies in the target exposure area is calculated. The exposure grid area corresponding to the dies with the largest number of exposed dies is taken as the target exposure layout of the wafer to be exposed. The wafer to be exposed is then exposed according to the target exposure layout, which simplifies the actual operation steps and maximizes the number of dies exposed. This improves the wafer product yield and the working efficiency of the wafer exposure process.

[0062] To facilitate understanding of this application, the technical solutions provided in this application will be described in detail below with reference to specific embodiments.

[0063] Please see Figure 1 , Figure 1 A flowchart illustrating a method for calculating wafer exposure layout provided in an embodiment of this application is shown below. Figure 1As shown, the calculation method includes:

[0064] S101. Place the wafer to be exposed in the pre-established exposure grid area, and move the exposure grid area according to the pre-set step offset.

[0065] In this step, the exposure grid area includes a target exposure area and a clearing area. The clearing area is used to correct the edges of the wafer to be exposed, making them smooth; it is the area removed from the exposure grid area and is not used for exposure. The target exposure area is the effective exposure area, that is, the area of ​​the wafer to be exposed where the exposure operation actually takes place, which is the internal area of ​​the wafer after the clearing area is removed. Here, when placing the wafer to be exposed in the pre-established exposure grid area, it should be noted that the steps for establishing the exposure grid area are described in [link to relevant documentation]. Figure 2 , Figure 2 A flowchart illustrating another method for calculating wafer exposure layout provided in this application embodiment is shown below. Figure 2 As shown, the exposure grid area is established through the following steps:

[0066] S201. Determine the size of each exposure grid unit according to the exposure requirements;

[0067] In this step, the size of each exposure grid cell is determined based on exposure requirements, such as the size of the pattern on the mask.

[0068] S202. Using the center position of the wafer to be exposed as the origin of the coordinate system, determine the position of each exposure grid unit in the coordinate system;

[0069] In this step, a coordinate system is established with the center position of the wafer to be exposed as the origin. Based on the size of each exposure grid unit determined in step S201, the position of each exposure grid unit in the coordinate system is determined, thus generating an initial, i.e., unoffset wafer layout.

[0070] S203. Set the edge removal amount of the wafer to be exposed according to historical data, determine the removal area, and determine the internal area of ​​the wafer to be exposed after removing the removal area as the target exposure area.

[0071] In this step, since the edges of the wafer to be exposed are not completely flat, the exposure result is not ideal. Therefore, an edge removal amount needs to be set to correct the edges of the wafer to be exposed. The size of the edge removal amount is determined by analyzing historical data. The edge removal amount is set to remove part of the edges of the wafer to be exposed. The removed area is defined as the removal area. The removal area is a ring-shaped area. The internal area of ​​the wafer to be exposed after removing the removal area is defined as the target exposure area.

[0072] S204. Establish the exposure grid area based on the clearing area, the target exposure area, the size of each exposure grid unit, and its position in the coordinate system.

[0073] In this step, an exposure grid area is established based on the determined clearing area, target exposure area, size of each exposure grid unit, and position in the coordinate system. This exposure grid area is movable, and it is moved according to the step offset to obtain the optimal exposure layout as the target exposure layout for exposing the wafer to be exposed, thereby improving the product yield of the wafer.

[0074] Here, the step offset in step S101 includes a horizontal step offset and a vertical step offset; the horizontal step offset is 1 / N of the horizontal dimension of the exposed die, and the vertical step offset is 1 / M of the vertical dimension of the exposed die; N and M are integers.

[0075] For example, 1 / 5 of the horizontal dimension of the exposed die is used as the step offset in the horizontal direction of the exposure grid area, and 1 / 5 of the vertical dimension of the exposed die is used as the step offset in the vertical direction of the exposure grid area. An offset wafer layout is generated by moving the exposure grid area once according to the step offset.

[0076] S102. Calculate the number of exposure dies in the target exposure area based on the moved exposure grid area;

[0077] In this step, each time the exposure grid area is moved, the number of exposed dies in the wafer to be exposed in the target exposure area needs to be calculated. After the movement is completed, the number of exposed dies in the target exposure area after each movement is counted, and the exposure grid area corresponding to the movement with the largest number is determined as the target exposure area.

[0078] Here, the step of calculating the number of exposed grains in the target exposure area of ​​the wafer to be exposed, based on the moved exposure grid area, includes:

[0079] S1021. Determine the center position of all exposed grains in the wafer to be exposed based on the moved exposure grid area.

[0080] In this step, after moving the exposure grid area according to the step offset, the size of the exposure grid cell (C) is determined. x C y ), the size of the exposed grain (D) x D y The center position of the exposed grain is calculated using the set step offset, and the specific formula is as follows:

[0081] Dcx =[(R w ±S x )÷C x -1]×C x +D x ×AD x ÷2;

[0082] D cy =[(R w ±S y )÷C y -1]×C y +D y ×BD y ÷2;

[0083] Among them, (D) cx D cy R is the center position of the exposed grain. w It is the radius of the wafer to be exposed, S x Let A be the horizontal offset, where A is an integer and its value ranges from (1, C). x / D x ), S y B is the vertical offset, where B is an integer and its value ranges from (1, C). y / D y ).

[0084] S1022. Determine the positions of the four corners of the exposed die based on the center position of each exposed die;

[0085] In this step, based on the center position (D) of each exposed grain... cx D cy ) and the size of the exposed grains (D x D y ), calculate the positions of the four corners of the exposed grain (D cox D coy The specific formula is as follows:

[0086] D cox =D cx ±D x ÷2;

[0087] D coy =D cy ±D y ÷2;

[0088] S1023. Determine whether the exposed die is within the target exposure area based on the positions of the four corners of the exposed die;

[0089] Here, the step of determining whether the exposed die is within the target exposure area based on the positions of its four corners includes:

[0090] 1) Determine the positional distance between the exposed die and the center of the wafer to be exposed based on the positions of the four corners of the exposed die;

[0091] In this step, the positions of the four corners of the exposed grain (D) are used to determine the location of the exposed grain. cox D coy The distance L between the exposed die and the center position (0, 0) of the wafer to be exposed is determined by the following formula:

[0092]

[0093] 2) Obtain the radius of the wafer to be exposed and the edge removal amount of the removal area, and determine the difference between the radius of the wafer to be exposed and the edge removal amount as the target detection value;

[0094] In this step, the radius R of the wafer to be exposed is obtained. w And the edge removal amount R of the removal area c The difference between the radius of the wafer to be exposed and the edge removal amount is determined as the target detection value.

[0095] 3) Detect whether the distance to the location is less than the target detection value;

[0096] In this step, the following formula can be used to detect whether the location distance is less than the target detection value:

[0097] L <R w -R c ;

[0098] Where L is the distance between the exposed die and the center position (0,0) of the wafer to be exposed, and R... w R is the radius of the wafer to be exposed. c It is the amount of edge clearing in the cleared area.

[0099] 4) If it is smaller than the target exposure area, then the exposed die is determined to be within the target exposure area;

[0100] In this step, if the position distance detected in step 3) is less than the target detection value, it is determined that the exposed grain is within the target exposure area, and then step S1024 is entered.

[0101] 5) If it is not less than, then the exposed die is determined to be outside the target exposure area.

[0102] In this step, if the position distance detected in step 3) is not less than the target detection value, it is determined that the exposed die is not in the target exposure area, and then step S1025 is entered.

[0103] S1024. If it is, then increment the number of exposed grains in the target exposure area by one, and execute the next step of determining whether the exposed grain is in the target exposure area, until all the exposed grains in the wafer to be exposed have been traversed, and calculate the number of exposed grains in the target exposure area.

[0104] In this step, if the detected exposed die is within the target exposure area, the number of exposed dies in the target exposure area is incremented by one, and the process continues to determine whether the next exposed die is within the target exposure area, until all exposed dies in the wafer to be exposed have been traversed, and the number of exposed dies in the target exposure area under the exposure grid area offset is counted.

[0105] S1025. If not, proceed to the step of determining whether the next exposed die is in the target exposure area, until all exposed dies in the wafer to be exposed have been traversed, and the number of exposed dies in the target exposure area is calculated.

[0106] In this step, if the detected exposed die is not in the target exposure area, the next exposed die is checked to see if it is in the target exposure area, until all exposed dies in the wafer to be exposed are traversed, and the number of exposed dies in the target exposure area under the exposure grid area offset is counted.

[0107] S103. Based on the number of times the exposure grid area moves, determine whether the total offset of the exposure grid area movement exceeds a preset threshold. If it does, take the exposure grid area corresponding to the largest number of exposure dies as the target exposure layout of the wafer to be exposed, and expose the wafer to be exposed according to the target exposure layout.

[0108] In this step, based on the number of times the exposure grid area is moved and the set step offset, it is determined whether the total offset of the exposure grid area exceeds a preset threshold. If it does not exceed the threshold, the number of moves is incremented by one, and the exposure grid area is moved again according to the step offset. The number of exposed grains in the target exposure area of ​​the exposure grid area is then recounted. For example, the preset threshold is 1 / 2 of the exposure grid unit size, the horizontal step offset is 1 / 5 of the horizontal size of the exposed grain, and the vertical step offset is 1 / 5 of the vertical size of the exposed grain. For example, the step offset ( 1 / 5, 1 / 5), preset threshold 1 / 2, the first horizontal movement is 1 / 5. If it does not exceed 1 / 2, the exposure grid area is moved another 1 / 5 in the horizontal direction. The number of exposed dies in the target exposure area of ​​the exposure grid area is re-counted when the total offset is 2 / 5. Until the total offset exceeds 1 / 2 of the exposure grid unit size, the exposure grid area corresponding to the total offset with the largest number of exposed dies in the target exposure area is selected according to the number of exposed dies in the target exposure area obtained by different advance offsets. This is then applied as the target exposure layout to expose the wafer to be exposed according to the target exposure layout.

[0109] Here, after determining the target exposure layout, the calculation method further includes:

[0110] 1) Divide the target exposure layout into an inner field and an outer field according to the exposure grid units;

[0111] In this step, the target exposure path is planned based on the obtained target exposure layout to obtain the best yield; wherein, the inner field is where all exposure grid units are within the target exposure layout area; the outer field is where the exposure grid units span the target exposure layout area and the clearing area.

[0112] 2) In the inner field, using the shortest adjacent distance as the target path, and employing a preset type of path, number each exposure grid unit from smallest to largest;

[0113] In this step, the inner field uses a preset type path, such as an S-shaped path, which can number each exposure grid unit in the target exposure layout. The target path is numbered from smallest to largest according to the preset type path, with the shortest adjacent distance as the target path.

[0114] 3) In the outer field, each exposure grid cell is numbered according to polar coordinates, following the order of the inner field number;

[0115] In this step, following the last number in the inner field, each exposure grid cell in the outer field is numbered in ascending order according to polar coordinates.

[0116] 4) The path determined by connecting each exposure grid unit in the order of the inner field number and the outer field number is determined as the target exposure path.

[0117] In this step, each exposure grid unit is connected in the order of the inner field number and the outer field number, and the path determined by the connection is identified as the target exposure path; for an example, please refer to [link to example target exposure path]. Figure 3 , Figure 3 This is a schematic diagram of the target exposure path provided in the embodiments of this application, as shown below. Figure 3 As shown, the target exposure path is planned on the target exposure layout. The square area is the exposure grid area, and multiple small rectangles in the exposure grid area are exposure grid units. The circular area is the target exposure area, and the circle is the wafer to be exposed. Each exposure grid unit has multiple exposure grains. Each exposure grid unit in the target exposure area has a triangle as an exposure marker. The inner field path is the S-shaped path from number 1 to 2, and the outer field path is the polar coordinate path from number 3 to 4. The path composed of number 1-2-3-4 is determined as the target exposure path.

[0118] Here, the target exposure path is planned and the required exposure time is calculated to obtain the wafer yield. This allows for the calculation of the target exposure layout with the best yield under different timing offsets. The calculated target exposure layout and target exposure path not only meet the optimal wafer yield but also improve work efficiency.

[0119] This application provides a method for calculating wafer exposure layout. The method includes: placing the wafer to be exposed in a pre-established exposure grid area; moving the exposure grid area according to a pre-set step offset; wherein the exposure grid area includes a target exposure area and a clearing area; calculating the number of exposure dies in the wafer to be exposed in the target exposure area based on the moved exposure grid area; determining whether the total offset of the exposure grid area movement exceeds a preset threshold based on the number of times the exposure grid area is moved; if it exceeds the threshold, then taking the exposure grid area corresponding to the exposure die with the largest number as the target exposure layout of the wafer to be exposed, and exposing the wafer to be exposed according to the target exposure layout.

[0120] In this way, the technical solution provided in this application can move the exposure grid area multiple times by setting the step offset. Each time it moves, the number of exposed dies in the target exposure area is calculated. The exposure grid area corresponding to the dies with the largest number of exposed dies is taken as the target exposure layout of the wafer to be exposed. The wafer to be exposed is then exposed according to the target exposure layout, which simplifies the actual operation steps and maximizes the number of dies exposed. This improves the wafer product yield and the working efficiency of the wafer exposure process.

[0121] Based on the same application concept, this application also provides a wafer exposure layout calculation device corresponding to the wafer exposure layout calculation method provided in the above embodiment. Since the principle of the device in this application is similar to the wafer exposure layout calculation method in the above embodiment, the implementation of the device can refer to the implementation of the method, and the repeated parts will not be described again.

[0122] Please see Figure 4 , Figure 5 , Figure 4 This is one of the structural schematic diagrams of a computing device for wafer exposure layout provided in an embodiment of this application. Figure 5 This is a second schematic diagram of a computing device for wafer exposure layout provided in an embodiment of this application, as shown below. Figure 4 , Figure 5 As shown, the computing device 410 includes:

[0123] The moving module 411 is used to place the wafer to be exposed in a pre-established exposure grid area and move the exposure grid area according to a pre-set step offset; wherein, the exposure grid area includes a target exposure area and a clearing area;

[0124] Calculation module 412 is used to calculate the number of exposure dies in the target exposure area of ​​the wafer to be exposed based on the moved exposure grid area;

[0125] The determining module 413 is used to determine whether the total offset of the exposure grid area movement exceeds a preset threshold based on the number of times the exposure grid area moves. If it exceeds the threshold, the exposure grid area corresponding to the largest number of exposure dies is taken as the target exposure layout of the wafer to be exposed, so as to expose the wafer to be exposed according to the target exposure layout.

[0126] Optional, such as Figure 5 As shown, the computing device 410 further includes a setup module 414; the setup module 414 is used for:

[0127] The size of each exposure grid unit is determined based on the exposure requirements;

[0128] Using the center position of the wafer to be exposed as the origin of the coordinate system, the position of each exposure grid unit in the coordinate system is determined.

[0129] The edge removal amount of the wafer to be exposed is set according to historical data, the removal area is determined, and the internal area of ​​the wafer to be exposed after removing the removal area is determined as the target exposure area.

[0130] The exposure grid area is established based on the clearing area, the target exposure area, the size of each exposure grid unit, and its position in the coordinate system.

[0131] Optionally, the step offset in the moving module 411 includes a horizontal step offset and a vertical step offset; the horizontal step offset is 1 / N of the horizontal dimension of the exposed die, and the vertical step offset is 1 / M of the vertical dimension of the exposed die; N and M are integers.

[0132] Optionally, the calculation module 412 is specifically used for:

[0133] Based on the moved exposure grid area, determine the center position of all exposed grains in the wafer to be exposed;

[0134] The positions of the four corners of the exposed die are determined based on the center position of each exposed die;

[0135] Based on the positions of the four corners of the exposed die, determine whether the exposed die is within the target exposure area;

[0136] If it is, then increment the number of exposed chips in the target exposure area by one, and execute the step of determining whether the next exposed chip is in the target exposure area, until all exposed chips in the wafer to be exposed have been traversed, and calculate the number of exposed chips in the target exposure area.

[0137] If not, proceed to the step of determining whether the next exposed die is within the target exposure area, until all exposed dies in the wafer to be exposed have been traversed, and the number of exposed dies in the target exposure area is calculated.

[0138] Optionally, when the calculation module 412 is used to determine whether the exposed die is within the target exposure area based on the positions of the four corners of the exposed die, the calculation module 412 is specifically used for:

[0139] Based on the positions of the four corners of the exposed die, determine the positional distance between the exposed die and the center of the wafer to be exposed;

[0140] The radius of the wafer to be exposed and the edge removal amount of the removal area are obtained, and the difference between the radius of the wafer to be exposed and the edge removal amount is determined as the target detection value.

[0141] Detect whether the distance to the location is less than the target detection value;

[0142] If it is smaller than the target exposure area, then the exposed grain is determined to be within the target exposure area;

[0143] If it is not smaller than, then the exposed die is determined to be outside the target exposure area.

[0144] Optional, such as Figure 5 As shown, the computing device 410 further includes a path planning module 415; the path planning module 415 is used for:

[0145] The target exposure layout is divided into an inner field and an outer field according to the exposure grid units; wherein, the inner field is where all the exposure grid units are within the target exposure layout area; and the outer field is where the exposure grid units span both the target exposure layout area and the clearing area.

[0146] In the inner field, the shortest adjacent distance is used as the target path, and a preset type path is used to number each exposure grid unit from smallest to largest;

[0147] In the outer field, each exposure grid cell is numbered according to polar coordinates, following the order of the inner field numbers.

[0148] The path determined by connecting each exposure grid unit in the order of the inner field number and the outer field number is used to determine the target exposure path.

[0149] This application provides a wafer exposure layout calculation device, comprising: a moving module for placing the wafer to be exposed in a pre-established exposure grid area and moving the exposure grid area according to a pre-set step offset; wherein the exposure grid area includes a target exposure area and a clearing area; a calculation module for calculating the number of exposure dies in the wafer to be exposed in the target exposure area based on the moved exposure grid area; and a determining module for determining whether the total offset of the exposure grid area movement exceeds a preset threshold based on the number of times the exposure grid area is moved. If it exceeds the threshold, the exposure grid area corresponding to the exposure die with the largest number is taken as the target exposure layout of the wafer to be exposed, and the wafer to be exposed is exposed according to the target exposure layout.

[0150] In this way, the technical solution provided in this application can move the exposure grid area multiple times by setting the step offset. Each time it moves, the number of exposed dies in the target exposure area is calculated. The exposure grid area corresponding to the dies with the largest number of exposed dies is taken as the target exposure layout of the wafer to be exposed. The wafer to be exposed is then exposed according to the target exposure layout, which simplifies the actual operation steps and maximizes the number of dies exposed. This improves the wafer product yield and the working efficiency of the wafer exposure process.

[0151] Please see Figure 6 , Figure 6 This is a schematic diagram of the structure of an electronic device provided in an embodiment of this application. Figure 6 As shown, the electronic device 600 includes a processor 610, a memory 620, and a bus 630.

[0152] The memory 620 stores machine-readable instructions executable by the processor 610. When the electronic device 600 is running, the processor 610 and the memory 620 communicate via the bus 630. When the machine-readable instructions are executed by the processor 610, they can perform the operations described above. Figure 1 as well as Figure 2 The steps of the wafer exposure layout calculation method in the method embodiment shown are described in detail in the method embodiment, and will not be repeated here.

[0153] This application also provides a computer-readable storage medium storing a computer program, which, when executed by a processor, can perform the above-described actions. Figure 1 as well as Figure 2 The steps of the wafer exposure layout calculation method in the method embodiment shown are described in detail in the method embodiment, and will not be repeated here.

[0154] Those skilled in the art will understand that, for the sake of convenience and brevity, the specific working processes of the systems, devices, and units described above can be referred to the corresponding processes in the foregoing method embodiments, and will not be repeated here.

[0155] In the several embodiments provided in this application, it should be understood that the disclosed systems, apparatuses, and methods can be implemented in other ways. The apparatus embodiments described above are merely illustrative. For example, the division of units is only a logical functional division, and in actual implementation, there may be other division methods. Furthermore, multiple units or components may be combined or integrated into another system, or some features may be ignored or not executed. Additionally, the shown or discussed mutual couplings, direct couplings, or communication connections may be through some communication interfaces; indirect couplings or communication connections between devices or units may be electrical, mechanical, or other forms.

[0156] The units described as separate components may or may not be physically separate. The components shown as units may or may not be physical units; that is, they may be located in one place or distributed across multiple network units. Some or all of the units can be selected to achieve the purpose of this embodiment according to actual needs.

[0157] In addition, the functional units in the various embodiments of this application can be integrated into one processing unit, or each unit can exist physically separately, or two or more units can be integrated into one unit.

[0158] If the aforementioned functions are implemented as software functional units and sold or used as independent products, they can be stored in a processor-executable, non-volatile, computer-readable storage medium. Based on this understanding, the technical solution of this application, in essence, or the part that contributes to the prior art, or a portion of the technical solution, can be embodied in the form of a software product. This computer software product is stored in a storage medium and includes several instructions to cause a computer device (which may be a personal computer, server, or network device, etc.) to execute all or part of the steps of the methods described in the various embodiments of this application. The aforementioned storage medium includes various media capable of storing program code, such as USB flash drives, portable hard drives, read-only memory (ROM), random access memory (RAM), magnetic disks, or optical disks.

[0159] Finally, it should be noted that the above-described embodiments are merely specific implementations of this application, used to illustrate the technical solutions of this application, and not to limit them. The scope of protection of this application is not limited thereto. Although this application has been described in detail with reference to the foregoing embodiments, those skilled in the art should understand that any person skilled in the art can still modify or easily conceive of changes to the technical solutions described in the foregoing embodiments, or make equivalent substitutions for some of the technical features, within the scope of the technology disclosed in this application. Such modifications, changes, or substitutions do not cause the essence of the corresponding technical solutions to deviate from the spirit and scope of the technical solutions of the embodiments of this application, and should all be covered within the scope of protection of this application. Therefore, the scope of protection of this application should be determined by the scope of the claims.

Claims

1. A method for calculating wafer exposure layout, characterized in that, The calculation method includes: The wafer to be exposed is placed in a pre-established exposure grid area, and the exposure grid area is moved according to a pre-set step offset; wherein, the exposure grid area includes the target exposure area and the clearing area; Based on the moved exposure grid area, calculate the number of exposure dies in the target exposure area of ​​the wafer to be exposed; The step of calculating the number of exposed grains in the target exposure area of ​​the wafer to be exposed based on the moved exposure grid area includes: Based on the moved exposure grid area, determine the center position of all exposed grains in the wafer to be exposed; The positions of the four corners of the exposed die are determined based on the center position of each exposed die; Based on the positions of the four corners of the exposed die, determine whether the exposed die is within the target exposure area; The step of determining whether the exposed die is within the target exposure area based on the positions of its four corners includes: Based on the positions of the four corners of the exposed die, determine the positional distance between the exposed die and the center of the wafer to be exposed; The radius of the wafer to be exposed and the edge removal amount of the removal area are obtained, and the difference between the radius of the wafer to be exposed and the edge removal amount is determined as the target detection value. Detect whether the distance to the location is less than the target detection value; If it is smaller than the target exposure area, then the exposed grain is determined to be within the target exposure area; If it is not less than, then the exposed die is determined to be outside the target exposure area; If it is, then increment the number of exposed chips in the target exposure area by one, and execute the step of determining whether the next exposed chip is in the target exposure area, until all exposed chips in the wafer to be exposed have been traversed, and calculate the number of exposed chips in the target exposure area. If not, proceed to the step of determining whether the next exposed die is in the target exposure area, until all exposed dies in the wafer to be exposed have been traversed, and the number of exposed dies in the target exposure area is calculated. Based on the number of times the exposure grid area moves, determine whether the total offset of the exposure grid area movement exceeds a preset threshold. If it does, then take the exposure grid area corresponding to the largest number of exposure dies as the target exposure layout of the wafer to be exposed, and expose the wafer to be exposed according to the target exposure layout.

2. The calculation method according to claim 1, characterized in that, The exposure grid area is established through the following steps: The size of each exposure grid unit is determined based on the exposure requirements; Using the center position of the wafer to be exposed as the origin of the coordinate system, the position of each exposure grid unit in the coordinate system is determined. The edge removal amount of the wafer to be exposed is set according to historical data, the removal area is determined, and the internal area of ​​the wafer to be exposed after removing the removal area is determined as the target exposure area. The exposure grid area is established based on the clearing area, the target exposure area, the size of each exposure grid unit, and its position in the coordinate system.

3. The calculation method according to claim 1, characterized in that, The step offset includes a horizontal step offset and a vertical step offset; the horizontal step offset is 1 / N of the horizontal dimension of the exposed die, and the vertical step offset is 1 / M of the vertical dimension of the exposed die; N and M are integers.

4. The calculation method according to claim 1, characterized in that, The calculation method further includes: The target exposure layout is divided into an inner field and an outer field according to the exposure grid units; wherein, the inner field is where all the exposure grid units are within the target exposure layout area; and the outer field is where the exposure grid units span both the target exposure layout area and the clearing area. In the inner field, the shortest adjacent distance is used as the target path, and a preset type path is used to number each exposure grid unit from smallest to largest; In the outer field, each exposure grid cell is numbered according to polar coordinates, following the order of the inner field numbers. The path determined by connecting each exposure grid unit in the order of the inner field number and the outer field number is used to determine the target exposure path.

5. A computing device for wafer exposure layout, characterized in that, The computing device includes: The moving module is used to place the wafer to be exposed into a pre-established exposure grid area and move the exposure grid area according to a pre-set step offset; wherein, the exposure grid area includes a target exposure area and a clearing area; The calculation module is used to calculate the number of exposure dies in the target exposure area of ​​the wafer to be exposed, based on the moved exposure grid area; In the step of calculating the number of exposed dies in the target exposure area of ​​the wafer to be exposed based on the moved exposure grid area, the calculation module is used to: Based on the moved exposure grid area, determine the center position of all exposed grains in the wafer to be exposed; The positions of the four corners of the exposed die are determined based on the center position of each exposed die; Based on the positions of the four corners of the exposed die, determine whether the exposed die is within the target exposure area; In the step of determining whether the exposed die is within the target exposure area based on the positions of its four corners, the calculation module is used to: Based on the positions of the four corners of the exposed die, determine the positional distance between the exposed die and the center of the wafer to be exposed; The radius of the wafer to be exposed and the edge removal amount of the removal area are obtained, and the difference between the radius of the wafer to be exposed and the edge removal amount is determined as the target detection value. Detect whether the distance to the location is less than the target detection value; If it is smaller than the target exposure area, then the exposed grain is determined to be within the target exposure area; If it is not less than, then the exposed die is determined to be outside the target exposure area; If it is, then increment the number of exposed chips in the target exposure area by one, and execute the step of determining whether the next exposed chip is in the target exposure area, until all exposed chips in the wafer to be exposed have been traversed, and calculate the number of exposed chips in the target exposure area. If not, proceed to the step of determining whether the next exposed die is in the target exposure area, until all exposed dies in the wafer to be exposed have been traversed, and the number of exposed dies in the target exposure area is calculated. The determination module is used to determine whether the total offset of the exposure grid area movement exceeds a preset threshold based on the number of times the exposure grid area moves. If it does, the exposure grid area corresponding to the exposure die with the largest number is taken as the target exposure layout of the wafer to be exposed, so as to expose the wafer to be exposed according to the target exposure layout.

6. The computing device according to claim 5, characterized in that, The computing device further includes a setup module; the setup module is used for: The size of each exposure grid unit is determined based on the exposure requirements; Using the center position of the wafer to be exposed as the origin of the coordinate system, the position of each exposure grid unit in the coordinate system is determined. The edge removal amount of the wafer to be exposed is set according to historical data, the removal area is determined, and the internal area of ​​the wafer to be exposed after removing the removal area is determined as the target exposure area. The exposure grid area is established based on the clearing area, the target exposure area, the size of each exposure grid unit, and its position in the coordinate system.

7. An electronic device, characterized in that, include: The device includes a processor, a memory, and a bus. The memory stores machine-readable instructions executable by the processor. When the electronic device is running, the processor communicates with the memory via the bus. The machine-readable instructions are executed by the processor to perform the steps of the wafer exposure layout calculation method as described in any one of claims 1 to 4.

8. A computer-readable storage medium, characterized in that, The computer-readable storage medium stores a computer program that, when executed by a processor, performs the steps of the wafer exposure layout calculation method as described in any one of claims 1 to 4.

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