Signal Line Electromigration Inspection Method and Device, Electronic Device, and Storage Medium

Abstract

A method and apparatus for checking electromigration of signal lines in a clock network, an electronic device, and a non-transitory computer-readable storage medium. The clock network includes a plurality of receiving units, at least one main clock signal line, and a plurality of connection structures. The method for checking electromigration of signal lines includes: determining at least one main connection hole located on at least one main clock signal line, wherein each main connection hole corresponds to at least one receiving unit; generating at least one hole network in one-to-one correspondence with the at least one main connection hole based on the at least one main connection hole, wherein each hole network includes the main connection hole corresponding to each hole network, at least one receiving unit connected to the main connection hole, and at least one connection structure for connecting the main connection hole and the at least one receiving unit; generating a target design interchange format file based on the at least one hole network; and performing signal line electromigration checking on the clock network based on the target design interchange format file.

Description

Technical Field

[0001] Embodiments of the present disclosure relate to a method for checking electromigration of signal lines in a clock network, an apparatus for checking electromigration of signal lines in a clock network, an electronic device, and a non-transitory computer-readable storage medium. Background Art

[0002] The electro-migration effect generally refers to the phenomenon of electron migration in a metal wire under the action of a large current. The electro-migration effect includes ion migration occurring on the surface of adjacent conductors (for example, common silver ion migration) and metallization electron migration occurring inside the metal conductor. The electro-migration effect mainly occurs on lines with high current density and high frequency variation, such as power lines, clock lines, etc. The electro-migration effect may cause the metal wires in an integrated circuit to break, thereby affecting the normal operation of the integrated circuit. Therefore, the electro-migration effect has become one of the most important problems affecting the reliability of interconnects in an integrated circuit. Summary of the Invention

[0003] At least one embodiment of the present disclosure provides a method for checking electromigration of signal lines in a clock network. The clock network includes a plurality of receiving units, at least one main clock signal line, and a plurality of connection structures. Each connection structure includes at least one secondary clock signal line. The method for checking electromigration of signal lines includes: determining at least one main connection hole located on the at least one main clock signal line, where each main connection hole corresponds to at least one receiving unit; generating at least one hole network corresponding one-to-one to the at least one main connection hole based on the at least one main connection hole, where each hole network includes the main connection hole corresponding to each hole network, at least one receiving unit connected to the main connection hole, and at least one connection structure for connecting the main connection hole and the at least one receiving unit; generating a target design interchange format file based on the at least one hole network; and performing signal line electromigration check on the clock network based on the target design interchange format file.

[0004] For example, in the signal line electromigration inspection method provided by at least one embodiment of the present disclosure, based on the at least one main connection hole, generating at least one via network corresponding one-to-one to the at least one main connection hole includes: for the i-th main connection hole among the at least one main connection hole: determining N receiving units among the multiple receiving units that are connected to the i-th main connection hole; determining N connection structures corresponding one-to-one to the N receiving units, where each of the N receiving units is connected to the i-th main connection hole through one of the N connection structures; generating a via network corresponding to the i-th main connection hole based on the i-th main connection hole, the N receiving units, and the N connection structures, where N and i are both positive integers.

[0005] For example, in the signal line electromigration inspection method provided by at least one embodiment of the present disclosure, each connection structure further includes at least one secondary via.

[0006] For example, in the signal line electromigration inspection method provided by at least one embodiment of the present disclosure, generating a target design interchange format file based on the at least one via network includes: obtaining an initial design interchange format file, where the initial design interchange format file includes description information of the clock network; deleting the description information of the clock network from the initial design interchange format file; respectively corresponding the at least one main connection hole to set at least one primary pin; adding at least one pin description corresponding to the at least one primary pin and at least one network description corresponding to the at least one via network in the initial design interchange format file to obtain the target design interchange format file.

[0007] For example, in the signal line electromigration inspection method provided by at least one embodiment of the present disclosure, the initial design interchange format file includes a pin part and a network part. Adding at least one pin description corresponding to the at least one primary pin and at least one network description corresponding to the at least one via network in the initial design interchange format file includes: adding the at least one pin description to the pin part of the initial design interchange format file; adding the at least one network description to the network part of the initial design interchange format file.

[0008] For example, in the signal line electromigration inspection method provided by at least one embodiment of the present disclosure, the pin description corresponding to each primary pin includes the name of the primary pin, the name of the via network to which the main connection hole corresponding to the primary pin belongs, the direction corresponding to the primary pin, the attribute corresponding to the primary pin, the position information and shape information of the main connection hole corresponding to the primary pin.

[0009] For example, in the signal line electromigration inspection method provided by at least one embodiment of the present disclosure, the network description corresponding to each hole network includes the name of the hole network, the logical connection relationship of the receiving units in the hole network, the physical information corresponding to the hole network, the wiring rules corresponding to the hole network, and the attributes corresponding to the hole network. The physical information includes the position information and shape information of the main connection holes in the hole network, and the shape information and position information of all secondary clock signal lines in the connection structure in the hole network.

[0010] For example, in the signal line electromigration inspection method provided by at least one embodiment of the present disclosure, in each hole network, the main connection hole is directly connected to each receiving unit in each hole network through a corresponding connection structure.

[0011] For example, in the signal line electromigration inspection method provided by at least one embodiment of the present disclosure, performing signal line electromigration inspection on the clock network based on the target design exchange format file includes: performing signal line electromigration inspection on the secondary clock signal lines in the plurality of connection structures based on the target design exchange format file.

[0012] At least one embodiment of the present disclosure provides a signal line electromigration inspection device for a clock network. The clock network includes a plurality of receiving units, at least one main clock signal line, and a plurality of connection structures. Each connection structure includes at least one secondary clock signal line. The signal line electromigration inspection device includes: a determination unit configured to determine at least one main connection hole located on the at least one main clock signal line; a network generation unit configured to generate at least one hole network corresponding one-to-one to the at least one main connection hole based on the at least one main connection hole, where each hole network includes the main connection hole corresponding to each hole network, at least one receiving unit connected to the main connection hole, and at least one connection structure for connecting the main connection hole and the at least one receiving unit; a file generation unit configured to generate a target design exchange format file based on the at least one hole network; and an inspection unit configured to perform signal line electromigration inspection on the clock network based on the target design exchange format file.

[0013] At least one embodiment of the present disclosure provides an electronic device, including: a memory that stores computer-executable instructions non-transiently; a processor configured to run the computer-executable instructions. When the computer-executable instructions are run by the processor, the signal line electromigration inspection method provided by any embodiment of the present disclosure is implemented.

[0014] At least one embodiment of the present disclosure provides a non-transitory computer-readable storage medium. The non-transitory computer-readable storage medium stores computer-executable instructions, and when the computer-executable instructions are executed by a processor, a signal line electromigration inspection method provided according to any embodiment of the present disclosure is implemented. Description of the Drawings

[0015] To more clearly illustrate the technical solutions of the embodiments of the present disclosure, the accompanying drawings of the embodiments will be briefly introduced below. Obviously, the drawings in the following description only relate to some embodiments of the present disclosure and do not limit the present disclosure.

[0016] Figure 1 A schematic flowchart of a signal line electromigration inspection method for a clock network provided by at least one embodiment of the present disclosure;

[0017] Figure 2 A schematic diagram of a clock network provided by at least one embodiment of the present disclosure;

[0018] Figure 3 A schematic diagram of a via network provided by at least one embodiment of the present disclosure;

[0019] Figure 4 A schematic diagram of a signal line electromigration inspection device for a clock network provided by at least one embodiment of the present disclosure;

[0020] Figure 5 A schematic diagram of an electronic device provided by at least one embodiment of the present disclosure;

[0021] Figure 6 A schematic diagram of a non-transitory computer-readable storage medium provided by at least one embodiment of the present disclosure. Detailed Embodiments

[0022] In order to make the objectives, technical solutions, and advantages of the embodiments of the present disclosure clearer, the technical solutions of the embodiments of the present disclosure will be clearly and completely described below in conjunction with the accompanying drawings of the embodiments of the present disclosure. Obviously, the described embodiments are some, but not all, of the embodiments of the present disclosure. All other embodiments obtained by those of ordinary skill in the art based on the described embodiments of the present disclosure without creative efforts fall within the scope of protection of the present disclosure.

[0023] Unless otherwise defined, the technical terms or scientific terms used in this disclosure shall have the ordinary meanings as understood by those of ordinary skill in the field to which this disclosure pertains. The terms "first", "second" and similar terms used in this disclosure do not denote any order, quantity or importance, but are only used to distinguish different components. Words such as "including" or "comprising" mean that the elements or objects appearing before this word cover the elements or objects listed after this word and their equivalents, without excluding other elements or objects. Words such as "connected" or "coupled" are not limited to physical or mechanical connections, but may include electrical connections, whether direct or indirect. "Upper", "lower", "left", "right", etc. are only used to indicate relative position relationships. When the absolute position of the object being described changes, the relative position relationship may also change accordingly.

[0024] To keep the following description of the embodiments of this disclosure clear and concise, some detailed descriptions of known functions and known components are omitted in this disclosure.

[0025] In the physical implementation of large-scale chips such as high-performance CPUs (central processing units) / GPUs (graphics processing units), a clock mesh structure is often used to optimize the clock tree structure. Due to the particularity of this clock mesh structure, there are a large number of multi-driven clock signal lines.

[0026] Currently, the method for the tool to perform electromigration checks on multi-driven clock signal lines has the problem of inaccuracy, which is mainly reflected in: First, the static timing analysis (STA) file cannot obtain the slew of the signals rising or falling on all driving units of the clock network; Second, the standard parasitic exchange format (Spef) file cannot accurately extract the capacitance information between each node; Third, the topological structure of the clock network is complex, and there will be errors in judging the current flow direction.

[0027] Generally, in the method for checking the electromigration of signal lines, the following information needs to be provided to the tool for electromigration analysis for the tool to perform calculations: the information on the physical connection and logical connection in the design interchange format file corresponding to the signal line; the capacitance information on the signal line in the spef file; the capacitance value of the signal port of the logic unit in the library file (lib); the clock frequency and the transition time of the signal rising or falling in the STA file; the toggle frequency (the number of signal flips from 0->1 and 1->0 of the logic unit within a unit time period) and mode setting in the control file; the electromigration rule provided by the technology file (the technology file contains process-related parameters and the rule definition for electromigration inspection). Then, the tool processes the information input into the tool as above, simulates the current waveforms in different modes, and calculates the average value (avg), root mean square value (rms), and peak value (peak) of the current. Next, the tool obtains the corresponding electromigration limiting current (em limitation) from the technology file according to the physical information. Finally, the tool compares the ratio of the calculated current to the electromigration limiting current (current / electromigration limiting current), and then determines whether the electromigration rule is violated. If the ratio * 100% is greater than 100% (i.e., the ratio is greater than 1), it is determined that the signal line violates the electromigration rule.

[0028] Currently, the tool's judgment on the current direction from multiple driving units of the clock network (the multiple driving units belong to the same clock network) to multiple first-level receiving units (i.e., each receiving unit (receiver) in all modules connected by the multiple driving units of the clock network) is inaccurate, and the calculation of the current is inaccurate. The tool cannot process the clock network with a multi-driven structure, thereby reducing the accuracy and coverage rate of the electromigration inspection, and greatly increasing the electromigration risk from multiple driving units of the clock network to multiple first-level receiving units.

[0029] At least one embodiment of the present disclosure provides a method for checking electromigration of signal lines in a clock network. The clock network includes a plurality of receiving units, at least one main clock signal line, and a plurality of connection structures, and each connection structure includes at least one secondary clock signal line. The method for checking electromigration of signal lines includes: determining at least one main connection hole located on at least one main clock signal line, where each main connection hole corresponds to at least one receiving unit; generating at least one via network in one-to-one correspondence with the at least one main connection hole based on the at least one main connection hole, where each via network includes the main connection hole corresponding to each via network, at least one receiving unit connected to the main connection hole, and at least one connection structure for connecting the main connection hole and the at least one receiving unit; generating a target design interchange format file based on the at least one via network; and performing an electromigration check on the signal lines of the clock network based on the target design interchange format file.

[0030] In the method for checking electromigration of signal lines provided in the embodiment of the present disclosure, by grouping the main connection holes on the main clock signal lines connected to each driving unit, the clock network in which multiple driving units are connected to multiple receiving units can be split into multiple single-driving structures, and each single-driving structure represents a structure in which one driving unit is connected to multiple receiving units. Thus, the clock network with multiple drivers (i.e., a structure in which multiple driving units are connected to multiple receiving units) is converted into a structure mode in which a single driving unit is connected to multiple receiving units that can be processed by the tool, improving the accuracy and credibility of the electromigration check of signal lines, greatly increasing the coverage rate and correct rate of the electromigration check of signal lines, and making up for the problem that the existing tool is inaccurate in checking the electromigration of signal lines in a large-scale multi-driver clock network.

[0031] At least one embodiment of the present disclosure further provides a device for checking electromigration of signal lines in a clock network, an electronic device, and a non-transitory computer-readable storage medium applied to the above method for checking electromigration of signal lines.

[0032] The embodiments of the present disclosure will be described in detail below with reference to the accompanying drawings, but the present disclosure is not limited to these specific embodiments.

[0033] Figure 1 It is a schematic flowchart of a method for checking electromigration of signal lines in a clock network provided by at least one embodiment of the present disclosure. Figure 2 It is a schematic diagram of a clock network provided by at least one embodiment of the present disclosure. Figure 3 It is a schematic diagram of a via network provided by at least one embodiment of the present disclosure.

[0034] For example, an integrated circuit includes multiple modules, each module includes at least one clock network and at least one combinational logic unit, and each clock network is used to provide a clock signal to the corresponding combinational logic unit to drive the combinational logic unit. Each clock network may include multiple receivers, at least one main clock signal line, and multiple connection structures, and each connection structure includes at least one secondary clock signal line. Both the main clock signal line and the secondary clock signal line may be metal signal lines. Each clock network may further include at least one driver. When the clock network includes multiple drivers, the multiple drivers may be connected to each other, and each driver is used to drive at least one main clock signal line. Each main clock signal line is connected to the pin of the receiver in the next N-level through one or more main vias to drive the receiver, so as to control the receiver to perform corresponding functions. Both the driver and the receiver are clock units (for example, sequential logic units). N is a positive integer. When N is 1, it means that the via layer where the main via is located and the metal layer where the pin of the receiver connected to the main via is located are directly adjacent to each other. For example, the integrated circuit includes multiple metal layers and multiple via layers. The metal layer may be the layer where the signal line or the pin in the receiver is located, and the via layer represents the layer where the via (main via and secondary via (described below)) is located. The next N-level refers to the layer that is separated from the via layer where the main via is located by (N - 1) layers.

[0035] For example, in an integrated circuit, multiple metal layers and multiple via layers may be arranged alternately with each other. That is to say, above each via layer is a metal layer, and below each via layer is also a metal layer. The via layer is used to connect the two metal layers on the upper and lower sides.

[0036] It should be noted that in each clock network, the clock signal lines other than the main clock signal line may all be referred to as secondary clock signal lines. Multiple secondary clock signal lines may be located in different metal layers, and the metal layer where each secondary clock signal line is located is below the metal layer where the main clock signal line is located, that is, on the side of the metal layer where the main clock signal line is located close to the receiver.

[0037] For example, the receiver may include sequential logic devices such as latches, flip-flops, buffers, registers, inverters, etc., or may include IP (intellectual property) modules, and each IP module may implement a specific function.

[0038] As Figure 1 shown, the method for checking the electromigration of the signal lines of the clock network includes the following steps S10 to S13.

[0039] Step S10: Determine at least one backbone connection hole located on at least one backbone clock signal line. For example, each backbone connection hole corresponds to at least one receiving unit. For example, each backbone connection hole is physically connected to at least one receiving unit.

[0040] Step S11: Based on at least one backbone connection hole, generate at least one via network that corresponds one-to-one with at least one backbone connection hole. For example, each via network includes the backbone connection hole corresponding to each via network, at least one receiving unit connected to the backbone connection hole, and at least one connection structure for connecting the backbone connection hole and at least one receiving unit.

[0041] Step S12: Generate a target design interchange format file based on at least one via network.

[0042] Step S13: Perform signal line electromigration inspection on the clock network based on the target design interchange format file.

[0043] For example, in Step S10, each backbone clock signal line includes at least one backbone connection hole. The backbone clock signal line is connected to the receiving unit through the backbone connection hole and the connection structure. The number of receiving units connected to each backbone connection hole can be set according to actual design requirements. For example, each connection structure is used to connect a backbone connection hole and a receiving unit, and the connection structure and the receiving unit are in one-to-one correspondence. For example, in some examples, each connection structure connects a backbone connection hole and a pin of a receiving unit, that is, each connection structure connects from the via layer where a backbone connection hole is located to the metal layer where a pin of a receiving unit is located.

[0044] For example, in the case where a backbone clock signal line includes multiple backbone connection holes, the multiple backbone connection holes are located at the same level.

[0045] For example, in one example, as Figure 2As shown, the clock network includes a main clock signal line S1 and multiple connection structures. Multiple main connection holes H1 are formed on the main clock signal line S1. The multiple main connection holes H1 include a main connection hole H11 and a main connection hole H12. The main connection hole H11 is connected to a receiving unit R11 through a secondary clock signal line S21 in a connection structure, connected to a receiving unit R12 through a secondary clock signal line S22 in a connection structure, connected to a receiving unit R13 through a secondary clock signal line S23 in a connection structure, connected to a receiving unit R14 through a secondary clock signal line S24 in a connection structure, connected to a receiving unit R15 through a secondary clock signal line S25 in a connection structure. The main connection hole H12 is connected to a receiving unit R21 through a secondary clock signal line S31 in a connection structure, connected to a receiving unit R22 through a secondary clock signal line S32 in a connection structure, connected to a receiving unit R23 through a secondary clock signal line S33 in a connection structure, connected to a receiving unit R24 through a secondary clock signal line S34 in a connection structure, connected to a receiving unit R25 through a secondary clock signal line S35 in a connection structure, and connected to a receiving unit R26 through a secondary clock signal line S36 in a connection structure. It can be seen from this that in Figure 2 In the illustrated example, the number of receiving units connected to the main connection hole H11 is 5, while the number of receiving units connected to the main connection hole H12 is 6.

[0046] It should be noted that although Figure 2 two main connection holes (i.e., the main connection hole H11 and the main connection hole H12) are schematically shown, the embodiments of the present disclosure are not limited thereto. The number of main connection holes on the main clock signal line S1 can be set according to actual design requirements. In addition, although in Figure 2 each connection structure only includes one secondary clock signal line, the present disclosure is not limited thereto. Each connection structure can include multiple secondary clock signal lines, and the multiple secondary clock signal lines can be located on different metal layers, so that multiple layers (metal layers) where the secondary clock signal lines are located can be spaced between the main connection hole and the receiving unit.

[0047] For example, the positions, shapes, and arrangements of the receiving units connected to each main connection hole are determined by the design process of the integrated circuit. For example, the multiple receiving units connected to the main connection hole can be located on the same level (metal layer) or on different levels.

[0048] For example, the main connection hole is a metal hole for realizing the electrical connection between the main clock signal line and the receiving unit, thereby realizing signal transmission.

[0049] For example, since the number and structure of receiving units connected to different main connection holes may be different, the magnitudes of currents flowing through different main connection holes may also be different.

[0050] For example, in some embodiments, step S11 includes: for the i-th main connection hole among at least one main connection hole: determining N receiving units among a plurality of receiving units that are connected to the i-th main connection hole; determining N connection structures corresponding one-to-one to the N receiving units, where each of the N receiving units is connected to the i-th main connection hole through one of the N connection structures; generating a hole network corresponding to the i-th main connection hole based on the i-th main connection hole, the N receiving units, and the N connection structures. For example, both N and i are positive integers.

[0051] For example, each connection structure further includes at least one secondary connection hole, that is to say, the main connection hole is connected to the receiving unit through at least one secondary clock signal line and at least one secondary connection hole.

[0052] For example, in some embodiments, each connection structure may include a plurality of secondary connection holes, and the plurality of secondary connection holes may be located in different hole layers, so that between the main connection hole and the receiving unit, there may be a plurality of metal layers where secondary clock signal lines are located and a plurality of hole layers where secondary connection holes are located in between.

[0053] It should be noted that in each clock network, connection holes other than the main connection hole may all be referred to as secondary connection holes. The plurality of secondary connection holes may be located in different layers, and the layer where each secondary connection hole is located is below the layer where the main connection hole is located, that is, on the side closer to the receiving unit of the layer where the main connection hole is located.

[0054] For example, the secondary connection hole is a metal hole, for realizing the electrical connection between the main connection hole and the receiving unit, so as to realize signal transmission.

[0055] For example, as Figure 3 shown, the hole network corresponding to the main connection hole H11 is Add_Net1. The hole network Add_Net1 includes receiving units R11 to R15, secondary clock signal lines S21 to S25, and the main connection hole H11. The hole network corresponding to the main connection hole H12 is Add_Net2. The hole network Add_Net2 includes receiving units R21 to R26, secondary clock signal lines S31 to S36, and the main connection hole H12.

[0056] For example, after determining the backbone connection holes, starting from the backbone connection holes, connect to the receiving unit through a connection structure (including secondary clock signal lines and secondary connection holes), and take all the physically connected connection structures, receiving units, and backbone connection holes as the hole network corresponding to the backbone connection holes. The hole network includes the positions and shapes of the connection structures, the positions and shapes of the backbone connection holes, and the overall shape of the connection structures, receiving units, and backbone connection holes. When the connection structure includes secondary clock signal lines, the position and shape of the connection structure represent the positions and shapes of the secondary clock signal lines in the connection structure; when the connection structure includes secondary clock signal lines and secondary connection holes, the position and shape of the connection structure represent the positions and shapes of the secondary clock signal lines and secondary connection holes in the connection structure.

[0057] For example, in each hole network, the backbone connection holes are directly connected to each receiving unit in each hole network through corresponding connection structures. That is to say, there is no physical connection between the receiving units and the backbone connection holes in each hole network through other logic devices.

[0058] For example, in some embodiments, the M receiving units include the a-th receiving unit. There is at least one metal layer and at least one hole layer between the hole layer where the j-th backbone connection hole is located and the metal layer where the pin of the a-th receiving unit is located. At this time, the pin of the a-th receiving unit is connected to the j-th backbone connection hole through the connection structure in at least one metal layer and at least one hole layer between the hole layer where the j-th backbone connection hole is located and the metal layer where the pin of the a-th receiving unit is located. For example, in some examples, there are multiple metal layers and multiple hole layers between the hole layer where the j-th backbone connection hole is located and the metal layer where the pin of the a-th receiving unit is located. The connection structure for connecting the pin of the a-th receiving unit and the j-th backbone connection hole includes multiple secondary clock signal lines and multiple secondary connection holes. The multiple secondary clock signal lines are located in the multiple metal layers, and the multiple secondary connection holes are located in the multiple hole layers.

[0059] It should be noted that in the present disclosure, one secondary clock signal line is located in one metal layer, and multiple secondary clock signal lines can be included in one metal layer. Similarly, one secondary connection hole is located in one hole layer, and multiple secondary connection holes can be included in one hole layer. One secondary clock signal line can be connected to other secondary clock signal lines or to the pins of the receiving units through secondary connection holes.

[0060] For example, step S12 includes: obtaining an initial design exchange format file, where the initial design exchange format file includes description information of a clock network; deleting the description information of the clock network from the initial design exchange format file; respectively corresponding at least one main connection hole to at least one primary pin; adding at least one pin description corresponding to each of the at least one primary pin and at least one network description corresponding to each of the at least one hole network to the initial design exchange format file to obtain a target design exchange format file. Step S12 is used to complete the connection description between the primary pins and all receiving units.

[0061] For example, the initial design exchange format file (def (Design exchange format) file) includes a pin part and a network part. The pin part is used to store descriptions related to pins, and the network part is used to store descriptions related to networks.

[0062] For example, in step S12, adding at least one pin description corresponding to each of the at least one primary pin and at least one network description corresponding to each of the at least one hole network to the initial design exchange format file includes: adding at least one pin description to the pin part of the initial design exchange format file; adding at least one network description to the network part of the initial design exchange format file.

[0063] For example, each main connection hole corresponds to a primary pin, and the physical description of the shape corresponding to the primary pin represents the description of the shape of the hole layer where the main connection hole corresponding to the primary pin is located, and the coordinates corresponding to the primary pin represent the position of the hole layer where the main connection hole corresponding to the primary pin is located.

[0064] For example, the pin description corresponding to each primary pin includes the name of the primary pin, the name of the hole network to which the main connection hole corresponding to the primary pin belongs, the direction corresponding to the primary pin, the attribute corresponding to the primary pin, the position information and shape information of the main connection hole corresponding to the primary pin, etc. The direction corresponding to the primary pin is in terms of logic, indicating whether the primary pin is an output pin or an input pin, and the attribute corresponding to the primary pin is used to indicate whether the primary pin belongs to a power supply, a ground terminal, a signal, a clock, or other types of pins.

[0065] For example, in one example, the pin description of a primary pin can be expressed as: -add_clock_mesh_group1+NET add_clock_mesh_group1+DIRECTION IINPUT+USE CLOCK+LAYER M13(0 0)(900 3200)+PLACED(7065532-12368400)N, where, "-add_clock_mesh_group1" represents the name of the primary pin; "NET add_clock_mesh_group1" represents the via network corresponding to the primary pin, and "add_clock_mesh_group1" in "NET add_clock_mesh_group1" represents the name of the via network corresponding to the primary pin; "DIRECTION IINPUT" represents the direction corresponding to the primary pin, and "IINPUT" indicates that the primary pin is an input pin. When "IINPUT" is changed to "OUTPUT", it indicates that the primary pin is an output pin; "USE CLOCK" represents the attribute corresponding to the primary pin, and "CLOCK" indicates that the primary pin is a pin for a clock signal; "LAYER M13(0 0)(900 3200)" represents the physical information of the backbone connection via corresponding to the primary pin. The physical information includes position information, coordinate information, shape information, etc. For example, "M13" represents the position information, and "(0 0)(900 3200)" represents the coordinate information; "PLACED(7065532-12368400)N" is the status information of the backbone connection via corresponding to the primary pin. Among them, "PLACED" indicates that the backbone connection via corresponding to the primary pin is in a state with position coordinates. If "PLACED" is changed to "FIXED", it indicates that the backbone connection via corresponding to the primary pin is in a locked state.

[0066] For example, the network description corresponding to each via network includes the name of the via network, the logical connection relationship of the receiving units in the via network (which can be represented by a netlist), the physical information corresponding to the via network, the routing rules corresponding to the via network (such as routing geometry data, etc.), the attributes corresponding to the via network, physical constraints, etc. The physical information is the physical information of the shape of the via network (such as the position, coordinates, shape, etc. of the metal layer and metal vias). The physical information includes the position information and shape information of the backbone connection vias in the via network, the shape information and position information of all secondary clock signal lines in the connection structure in the via network, the layout plan of the via network, the layout position and direction of the via network, etc. Similar to the attributes corresponding to the primary pins, the attributes corresponding to the via network are used to indicate whether the via network belongs to a network such as power supply, ground, signal, or clock.

[0067] For example, in one example, the network description corresponding to a via network can be expressed as: -add_clock_mesh_group1+PIN add_clock_mesh_group1+(inst1 CLK)(inst2 CLK)(inst3 CLK)…+NONDEFAULTRULE single+ROUTE M13(x y)(x y)NEW M13(x y)via13…+USE CLOCK.

[0068] In the network description corresponding to the above via network, "-add_clock_mesh_group1" represents the name of the via network; "PIN add_clock_mesh_group1" represents the primary pin corresponding to the via network, and "add_clock_mesh_group1" in "PIN add_clock_mesh_group1" represents the name of the primary pin corresponding to the via network; "(inst1 CLK)(inst2 CLK)(inst3 CLK)…" represents the logical connection relationship of the receiving units in the via network, where "inst1", "inst2", "inst3", etc. represent multiple receiving units, and "CLK" represents the pin in the receiving unit. The receiving units are connected to the connection structure in the via network through the CLK pin; here, all information such as the receiving units (e.g., inst1, inst2, inst3, etc.) connected to the via network and the names of the pins (i.e., CLK) of the receiving units connected to the via network need to be described; "NONDEFAULTRULE single" represents the routing rule; "ROUTE M13(x y)(x y)NEW M13(x y)via13…" represents the physical information such as the metal layer, via layer, secondary clock signal line, and via in the via network. Here, the layer of the main connection via connected to the via network, the metal shape and physical information (e.g., position, shape, and coordinates, etc.) of the secondary clock signal line and the via need to be described; "USE CLOCK" represents the attribute corresponding to the via network, where "CLOCK" indicates that the via network is a clock network.

[0069] For example, step S13 may include: performing signal line electromigration inspection on the secondary clock signal lines in multiple connection structures based on the target design interchange format file. Performing signal line electromigration inspection based on the target design interchange format file greatly increases the coverage rate and accuracy rate of signal line electromigration inspection.

[0070] The signal line electromigration inspection method provided by the embodiments of the present disclosure can process multiple modules in an integrated circuit in parallel, thereby realizing parallel electromigration inspection of multiple modules.

[0071] Figure 4 Schematic diagram of a signal line electromigration inspection device for a clock network provided by at least one embodiment of the present disclosure.

[0072] At least one embodiment of the present disclosure further provides a signal line electromigration inspection device for a clock network.

[0073] The clock network includes a plurality of receiving units, at least one main clock signal line, and a plurality of connection structures, and each connection structure includes at least one secondary clock signal line.

[0074] As Figure 4 shown, the signal line electromigration inspection device 400 may include a determination unit 401, a network generation unit 402, a file generation unit 403, and an inspection unit 404.

[0075] The determination unit 401 is configured to determine at least one main connection hole located on at least one main clock signal line. The determination unit 401 is used to implement Figure 1 the step S10 shown. For the specific operations performed by the determination unit 401, reference may be made to the description of step S10 above, and details will not be repeated here.

[0076] The network generation unit 402 is configured to generate at least one hole network corresponding one-to-one to at least one main connection hole based on at least one main connection hole. For example, each hole network includes the main connection hole corresponding to each hole network, at least one receiving unit connected to the main connection hole, and at least one connection structure for connecting the main connection hole and at least one receiving unit. The network generation unit 402 is used to implement Figure 1 the step S11 shown. For the specific operations performed by the network generation unit 402, reference may be made to the description of step S11 above, and details will not be repeated here.

[0077] The file generation unit 403 is configured to generate a target design exchange format file based on at least one hole network. The file generation unit 403 is used to implement Figure 1 the step S12 shown. For the specific operations performed by the file generation unit 403, reference may be made to the description of step S12 above, and details will not be repeated here.

[0078] The inspection unit 404 is configured to perform signal line electromigration inspection on the clock network based on the target design exchange format file. The inspection unit 404 is used to implement Figure 1 the step S13 shown. For the specific operations performed by the inspection unit 404, reference may be made to the description of step S13 above, and details will not be repeated here.

[0079] For example, in some embodiments, the determination unit 401, the network generation unit 402, the file generation unit 403, and / or the inspection unit 404 may be implemented by hardware, software, firmware, and combinations thereof.

[0080] For example, in some embodiments, the determination unit 401, the network generation unit 402, the file generation unit 403, and / or the inspection unit 404 may include code and programs stored in a memory; the processor may execute the code and programs to implement some or all of the functions of the determination unit 401, the network generation unit 402, the file generation unit 403, and / or the inspection unit 404 as described above. For example, the determination unit 401, the network generation unit 402, the file generation unit 403, and / or the inspection unit 404 may be dedicated hardware devices for implementing some or all of the functions of the determination unit 401, the network generation unit 402, the file generation unit 403, and / or the inspection unit 404 as described above. For example, the determination unit 401, the network generation unit 402, the file generation unit 403, and / or the inspection unit 404 may be a circuit board or a combination of multiple circuit boards for implementing the functions as described above. In the embodiments of the present disclosure, the circuit board or the combination of multiple circuit boards may include: (1) one or more processors; (2) one or more non-transitory memories connected to the processor; and (3) firmware stored in the memory executable by the processor.

[0081] For example, in some embodiments, when performing the step of generating at least one via network corresponding to at least one main connection via, the network generation unit 402 is configured to: for the i-th main connection via among the at least one main connection via: determine N receiving units among the plurality of receiving units that are connected to the i-th main connection via; determine N connection structures corresponding to the N receiving units one by one, where each of the N receiving units is connected to the i-th main connection via through one of the N connection structures; generate a via network corresponding to the i-th main connection via based on the i-th main connection via, the N receiving units, and the N connection structures, where N and i are both positive integers.

[0082] For example, in some embodiments, each connection structure further includes at least one secondary connection via.

[0083] For example, in some embodiments, when performing the step of generating a target design interchange format file based on at least one hole network, the file generation unit 403 is configured to: obtain an initial design interchange format file, where the initial design interchange format file includes description information of a clock network; delete the description information of the clock network from the initial design interchange format file; respectively set at least one backbone connection hole to correspond to at least one primary pin; and add at least one pin description corresponding to each of the at least one primary pin and at least one network description corresponding to each of the at least one hole network in the initial design interchange format file to obtain the target design interchange format file.

[0084] For example, in some embodiments, the initial design interchange format file includes a pin part and a network part. When performing the step of adding at least one pin description corresponding to each of the at least one primary pin and at least one network description corresponding to each of the at least one hole network in the initial design interchange format file, the file generation unit 403 is configured to: add at least one pin description to the pin part of the initial design interchange format file; and add at least one network description to the network part of the initial design interchange format file.

[0085] For example, in some embodiments, the pin description corresponding to each primary pin includes the name of the primary pin, the name of the hole network to which the backbone connection hole corresponding to the primary pin belongs, the direction corresponding to the primary pin, the attribute corresponding to the primary pin, the position information and shape information of the backbone connection hole corresponding to the primary pin.

[0086] For example, in some embodiments, the network description corresponding to each hole network includes the name of the hole network, the logical connection relationship of the receiving units in the hole network, the physical information corresponding to the hole network, the routing rules corresponding to the hole network, the attribute corresponding to the hole network. The physical information includes the position information and shape information of the backbone connection holes in the hole network, and all the shape information and position information in the connection structure in the hole network.

[0087] For example, in some embodiments, in each hole network, the backbone connection hole is directly connected to each receiving unit in each hole network through a corresponding connection structure.

[0088] For example, in some embodiments, when performing the step of performing signal line electromigration inspection on the clock network based on the target design interchange format file, the inspection unit 404 is configured to: perform signal line electromigration inspection on the secondary clock signal lines in multiple connection structures based on the target design interchange format file.

[0089] It should be noted that the signal line electromigration inspection device can achieve technical effects similar to those of the foregoing signal line electromigration inspection method, which will not be elaborated here.

[0090] At least one embodiment of the present disclosure further provides an electronic device. Figure 5 It is a schematic diagram of an electronic device provided by at least one embodiment of the present disclosure.

[0091] For example, as Figure 5 shown, the electronic device 500 includes a processor 501 and a memory 502. It should be noted that Figure 5 the components of the electronic device 500 shown are exemplary and not restrictive. According to actual application needs, the electronic device 500 may also have other components.

[0092] For example, the processor 501 and the memory 502 can communicate with each other. In some examples, the processor 501 and the memory 502 can communicate through a communication bus 503 or through a network. For example, the communication bus 503 can be a Peripheral Component Interconnect (PCI) bus or an Extended Industry Standard Architecture (EISA) bus, etc. The communication bus 503 can be divided into an address bus, a data bus, a control bus, etc. For the sake of simplicity of representation, Figure 5 only a thick line is used to represent the communication bus 503 in [figure], but it does not mean that there is only one bus or one type of bus. The network can include a wireless network, a wired network, and / or any combination of a wireless network and a wired network. The embodiments of the present disclosure do not limit the types and functions of the network and the communication bus 503.

[0093] For example, the memory 502 is used to non-transiently store computer-executable instructions. The processor 501 is used to execute the computer-executable instructions. When the computer-executable instructions are run by the processor 501, the signal line electromigration inspection method according to any one of the above embodiments is implemented. For the specific implementation of each step of the signal line electromigration inspection method and the related explanatory content, reference can be made to the embodiments of the signal line electromigration inspection method above, and details are not described here.

[0094] For example, other implementation manners of the signal line electromigration inspection method implemented by the processor 501 executing the computer-readable instructions stored on the memory 502 are the same as those mentioned in the method embodiment part above, and details are not described here.

[0095] For example, the electronic device 500 may further include a communication interface 504, and the communication interface is used to implement communication between the electronic device 500 and other devices.

[0096] For example, the processor 501 and the memory 502 can be disposed on the server side (or cloud).

[0097] For example, the processor 501 may control other components in the electronic device 500 to perform desired functions. The processor 501 may be a central processing unit (CPU), a network processor (NP), a tensor processing unit (TPU), a graphics processing unit (GPU), or other devices with data processing capabilities and / or program execution capabilities; it may also be a digital signal processor (DSP), an application specific integrated circuit (ASIC), a field programmable gate array (FPGA), or other programmable logic devices, discrete gate or transistor logic devices, discrete hardware components. The central processing unit (CPU) may be of the X86 or ARM architecture, etc.

[0098] For example, the memory 502 may include any combination of one or more computer program products, and the computer program products may include various forms of computer-readable storage media, such as volatile memory and / or non-volatile memory. Volatile memory may include, for example, random access memory (RAM) and / or cache memory, etc. Non-volatile memory may include, for example, read-only memory (ROM), hard disk, erasable programmable read-only memory (EPROM), portable compact disc read-only memory (CD-ROM), USB memory, flash memory, etc. One or more computer-readable instructions may be stored on the computer-readable storage medium, and the processor 501 may run the computer-readable instructions to implement various functions of the electronic device 500. Various application programs and various data, etc. may also be stored in the storage medium.

[0099] For example, for a detailed description of the process of the electronic device 500 performing signal line electromigration inspection, reference may be made to the relevant description in the embodiments of the signal line electromigration inspection method, and repeated parts will not be elaborated.

[0100] Figure 6 Schematic diagram of a non-transitory computer-readable storage medium provided by at least one embodiment of the present disclosure. For example, as Figure 6 shown, one or more computer-executable instructions 601 may be non-temporarily stored on the non-transitory computer-readable storage medium 600. For example, when the computer-executable instructions 601 are executed by the processor, one or more steps in the signal line electromigration inspection method described above may be executed.

[0101] For example, the non-transitory computer-readable storage medium 600 may be applied to the above-mentioned electronic device 500. For example, the non-transitory computer-readable storage medium 600 may include the memory 502 in the electronic device 500.

[0102] For example, for the description of the non-transitory computer-readable storage medium 600, reference may be made to the description of the memory 502 in the embodiments of the electronic device 500, and repeated parts will not be elaborated.

[0103] For the present disclosure, the following points also need to be noted:

[0104] (1) The accompanying drawings of the embodiments of the present disclosure only relate to the structures involved in the embodiments of the present disclosure, and other structures can refer to the general design.

[0105] (2) For clarity, in the accompanying drawings used to describe the embodiments of the present invention, the thickness and dimensions of layers or structures are enlarged. It can be understood that when an element such as a layer, film, region, or substrate is referred to as being "on" or "under" another element, the element can be "directly" on or under the other element, or there can be intermediate elements.

[0106] (3) Without conflict, the embodiments of the present disclosure and the features in the embodiments can be combined with each other to obtain new embodiments.

[0107] The above is only the specific implementation manner of the present disclosure, but the protection scope of the present disclosure is not limited thereto. The protection scope of the present disclosure shall be subject to the protection scope of the claims.

Claims

1. A method for checking the electromigration of signal lines in a clock network, wherein, The clock network includes a plurality of receiving units, at least one main clock signal line, and a plurality of connection structures. Each connection structure includes at least one secondary clock signal line. The method for checking electromigration of the signal line includes: Determine at least one main connection hole located on the at least one main clock signal line, where each main connection hole corresponds to at least one receiving unit; Based on the at least one main connection hole, generate at least one hole network corresponding one-to-one to the at least one main connection hole. Each hole network includes the main connection hole corresponding to each hole network, at least one receiving unit connected to the main connection hole, and at least one connection structure for connecting the main connection hole and the at least one receiving unit; Generate a target design interchange format file based on the at least one hole network; Perform signal line electromigration inspection on the clock network based on the target design interchange format file.

2. The signal line electromigration inspection method according to claim 1, wherein, Generating at least one hole network corresponding one-to-one to the at least one main connection hole based on the at least one main connection hole includes: For the i-th main connection hole among the at least one main connection hole: Determine N receiving units among the plurality of receiving units that are connected to the i-th main connection hole; Determine N connection structures corresponding one-to-one to the N receiving units, where each of the N receiving units is connected to the i-th main connection hole through one of the N connection structures; Generate a hole network corresponding to the i-th main connection hole based on the i-th main connection hole, the N receiving units, and the N connection structures, where both N and i are positive integers.

3. The signal line electromigration inspection method according to claim 1, wherein, Each connection structure further includes at least one secondary connection hole.

4. The signal line electromigration inspection method according to claim 1, wherein, Generating a target design interchange format file based on the at least one hole network includes: Obtain an initial design interchange format file, where the initial design interchange format file includes description information of the clock network; Delete the description information of the clock network from the initial design interchange format file; Correspondingly set at least one primary pin for each of the at least one main connection hole; Add at least one pin description corresponding to each of the at least one primary pin and at least one network description corresponding to each of the at least one hole network to the initial design interchange format file to obtain the target design interchange format file.

5. The signal line electromigration inspection method according to claim 4, wherein, The initial design interchange format file includes a pin part and a network part, Adding at least one pin description corresponding to each of the at least one primary pin and at least one network description corresponding to each of the at least one hole network to the initial design interchange format file includes: Add the at least one pin description to the pin part of the initial design interchange format file; Add the at least one network description to the network part of the initial design interchange format file.

6. The signal line electromigration inspection method according to claim 4, wherein, The pin description corresponding to each primary pin includes the name of the primary pin, the name of the via net to which the main connection via corresponding to the primary pin belongs, the direction corresponding to the primary pin, the attributes corresponding to the primary pin, the position information and shape information of the main connection via corresponding to the primary pin.

7. The signal line electromigration inspection method according to claim 4, wherein, The net description corresponding to each via net includes the name of the via net, the logical connection relationship of the receiving units in the via net, the physical information corresponding to the via net, the routing rules corresponding to the via net, the attributes corresponding to the via net. The physical information includes the position information and shape information of the main connection vias in the via net, and the shape information and position information of all secondary clock signal lines in the connection structure in the via net.

8. The signal line electromigration inspection method according to any one of claims 1-7, wherein, In each via net, the main connection via is directly connected to each receiving unit in each via net through a corresponding connection structure.

9. The signal line electromigration inspection method according to any one of claims 1-7, wherein Performing signal line electromigration inspection on the clock network based on the target design interchange format file includes: Performing signal line electromigration inspection on the secondary clock signal lines in the multiple connection structures based on the target design interchange format file.

10. An apparatus for checking electromigration of signal lines in a clock network, wherein, The clock network includes multiple receiving units, at least one main clock signal line, and multiple connection structures, and each connection structure includes at least one secondary clock signal line. The signal line electromigration inspection device includes: A determination unit configured to determine at least one main connection via located on the at least one main clock signal line; A net generation unit configured to generate at least one via net corresponding one-to-one to the at least one main connection via based on the at least one main connection via, where each via net includes the main connection via corresponding to each via net, at least one receiving unit connected to the main connection via, and at least one connection structure for connecting the main connection via and the at least one receiving unit; A file generation unit configured to generate a target design interchange format file based on the at least one via net; An inspection unit configured to perform signal line electromigration inspection on the clock network based on the target design interchange format file.

11. An electronic device, comprising: A memory that stores computer-executable instructions non-transiently; A processor configured to run the computer-executable instructions, wherein, when the computer-executable instructions are run by the processor, the signal line electromigration inspection method according to any one of claims 1-9 is implemented.

12. A non-transitory computer-readable storage medium, wherein, The non-transient computer-readable storage medium stores computer-executable instructions, and when the computer-executable instructions are executed by a processor, the signal line electromigration inspection method according to any one of claims 1-9 is implemented.

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