Semiconductor device having multiple signal buses for multiple purposes

Abstract

A semiconductor device having multiple signal buses for multiple purposes is disclosed. A method for designing a semiconductor device is disclosed herein, the method comprising: allocating a plurality of routing tracks including a first track and a second track; connecting a first data I / O circuit to a first data node of a first circuit through a first signal bus disposed on the first routing track; connecting a second data I / O circuit to a second data node of the first circuit through a second signal bus disposed on the second routing track when a first design mode is selected; and connecting the first data I / O circuit to a second circuit through the second signal bus disposed on the second routing track when a second design mode is selected.

Description

TECHNICAL FIELD

[0001] The present application relates to a semiconductor device having a plurality of signal buses for a plurality of purposes. BACKGROUND

[0002] There are cases where a semiconductor device such as a DRAM is designed to be switchable to a plurality of operation modes at the time of manufacture by changing a mask or switching a fuse. For example, there are semiconductor devices designed to allow the number of data I / O terminals for inputting and outputting data to be switched. In this case, a part of a read / write bus can become unused depending on the number of data I / O terminals to be used. SUMMARY

[0003] In one aspect, the present application provides an apparatus comprising: an array of memory cells; a data connection circuit coupled to the array of memory cells; a first data I / O circuit and a second data I / O circuit, each comprising a data I / O terminal; a first signal bus and a second signal bus; and a data interface circuit comprising another data I / O terminal, wherein the first data I / O circuit is coupled to the array of memory cells through the first signal bus and the data connection circuit, wherein the first data I / O circuit is further coupled to the data interface circuit through the second signal bus, and wherein the second data I / O circuit is disconnected from the data connection circuit so as to be unable to input / output data to / from the array of memory cells.

[0004] In another aspect, the present application provides an apparatus comprising: a data I / O circuit comprising a data I / O terminal; a data interface circuit comprising another data I / O terminal; a command / address input circuit comprising a command / address terminal; a command / address interface circuit comprising another command / address terminal; a data control circuit coupled to the data I / O circuit; a command / address control circuit coupled to the command / address input circuit; a first signal bus arranged on a first routing track, the first signal bus coupling the data control circuit to the data I / O circuit; a second signal bus arranged on a first section of a second routing track, the second signal bus coupling the data interface circuit to the data I / O circuit; and a third signal bus arranged on a second section of the second routing track, the third signal bus coupling the command / address control circuit to the command / address interface circuit.

[0005] In yet another aspect, the present application provides a method for designing a semiconductor device, the method including: allocating a plurality of wiring tracks including a first track and a second track; connecting a first data I / O circuit to a first data node of a first circuit through a first signal bus disposed on the first wiring track; connecting a second data I / O circuit to a second data node of the first circuit through a second signal bus disposed on the second wiring track when a first design mode is selected; and connecting the first data I / O circuit to a second circuit through the second signal bus disposed on the second wiring track when a second design mode is selected. BRIEF DESCRIPTION OF DRAWINGS

[0006] Figure 1 is a schematic plan view of a semiconductor device according to the present disclosure;

[0007] Figures 2A to 2C is a schematic diagram for explaining how to use a plurality of tracks on which read / write buses are formed;

[0008] Figure 3A and 3B is a schematic diagram for explaining how to use read / write buses when an x8 operation mode is selected in a first operation mode;

[0009] Figure 4 is a block diagram for explaining a circuit configuration of a data I / O circuit;

[0010] Figure 5A and 5B is a schematic diagram for explaining how to use read / write buses when an x4 operation mode is selected in a first operation mode;

[0011] Figure 6 is a block diagram for explaining a connection relationship between a master chip and a slave chip;

[0012] Figure 7A and 7B is a schematic diagram for explaining a connection method of a master chip and a slave chip; and

[0013] Figure 8A and 8B is a schematic diagram for explaining how to use read / write buses in a second operation mode. DETAILED DESCRIPTION

[0014] Various embodiments of the present application will be explained in detail below with reference to the drawings. The following detailed description references the drawings, wherein the same reference numbers in different drawings represent the same elements. The drawings supplied herewith are for purposes of explanation and are not limiting on the application, unless otherwise specified. The detailed description is described with reference to the accompanying drawings in which the same or similar elements refer to the same or similar elements. Various embodiments of the present application are disclosed herein. The various embodiments disclosed herein are not necessarily mutually exclusive, as some disclosed embodiments can be combined with one or more other disclosed embodiments to form new embodiments.

[0015] Figure 1 The illustrated semiconductor device 10 includes memory cell arrays 11 and 12, a plurality of data I / O terminals 13, and a plurality of command / address input terminals 14. The data I / O terminals 13 and the command / address input terminals 14 are located in a central portion in a y direction of the semiconductor device 10 and are arranged in an x direction. A read / write bus 15 extending in the x direction is provided in the central portion in the y direction of the semiconductor device 10. As shown in FIG. 1, the read / write bus 15 includes a plurality of tracks 15A assigned to input / output data DQ0 to DQ3 and a plurality of tracks 15B assigned to input / output data DQ4 to DQ7. The tracks all extend parallel to each other in the x direction and are located in the same wiring layer. The cross-sectional area of the read / write bus 15 formed on each track is equal to the cross-sectional area of the read / write bus 15 on another track. Figure 2A As shown, the read / write bus 15 includes a plurality of tracks 15A assigned to input / output data DQ0 to DQ3 and a plurality of tracks 15B assigned to input / output data DQ4 to DQ7. The tracks all extend parallel to each other in the x direction and are located in the same wiring layer. The cross-sectional area of the read / write bus 15 formed on each track is equal to the cross-sectional area of the read / write bus 15 on another track.

[0016] The semiconductor device 10 according to the present embodiment is designed to be switchable to a plurality of operating modes at the time of manufacture by changing a mask. A first operating mode is designed for a single-die package. In the case where the first operating mode is selected, the number of data I / O terminals 13 for input and output data can also be changed. For example, a mode using eight of the data I / O terminals 13 (x8 operating mode) or a mode using four of the data I / O terminals 13 (x4 operating mode) can be selected. A second operating mode is designed for a 3D stacked package. In the 3D stacked package, a plurality of semiconductor devices 10 are stacked, the lowermost semiconductor device 10 is used as a master chip, and the remaining semiconductor devices 10 are used as slave chips. In the second operating mode, operation is performed in the mode using four of the data I / O terminals 13 (x4 operating mode).

[0017] In the case where the x8 operating mode is selected in the first operating mode, as shown in FIG. 2, the data I / O terminals 13 are used as input / output data terminals for input / output data DQ0 to DQ7. In the case where the x4 operating mode is selected in the first operating mode, as shown in FIG. 3, the data I / O terminals 13 are used as input / output data terminals for input / output data DQ0 to DQ3. Figure 3AAs shown, data I / O circuits 20 to 27, corresponding to input / output data DQ0 to DQ7 respectively, are connected to data connection circuit 16 via read / write bus 15. Data connection circuit 16 controls the transmission and reception of data read and write between data I / O circuits 20 to 27 and each memory cell in memory cell arrays 11 and 12.

[0018] like Figure 4 As shown, data I / O circuits 20 to 27 each include a corresponding data I / O terminal of data I / O terminals 13, both an output buffer 31 and an input receiver 32 connected to the data I / O terminal 13, a parallel / serial conversion circuit 33 connected to the output buffer 31, and a serial / parallel conversion circuit 34 connected to the input receiver 32. The parallel / serial conversion circuit 33 converts parallel read data DQ supplied from the data connection circuit 16 via the read / write bus 15 into serial data and supplies the serial data to the output buffer 31. The serial / parallel conversion circuit 34 converts serial write data DQ output from the input receiver 32 into parallel data and supplies the parallel data to the read / write bus 15. Data I / O circuits 20 to 23, corresponding to input / output data DQ0 to DQ3, are connected to the data connection circuit 16 via a read / write bus 15 routed on track 15A, and data I / O circuits 24 to 27, corresponding to input / output data DQ4 to DQ7, are connected to the data connection circuit 16 via a read / write bus 15 routed on track 15B. That is, as... Figure 2A As shown, the read / write bus 15 on both tracks 15A and 15B is used for inputting and outputting data.

[0019] When the x8 operation mode is selected in the first operation mode, such as Figure 3B As shown, the command / address signals input via command / address input circuits 40 to 49 are input to command / address decoder 17. Each command / address circuit in command / address circuits 40 to 49 includes a corresponding command / address terminal in command / address terminal 14. Figure 3B In the illustrated example, command address signals CA0 through CA7 are input to command / address input circuits 40 through 47, and complementary clock signals CK_t and CK_c are input to command / address input circuits 48 and 49, respectively. Command / address decoder 17 decodes command / address signals CA0 through CA7 synchronously with clock signals CK_t and CK_c, thereby generating internal commands and internal addresses. The internal commands and internal addresses are supplied to memory cell arrays 11 and 12.

[0020] When the x4 operation mode is selected in the first operation mode, such as Figure 5AThe data I / O circuits 20 to 23 corresponding to the input / output data DQ0 to DQ3, respectively, are connected to the data connection circuit 16 through the read / write bus 15 on the track 15A by wiring as shown. The data I / O circuits 24 to 27 corresponding to the input / output data DQ4 to DQ7 are not used. That is, as shown in FIG. 2, the data I / O circuits 20 to 23 are connected to the data connection circuit 16 through the read / write bus 15 on the track 15A by wiring, and the data I / O circuits 24 to 27 are not connected to the data connection circuit 16. Figure 2B As shown, the track 15A in the read / write bus 15 is used for input and output of data, and the track 15B is not used. The connections between the command / address input circuits 40 to 49 and the command / address decoder 17 are the same as in the case where the x8 operation mode is selected in the first operation mode. The read / write bus 15 on the unused track 15B can be disconnected near the data I / O circuits 24 to 27 and near the data connection circuit 16. In this case, the data connection circuit 16 inputs and outputs data through the nodes 16A connected to the read / write bus 15 on the track 15A, respectively. At the same time, the nodes 16B corresponding to the read / write bus 15 on the track 15B are deactivated so that input and output of data through the nodes 16B cannot be performed. Figure 5B As shown, the track 15A in the read / write bus 15 is used for input and output of data, and the track 15B is not used. The connections between the command / address input circuits 40 to 49 and the command / address decoder 17 are the same as in the case where the x8 operation mode is selected in the first operation mode. The read / write bus 15 on the unused track 15B can be disconnected near the data I / O circuits 24 to 27 and near the data connection circuit 16. In this case, the data connection circuit 16 inputs and outputs data through the nodes 16A connected to the read / write bus 15 on the track 15A, respectively. At the same time, the nodes 16B corresponding to the read / write bus 15 on the track 15B are deactivated so that input and output of data through the nodes 16B cannot be performed.

[0021] As described above, in the first operation mode, in the case where the x8 operation mode is selected, both the tracks 15A and 15B are used for input and output of data, and in the case where the x4 operation mode is selected, only the track 15A is used for input and output of data.

[0022] As shown, in the case where the second operation mode is selected, at least two semiconductor devices 10M and 10S are packaged as a 3D stacked package. The semiconductor device 10M is a master chip, and the semiconductor device 10S is a slave chip. The semiconductor device 10M as the master chip is directly connected to the controller 2, and the semiconductor device 10S as the slave chip is connected to the controller 2 through the master chip. The semiconductor devices 10M and 10S are stacked on the substrate 60 as shown in FIG. 4. Figure 6 As shown, in the case where the second operation mode is selected, at least two semiconductor devices 10M and 10S are packaged as a 3D stacked package. The semiconductor device 10M is a master chip, and the semiconductor device 10S is a slave chip. The semiconductor device 10M as the master chip is directly connected to the controller 2, and the semiconductor device 10S as the slave chip is connected to the controller 2 through the master chip. The semiconductor devices 10M and 10S are stacked on the substrate 60 as shown in FIG. 4. Figure 7A and 7B As shown, in the case where the second operation mode is selected, at least two semiconductor devices 10M and 10S are packaged as a 3D stacked package. The semiconductor device 10M is a master chip, and the semiconductor device 10S is a slave chip. The semiconductor device 10M as the master chip is directly connected to the controller 2, and the semiconductor device 10S as the slave chip is connected to the controller 2 through the master chip. The semiconductor devices 10M and 10S are stacked on the substrate 60 as shown in FIG. 4. Figure 7B As shown, the semiconductor device 10S can be connected to the semiconductor device 10M through the TSV 61 provided to penetrate the semiconductor device 10M or through the bonding wire 62 and the wiring pattern 63 provided on the substrate 60 as shown in FIG. 5. Figure 7A As shown, the semiconductor device 10S can be connected to the semiconductor device 10M through the TSV 61 provided to penetrate the semiconductor device 10M or through the bonding wire 62 and the wiring pattern 63 provided on the substrate 60 as shown in FIG. 5.

[0023] The connection between semiconductor device 10M and semiconductor device 10S is established via 3DS interface circuits 51 and 52. 3DS interface circuit 51 is used for data, and 3DS interface circuit 52 is used for commands and addresses. When semiconductor device 10S performs a write operation, the write data DQ0 to DQ3 to be written to semiconductor device 10S is input from controller 2 to data I / O circuits 20 to 23 of semiconductor device 10M, and then transmitted to data I / O circuits 20 to 23 of semiconductor device 10S via 3DS interface circuit 51. Therefore, semiconductor device 10S can perform a write operation as if the write data DQ0 to DQ3 were input to its own data I / O circuits 20 to 23. Simultaneously, when semiconductor device 10S performs a read operation, the read data DQ0 to DQ3 read from semiconductor device 10S is transmitted to data I / O circuits 20 to 23 of semiconductor device 10M via its own data I / O circuits 20 to 23 and 3DS interface circuit 51. Therefore, controller 2 can receive read data DQ0 to DQ3 as if read data DQ0 to DQ3 were output from semiconductor device 10M.

[0024] Command / address signals supplied from controller 2 are input to command / address input circuits 40 to 49 of semiconductor device 10M and decoded by command / address decoder 17 in semiconductor device 10M. When accessing semiconductor device 10M, internal commands and internal addresses are supplied to memory cell arrays 11 and 12 in semiconductor device 10M. Simultaneously, when accessing semiconductor device 10S, internal commands and internal addresses are supplied to semiconductor device 10S via 3DS interface circuit 52. Therefore, command / address input circuits 40 to 49 are not used in semiconductor device 10S, which is a slave chip.

[0025] like Figure 8A As shown, in the second operating mode, data I / O circuits 20 to 23 corresponding to input / output data DQ0 to DQ3 are connected to the data connection circuit 16 via a read / write bus 15 wired on track 15A, and are also connected to the 3DS interface circuit 51 via a read / write bus 15 wired on track 15B. Data I / O circuits 24 to 27 are unused and disconnected from the data connection circuit 16. Additionally, as... Figure 8BAs shown, the command / address decoder 17 is connected to the 3DS interface circuit 52 through the read / write bus 15 on the track 15B by wiring. That is, the track 15A in the read / write bus 15 is used for inputting and outputting data to and from the corresponding semiconductor device 10, the section 15B1 of the track 15B is used for data transfer between the corresponding semiconductor device 10 and another semiconductor device 10, and the other section 15B2 of the track 15B is used for transferring command / address signals between the corresponding semiconductor device 10 and another semiconductor device 10, as shown in FIG. 2. Figure 2C The sections 15B1 and 15B2 of the track 15B are shorter than the track 15A. Such switching of the wiring can be easily achieved by changing a mask pattern in the manufacture of the semiconductor device 10.

[0026] In the second operation mode, the node 16B of the data connection circuit 16 is disconnected from the track 15B. That is, the node 16B is deactivated so that data input and output through the node 16B cannot be performed.

[0027] As described above, in the second operation mode designed for 3D package-on-package, the semiconductor device 10 according to the present embodiment uses the track 15B which is not used for inputting and outputting data to and from the semiconductor device 10, and allocates a part of those tracks to data transfer and another part to command / address transfer. Therefore, it is not necessary to add wiring for data transfer and command / address transfer, respectively. Thus, the chip size can be reduced while ensuring compatibility between the first operation mode and the second operation mode.

[0028] While the application has been disclosed in the context of certain preferred embodiments and examples, it will be understood that the application extends beyond the specifically disclosed embodiments to other alternative embodiments and / or uses of the application and obvious modifications and equivalents thereof. Further, it will be understood that other modifications are possible within the scope of the application. It will be understood that various features and aspects of the disclosed embodiments can be combined or substituted with one another to form various modes of the disclosed application. Accordingly, it is intended that the scope of at least some of the application herein disclosed should be limited only by the appended claims.

Claims

1. A semiconductor device comprising: an array of memory cells; data connection circuitry coupled to the array of memory cells; first and second data I / O circuitry each including a data I / O terminal; first and second signal buses; and data interface circuitry including another data I / O terminal, wherein the first data I / O circuitry is coupled to the array of memory cells through the first signal bus and the data connection circuitry, wherein the first data I / O circuitry is further coupled to the data interface circuitry through the second signal bus when a first design mode is selected, wherein the second data I / O circuitry is disconnected from the data connection circuitry to be unable to input / output data to / from the array of memory cells when the first design mode is selected, and wherein the second data I / O circuitry is coupled to the array of memory cells through the second signal bus and the data connection circuitry when a second design mode is selected.

2. The semiconductor device of claim 1, wherein the first and second signal buses extend in parallel to each other.

3. The semiconductor device of claim 2, wherein the second signal bus is shorter than the first signal bus.

4. The semiconductor device of claim 3, wherein the first and second signal buses are located at the same wiring layer as each other.

5. The semiconductor device of claim 4, wherein the first and second signal buses have the same cross-sectional area as each other.

6. The semiconductor device of claim 1, wherein the data connection circuitry has first and second data nodes respectively assigned to the first and second data I / O circuitry, wherein the first data node is coupled to the first data I / O circuitry through the first signal bus, and wherein the second data node is configured to be deactivated to be unable to input / output data.

7. The semiconductor device of claim 1, further comprising: command / address input circuitry including command / address terminals; a third signal bus extending in parallel to the first and second signal buses; command / address decoder circuitry; and command / address interface circuitry including another command / address terminal, wherein the command / address decoder circuitry is coupled to the command / address input circuitry, and wherein the command / address decoder circuitry is further coupled to the command / address interface circuitry through the third signal bus.

8. The semiconductor device of claim 7, wherein the third signal bus is shorter than the first signal bus.

9. The semiconductor device of claim 8, wherein the first, second, and third signal buses are located at the same wiring layer as each other. ​ ​ 10. The semiconductor device of claim 9, wherein the first signal bus, the second signal bus, and the third signal bus have the same cross-sectional area as one another.

11. The semiconductor device of claim 7, wherein the second signal bus and the third signal bus are arranged at different routing tracks than the first signal bus.

12. The semiconductor device of claim 11, wherein the second signal bus and the third signal bus are arranged at the same routing track as one another.

13. A semiconductor device, comprising: a first data I / O circuit including first data I / O terminals; a second data I / O circuit including second data I / O terminals; a third data I / O circuit including third data I / O terminals; a data interface circuit including further data I / O terminals; a command / address input circuit including command / address terminals; a command / address interface circuit including further command / address terminals; a data control circuit coupled to the data I / O circuit; a command / address control circuit coupled to the command / address input circuit; a first signal bus arranged on a first routing track, the first signal bus coupling the data control circuit to the first data I / O circuit; a second signal bus arranged on a first section of a second routing track, wherein the second signal bus couples the data interface circuit to the first data I / O circuit when a first design mode is selected, and wherein the second signal bus couples the data control circuit to the second data I / O circuit when a second design mode is selected; and a third signal bus arranged on a second section of the second routing track, wherein the third signal bus couples the command / address control circuit to the command / address interface circuit when the first design mode is selected, and wherein the third signal bus couples the data control circuit to the third data I / O circuit when the second design mode is selected.

14. The semiconductor device of claim 13, wherein the first routing track and the second routing track extend parallel to one another.

15. The semiconductor device of claim 14, wherein the first routing track and the second routing track are located at the same routing layer as one another.

16. The semiconductor device of claim 15, wherein the first signal bus, the second signal bus, and the third signal bus have the same cross-sectional area as one another.

17. A method for designing a semiconductor device, the method comprising: allocating a plurality of routing tracks including a first routing track and a second routing track; connecting a first data I / O circuit to first data nodes of a first circuit by a first signal bus arranged on the first routing track; when the first design mode is selected, connecting a second data I / O circuit to a second data node of the first circuit through a second signal bus disposed on the second routing track; and when the second design mode is selected, connecting the first data I / O circuit to a second circuit through the second signal bus disposed on the second routing track.

18. The method of claim 17, further comprising: when the second design mode is selected, disconnecting the second data I / O circuit from the first circuit.

19. The method of claim 17, further comprising: when the second design mode is selected, connecting a command / address control circuit to a third circuit through a third signal bus disposed on the second routing track.

20. The method of claim 19, further comprising: when the first design mode is selected, disconnecting the command / address control circuit from the third circuit.

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