Fast and low power word line driver circuit for NOR Flash

Abstract

The present invention discloses a fast and low-power word line driving circuit applied to NOR Flash, including an operating mode and a standby mode. The operating mode includes a charge pump power stage composed of a cross-coupled charge pump; a dynamic frequency modulation voltage stabilization circuit composed of a non-overlapping clock generation circuit, a voltage-controlled oscillator, an error amplifier and a resistor divider. The standby mode includes a charge pump power stage composed of a Dickson charge pump; a SKIP modulation voltage stabilization circuit composed of a non-overlapping clock generator, a current-starved oscillator, a hysteresis comparator, a subtraction counter, an inverter, a NOR gate, a capacitor divider and a VD point refresh circuit. In addition, an ultra-low power consumption voltage reference source continuously provides a reference voltage in two modes, and a diode-connected NMOS device M5 and an output load capacitor Cout form a low-pass filter to optimize the output voltage ripple. The present invention can achieve fast and efficient voltage boosting in the operating mode, and output with stable low ripple; at the same time, it can maintain the required voltage with low power consumption in the standby mode.

Description

Technical Field

[0001] The present invention relates to the technical field of semiconductor memory, and in particular to a fast and low-power word line driving circuit applied to NOR Flash. Background Art

[0002] In recent years, memory has continued to attract attention as the device category with the best revenue in the global semiconductor industry. As a type of flash memory, NOR (non-OR) Flash is widely used in automotive electronics, smart wearables, mobile phone displays, the Internet of Things and other fields due to its fast access speed. Especially in the field of high-reliability memory chips that require automotive-grade certification, the value of NOR Flash is irreplaceable.

[0003] The read, write, and erase operations of the Flash memory require the application of multiple different operating voltages to each port, but only a uniform power supply voltage is provided outside the memory, so a boost circuit is required inside the chip.

[0004] Since NOR Flash has the characteristic of fast access, the word line voltage needs to be quickly established by the boost circuit to be satisfied; and the ripple of the output voltage is also a kind of noise for the load. Large ripple will make the load circuit unable to work normally. For Flash devices, large voltage ripple will affect the erasure and programming of the storage unit, causing the threshold voltage of the floating gate transistor to deviate from the expected value, thus causing data access errors.

[0005] In addition to the charge pump boost system required for various operations, NOR Flash also needs to meet the special requirements of maintaining the required voltage and reducing chip power consumption under the premise of fast random read time. This is a problem that needs to be solved in NOR Flash standby mode.

[0006] For traditional word line driver circuits, the same type of charge pump and voltage regulator are used in both the working mode and standby mode. In fact, the requirements for word line driver circuits in the two modes are different: in the working mode, a fast boost and low ripple stable output voltage is required for memory read, write, and erase operations; in the standby mode, the required voltage needs to be maintained and low power consumption is achieved. The charge pump type and voltage regulator system used in the working mode of traditional word line driver circuits are very difficult to meet higher circuit performance requirements, and the standby power consumption is high in the standby mode. Summary of the invention

[0007] In order to enable a word line driving circuit to achieve higher performance index requirements in both an operating mode and a standby mode, an object of the present invention is to provide a fast and low-power word line driving circuit applied to NOR Flash.

[0008] A fast and low-power word line driving circuit applied to NOR Flash, including two modes: working mode and standby mode;

[0009] The circuit in the working mode includes:

[0010] An operating mode charge pump power stage, including a cross-coupled charge pump, for generating high voltage;

[0011] The dynamic frequency modulation voltage stabilization circuit includes a voltage-controlled oscillator, a non-overlapping clock generation circuit module, an error amplifier EA, and resistor dividers R1 and R2, and is used to output the high voltage generated by the charge pump stably and with low ripple under all PVT (process, voltage, temperature);

[0012] Ultra-low power voltage reference source, providing reference voltage VREF for error amplifier EA;

[0013] The NMOS device M1 is used as a switch tube and is controlled by the signal ACT_EN to trigger the working mode; The NMOS device M5 can form a low-pass filter with the load capacitor Cout to effectively suppress the output voltage ripple;

[0014] The circuit in the standby mode includes:

[0015] Standby mode charge pump power stage, including a DICKSON charge pump, for generating high voltage;

[0016] The SKIP modulation voltage stabilization circuit includes, in sequence, a current starved oscillator, a non-overlapping clock generation circuit, a hysteresis comparator, a subtraction counter, an inverter module, a NOR gate, a capacitive voltage divider, and a refresh circuit of a connection point VD of the capacitive voltage divider C1 and C2, for maintaining the output voltage in the standby mode;

[0017] An ultra-low power voltage reference source, used to provide a reference voltage VREF for the hysteresis comparator COM and a bias voltage VBIAS for the current-starved oscillator;

[0018] The NMOS device M2, as a switch tube, is controlled by the signal ACT_ENB to trigger the standby mode;

[0019] The subtraction counter counts to control the charging time of the charge pump in each standby mode, and continues to work before the subtraction counter counts to 0 to avoid overshoot of the output voltage;

[0020] The inverter module includes inverters INV1 to INV3, INV1 and INV2 are used to rectify the output signal of the hysteresis comparator COM, and INV3 is used to invert the output signal of the subtractor to generate an ENPD signal;

[0021] The NOR gate is used to generate a standby mode enable signal STB_EN to control a current starved oscillator and a DICKSON charge pump under the control of the signal ENPD and the signal ACT_EN;

[0022] The refresh circuit of the connection point VD of the capacitors C1 and C2 includes, in sequence, an NMOS device M3 controlled by an enable signal ACT_EN, a PMOS device M4 controlled by an enable signal ACT_ENB, and resistors R3 and R4, which are used to provide an initial voltage for the connection point VD and refresh the connection point VD when switching between the two modes.

[0023] The cross-coupled charge pump in the described working mode is provided with a pre-charge tube to optimize the rise time and a substrate modulation tube to suppress the reverse leakage current.

[0024] The ultra-low power consumption voltage reference source adopts a resistor-free full MOS tube structure, uses NMOS devices in the deep triode region to replace resistors, and the remaining MOS devices are in the subthreshold region, thereby achieving nw-level power consumption.

[0025] The current starved oscillator in the standby mode circuit and the MOS devices in the hysteresis comparator all work in the subthreshold region, with low static power consumption and a static current at the nA level.

[0026] The NMOS device M5 is connected in a diode manner and uses a low threshold voltage NMOS device to reduce the threshold voltage loss of the output voltage.

[0027] The PMOS device, NMOS device, MOS device and switch MOS tube are all metal oxide semiconductor MOS transistors.

[0028] Compared with the prior art, the present invention has the following beneficial technical effects:

[0029] In the working mode, a cross-coupled charge pump with small ripple, high efficiency and suitable for low-voltage process is used as the charge pump power stage. A pre-charge tube and a substrate modulation tube are added to the original cross-coupled charge pump structure to optimize the rise time and suppress the reverse leakage current respectively. At the same time, a dynamic frequency modulation voltage stabilization circuit with small ripple, high efficiency and high design complexity is adopted to achieve stable output voltage under different PVT (process, voltage, temperature).

[0030] In standby mode, the Dickson charge pump with simple structure, low power consumption but low efficiency is still used as the charge pump power stage; at the same time, a simple SKIP modulation voltage regulator circuit is used to stabilize the output voltage, and the charging time of the charge pump in each standby mode is controlled by counting the subtraction counter to avoid overshoot. In addition, the MOS devices in the hysteresis comparator and current starved oscillator in standby mode are in the subthreshold region, and the traditional resistor divider as the feedback network is replaced by a capacitor divider. The above measures are used to further reduce the standby power consumption. BRIEF DESCRIPTION OF THE DRAWINGS

[0031] Figure 1 This is a schematic diagram of a traditional word line driving circuit.

[0032] Figure 2 It is a schematic diagram of a fast and low power word line driving circuit in the present invention.

[0033] Figure 3 It is a schematic diagram of the timing waveform of the word line driver system in the present invention.

[0034] Figure 4 It is a schematic diagram of the structure of an optimized single-stage cross-coupled charge pump circuit used in the working mode of the present invention.

[0035] Figure 5 It is a schematic diagram of the spectre simulation transient simulation result of the word line driving circuit in the present invention in the working mode.

[0036] Figure 6 It is a schematic diagram of the spectre simulation transient simulation result of the word line driving circuit in the standby mode of the present invention. DETAILED DESCRIPTION

[0037] The present invention is further described below in conjunction with the accompanying drawings and specific embodiments, but the examples are not intended to limit the present invention.

[0038] As attached Figure 1 The figure shows a schematic diagram of a conventional word line voltage driving circuit. The circuit in the working mode includes a DICKSON charge pump, a ring oscillator, a comparator, and a resistor divider composed of small resistors R1 and R2 (K ohm level); the circuit in the standby mode includes a DICKSON charge pump, a ring oscillator, a comparator, a latch and a counter, and a resistor divider composed of large resistors R3 and R4 (M ohm level). In addition, a high-resistance, low-power voltage reference source continuously provides a reference voltage for both modes. It can be seen that both modes use a DICKSON charge pump as the charge pump power stage and a SKIP modulation voltage regulator circuit to stabilize the output voltage. In addition, both modes use a resistor divider as the feedback network in the voltage regulator circuit.

[0039] The disadvantage of the traditional word line drive circuit is that both modes use the same charge pump type and the same voltage regulator system, which cannot better meet the different performance requirements of the two modes. For the working mode, since the DICKSON charge pump has the disadvantage of low boost efficiency due to large threshold voltage loss, and the SKIP modulation voltage regulator circuit has the disadvantage of large ripple, the two circuit structures make it difficult to achieve fast word line voltage establishment and low ripple output; and the use of a resistor divider in standby mode will generate additional static power consumption and slow response speed. In addition, the use of a high-resistance voltage reference source as a reference circuit will also reduce chip area utilization.

[0040] As attached Figure 2 The figure shows a schematic diagram of a fast low-power word line driving circuit in the present invention. It includes two modes: working mode and standby mode; the circuit in the working mode includes:

[0041] An operating mode charge pump power stage, including a cross-coupled charge pump, for generating high voltage;

[0042] The dynamic frequency modulation voltage stabilization circuit includes a voltage-controlled oscillator, a non-overlapping clock generation circuit module, an error amplifier EA, and resistor dividers R1 and R2, and is used to output the high voltage generated by the charge pump stably and with low ripple under all PVT (process, voltage, temperature);

[0043] Ultra-low power voltage reference source, providing reference voltage VREF for error amplifier EA;

[0044] The NMOS device M1, as a switch tube, is controlled by the signal ACT_EN for triggering the working mode. In fact, the first-stage cross-coupled charge pump, voltage-controlled oscillator and other modules all have switch MOS tubes controlled by the signal ACT_EN and its inverted signal ACT_ENB for switching between the two modes.

[0045] The NMOS device M5 can form a low-pass filter with the load capacitor Cout to effectively suppress the output voltage ripple.

[0046] The circuit in the standby mode includes:

[0047] Standby mode charge pump power stage, including a DICKSON charge pump, for generating high voltage;

[0048] The SKIP modulation voltage stabilization circuit includes, in sequence, a current starved oscillator, a non-overlapping clock generation circuit, a hysteresis comparator, a subtraction counter, an inverter module, a NOR gate, a capacitive voltage divider, and a refresh circuit of a connection point VD of the capacitive voltage divider C1 and C2, for maintaining the output voltage in the standby mode;

[0049] An ultra-low power voltage reference source, used to provide a reference voltage VREF for the hysteresis comparator COM and a bias voltage VBIAS for the current-starved oscillator;

[0050] The NMOS device M2, as a switch tube, is controlled by the signal ACT_ENB for triggering the standby mode; in fact, the first-stage DICKSON charge pump, current-starved oscillator and other modules all have switch MOS tubes controlled by the signal STB_EN for switching between the two modes.

[0051] The subtraction counter counts to control the charging time of the charge pump in each standby mode, and continues to work before the subtraction counter counts to 0 to avoid overshoot of the output voltage.

[0052] The inverter module includes inverters INV1 to INV3, INV1 and INV2 are used to rectify the output signal of the hysteresis comparator COM, and INV3 is used to invert the output signal of the subtractor to generate an ENPD signal.

[0053] The NOR gate is used to generate a standby mode enable signal STB_EN to control a current starved oscillator and a DICKSON charge pump under the control of the signal ENPD and the signal ACT_EN.

[0054] The refresh circuit of the connection point VD of the capacitors C1 and C2 includes, in sequence, an NMOS device M3 controlled by an enable signal ACT_EN, a PMOS device M4 controlled by an enable signal ACT_ENB, and resistors R3 and R4, which are used to provide an initial voltage for the connection point VD and refresh the connection point VD when switching between the two modes.

[0055] The same as the traditional word line driving circuit is that it also includes two modes, the working mode and the standby mode. The difference is that: the word line driving circuit in the present invention replaces the DICKSON charge pump in the working mode of the traditional circuit with a cross-coupled charge pump after structural optimization, and replaces the SKIP modulation voltage stabilization circuit with a dynamic frequency modulation voltage stabilization circuit; since the output voltage needs to drop slightly when the word line driving circuit starts to work, the output voltage in the standby mode does not need to be particularly accurate, etc., the present invention still uses the DICKSON charge pump in the traditional word line driving circuit as the charge pump power stage, and the SKIP modulation voltage stabilization circuit to stabilize the output voltage, and also replaces the resistor voltage divider in the SKIP modulation voltage stabilization circuit in the standby mode with a capacitor voltage divider to reduce the standby power consumption and improve the response time of the feedback loop; in addition, the high-resistance low-power consumption voltage reference source in the traditional circuit is replaced by an ultra-low-power consumption voltage reference source of all MOS tubes, thereby improving the chip area utilization rate, and at the same time, an NMOS device connected in a diode manner is added at the voltage output position to further optimize the output voltage ripple.

[0056] The following is an introduction to the implementation methods of the two modes:

[0057] When the word line drive circuit is in working mode, the three-stage cross-coupled charge pump quickly boosts the voltage. When the charge pump is just charged, the output voltage is low. After detection by the resistor divider R1 and R2, the feedback voltage VFB obtained is less than the reference voltage VREF, and the output VCTRL of the error amplifier EA will tend to saturate, so that the voltage-controlled oscillator generates a high-frequency clock signal ACT_CLK, and the charge pump charging will be accelerated and quickly stabilized to the target word line voltage. A diode-connected NMOS device M5 is also added at the output position of the word line voltage Vwl, which forms a low-pass filter with the output load capacitor Cout to further optimize the output voltage ripple.

[0058] When the word line driving circuit enters the standby mode, the six-stage Dickson charge pump starts charging. When the output voltage is detected by the capacitor voltage divider and the voltage at the VD point is less than the reference voltage VREF, the hysteresis comparator COM outputs a high level. After rectification by the two-stage inverters INV1 and INV2, the signal ENP is generated to trigger the subtraction counter to count. After passing through the inverter INV3, the signal ENPD is generated. The enable signal STB_EN generated by the signal ENPD and the signal ACT_EN through the NOR gate will start the current starved oscillator to generate the low-frequency clock STB_CLK to drive the charge pump. The charge pump will continue to work before the subtraction counter counts to 0.

[0059] After the charge pump is charged in standby mode, the signal STB_EN returns to a low level, and the DICKSON charge pump and the current-starved oscillator stop working. However, since there is inevitably leakage current at the output voltage Vwl, which will cause the output voltage to drop, the voltage detector composed of the capacitor voltage divider C1, C2, the hysteresis comparator, etc. needs to continue to work to detect the output voltage. Once it is detected that the output voltage drops below the target value, the standby mode enable signal STB_EN will once again flip to a high level to start the charge pump and oscillator. We note that in standby mode, a circuit is required to refresh the connection point VD of the capacitors C1 and C2, which includes an NMOS device M3 controlled by the enable signal ACT_EN, a PMOS device M4 controlled by the enable signal ACT_ENB, and resistors R3 and R4. This circuit is used to provide an initial voltage for the connection point VD and refresh the connection point VD when switching between the two modes.

[0060] As attached Figure 3It is a timing waveform diagram of the word line driving circuit system in the present invention. When the circuit is in working mode, the ACT_EN signal is high, and the ACT_ENB signal and the STB_EN signal are both low. At this time, the voltage-controlled oscillator in the working mode starts to oscillate at high frequency, generating a clock signal ACT_CLK to charge the cross-coupled charge pump, so that the output voltage rises rapidly and stabilizes to the target voltage VOUT_R. The output voltage generates a word line voltage Vwl after ripple optimization.

[0061] When the circuit is in standby mode, the signal ACT_EN is at a low level and the signal ACT_ENB remains at a high level. In standby mode 1, the STB_EN signal becomes high and turns on the current-starved oscillator and DICKSON charge pump in standby mode, raising the output voltage to a value slightly higher than the target voltage. In standby mode 2, the oscillator and charge pump in standby mode do not work, and the voltage detector formed by the hysteresis comparator and the capacitor voltage divider continuously detects whether the output voltage is lower than the target voltage value, thereby entering standby mode 1 again to raise the output voltage.

[0062] As attached Figure 4 The figure shows a schematic diagram of the optimized single-stage cross-coupled charge pump structure used in the working mode of the present invention. The switch tube NMOS devices MN1, MN2 and the PMOS devices MP1 and MP2 are alternately turned on under the drive of two anti-phase clock signals to charge the pump capacitors C1 and C2 to achieve the output voltage Vout lift; in addition, on the basis of the original structure, the NMOS devices MN3 and MN4 connected in a diode manner are added as pre-charge tubes to optimize the output voltage rise time, and the PMOS devices MP10 and MP20 are added so that the substrate potential of MP1 and MP2 is always at a high level, thereby suppressing the reverse leakage current to further improve the pump efficiency.

[0063] As attached Figure 5 The figure shows a schematic diagram of the spectre analog transient simulation results of the word line driving circuit in the present invention in the working mode. In the working mode, the ACT_EN signal is at a high level, and the ACT_ENB signal and the STB_EN signal are at a low level. At this time, the voltage-controlled oscillator in the working mode starts to oscillate at a high frequency, and generates a high-frequency clock signal ACT_CLK to drive the cross-coupled charge pump, so that the output voltage rises quickly to the target voltage VOUT_R. After the output voltage is ripple optimized, the word line voltage Vwl is generated.

[0064] As attached Figure 6The figure shows the schematic diagram of the transient simulation results of the spectre simulation of the word line driving circuit in the standby mode of the present invention. The signal ACT_EN is at a low level, and the signal ACT_ENB continues to be at a high level. When the signal STB_EN becomes high, the current starved oscillator in the standby mode will be turned on to generate a low-frequency clock signal STB_CLK to drive the DICKSON charge pump. The charge pump will continue to work before the subtraction counter counts to 0, and the output voltage will be raised to a value slightly higher than the target voltage; when the signal STB_EN is at a low level, the oscillator and charge pump in the standby mode do not work, and the voltage detector formed by the comparator and the capacitor voltage divider continuously detects whether the output voltage is lower than the target voltage value, thereby turning on the oscillator and the charge pump again. At the same time, since the time required for the modules such as the current starved oscillator, the DICKSON charge pump, and the subtraction counter to work in the entire standby mode is very short compared to the time the entire standby mode lasts, the average power consumption in the standby mode mainly comes from the static power consumption of the circuit. Since the capacitor voltage divider is used to avoid part of the static power consumption, the overall average standby power consumption of the standby mode has been significantly reduced.

[0065] The embodiments described above can be further combined or replaced, and the embodiments are only descriptions of preferred embodiments of the present invention, and do not limit the concept and scope of the present invention. Without departing from the design concept of the present invention, various changes and improvements made by ordinary technicians in this field to the technical solution of the present invention belong to the protection scope of the present invention. The protection scope of the present invention is given by the attached claims and any equivalents thereof.

Claims

1. A fast and low power word line driving circuit applied to NOR Flash, characterized in that: It includes two modes: working mode and standby mode; the circuit in the working mode includes: An operating mode charge pump power stage, including a cross-coupled charge pump, for generating high voltage; The dynamic frequency modulation voltage stabilization circuit includes a voltage controlled oscillator, a non-overlapping clock generation circuit module, an error amplifier EA, and resistor dividers R1 and R2, and is used to output the high voltage generated by the charge pump stably and with low ripple under all PVT conditions; Ultra-low power voltage reference source, providing reference voltage VREF for error amplifier EA; NMOS device M1, as a switch tube, is controlled by signal ACT_EN and used for operating mode triggering; The NMOS device M5 can form a low-pass filter with the load capacitor Cout to effectively suppress the output voltage ripple; The circuit in the standby mode includes: Standby mode charge pump power stage, including a DICKSON charge pump, for generating high voltage; The SKIP modulation voltage stabilization circuit includes, in sequence, a current starved oscillator, a non-overlapping clock generation circuit, a hysteresis comparator, a subtraction counter, an inverter module, a NOR gate, a capacitive voltage divider, and a refresh circuit of a connection point VD of the capacitive voltage divider C1 and C2, for maintaining the output voltage in the standby mode; An ultra-low power voltage reference source, used to provide a reference voltage VREF for the hysteresis comparator COM and a bias voltage VBIAS for the current-starved oscillator; The NMOS device M2, as a switch tube, is controlled by the signal ACT_ENB to trigger the standby mode; The subtraction counter counts to control the charging time of the charge pump in each standby mode, and continues to work before the subtraction counter counts to 0 to avoid overshoot of the output voltage; The inverter module includes inverters INV1 to INV3, INV1 and INV2 are used to rectify the output signal of the hysteresis comparator COM, and INV3 is used to invert the output signal of the subtractor to generate an ENPD signal; The NOR gate is used to generate a standby mode enable signal STB_EN to control a current starved oscillator and a DICKSON charge pump under the control of the signal ENPD and the signal ACT_EN; The refresh circuit of the connection point VD of the capacitors C1 and C2 includes, in sequence, an NMOS device M3 controlled by an enable signal ACT_EN, a PMOS device M4 controlled by an enable signal ACT_ENB, and resistors R3 and R4, which are used to provide an initial voltage for the connection point VD and refresh the connection point VD when switching between the two modes.

2. A fast and low power word line driving circuit for NOR Flash as claimed in claim 1, characterized in that: The cross-coupled charge pump in the described working mode is provided with a pre-charge tube to optimize the rise time and a substrate modulation tube to suppress the reverse leakage current.

3. A fast and low power word line driving circuit for NOR Flash as claimed in claim 1, characterized in that: The ultra-low power consumption voltage reference source adopts a resistor-free full MOS tube structure, uses NMOS devices in the deep triode region to replace resistors, and the remaining MOS devices are in the subthreshold region, thereby achieving nw-level power consumption.

4. A fast and low power word line driving circuit for NOR Flash as claimed in claim 1, characterized in that: The current starved oscillator in the standby mode circuit and the MOS devices in the hysteresis comparator all work in the subthreshold region, with low static power consumption and a static current at the nA level.

5. A fast and low power word line driving circuit for NOR Flash as claimed in claim 1, characterized in that: The NMOS device M5 is connected in a diode manner and uses a low threshold voltage NMOS device to reduce the threshold voltage loss of the output voltage.

6. A fast and low power word line driving circuit for NOR Flash as claimed in claim 1, characterized in that: The PMOS device, NMOS device, MOS device and switch MOS tube are all metal oxide semiconductor MOS transistors.

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