Memory device and method of operation thereof

Abstract

Embodiments of the present disclosure relate to a memory device and an operating method thereof. A memory device includes a common source line, a memory cell array, a bit line, and a conductive layer. The common source line is formed on a substrate. The memory cell array is formed on the common source line. The bit line is connected to the memory cell array. The conductive layer is formed over the bit line. In an erase operation, the memory device increases a voltage of the bit line to an erase voltage by capacitive coupling by increasing a voltage applied to the conductive layer.

Description

[0001] Cross-references to related applications

[0002] This application claims priority to Korean Patent Application No. 10-2020-0166027, filed on December 1, 2020, which is incorporated herein by reference in its entirety. Technical Field

[0003] This disclosure generally relates to memory devices, and more specifically, to three-dimensional memory devices and methods of operating thereof. Background Technology

[0004] Memory devices comprise memory cells capable of storing data. To improve the integration density of memory cells, three-dimensional memory devices have been proposed.

[0005] A three-dimensional memory device may include multiple memory cells connected in series via a channel structure extending in a vertical direction. Data stored in the memory cells of a three-dimensional memory device can be erased by a GIDL erase operation that generates holes using gate-induced drain leakage (GIDL) current. Summary of the Invention

[0006] Embodiments of this disclosure provide a memory device with improved erasure performance and a method of operating the same.

[0007] According to one aspect of this disclosure, a memory device is provided, comprising: a common source line formed on a substrate; a memory cell array formed on the common source line; a bit line connected to the memory cell array; and a conductive layer formed on the bit line, wherein the memory device is configured to increase the voltage of the bit line to an erase voltage by increasing the voltage applied to the conductive layer during an erase operation, through capacitive coupling between the conductive layer and the bit line.

[0008] The memory cell array may include: a gate stack structure comprising alternately stacked interlayer insulating layers and conductive patterns; and a channel structure connected to a common source line while penetrating the gate stack structure. Each channel structure in the channel structure may be connected to a bit line corresponding to that channel structure.

[0009] The common source line may include a contact region that does not overlap with the gate stack structure.

[0010] The memory device may also include a conductive power electrode contact structure that extends from the contact area of ​​the common source line toward the conductive layer.

[0011] The memory device may further include: peripheral circuitry, including a source line driver configured to provide an erase voltage to a common source line or to discharge the common source line; and an internal voltage generator configured to provide an internal voltage to the peripheral circuitry.

[0012] The conductive layer can connect the common source line to the source line driver.

[0013] The conductive layer allows the internal voltage generator to be connected to the external circuitry.

[0014] During the erase operation, the memory device can also be configured to apply an initialization voltage to the bit line and float the bit line before increasing the voltage of the bit line. Furthermore, the memory device can increase the voltage of the bit line from the initialization voltage to the erase voltage by increasing the voltage of the conductive layer.

[0015] The memory device can increase the voltage of the bit lines by: applying a first voltage to the first bit line of the bit lines, the first bit line being connected to a memory string where the erase verification operation has passed; applying a second voltage higher than the first voltage to the second bit line of the bit lines, the second bit line being connected to a memory string where the erase verification operation has failed; floating the first and second bit lines; and increasing the voltage of the first bit line from the first voltage to a first erase voltage and the voltage of the second bit line from the second voltage to a second erase voltage higher than the first erase voltage by increasing the voltage of the conductive layer.

[0016] The memory device can increase the voltage of the bit line by: applying a first voltage to the first bit line of the bit line, which is connected to the memory string where the erase verification operation has passed; applying a second voltage higher than the first voltage to the second bit line of the bit line, which is connected to the memory string where the erase verification operation has failed; floating the second bit line; and increasing the voltage of the second bit line from the second voltage to the erase voltage by increasing the voltage of the conductive layer.

[0017] According to another aspect of this disclosure, a method for operating a memory device is provided, the memory device including a plurality of bit lines and a conductive layer formed on the plurality of bit lines, the method comprising: applying an initialization voltage to the bit lines; floating the bit lines; and increasing the voltage of the bit lines from the initialization voltage to an erase voltage by capacitive coupling between the conductive layer and the bit lines.

[0018] The initial voltage can be the ground voltage.

[0019] The initial voltage can be a voltage higher than 0V.

[0020] When the voltage of the bit line is increased to the erase voltage, a gate-induced drain leakage (GIDL) current is generated between the junction region of the select transistor connected to the bit line and the drain select line.

[0021] Applying an initialization voltage to a bit line may include: applying a first voltage to a first bit line of the bit line, the first bit line being connected to a memory string for which an erase verification operation has been passed; and applying a second voltage higher than the first voltage to a second bit line of the bit line, the second bit line being connected to a memory string for which an erase verification operation has failed.

[0022] Floating bit lines can include floating the first bit line and the second bit line.

[0023] Increasing the voltage of a bit line from the initialization voltage to the erase voltage via capacitive coupling can include: increasing the voltage of the first bit line from a first voltage to a first erase voltage by increasing the voltage of the conductive layer, and increasing the voltage of the second bit line from a second voltage to a second erase voltage higher than the first erase voltage.

[0024] Floating a bit line can include floating a second bit line.

[0025] Increasing the voltage of a bit line from the initial voltage to the erase voltage via capacitive coupling can include increasing the voltage of the second bit line from the second voltage to the erase voltage by increasing the voltage of the conductive layer.

[0026] According to another aspect of this disclosure, a memory device is provided, comprising: a common source line formed on a substrate; a memory cell array formed on the common source line, the memory cell array including a first memory cell string and a second memory cell string; a first bit line and a second bit line electrically coupled to the first memory cell string and the second memory cell string, respectively; a conductive layer disposed on the bit line; and logic circuitry electrically coupled to the conductive layer and the bit line. The logic circuitry is configured to: apply a first initialization voltage and a second initialization voltage to the first bit line and the second bit line, respectively, to float the second bit line; and to increase the voltage of the conductive layer to raise the voltage of the second bit line to a second erase voltage through capacitive coupling between the conductive layer and the second bit line.

[0027] The first memory string can be a memory string from a previous erase verification operation that passed. The second memory string can be a memory string from a previous erase verification operation that failed.

[0028] The first initialization voltage can be lower than the second initialization voltage.

[0029] The logic circuit can also be configured to raise the voltage of the first bit line to a first erase voltage. The first erase voltage can be lower than a second erase voltage.

[0030] The logic circuit can also be configured to float the first bit line. The logic circuit can raise the voltage of the first bit line to a first erase voltage through capacitive coupling between the conductive layer and the first bit line.

[0031] The memory cell array may include gate stack structures and channel structures. The gate stack structures may be spaced apart from each other. Each gate stack structure may include alternating stacked interlayer insulating layers and conductive patterns. A channel structure may be electrically coupled to a common source line when penetrating the gate stack structure. Each channel structure in the channel structure may be electrically coupled to a corresponding bit line in the bit line.

[0032] The common source line may include the contact area between the gate stack structures.

[0033] The memory device may also include a conductive electrode contact structure extending from the contact area toward the conductive layer. Attached Figure Description

[0034] Various embodiments of the present disclosure will now be described more fully with reference to the accompanying drawings; however, embodiments may be embodied in different forms and should not be construed as limited to the embodiments set forth herein. Rather, these embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the scope of the embodiments to those skilled in the art.

[0035] In the accompanying drawings, dimensions may be exaggerated for clarity. It should be understood that when an element is referred to as "between" two elements, it can be the only element between the two elements, or there may be one or more intermediate elements. Throughout the text, the same reference numerals refer to the same elements.

[0036] Figure 1 and Figure 2 This is a block diagram illustrating a memory device according to an embodiment of the present disclosure.

[0037] Figure 3 This is an equivalent circuit diagram illustrating a memory block according to an embodiment of the present disclosure.

[0038] Figure 4 This is a diagram illustrating a conductive layer located above the bit lines of a memory cell array according to an embodiment of the present disclosure.

[0039] Figure 5 and Figure 6 This is a cross-sectional view illustrating a memory device according to an embodiment of the present disclosure.

[0040] Figure 7 This is a diagram illustrating an erase operation of a memory device according to an embodiment of the present disclosure.

[0041] Figure 8This is a flowchart illustrating an operation method of a memory device according to an embodiment of the present disclosure.

[0042] Figure 9A and Figure 9B This is a timing diagram illustrating an operation method of a memory device according to an embodiment of the present disclosure.

[0043] Figure 10 This is a flowchart illustrating an operation method of a memory device according to an embodiment of the present disclosure.

[0044] Figure 11 This is a flowchart illustrating an embodiment of the present disclosure of the operation for distinguishing between fast bit lines and slow bit lines.

[0045] Figure 12 This is a timing diagram illustrating an operation method of a memory device according to an embodiment of the present disclosure.

[0046] Figure 13 This is a block diagram illustrating the configuration of a memory system according to an embodiment of the present disclosure.

[0047] Figure 14 This is a block diagram illustrating the configuration of a computing system according to an embodiment of the present disclosure. Detailed Implementation

[0048] The specific structural or functional descriptions disclosed herein are merely for the purpose of describing embodiments based on the concepts of this disclosure. Embodiments based on the concepts of this disclosure may be implemented in various forms and should not be construed as limited to the embodiments set forth herein.

[0049] Figure 1 This is a block diagram schematically illustrating a memory device 10 according to an embodiment of the present disclosure.

[0050] refer to Figure 1 The memory device 10 may include logic circuitry LC and memory cell array 40. The logic circuitry LC may include an internal voltage generator 20 and peripheral circuitry 30.

[0051] The internal voltage generator 20 can be configured to generate various internal voltages by receiving external voltages. In an embodiment, the internal voltages may include internal ground voltage and internal power supply voltage.

[0052] The peripheral circuit 30 can be configured to perform programming operations for storing data in the memory cell array 40; reading operations for outputting data stored in the memory cell array 40; and erasing operations for erasing data stored in the memory cell array 40. The internal voltage required to activate the peripheral circuit 30 can be generated from the internal voltage generator 20 and supplied to the external circuit 30.

[0053] Figure 2 This illustrates an embodiment according to the present disclosure. Figure 1 The block diagram of the peripheral circuit 30 shown.

[0054] refer to Figure 2 The peripheral circuit 30 may include: control logic 39, operating voltage generator 31, row decoder 33, source line driver 37, and page buffer group 35.

[0055] The memory cell array 40 may include multiple memory blocks. Each memory block may be connected to one or more drain select lines DSL, multiple word lines WL, one or more source select lines SSL, multiple bit lines BL, and at least one common source line.

[0056] Control logic 39 can control peripheral circuit 30 in response to commands CMD and addresses ADD.

[0057] Operating voltage generator 31 can generate various operating voltages VOP for programming, reading, and erasing operations under the control of control logic 39. Operating voltages VOP may include programming voltage, verification voltage, pass voltage, selection line voltage, etc.

[0058] The row decoder 33 can select a memory block under the control of the control logic 39. The row decoder 33 can apply the operating voltage VOP to the drain select line DSL, word line WL, and source select line SSL connected to the selected memory block.

[0059] The source line driver 37 can be connected to the memory cell array 40 via the common source line CSL. The source line driver 37 can perform a discharge operation on the common source line under the control of the control logic 39. Under the control of the control logic 39, the source line driver 37 can apply a pre-erase voltage and an erase voltage to the common source line CSL during an erase operation.

[0060] Page buffer group 35 can be connected to memory cell array 40 via bit line BL. Under the control of control logic 39, page buffer group 35 can temporarily store data to be programmed received from input / output circuitry (not shown) during programming operations. Page buffer group 35 can sense the voltage or current of bit line BL during read or verification operations under the control of control logic 39. Page buffer group 35 can selectively float bit line BL under the control of control logic 39.

[0061] The internal voltage output from the internal voltage generator 20 can be supplied to the peripheral circuitry 30. In this embodiment, an internal ground voltage VSSI can be output from the internal voltage generator 20. The internal ground voltage VSSI can be supplied to the peripheral circuitry 30 via a line overlapping with the memory cell array 40.

[0062] Figure 3 This is an equivalent circuit diagram illustrating a memory block according to an embodiment of the present disclosure.

[0063] refer to Figure 3 A memory block may include multiple memory cell strings STRs that are commonly connected to a common source line CSL. The memory cell strings STRs may be connected to multiple bit lines BL1 to BLm. The memory cell strings STRs may be divided into multiple column groups, each connected to bit lines BL1 to BLm. The memory cell strings STRs of each column group may be connected in parallel to their corresponding bit line.

[0064] Each memory cell string STR may include one or more drain-select transistors disposed between its corresponding bit line and common source line CSL, multiple memory cells, and one or more source-select transistors. The gate of each drain-select transistor may be connected to its corresponding drain-select line, the gate of each memory cell may be connected to its corresponding word line, and the gate of each source-select transistor may be connected to its corresponding source-select line.

[0065] In an embodiment, each memory cell string in the memory cell string STR may be connected to a drain select line DSL, multiple word lines WL1 to WLn, and a source select line SSL. Each memory cell string in the memory cell string STR may include a drain select transistor DST connected to the drain select line DSL, multiple memory cells MC connected to the word lines WL1 to WLn, and a source select transistor SST connected to the source select line SSL.

[0066] Multiple memory cells MC can be connected in series. A drain-select transistor DST can be disposed between the multiple memory cells MC and their corresponding bit lines. The drain-select transistor DST may include a junction region connected to its corresponding bit line. A source-select transistor SST can be disposed between the multiple memory cells MC and the common source line CSL. The source-select transistor SST may include a junction region connected to the common source line CSL.

[0067] The structure of each memory cell string in the memory cell string STR is not limited to Figure 3The illustrated embodiment. In this embodiment, each memory cell string STR may include two or more drain-select transistors, which are disposed and connected in series between a plurality of memory cells MC connected in series and their corresponding bit lines. Two or more drain-select lines may be disposed between bit lines BL1 to BLm and word lines WL1 to WLn. In this embodiment, each memory cell string STR may include two or more source-select transistors, which are disposed and connected in series between a plurality of memory cells MC connected in series and a common source line CSL. Two or more source-select lines may be disposed between the common source line CSL and word lines WL1 to WLn.

[0068] In an embodiment, at least one of the word lines WL1 to WLn can be used as a dummy word line. For example, at least one of the word lines WL1 adjacent to the source select line SSL and WLn adjacent to the drain select line DSL can be used as a dummy word line.

[0069] The erase operation of a memory device may include a thermal hole formation period and an erase period.

[0070] refer to Figure 2 and Figure 3 During the hot hole formation period of the erase operation, the row decoder 33 can control the word lines WL1 to WLn of the selected memory block to be in a floating state and control the bit lines BL1 to BLm of the selected memory block to be in a floating state.

[0071] During the hot hole formation phase of the erase operation, the operating voltage generator 31 can apply a pre-erasure voltage to the common source line CSL to generate the gate-induced drain leakage (GIDL) current. When the voltage level of the source select line SSL is low, a GIDL current is generated between the junction region of the source select transistor SST and the source select line SSL. In an embodiment, during the hot hole formation phase of the erase operation, the line decoder 33 can control the source select line SSL to have a ground voltage level.

[0072] When a GIDL current is generated, hot holes can be created. These hot holes can be injected into the channel region of the memory cell string STR, and GIDL current can be generated in the channel region.

[0073] Subsequently, during the erase phase of the erase operation, the operating voltage generator 31 can apply an erase voltage higher than the pre-erase voltage to the common source line CSL. As a result, the channel voltage of the memory cell string STR increases further.

[0074] During the erase phase of the erase operation, the line decoder 33 can control the source select line SSL to be in a floating state and control the word lines WL1 to WLn to have a ground voltage level. Therefore, the data stored in the memory cell MC can be erased by the voltage difference between the channel region of the memory cell string STR and the word lines WL1 to WLn, where the channel region of the memory cell string STR has an increased potential level and the word lines WL1 to WLn have a ground voltage level.

[0075] The erase operation can be terminated when the source select line SL is turned off with a ground voltage level by controlling the source select line SSL via the line decoder 33.

[0076] In this embodiment, to improve the efficiency of the GIDL erase operation, during the erase operation, the voltage applied to the common source line CSL can be applied to bit lines BL1 to BLm, and the voltage applied to the source select line SSL can be applied to the drain select line DSL. Therefore, during the erase operation, a GIDL current is generated between the junction region of the drain select transistor DST and the drain select line DSL, thereby improving the efficiency of the erase operation.

[0077] In one embodiment, a high voltage can be applied to the conductive layer located above bit lines BL1 to BLm, such that the voltage of bit lines BL1 to BLm is increased to the erase voltage through capacitive coupling. Although the transistors for directly applying the high voltage to bit lines BL1 to BLm are not separately provided... Figure 2 The page buffer group 35 shown can improve the efficiency of erase operations. Therefore, when a high voltage for erasing is applied to the bit lines BL1 to BLm using capacitive coupling, it has advantages due to the high integration of the memory device.

[0078] Figure 4 This is a diagram illustrating a conductive layer located above the bit lines of a memory cell array according to an embodiment of the present disclosure.

[0079] refer to Figure 4 The memory cell array 40 can be disposed between the common source line CSL and the bit lines BL1 to BLm. The memory cell array 40 may include a gate stack structure GST and channel structures CH that penetrate the gate stack structure GST. The bit lines BL1 to BLm can extend in a first direction D1. Although not explicitly stated... Figure 4 As shown, multiple word lines can extend in the second direction D2. Furthermore, the channel structure CH can extend in the third direction D3.

[0080] Gate stack structures (GSTs) can be spaced apart from each other. Figure 4 This illustrates two spaced-apart gate stack structures (GSTs) with conductive power electrode contact structures (SCTs) inserted between them. Besides... Figure 4 In addition to the structure shown, the memory cell array 40 may include three or more gate stack structures (GSTs) spaced apart from each other.

[0081] Each channel structure in the channel structure CH may include one end connected to the common source line CSL and the other end connected to a corresponding bit line among the bit lines BL1 to BLm. Each channel structure in the channel structure CH and the common source line CSL can be directly connected to each other. Alternatively, a lower channel structure or contact structure for connecting each channel structure in the channel structure CH to the common source line CSL can be formed between each channel structure in the channel structure CH and the common source line CSL. Each channel structure in the channel structure CH and its corresponding bit line can be directly connected to each other. Alternatively, a contact structure for connecting each channel structure in the channel structure CH and its corresponding bit line can be formed between each channel structure in the channel structure CH and its corresponding bit line.

[0082] The channel structure CH can be arranged in a sawtooth or matrix form in its corresponding gate stack structure.

[0083] A common source line (CSL) can be formed on a substrate including logic circuitry (LC). The common source line (CSL) may include a contact region (CTA) that does not overlap with the gate stack structure (GST). In an embodiment, the contact region (CTA) of the common source line (CSL) may be disposed between adjacent gate stack structures (GST). A source contact structure (SCT) extends from the contact region (CTA) of the common source line (CSL) toward the upper conductive layer (L1).

[0084] In an embodiment, such as Figure 4 As shown, the upper conductive layer L1 can be used to connect the common source line CSL to... Figure 2 The source line driver 37 is shown. Therefore, the potential level of the common source line CSL can be transmitted through the upper conductive layer L1. Figure 2 The source line driver 37 shown is discharged. Furthermore, during the erase operation, via... Figure 2 The erase voltage provided by the source line driver 37 shown can be sent to the common source line CSL via the upper conductive layer L1. However, embodiments of this disclosure are not limited thereto. The upper conductive layer L1 according to embodiments of this disclosure may not be connected to the common source line CSL. In addition to connecting the common source line CSL to... Figure 2 In addition to the source line driver 37 shown, the upper conductive layer L1 can also be used as another object. For example, the upper conductive layer L1 can be used as a means to... Figure 2 The lines shown connect the internal voltage generator 20 to the peripheral circuit 30.

[0085] Figure 4 A conductive upper layer L1 formed between bit lines BL1 and BLm is shown. However, this disclosure is not limited to this, and multiple conductive upper layers disposed on a first direction D1 or a second direction D2 can be formed. Furthermore, multiple conductive upper layers disposed on a third direction D3 can be formed.

[0086] The upper conductive layer L1 may include a low-resistance metal. The upper conductive layer L1 may include a metal (such as copper or aluminum).

[0087] Figure 5 and Figure 6 A cross-sectional view of a memory device according to an embodiment of the present disclosure is shown.

[0088] refer to Figure 5 A common source line (CSL) can be formed on substrate 51. Substrate 51 may include the components referenced above. Figure 1 The logic circuit described is LC.

[0089] For example, substrate 51 can be a bulk silicon substrate, a silicon-on-insulator substrate, a germanium substrate, a germanium-on-insulator substrate, a silicon-germanium substrate, or an epitaxial thin film formed by a selective epitaxial growth process.

[0090] The common source line (CSL) may overlap with the transistor TR of the logic circuit LC. Each transistor in the transistor TR may be formed in an active region of the substrate 51 defined by the isolation layer 53. Each transistor in the transistor TR may include a gate insulating layer 57 and a gate electrode 59 stacked on its corresponding active region, and includes junction regions 55a and 55b formed in the active region on both sides of the gate electrode 59. One of the junction regions 55a and 55b may be used as a source region, and the other junction region 55a and 55b may be used as a drain region.

[0091] The logic circuit LC may include interconnect structures 60 connected to transistors TR constituting the logic circuit LC. Each interconnect structure in interconnect structure 60 may include multiple conductive patterns 61, 63, 65, and 67. The configuration of interconnect structure 60 is not limited to the configuration shown in the figure and can be modified in various ways. The multiple conductive patterns 61, 63, 65, and 67 included in each interconnect structure in interconnect structure 60 may include at least one wire, conductive pad, and contact plug.

[0092] The substrate 51, including the logic circuit LC, can be covered by an insulating structure 69. The insulating structure 69 may include two or more insulating layers. A common source line CSL may be disposed on the insulating structure 69.

[0093] The memory cell array 40 can be disposed on a common source line CSL. The gate stack structure GST of the memory cell array 40 may include an interlayer insulating layer 71 and a conductive pattern 73 alternately stacked on the common source line CSL. The conductive pattern 73 can be used as a reference above. Figure 3 The source select line SSL, word lines WL1 to WLn, and drain select line DSL are described. In an embodiment, at least one lower conductive pattern in conductive pattern 73 disposed adjacent to the common source line CSL can be used as a reference above. Figure 3 The source selection line SSL is described. In an embodiment, at least one upper conductive pattern in conductive pattern 73 disposed adjacent to bit line BL can be used as a reference above. Figure 3 The drain selection line DSL is described. The intermediate conductive pattern between the lower and upper conductive patterns in conductive pattern 73 can be used as a reference above. Figure 3 The word lines described are WL1 to WLn.

[0094] The channel structure CH of the memory cell array 40 can penetrate its corresponding gate stack structure GST. The memory cell array 40 can be connected to the common source line CSL through the channel structure CH. A memory layer 81 can be disposed between each channel structure in the channel structure CH and the gate stack structure GST. The memory layer 81 can extend along the sidewall of each channel structure in the channel structure CH.

[0095] refer to Figure 4 and Figure 5 An embodiment of a structure with logic circuitry LC located below the gate stack structure GST and the common source line CSL is shown. This structure is a Peri-Under Cell (PUC) structure with the logic circuitry LC located below the memory cell. However, this disclosure is not limited thereto, and a structure with the logic circuitry located above the gate stack structure GST (i.e., a Peri-Over Cell (POC) structure with the logic circuitry above the memory cell) is possible. In another embodiment, the logic circuitry LC may be formed at a different location than above or below the gate stack structure GST. That is, the logic circuitry LC may be formed at a location spaced apart from the gate stack structure GST in direction D1 or D2. Additionally, the logic circuitry LC may be formed on a separate substrate different from the substrate on which the gate stack structure GST and the common source line CSL are located.

[0096] Figure 6 This is an enlarged cross-sectional view showing a channel structure CH according to an embodiment of the present disclosure and a memory layer 81 surrounding the channel structure.

[0097] refer to Figure 6The memory layer 81 may surround the sidewalls of its corresponding channel structure CH. The memory layer 81 may include a tunnel insulating layer TI, a data storage layer DS, and a barrier insulating layer BI stacked on the sidewalls of its corresponding channel structure CH. The tunnel insulating layer TI may include silicon oxide through which charge can tunnel. The data storage layer DS may be formed as a charge trapping layer. For example, the charge trapping layer may include silicon nitride. The barrier insulating layer BI may include an oxide capable of blocking charge. In addition to the charge trapping layer, the data storage layer DS may be formed of various materials and modified in various ways between the tunnel insulating layer TI and the barrier insulating layer BI depending on the structure of the cell to be implemented. For example, the data storage layer DS may be formed as a material layer including conductive nanodots, as a phase change material layer, or as a material layer for a floating gate.

[0098] Let's refer to each other. Figure 5 and Figure 6 The channel structure CH may include a channel layer 83. In an embodiment, the channel layer 83 may be formed as a hollow structure. The channel structure CH may also include a core insulating layer 85 and a doped semiconductor layer 87 filling the central region COA of the channel structure CH defined by the channel layer 83. The doped semiconductor layer 87 may be disposed between the core insulating layer 85 and a corresponding bit line BL in the bit line BL.

[0099] The trench structure CH is not limited to the example shown in the figure. For example, the trench structure CH may include a buried trench layer buried in the central region COA of the trench structure CH, and the core insulation layer 85 may be omitted.

[0100] The channel layer 83 can be used as the channel region for the corresponding memory cell string. The channel layer 83 can be formed of a semiconductor material. In an embodiment, the channel layer 83 may include a silicon layer.

[0101] refer to Figure 5 One end of the channel structure CH facing the common source line CSL can be connected to the common source line CSL. In an embodiment, a portion of the channel layer 83 constituting one end of the channel structure CH can be directly connected to the common source line CSL.

[0102] The other end of the channel structure CH facing its corresponding bit line BL can be connected to the corresponding bit line BL via a contact plug 93 formed of conductive material. In an embodiment, the doped semiconductor layer 87 constituting the other end of the channel structure CH can be directly connected to the contact plug 93.

[0103] A conductive dopant may be distributed in a portion of the channel layer 83, which forms the other end of the channel structure CH, and the doped semiconductor layer 87. The conductive dopant may include an n-type dopant for the junction. The conductive dopant may include an anti-doped p-type dopant.

[0104] Based on the above structure, the reference above can be defined at the intersection of the conductive pattern 73 and the channel structure CH, which serves as the intermediate conductive pattern for word lines. Figure 3 The memory cell MC described above can be defined at the intersection of the lower conductive pattern, which serves as the source select line in the conductive pattern 73 and the channel structure CH. Figure 3 The described source-select transistor SST. The above reference can be defined at the intersection of the upper conductive pattern 73 and the channel structure CH, which serves as the drain-select line. Figure 3 Described as a drain-select transistor (DST). Reference Figure 3 The source selection transistor (SST), memory cell (MC), and drain selection transistor (DST) described above can be found in the reference above. Figure 5 The described channel structures CH are connected in series to form the above reference. Figure 3 The memory cell string STR is described.

[0105] The gate stack structure GST of the memory cell array 40 can be covered by the first upper insulating layer 89. The channel structure CH can extend to penetrate the first upper insulating layer 89.

[0106] Bit lines BL can be connected to the memory cell array 40 via a channel structure CH. Each bit line in the bit line BL can be connected to its corresponding channel structure CH via a corresponding contact plug 93. The contact plug 93 can be disposed in a second upper insulating layer 91, which is disposed on a first upper insulating layer 89. The bit line BL can be disposed in a third upper insulating layer 95, which is disposed on a second upper insulating layer 91. The bit lines BL and contact plugs 93 can be formed from various conductive materials.

[0107] Figure 5 The bit line BL shown can be included Figure 4 The bit lines BL1 to BLm are shown. The third upper insulating layer 95 penetrated by the bit line BL can be covered by the fourth upper insulating layer 99. An etch stop layer 98 can be further formed between the fourth upper insulating layer 99 and the third upper insulating layer 95 penetrated by the bit line BL. Each of the first to fourth upper insulating layers 89, 91, 95 and 99 may include an oxide, and the etch stop layer 98 may include a nitride.

[0108] The fourth upper insulating layer 99 may extend to overlap with the bit line BL. An upper conductive layer L1 may be disposed on the fourth upper insulating layer 99. The upper conductive layer L1 may overlap with the bit line BL and be spaced apart from the bit line BL by the fourth upper insulating layer 99.

[0109] The upper conductive layer L1 can be formed from various conductive materials. In an embodiment, the upper conductive layer L1 may include a metal layer M2 with low resistance. Copper or aluminum can be used as the metal layer M2 with low resistance. The upper conductive layer L1 may also include at least one of a conductive barrier layer M1 disposed between the metal layer M2 and the fourth upper insulating layer 99 and a conductive anti-reflective coating (ARC) layer M3 retained on the fourth upper insulating layer 99. The barrier layer M1 and the ARC layer M3 can be formed from various conductive materials (such as titanium nitride (TiN)).

[0110] The upper conductive layer L1 can be used as a means to... Figure 2 The source line driver 37 shown is connected to the common source line CSL. This is merely illustrative, and the function of the upper conductive layer L1 according to this disclosure is not limited thereto. For example, the upper conductive layer L1 can be used for connection Figure 2 The internal voltage generator 20 shown is connected to the external circuit 30.

[0111] During the erase operation, a high voltage is sent to the upper conductive layer L1, which allows the voltage of the bit line BL located below the upper conductive layer L1 to be increased.

[0112] Figure 7 This is a diagram illustrating an erase operation of a memory device according to an embodiment of the present disclosure.

[0113] refer to Figure 7 The erase operation of a memory device may include multiple erase cycles. Each erase cycle may include an erase pulse application operation and an erase verification operation. That is, the first erase cycle includes a first erase pulse application operation and a first erase verification operation, and the second erase cycle includes a second erase pulse application operation and a second erase verification operation. The erase cycle is repeated until the erase verification passes. If the erase verification fails even after the erase cycle has been repeated a threshold number of times, the erase operation is considered to have failed.

[0114] In the erase pulse operation, the erase voltage is applied in pulse form to the memory string included in the memory block selected as the erase target. As described above, in the erase pulse operation, the erase voltage can be applied to the common source line CSL, the source select line SSL can be controlled to be in a floating state, and the word lines WL1 to WLn can be controlled to be at a ground voltage level. Data stored in the memory cells can be erased by the voltage difference between the channel region of the memory cell string STR and the word lines WL1 to WLn, where the channel region of the memory cell string STR has an increased potential level and the word lines WL1 to WLn have a ground voltage level. During the erase operation, to improve the efficiency of the above-mentioned GIDL erase operation, the voltage applied to the common source line CSL can be applied to the bit lines BL1 to BLm, and the voltage applied to the source select line SSL can be applied to the drain select line DSL. Therefore, during the erase operation, a GIDL current is generated between the junction region of the drain select transistor DST and the drain select line DSL, thereby improving the efficiency of the erase operation.

[0115] In some embodiments, the erase voltage is not applied to the common source line CSL but can be applied to bit lines BL1 to BLm. A GIDL current can be generated between the junction region of the drain select transistor DST and the drain select line DSL to erase the memory cell.

[0116] In the erase verification operation, it is verified whether the memory cells included in the selected memory block have been erased. For this purpose, an erase verification voltage can be applied to the word lines WL1 to WLn connected to the memory block selected as the erase target. When the threshold voltages of the memory cells included in the memory string are all below the erase verification voltage, current can flow through the bit lines connected to the corresponding memory string. When the threshold voltages of some memory cells included in the memory string are above the erase verification voltage, current does not flow through the bit lines connected to the corresponding memory string. In this way, it can be verified whether the memory cells have been completely erased for each string.

[0117] Figure 8 This is a flowchart illustrating an operation method of a memory device according to an embodiment of the present disclosure. More specifically, Figure 8 It is shown in Figure 7 The flowchart illustrates an embodiment of the operation of applying erase pulses in multiple erase cycles.

[0118] refer to Figure 8An operation method of a memory device according to an embodiment of the present disclosure includes: an operation S110 of applying an initialization voltage to a bit line connected to a memory block selected as an erasure target, an operation S130 of floating the bit line connected to the selected memory block, and an operation S150 of increasing the voltage of the bit line connected to the selected memory block to an erasure voltage by increasing the voltage of a conductive layer located above the selected memory block.

[0119] In operation S110, an initialization voltage is applied to multiple bit lines. Therefore, the voltages of the multiple bit lines can be initialized equally to each other. In one embodiment, the initialization voltage can be ground voltage. In another embodiment, the initialization voltage can be a voltage higher than ground voltage.

[0120] In operation S130, the bit line initialized to the initialization voltage is floated. Subsequently, in operation S150, the bit line is increased. Figure 4 and Figure 5 The voltage of the upper conductive layer L1 is shown. Therefore, through the capacitive coupling between the upper conductive layer L1 and the bit line, the voltage of the bit line is increased to the erase voltage.

[0121] Figure 9A and Figure 9B This is a timing diagram illustrating an operation method of a memory device according to an embodiment of the present disclosure.

[0122] refer to Figure 9A The voltage of the upper conductive layer L1 and the voltage of the bit line BL are shown according to time. Figure 9A In the diagram, the voltages of the word line, common source line, source select line, and drain select line are omitted.

[0123] Before time t1, the voltage of the upper conductive layer L1 can be voltage V0. In this embodiment, voltage V0 can be ground voltage. Before time t1, the voltage of the bit line BL can have different values.

[0124] according to Figure 8 The operation S110 shown allows an initialization voltage Vint to be applied to bit line BL at time t1. In this embodiment, the initialization voltage Vint can be ground voltage. Subsequently, at time t2, bit line BL can be floated (S130). Although bit line BL is floated, the initialization voltage Vint of bit line BL is maintained.

[0125] Subsequently, at time t3, the voltage of the upper conductive layer L1 is increased (S150). The voltage of the upper conductive layer L1 can reach a high voltage VML at time t4. Therefore, through the capacitive coupling between the upper conductive layer L1 and the bit line, the voltage of the bit line BL is increased from the initialization voltage Vint to the erase voltage VERa. Therefore, during the period between time t4 and time t5, a GIDL current appears between the junction region of the drain select transistor DST and the drain select line DSL, thus performing an erase operation on the memory cell. Subsequently, at time t5, the voltage of the upper conductive layer L1 is decreased. Therefore, the voltage of the bit line BL is also decreased.

[0126] refer to Figure 9B The voltage of the upper conductive layer L1 and the voltage of the bit line BL are shown according to time.

[0127] Before time t6, the voltage of the upper conductive layer L1 can be voltage V0. In this embodiment, voltage V0 can be ground voltage. Before time t6, the voltage of the bit line BL can have different values.

[0128] according to Figure 8 As shown in operation S110, the initialization voltage Vint can be applied to bit line BL at time t6. Figure 9B The initial voltage Vint shown can be a voltage higher than the ground voltage. Figure 9B The initialization voltage Vint shown can be a voltage that is higher than the voltage of bit line BL before time t6.

[0129] Subsequently, at time t7, bit line BL can be floated (S130). Although bit line BL is floated, the initial voltage Vint of bit line BL is maintained.

[0130] Subsequently, at time t8, the voltage of the upper conductive layer L1 is increased (S150). The voltage of the upper conductive layer L1 can reach a high voltage VML at time t9. Therefore, through the capacitive coupling between the upper conductive layer L1 and the bit line, the voltage of the bit line BL is increased from the initialization voltage Vint to the erase voltage VERb. Therefore, during the period between time t8 and time t10, a GIDL current appears between the junction region of the drain select transistor DST and the drain select line DSL, thus performing an erase operation on the memory cell. Subsequently, at time t10, the voltage of the upper conductive layer L1 is decreased. Therefore, the voltage of the bit line BL is also decreased.

[0131] exist Figure 9A In the illustrated embodiment, the initialization voltage Vint can have a relatively low voltage value. For example, Figure 9AThe initialization voltage Vint shown can be ground voltage. The initialization voltage Vint is used to initialize different voltages on the bit line BL equally.

[0132] On the other hand, Figure 9B In the illustrated embodiment, the initialization voltage Vint can have a relatively high value. Therefore, Figure 9B The erase voltage VERb shown can have the following value, which is relatively greater than Figure 9A The erase voltage VERa is shown as a value. The initialization voltage Vint can be used as a precharge voltage to further increase the erase voltage VERb when different voltages are initialized to the bit line BL equally.

[0133] Figure 10 This is a flowchart illustrating a method of operating a memory device according to another embodiment of the present disclosure. More specifically, Figure 10 It is shown in Figure 7 A flowchart of another embodiment of the operation of applying erase pulses in multiple erase cycles is shown.

[0134] refer to Figure 10 An operation method of a memory device according to an embodiment of the present disclosure includes: an operation S210 of applying a first voltage to a fast bit line connected to a bit line of a memory block selected as an erasure target; an operation S220 of applying a second voltage to a slow bit line connected to a bit line of the memory block selected as an erasure target; an operation S230 of floating the bit line connected to the selected memory block; and an operation S250 of increasing the voltage of the bit line connected to the selected memory block to an erasure voltage by increasing the voltage of a conductive layer located above the selected memory block.

[0135] In operation S210, a first voltage is applied to the fast bit lines among the plurality of bit lines. The fast bit lines may be bit lines connected to memory strings whose erase verification was determined to have passed in the erase verification step of a previous erase cycle. In operation S220, a second voltage higher than the first voltage is applied to the slow bit lines, which are the other bit lines among the plurality of bit lines besides the fast bit lines. The slow bit lines may be bit lines connected to memory strings whose erase verification was determined to have failed in the erase verification operation of a previous erase cycle.

[0136] exist Figure 10In this paper, operation S220 is shown to be performed after operation S210, but this disclosure is not limited thereto. Operation S210 can be performed after operation S220, and operations S210 and S220 can be performed simultaneously. When operations S210 and S220 are performed, the fast bit line and the slow bit line are initialized to different voltage values. As mentioned above, the value of the second voltage can be greater than the value of the first voltage. That is, the fast bit line is initialized to a relatively low voltage, and the slow bit line is initialized to a relatively high voltage.

[0137] In operation S230, the bit lines connected to the selected memory block are floated. In one embodiment, both the fast bit lines and the slow bit lines can be floated. In another embodiment, the fast bit lines are not floated, but only the slow bit lines can be floated.

[0138] Subsequently, during the operation of S250, Figure 4 and Figure 5 The voltage of the upper conductive layer L1 shown can be increased. Therefore, the voltage of the bit line is increased to the erase voltage through capacitive coupling between the upper conductive layer L1 and the bit line. When both the fast and slow bit lines are floating in operation S230, both the voltages of the fast and slow bit lines are increased through capacitive coupling in operation S250. When only the slow bit line is floating in operation S230, the voltage of the slow bit line is increased through capacitive coupling in operation S250.

[0139] Figure 11 This is a flowchart illustrating the operation of distinguishing between fast and slow bit lines according to embodiments of the present disclosure. More specifically, Figure 11 This is a flowchart illustrating an embodiment of the operation of performing an erase verification operation in multiple erase cycles.

[0140] refer to Figure 11 To distinguish between fast and slow bit lines, an erase verification voltage is first applied to the word line connected to the selected memory block (S310). Therefore, each page buffer group in the page buffer set can determine the erase verification result of the corresponding memory string and store the result in a latch. As described above, when the threshold voltages of all memory cells included in the memory string are below the erase verification voltage, current can flow through the bit line connected to the corresponding memory string. When the threshold voltages of some memory cells included in the memory string are above the erase verification voltage, no current flows through the bit line connected to the corresponding memory string. In this way, it can be verified whether the memory cells have been completely erased for each memory string.

[0141] In operation S330, based on the verification result of operation S310, the bit lines connected to the verified string are determined as fast bit lines. Memory cells included in the memory string connected to the fast bit lines are memory cells that have passed erasure, and may be memory cells that do not require additional erasure. In operation S330, the bit lines connected to the verified failed string are determined as slow bit lines. Memory cells included in the memory string connected to the slow bit lines are memory cells that failed erasure, and may be memory cells that require additional erasure.

[0142] Figure 12 This is a timing diagram illustrating an operation method of a memory device according to another embodiment of the present disclosure.

[0143] refer to Figure 12 The voltage of the upper conductive layer L1, the voltage of the fast bit line BLa in the bit line, and the voltage of the slow bit line BLb in the bit line are shown according to time. Figure 12 The voltage diagrams for the word line, common source line, source select line, and drain select line are omitted.

[0144] Before time t11, the voltage of the upper conductive layer L1 can be voltage V0. In this embodiment, voltage V0 can be ground voltage. Before time t11, the voltages of the fast bit line BLa and the slow bit line BLb can have different values.

[0145] according to Figure 10 As shown in operation S210, the first voltage Vinta can be applied to the fast bit line BLa at time t11. According to... Figure 10 In the operation S220 shown, a second voltage Vintb can be applied to the slow bit line BLb at time t11. As mentioned above, the second voltage Vintb is higher than the first voltage Vinta.

[0146] Subsequently, at time t12, the fast bit line BLa and the slow bit line BLb are floated (S230). However, this disclosure is not limited to the above. At time t12, the fast bit line BLa is not floated, but only the slow bit line BLb can be floated.

[0147] Subsequently, at time t13, the voltage of the upper conductive layer L1 is increased (S250). The voltage of the upper conductive layer L1 can reach a high voltage VML at time t14. Therefore, the voltages of the fast bit line BLa and the slow bit line BLb can be increased through the capacitive coupling between the upper conductive layer L1 and the bit lines. More specifically, the voltage of the fast bit line BLa can be increased from the first voltage Vinta to the erase voltage VERa. The voltage of the slow bit line BLb can be increased from the second voltage Vintb to the erase voltage VERb. Therefore, during the period between time t14 and time t15, a GIDL current is generated between the junction region of the drain select transistor DST and the drain select line DSL, thus performing the erase operation of the memory cell.

[0148] When the voltage increments caused by capacitive coupling are similar, the second voltage Vintb is higher than the first voltage Vinta, therefore the erase voltage VERb can be higher than the erase voltage VERa. Consequently, the threshold voltage offset width of the memory cells in the memory string connected to the fast bit line BLa is smaller than the threshold voltage offset width of the memory cells in the memory string connected to the slow bit line BLb. Therefore, the threshold voltage distribution width of the memory cells according to the erase operation can be narrowed. Thus, the threshold voltage distribution of the memory cells after the erase operation can be further improved.

[0149] Subsequently, at time t15, the voltage of the upper conductive layer L1 is increased. Therefore, the voltage of the fast bit line BLa and the voltage of the slow bit line BLb are also decreased.

[0150] Figure 13 This is a block diagram illustrating the configuration of a memory system according to an embodiment of the present disclosure. Reference Figure 13 The memory system 1100 includes a memory device 1120 and a memory controller 1110.

[0151] The memory device 1120 may be a multi-chip package configured with multiple flash memory chips. In an embodiment, the memory device 1120 may include a memory cell array, bit lines connected to the memory cell array, and a conductive layer located above the bit lines.

[0152] Memory controller 1110 controls memory device 1120 and may include static random access memory (SRAM) 1111, central processing unit (CPU) 1112, host interface 1113, error correction block 1114, and memory interface 1115. SRAM 1111 serves as the operating memory for CPU 1112, which performs overall control operations for data exchange with memory controller 1110. Host interface 1113 includes a data exchange protocol for a host connected to memory system 1100. Error correction block 1114 detects and corrects errors included in data read from memory device 1120. Memory interface 1115 interfaces with memory device 1120. Memory controller 1110 may also include read-only memory (ROM) for storing code data for interfacing with the host.

[0153] The memory system 1100 configured as described above can be a memory card or a solid-state drive (SSD), wherein the memory device 1120 is combined with the memory controller 1110. For example, when the memory system 1100 is an SSD, the memory controller 1110 can communicate with an external (e.g., a host) via one of a variety of interface protocols, such as the Universal Serial Bus (USB) protocol, the Multimedia Card (MMC) protocol, the Peripheral Component Interconnect (PCI) protocol, the PCI Express (PCI-E) protocol, the Advanced Technology Attachment (ATA) protocol, the Serial ATA (SATA) protocol, the Parallel ATA (PATA) protocol, the Small Computer System Interface (SCSI) protocol, the Enhanced Small Disk Interface (ESDI) protocol, and the Integrated Drive Electronics (IDE) protocol.

[0154] Figure 14 This is a block diagram illustrating the configuration of a computer system according to an embodiment of the present disclosure.

[0155] refer to Figure 14 The computing system 1200 may include a CPU 1220, random access memory (RAM) 1230, user interface 1240, modem 1250, and memory system 1210 electrically connected to a system bus 1260. When the computing system 1200 is a mobile device, it may also include a battery for supplying operating voltage to the computing system 1200, and may also include an application chip suite, a camera image processor (CIS), mobile DRAM, etc.

[0156] The memory system 1210 may be configured with a memory device 1212 and a memory controller 1211.

[0157] According to this disclosure, a memory device with improved erasure performance and a method of operating the same can be provided.

[0158] Embodiments of this disclosure have been described in the accompanying drawings and specification. Although specific terminology is used herein, it is only for describing embodiments of this disclosure. Therefore, this disclosure is not limited to the above-described embodiments and many variations are possible within the spirit and scope of this disclosure. Those skilled in the art will understand that various modifications can be made based on the technical scope of this disclosure in addition to the embodiments disclosed herein.

[0159] Unless otherwise defined, all terms used herein, including technical or scientific terms, have the meaning commonly understood by one of ordinary skill in the art to which this disclosure pertains. Terms with dictionary definitions should be understood to have a meaning consistent with the context of the relevant art. Terms not explicitly defined in this application should not be interpreted in an idealized or overly formal manner.

[0160] As can be understood from the foregoing, although specific embodiments of the invention have been described herein for illustrative purposes, various modifications may be made without departing from the spirit and scope of the invention. Therefore, the invention should not be limited except as provided in the appended claims.

Claims

1. A memory device, comprising: Common source line formed on the substrate; An array of memory cells is formed on the common source line; Bit lines connected to the memory cell array; as well as A conductive layer formed on the bit line, The memory device is configured to increase the voltage of the bit line to the erase voltage by increasing the voltage applied to the conductive layer during an erase operation, through capacitive coupling between the conductive layer and the bit line.

2. The memory device according to claim 1, The memory cell array includes: A gate stack structure comprising alternately stacked interlayer insulating layers and conductive patterns; as well as The channel structure penetrates the gate stack structure while connecting to the common source line, and Each of the channel structures is connected to the bit line corresponding to that channel structure in the bit line.

3. The memory device of claim 2, wherein the common source line includes a contact region that does not overlap with the gate stack structure.

4. The memory device of claim 3 further includes a power supply electrode contact structure extending from the contact area of ​​the common source line toward the conductive layer.

5. The memory device according to claim 4, further comprising: Peripheral circuitry, including a source line driver configured to provide an erase voltage to the common source line or to discharge the common source line; as well as An internal voltage generator is configured to provide an internal voltage to the peripheral circuit.

6. The memory device of claim 5, wherein the conductive layer connects the common source line to the source line driver.

7. The memory device of claim 5, wherein the conductive layer connects the internal voltage generator to the peripheral circuitry.

8. The memory device according to claim 1, in, During the erase operation, the memory device is further configured to apply an initialization voltage to the bit line and float the bit line before the voltage on the bit line is increased. The memory device increases the voltage of the bit line from the initialization voltage to the erase voltage by increasing the voltage of the conductive layer.

9. The memory device of claim 1, wherein the memory device increases the voltage of the bit line by: A first voltage is applied to the first bit line of the bit line, which is connected to the memory string where the erase verification operation has been completed. A second voltage higher than the first voltage is applied to a second bit line in the bit line, the second bit line being connected to the memory string where the erase verification operation has failed; Make the first bit line and the second bit line float; as well as By increasing the voltage of the conductive layer, the voltage of the first bit line is increased from the first voltage to a first erase voltage, and the voltage of the second bit line is increased from the second voltage to a second erase voltage higher than the first erase voltage.

10. The memory device of claim 1, wherein the memory device increases the voltage of the bit line by: A first voltage is applied to the first bit line of the bit line, which is connected to the memory string where the erase verification operation has been completed. A second voltage higher than the first voltage is applied to a second bit line in the bit line, the second bit line being connected to the memory string where the erase verification operation has failed; Set the second bit line to float; as well as By increasing the voltage of the conductive layer, the voltage of the second bit line is increased from the second voltage to the erase voltage.

11. A method for operating a memory device, the memory device comprising a plurality of bit lines and a conductive layer formed over the plurality of bit lines, the method comprising: Apply an initialization voltage to the bit line; Make the bit line float; as well as By increasing the voltage of the conductive layer, the voltage of the bit line is increased from the initial voltage to the erase voltage through capacitive coupling between the conductive layer and the bit line.

12. The method of claim 11, wherein the initialization voltage is a ground voltage.

13. The method of claim 11, wherein the initialization voltage is a voltage higher than 0V.

14. The method of claim 11, wherein when the voltage of the bit line is increased to the erase voltage, a gate-induced drain leakage (GIDL) current is generated between the junction region of the select transistor connected to the bit line and the drain select line.

15. The method of claim 11, wherein applying the initialization voltage to the bit line comprises: A first voltage is applied to the first bit line of the bit line, which is connected to the memory string where the erase verification operation has been completed. as well as A second voltage higher than the first voltage is applied to a second bit line in the bit line, the second bit line being connected to the memory string where the erase verification operation has failed.

16. The method of claim 15, wherein floating the bit lines comprises floating the first bit line and the second bit line.

17. The method of claim 16, wherein increasing the voltage of the bit line from the initialization voltage to the erase voltage via the capacitive coupling comprises: By increasing the voltage of the conductive layer, the voltage of the first bit line is increased from the first voltage to a first erase voltage, and the voltage of the second bit line is increased from the second voltage to a second erase voltage higher than the first erase voltage.

18. The method of claim 15, wherein floating the bit line comprises floating the second bit line.

19. The method of claim 18, wherein increasing the voltage of the bit line from the initialization voltage to the erase voltage via the capacitive coupling comprises: By increasing the voltage of the conductive layer, the voltage of the second bit line is increased from the second voltage to the erase voltage.

20. A memory device, comprising: A common source line is formed on the substrate; A memory cell array is formed on the common source line and includes a first memory cell string and a second memory cell string; The first bit line and the second bit line are electrically coupled to the first memory cell string and the second memory cell string, respectively. A conductive layer is disposed on the bit line; as well as A logic circuit, electrically coupled to the conductive layer and the bit line, is configured as follows: The first initialization voltage and the second initialization voltage are applied to the first bit line and the second bit line, respectively. Make the second bit line float, and Increase the voltage of the conductive layer to raise the voltage of the second bit line to the second erase voltage through capacitive coupling between the conductive layer and the second bit line.

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