Semiconductor device and method of forming the same

Abstract

The present invention discloses a semiconductor device and a method for forming the same. The method includes: providing a substrate, on which a dielectric layer is disposed, the dielectric layer includes at least one opening filled with an organic coating, and a pattern layer is disposed on a part of the dielectric layer; introducing a deposition gas and a dilution gas to form a protective layer on the surfaces of the dielectric layer and the organic coating, and on the sidewalls and top surface of the pattern layer, wherein the thicknesses of the protective layer on the sidewalls and top surface of the pattern layer and the protective layer on the surface of the dielectric layer are both greater than the thickness of the protective layer on the surface of the organic coating. Before small hole etching, the present invention introduces a deposition gas and a dilution gas to deposit a polymer protective layer on the surface of the dielectric layer, on the sidewalls and top surface of the pattern layer, and there is very little or almost no deposition on the organic coating at the top of the opening. Due to the blocking of the protective layer, it is possible to increase the small hole etching ability and reduce the film damage of the dielectric layer and the pattern layer at the same time.

Description

Technical Field

[0001] The present invention belongs to the field of semiconductor technology, and particularly relates to a method for forming a semiconductor device and a semiconductor device. Background Art

[0002] With the increasing update of the chip industry and the rising of technology nodes, the requirements for the refinement of processes and technologies are getting higher and higher. Especially when it comes to 3 nanometers and below, the refined processes become increasingly prominent. For example, the uniformity of most processes (uniformity), whether in the deposition of thin films, etching, polishing, etc., requires high uniformity as the nanometer nodes increase. In terms of etching, for another example, the accuracy of the process, low damage, and strong etching ability are required.

[0003] Currently, at 3nm and below, the etching of organic materials faces great challenges, especially the etching of small holes (width dimensions less than 15nm). Due to the high aspect ratio of these small holes, the etching ability at the bottom of the small holes decreases sharply. Coupled with the complexity of the dielectric layer and the density of the photoresist pattern layer, the small hole etching encounters bottlenecks in many aspects and needs to meet conditions such as lower film loss, appropriate photoresist size, and strong organic etching ability simultaneously.

[0004] The current chemical environment is difficult to fully meet these conditions, and it is the same in practical applications. Figure 1 Shows a schematic diagram of the states before and after the completion of small hole etching of an organic coating with a high aspect ratio and small size. Figure 1 In [diagram], a is a schematic diagram of the initial state of the semiconductor device. After etching, the following problems usually exist: as Figure 1 Shown in b of [diagram], 1) The film loss of the top dielectric layer is relatively large (losing the film layer 11); 2) There is a residual organic layer 12 at the bottom. The main reason for these problems is that the etchant for etching is insufficient and the bombardment force is relatively strong, resulting in the photoresist being sputtered into the small holes and the loss of the film.

[0005] Therefore, it is urgent to develop a small hole etching process suitable for reducing the loss at the top of the dielectric layer and at the same time reducing the residue of the organic layer. Summary of the Invention

[0006] The object of the present invention is to solve the problems of relatively large film loss of the top dielectric layer and easy residue of the organic layer at the bottom of the small hole etching process with a high aspect ratio, and provide a method to form a protective layer on the surface of the dielectric layer and the pattern layer before small hole etching, so that there is no need to reduce the bombardment force to avoid splashing the photoresist material of the pattern layer into the small holes, nor to reduce the concentration of the etchant to reduce the loss of the dielectric layer, making the etching ability in the small holes stronger, with no residual organic layer at the bottom and less loss of the dielectric layer.

[0007] To achieve the above object, the present invention provides a method for forming a semiconductor device, comprising:

[0008] Providing a substrate, on which a dielectric layer is provided, the dielectric layer comprising at least one opening filled with an organic coating, and a pattern layer is provided on a part of the dielectric layer;

[0009] Introducing a deposition gas and a dilution gas to form a protective layer on the surfaces of the dielectric layer and the organic coating, and on the sidewalls and top surfaces of the pattern layer, wherein the thicknesses of the protective layers on the sidewalls and top surfaces of the pattern layer and on the surface of the dielectric layer are both greater than the thickness of the protective layer on the surface of the organic coating.

[0010] Optionally, the deposition gas is C x H y , where x = 1 to 5, y = 2 to 8, and the dilution gas includes at least one of CO and CO2.

[0011] Optionally, the deposition gas includes at least one of CH4, C2H6, and C2H4.

[0012] Optionally, the volume ratio of the deposition gas to the dilution gas is 1:1 to 3:1.

[0013] Optionally, the width of the opening is 5 nm to 15 nm.

[0014] Optionally, the width of the opening is 6 nm to 8 nm.

[0015] Optionally, the organic coating is a bottom anti-reflection layer.

[0016] Optionally, the pattern layer is a photoresist.

[0017] Optionally, the process conditions for depositing the protective layer include: a pressure of 40 mT to 120 mT, a radio frequency of 50 MHz to 70 MHz, a power of 150 W to 600 W, an upper electrode temperature of 80 °C to 120 °C, and a lower electrode temperature of 15 °C to 30 °C.

[0018] Optionally, after forming the protective layer, it further includes: etching the organic coating to expose the substrate at the bottom of the opening.

[0019] Optionally, the step of forming the protective layer and the step of etching the organic coating are alternately performed until the substrate at the bottom of the opening is exposed.

[0020] The present invention further provides a semiconductor device, comprising:

[0021] A substrate having a dielectric layer thereon, the dielectric layer including at least one opening filled with an organic coating, and a pattern layer on a part of the dielectric layer;

[0022] A protective layer on the surfaces of the dielectric layer and the organic coating, as well as on the sidewalls and top surface of the pattern layer, and the thicknesses of the protective layers on the sidewalls and top surface of the pattern layer and on the surface of the dielectric layer are greater than the thickness of the protective layer on the surface of the organic coating.

[0023] The technical concept of the present invention: By selecting deposition gas and dilution gas and adjusting the ratio between the two, a uniform protective layer is formed on the top and sidewall surfaces of the pattern layer and on the surface of the dielectric layer, while very little deposition occurs on the organic coating at the top of the opening. This protective layer has a certain passivation effect on the sidewalls of the pattern layer, can protect the sidewalls of the pattern layer from being sputtered into the opening; and a thick enough protective layer on the sidewalls can also protect the area where the bottom of the pattern layer contacts the dielectric layer from interference, reducing the film loss between the pattern layer and the dielectric layer. Very little polymer deposition occurs on the top of the opening, which will not interfere with the small hole etching, and can ensure selective etching of the organic coating in the opening; and because a relatively thick protective layer is formed on the surface of the dielectric layer and the surface of the pattern layer, the etching rate of the small hole can be guaranteed without reducing the etching power and / or the concentration of the etchant to avoid film damage.

[0024] The beneficial effects of the present invention:

[0025] Due to the thickness difference of the protective layer formed by the deposition gas and the dilution gas provided by the present invention on the top of the opening and on the pattern layer and dielectric layer surfaces around the opening, that is, the thicknesses of the protective layers on the sidewalls and top surface of the pattern layer and on the surface of the dielectric layer are greater than the thickness of the protective layer on the surface of the organic coating, it is possible to avoid reducing the etching power to avoid damage to the pattern layer or the dielectric layer during the subsequent etching process of the opening, thereby ensuring the etching rate of the opening (small size structure). Therefore, the process method provided by the present invention takes into account the advantages of increasing the etching ability of the small hole and reducing the damage to the dielectric layer. Description of the Drawings

[0026] Figure 1 Schematic diagrams of the states before and after the completion of small hole etching of an organic coating with a high aspect ratio and small size in the prior art.

[0027] Figure 2 Flow chart of a method for forming a semiconductor device according to the present invention.

[0028] Figure 3 Schematic diagram of the reaction principle for depositing the protective layer according to the present invention.

[0029] Figure 4Schematic diagram of the etching rate comparison between the center and the edge of the protective layer deposited for the present invention in a device.

[0030] Figure 5a Cross-sectional view of the semiconductor device before treatment in Example 1 of the present invention;

[0031] Figure 5b Cross-sectional view of the semiconductor device in Example 1 of the present invention after the deposition of the protective layer;

[0032] Figure 5c Cross-sectional view of the semiconductor device in Example 1 of the present invention after one cycle of the deposition of the protective layer - etching step;

[0033] Figure 5d Cross-sectional view of the semiconductor device in Example 1 of the present invention after two cycles of the deposition of the protective layer - etching step.

[0034] Figure 6 Schematic diagram of the states before and after the completion of several depositions of the protective layer - etching for the semiconductor device in Example 2 of the present invention.

[0035] Lost thin film layer 11

[0036] Residual organic layer 12

[0037] Substrate 21

[0038] Dielectric layer 22

[0039] Lost layer 221

[0040] Opening 23

[0041] Organic coating 24

[0042] Pattern layer 25

[0043] Protective layer 26. Detailed implementation manners

[0044] The technical solutions of the present invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are some but not all of the embodiments of the present invention. All other embodiments obtained by those of ordinary skill in the art based on the embodiments of the present invention without creative efforts shall fall within the protection scope of the present invention.

[0045] In the description of the present invention, it should be noted that the orientation or positional relationship indicated by the terms "upper", "lower", "inner", "top", "sidewall", "bottom", etc. is based on the orientation or positional relationship shown in the drawings. It is only for the convenience of describing the present invention and simplifying the description, rather than indicating or implying that the device or element referred to must have a specific orientation, be constructed and operated in a specific orientation, and therefore cannot be construed as a limitation of the present invention.

[0046] As Figure 2 shown, the present invention provides a method for forming a semiconductor device, which includes:

[0047] Step S1: Provide a substrate, on which a dielectric layer is provided. The dielectric layer includes at least one opening, and the opening is filled with an organic coating. A pattern layer is provided on at least a part of the dielectric layer. The width of the opening is less than 15 nm, and the opening is a small hole with a high aspect ratio.

[0048] In some embodiments, the organic coating is a bottom anti-reflection layer. The pattern layer is a photoresist (abbreviated as PR).

[0049] Step S2: Introduce a deposition gas and a dilution gas to form a protective layer on the surface of the dielectric layer and the organic coating, as well as on the sidewalls and top surface of the pattern layer. Among them, the thickness of the protective layer on the sidewalls and top surface of the pattern layer and the protective layer on the surface of the dielectric layer is greater than the thickness of the protective layer on the surface of the organic coating.

[0050] The process conditions for depositing and forming the protective layer include: the pressure is 40 mT to 120 mT, the radio frequency frequency is high frequency, such as 50 MHz to 70 MHz can be selected, the power is 150 W to 600 W, the temperature of the upper electrode is 80 to 120 °C, and the temperature of the lower electrode is 15 to 30 °C.

[0051] For small-sized structures with a high aspect ratio and an opening width less than 15 nm, due to the size effect, it is difficult for deposited ions to enter the small-sized opening, and it is not easy to form polymer deposition on the top of the opening, making it easier for the polymer protective layer to form on the pattern layer and the surface of the dielectric layer near the opening, rather than on the top of the opening.

[0052] Furthermore, due to the exposure area, the thickness of the protective layer on the sidewalls and top surface of the pattern layer > the thickness of the protective layer on the surface of the dielectric layer > the thickness of the protective layer on the surface of the organic coating. There is almost no polymer protective layer formed on the surface of the organic coating at the top of the opening.

[0053] The deposition gas is C x H y, where x = 1 - 5 and y = 2 - 8, for forming a protective layer. In some embodiments, the deposition gas can be selected from at least one of CH4, C2H6, and C2H4.

[0054] The dilution gas includes at least one of CO and CO2.

[0055] As Figure 3 shown, it is a schematic diagram of the reaction principle for depositing the protective layer of the present invention. The mixed gas C x1 H y1 O z (where x1, y1, and z are used to represent the atomic ratios of C, H, and O respectively, and are all positive numbers greater than 0) contains the deposition gas C x H y and the dilution gas CO or CO2. Among them, C x H y is used as a polymer source to deposit a polymer to form a protective layer, and CO or CO2 is used as a dilution gas and can participate in the reaction: on the one hand, it is used to adjust the polymer deposition to make it evenly distributed to achieve uniformity, and on the other hand, it generates positive ions, and the positive ions have a directional property to promote faster polymer deposition in a specific structure (such as a pattern layer, a dielectric layer). The present invention also uses Ar, N2, and He as dilution gases respectively to replace CO or CO2 for comparative experiments. The results show that under the same conditions, using Ar as the dilution gas results in more loss of the dielectric layer; and when Ar, N2, and He are used as dilution gases, the uniformity is relatively poor.

[0056] By adjusting the ratio of the deposition gas / dilution gas, faster and more uniform polymer deposition can be achieved on the top and sidewalls of the pattern layer (photoresist), while slower polymer deposition occurs at the bottom (on the organic coating), and no etching stop phenomenon will occur. If there is too much dilution gas (such as CO), the thickness of the formed protective layer will become thinner and the uniformity will be uncontrollable; if there is too little CO, the nucleation will be uneven and it cannot play a protective role. Optionally, the volume ratio of the deposition gas to the dilution gas is 1:1 - 3:1, and the formed protective layer has good uniformity, whether on a light sheet or on a chip with a characteristic pattern.

[0057] This uniformity is verified on Figure 4 : After 10 s of deposition, etching can be carried out for 15 s, and even up to 30 s, and the uniform etching effect at the center / edge of the device can be continuously maintained. It can be seen that this deposition gas / dilution gas has a very good deposition effect. Further discovery shows that as the power increases, the uniformity effect is better.

[0058] Example 1

[0059] As Figure 5aAs shown, the semiconductor device before processing includes: a substrate 21, a dielectric layer 22 on the substrate, the dielectric layer is provided with a number of openings 23, and a BARC organic coating 24 is spin-coated and filled in both the dielectric layer and the openings. A pattern layer 25 is provided on the dielectric layer around the openings. Among them, the height of the pattern layer is 138.5 nm, the width of the pattern layer is 65.9 nm, and the size of the BARC depression in the opening is 46.0 nm.

[0060] CH4 / CO with a volume ratio of 3:1 is used as the precursor of the polymer, the pressure is 60 mT, the radio frequency is 60 MHz, the power is 300 W, the temperature of the upper electrode is 80 °C, and the temperature of the lower electrode is 23 °C. The polymer is deposited to form a protective layer.

[0061] The results of depositing for 10 s are as follows: As Figure 5b shown, it is found that the top and side walls of the pattern layer have a relatively uniform protective layer 26 (the height of the pattern layer thickens to 157.7 nm, an increase of 19.2 nm, the width of the pattern layer 25 thickens to 95.0 nm, an increase of 29.1 nm). This protective layer protects the side walls and the top of the pattern layer; moreover, at the bottom of the pattern layer, that is, at the top of the opening, almost no polymer is deposited (the size of the BARC depression is 44.7 nm, an increase of 1.3 nm), which brings great advantages to the small hole etching.

[0062] The semiconductor device with the protective layer deposited above is subjected to small hole etching. After etching for 30 s, as Figure 5c shown, the height of the pattern layer 25 is 106.5 nm (a decrease of 51.2 nm), the width of the pattern layer is 71.2 nm (a decrease of 23.8 nm), and the size of the BARC depression on the opening is 86.2 nm (etched 41.5 nm, etched 40.2 nm relative to before forming the protective layer). It can be seen that the side walls of the pattern layer do not completely consume the protective layer, and a certain amount of etching has occurred at the top of the opening.

[0063] Deposit again (for 5 s) and etch (for 20 s). As Figure 5d shown, the height of the pattern layer 25 is 88.4 nm (relative to Figure 5c the height of the pattern layer in which it has decreased by 18.1 nm), the width of the pattern layer is 69.7 nm (relative to Figure 5c the width of the pattern layer in which it has decreased by 1.5 nm), and the size of the BARC depression on the opening is 116.7 nm (relative to Figure 5c the pattern depression in which it has been etched by 30.5 nm). It can be seen that the side walls of the pattern layer still maintain an appropriate thickness, and the etching of the small holes is not disturbed at all, proving that the uniform polymer deposition can well protect the side walls of the pattern layer without affecting the etching of the underlying openings.

[0064] Example 2

[0065] Place the substrate 21 in a plasma etching chamber. As shown in a of Figure 6 , a dielectric layer 22 is provided on the substrate 21. The dielectric layer 22 includes at least one opening 23, and the opening 23 is filled with an organic coating 24. A pattern layer 25 is provided on a part of the dielectric layer.

[0066] Introduce deposition gas CH4 and dilution gas CO respectively, and the flow rate ratio of the two is 1:1. Deposit a protective layer: the pressure is 40 mT, the radio frequency is 60 MHz, the power is 150 W, the temperature of the upper electrode is 120 °C, and the temperature of the lower electrode is 30 °C. After 10 s, a protective layer 26 is formed on the surfaces of the dielectric layer 22 and the organic coating 24, and on the sidewalls and top surfaces of the pattern layer 25. Among them, the protective layer 26 is located on the surfaces of the dielectric layer 22 and the organic coating 24, and on the sidewalls and top surfaces of the pattern layer 25, and the thicknesses of the protective layers on the sidewalls and top surfaces of the pattern layer and the protective layer on the dielectric layer surface are both greater than the thickness of the protective layer on the organic coating surface.

[0067] In order to make the subsequent etching process selectively etch mainly the organic coating 24 in the opening 23, the thinner the protective layer formed on its surface, the better.

[0068] Etch for 15 s. Since a relatively thick protective layer is formed on the sidewalls and top of the pattern layer 25, during ion bombardment, the photoresist material of the pattern layer is not easily sputtered into the opening, reducing the consumption of the etchant due to the photoresist material in the opening, thereby improving the etching rate of the organic coating in the opening. Since the protective layer formed on the surface of the dielectric layer 22 is thicker than the protective layer on the organic coating, during the etching process, all the protective layers on the organic coating are etched off first, and then the organic coating is etched. Due to the barrier of the protective layer on the surface of the dielectric layer 22, the dielectric layer is less damaged.

[0069] Alternately perform the above steps of depositing the protective layer and the etching step until the organic coating in the opening is completely etched. As shown in b of Figure 6 , there is no residue of the organic coating at the bottom of the opening, the loss layer 221 of the dielectric layer is small, and the height and width of the pattern layer are also less lost.

[0070] In summary, the method provided by the present invention is to deposit a polymer protective layer on the surface of the dielectric layer, the sidewalls and top surfaces of the pattern layer by introducing deposition gas and dilution gas before small hole etching. There is little or almost no deposition on the organic coating at the top of the opening. Due to the barrier of the protective layer, it is possible to increase the small hole etching ability and reduce the film damage of the dielectric layer and the pattern layer.

[0071] Although the content of the present invention has been described in detail through the above preferred embodiments, it should be recognized that the above description should not be considered as a limitation of the present invention. After those skilled in the art have read the above content, various modifications and alternatives to the present invention will be obvious. Therefore, the protection scope of the present invention should be defined by the appended claims.

Claims

1. A method for forming a semiconductor device, characterized in that, The method includes: providing a substrate, on which a dielectric layer is provided, the dielectric layer includes at least one opening, the width of the opening is less than 15 nm; the opening is filled with an organic coating, and a pattern layer is provided on a part of the dielectric layer; Introduce deposition gas and dilution gas to form a protective layer on the surface of the dielectric layer and the organic coating, as well as on the sidewalls and top surface of the pattern layer. Among them, the thicknesses of the protective layers on the sidewalls and top surface of the pattern layer and on the surface of the dielectric layer are both greater than the thickness of the protective layer on the surface of the organic coating; the deposition gas is C x H y , where x = 1 to 5, y = 2 to 8, and the dilution gas includes at least one of CO and CO2; etching the organic coating after forming the protective layer.

2. The method for forming a semiconductor device according to claim 1, wherein, The deposition gas includes at least one of CH4, C2H6, and C2H4.

3. The method for forming a semiconductor device according to claim 1, wherein, The volume ratio of the deposition gas to the dilution gas is 1:1 to 3:

1.

4. The method for forming a semiconductor device according to claim 1, wherein, The width of the opening is 5 nm to 15 nm.

5. The method for forming a semiconductor device according to claim 4, wherein, The width of the opening is 6 nm to 8 nm.

6. The method for forming a semiconductor device according to claim 1, wherein, The organic coating is a bottom anti-reflection layer.

7. The method for forming a semiconductor device according to claim 1, wherein, The pattern layer is a photoresist.

8. The method for forming a semiconductor device according to claim 1, wherein, The process conditions for depositing to form the protective layer include: the pressure is 40 mT to 120 mT, the radio frequency is 50 MHz to 70 MHz, the power is 150 W to 600 W, the temperature of the upper electrode is 80 °C to 120 °C, and the temperature of the lower electrode is 15 °C to 30 °C.

9. The method for forming a semiconductor device according to claim 1, wherein, The step of forming the protective layer and the step of etching the organic coating are alternately performed until the substrate at the bottom of the opening is exposed.

10. A semiconductor device, characterized in that, Formed by using the method for forming a semiconductor device according to any one of claims 1-9, including: a substrate, on which a dielectric layer is provided, the dielectric layer includes at least one opening, the opening is filled with an organic coating, and a pattern layer is provided on a part of the dielectric layer; a protective layer located on the surfaces of the dielectric layer and the organic coating, as well as the sidewalls and top surface of the pattern layer, and the thicknesses of the protective layers on the sidewalls and top surface of the pattern layer and the surface of the dielectric layer are all greater than the thickness of the protective layer on the surface of the organic coating.

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