Semiconductor element with decoupling unit and method for producing same

Abstract

The present disclosure provides a semiconductor device with a decoupling unit and a method of manufacturing the same. The semiconductor device has a substrate, including an array region and a surrounding region disposed adjacent to the array region; a first decoupling unit in the surrounding region of the substrate; a memory unit in the array region of the substrate; a redistribution structure on the surrounding region and the array region of the substrate; an intermediate isolation layer on the redistribution structure in the surrounding region; and an upper conductive layer on the intermediate isolation layer. The redistribution structure, the intermediate isolation layer, and the upper conductive layer on the surrounding region are configured together as a second decoupling unit.

Description

[0001] CROSS-REFERENCE

[0002] This disclosure claims priority to and the benefit of U.S. Nonprovisional Application No. 17 / 108,736, filed on December 1, 2020, the contents of which are incorporated herein by reference in their entirety. TECHNICAL FIELD

[0003] The present disclosure relates to a semiconductor device and a method of manufacturing the same. In particular, the present disclosure relates to a semiconductor device having a decoupling unit and a method of manufacturing the same. BACKGROUND

[0004] Semiconductor devices are used in different electronic applications, such as personal computers, cell phones, digital cameras, or other electronic devices. The size of semiconductor devices is gradually reduced to meet the increasing demand for computing power. However, during the process of size reduction, different problems are increased, and such problems continue to increase in number and complexity. Therefore, there are still challenges in achieving improved quality, yield, performance, and reliability, as well as reducing complexity.

[0005] The above description of background art is provided merely for generally presenting the technical field of the disclosure and does not acknowledge that any of the above description of background art discloses the subject matter of the present disclosure, does not constitute the prior art of the present disclosure, and any description of the above background art should not be considered as part of the present disclosure. SUMMARY

[0006] One embodiment of the present disclosure provides a semiconductor device having a substrate including an array region and a surrounding region disposed adjacent to the array region; a first decoupling unit in the surrounding region of the substrate; a memory unit in the array region of the substrate; a redistribution structure on the surrounding region and the array region of the substrate; an intermediate isolation layer on the redistribution structure on the surrounding region; and an upper conductive layer on the intermediate isolation layer. The redistribution structure, the intermediate isolation layer, and the upper conductive layer on the surrounding region are configured together as a second decoupling unit.

[0007] In some embodiments, the first decoupling unit and the memory unit are a plurality of trench capacitors.

[0008] In some embodiments, the first decoupling unit includes an inner conductive layer in the substrate; a buried plate disposed around a lower portion of the inner conductive layer; a capacitor dielectric layer between the lower portion of the inner conductive layer and the buried plate; a strap conductive layer on the inner conductive layer; a cover isolation layer on the strap conductive layer; and a joint portion adjacent to the strap conductive layer.

[0009] In some embodiments, the inner conductive layer includes a lower portion surrounded by the buried plate and a collar portion on the lower portion, and the strip conductive layer is on the collar portion.

[0010] In some embodiments, the joint portion and the strip conductive layer have the same conductive type.

[0011] In some embodiments, the semiconductor element further includes a recessed annular dielectric layer disposed on a lower portion of the collar portion of the inner conductive layer.

[0012] In some embodiments, the recessed annular dielectric layer includes silicon oxide, silicon nitride, silicon oxynitride, or silicon oxynitride.

[0013] In some embodiments, the semiconductor element further includes a first switching unit on the peripheral region of the substrate and adjacent to the joint portion of the first decoupling unit, wherein the first switching unit is electrically coupled to the first decoupling unit.

[0014] In some embodiments, the intermediate isolation layer has a thickness between about 5 nm and about 100 nm.

[0015] In some embodiments, the intermediate isolation layer includes silicon oxide, silicon nitride, silicon oxynitride, silicon oxynitride, hafnium oxide, silicon hafnium oxide, silicon hafnium oxynitride, lanthanum oxide, lanthanum aluminum oxide, zirconium oxide, silicon zirconium oxide, silicon zirconium oxynitride, aluminum oxide, or combinations thereof.

[0016] In some embodiments, the semiconductor element further includes a pad layer under the redistribution structure and electrically connected to the redistribution structure.

[0017] In some embodiments, the redistribution layer includes a seed layer on the peripheral region and the array region and a plating layer on the seed layer.

[0018] In some embodiments, the semiconductor element further includes a barrier layer between the pad layer and the redistribution structure, wherein the barrier layer includes titanium, titanium nitride, titanium silicon nitride, tantalum, tantalum nitride, tantalum silicon nitride, or combinations thereof.

[0019] In some embodiments, the barrier layer has a thickness between about and about .

[0020] In some embodiments, the semiconductor element further includes an adjustment layer between the barrier layer and the redistribution structure, wherein the adjustment layer includes graphene or graphite.

[0021] In some embodiments, the redistribution structure includes a peripheral portion, an array portion, and a connecting portion, the peripheral portion is located on the peripheral region, the array portion is located on the array region, the connecting portion connects the peripheral portion and the array portion, and the intermediate isolation layer is located on the peripheral portion.

[0022] In some embodiments, the conductor element further includes a heat release layer located on the array portion of the redistribution structure, wherein the heat release layer is configured to maintain a thermal resistance between about 0.04°C cm 2 / Watt to about 0.25°C cm 2 / Watt.

[0023] In some embodiments, the heat release layer includes an organic material interstitially mingled with carbon nanotubes.

[0024] Another embodiment of the present disclosure provides a method of fabricating a semiconductor element, including: providing a substrate including an array region and a peripheral region, the peripheral region is disposed adjacent to the array region; simultaneously forming a first decoupling unit in the peripheral region of the substrate and a memory unit in the array region of the substrate; forming a redistribution structure on the peripheral region of the substrate and on the array region of the substrate; forming an intermediate isolation layer on the redistribution structure formed on the peripheral region of the substrate; and forming an upper conductive layer on the intermediate isolation layer. The redistribution structure formed on the peripheral region, the intermediate isolation layer, and the upper conductive layer together configure a second decoupling unit.

[0025] In some embodiments, the first decoupling unit and the memory unit are trench capacitors.

[0026] Due to the design of the semiconductor element of the present disclosure, the first decoupling unit and the second decoupling unit can act as temporary charge reservoirs to avoid momentary fluctuation under a supply voltage condition. Therefore, the reliability of the semiconductor element can be improved.

[0027] The technical features and advantages of this disclosure have been broadly summarized above, thus enabling a better understanding of the detailed description of this disclosure that follows. Other technical features and advantages constituting the subject matter of the claims will be described below. Those skilled in the art to which this disclosure pertains will understand that the concepts and specific embodiments disclosed below can be readily utilized to achieve the same purpose as this disclosure through modifications or design of other structures or processes. Those skilled in the art will also understand that such equivalent constructions cannot depart from the concept and scope of this disclosure as defined by the claims. Attached Figure Description

[0028] The contents of this disclosure can be more fully understood by referring to the accompanying drawings in conjunction with the embodiments and claims, where the same element symbols refer to the same elements.

[0029] FIG. 1 A schematic flowchart illustrating a method for fabricating a semiconductor device according to an embodiment of the present disclosure is shown.

[0030] FIGS. 2-22 A cross-sectional schematic diagram illustrating a portion of the process for fabricating the semiconductor device according to an embodiment of the present disclosure.

[0031] FIG. 23 A top view schematic diagram illustrating an intermediate semiconductor element according to an embodiment of the present disclosure.

[0032] FIG. 24 An embodiment of this disclosure is illustrated along the edge FIG. 23 A cross-sectional view of section line A-A'.

[0033] FIG. 25 A top view schematic diagram illustrating an intermediate semiconductor element according to an embodiment of the present disclosure.

[0034] FIG. 26 An embodiment of this disclosure is illustrated along the edge FIG. 25 A cross-sectional view of section line A-A'.

[0035] FIG. 27 A top view schematic diagram illustrating an intermediate semiconductor element according to an embodiment of the present disclosure.

[0036] FIG. 28 An embodiment of this disclosure is illustrated along the edge FIG. 27 A cross-sectional view of section line A-A'.

[0037] FIG. 29 An embodiment of this disclosure is illustrated along the edge FIG. 27 A schematic cross-sectional view along section line B-B'.

[0038] FIG. 30 A top view schematic diagram illustrating an intermediate semiconductor element according to an embodiment of the present disclosure.

[0039] FIG. 31 An embodiment of this disclosure is illustrated along the edge FIG. 30 A cross-sectional view of section line A-A'.

[0040] FIG. 32 An embodiment of this disclosure is illustrated along the edge FIG. 30 A schematic cross-sectional view along section line B-B'.

[0041] FIG. 33 This embodiment of the present disclosure illustrates a portion of the process for fabricating the semiconductor device. FIG. 30 A cross-sectional view of section line A-A'.

[0042] FIGS. 34-38 A cross-sectional schematic diagram illustrating a process for fabricating the semiconductor device according to some embodiments of this disclosure is shown.

[0043] Explanation of reference numerals in the attached figures:

[0044] 1A: Semiconductor components

[0045] 1B: Semiconductor components

[0046] 1C: Semiconductor components

[0047] 1D: Semiconductor components

[0048] 1E: Semiconductor components

[0049] 1F: Semiconductor components

[0050] 10: Preparation method

[0051] 101: Base

[0052] 103: Insulation layer

[0053] 105: Inner Connector Layer

[0054] 107: Lower passivation layer

[0055] 107O: Opening in the lower passivation layer

[0056] 109A: Subbase

[0057] 109P: Subbase

[0058] 111: Upper passivation layer

[0059] 111BE: Lower edge

[0060] 111E: Lower edge

[0061] 111O: Opening in the upper passivation layer

[0062] 111SW: Sidewall

[0063] 111TE: upper edge

[0064] 113: pad dielectric layer

[0065] 113SW: sidewall

[0066] 115: heat release layer

[0067] 117: upper gap sub

[0068] 200A: storage cell

[0069] 200P: first decoupling cell

[0070] 201-1: buried plate

[0071] 201-3: buried plate

[0072] 203-1: inner conductive layer

[0073] 203-3: inner conductive layer

[0074] 203B-1: lower portion

[0075] 203B-3: lower portion

[0076] 203C-1: ring portion

[0077] 203C-3: ring portion

[0078] 205-1: capacitor dielectric layer

[0079] 205-3: capacitor dielectric layer

[0080] 207-1: recessed ring dielectric layer

[0081] 207-3: recessed ring dielectric layer

[0082] 209-1: strip conductive layer

[0083] 209-3: strip conductive layer

[0084] 211-1: cover isolation layer

[0085] 211-3: cover isolation layer

[0086] 213-1: tab portion

[0087] 213-3: tab portion

[0088] 300A: second switching cell

[0089] 300P: first switching cell

[0090] 301-1: gate dielectric layer

[0091] 301-3: gate dielectric layer

[0092] 303-1: conductive layer under gate

[0093] 303-3: conductive layer under gate

[0094] 305-1: conductive layer over gate

[0095] 305-3: conductive layer over gate

[0096] 307-1: gate gap sub

[0097] 307-3: gate gap sub

[0098] 309-1: impurity region

[0099] 309-3: impurity region

[0100] 400A: third decoupling unit

[0101] 400P: second decoupling unit

[0102] 401: redistribution structure

[0103] 401-1: seed layer

[0104] 401-3: plating layer

[0105] 401A: array portion

[0106] 401B: lower portion

[0107] 401C: connecting portion

[0108] 401CSW-1: first curved sidewall

[0109] 401CSW-3: second curved sidewall

[0110] 401E-1: first extension portion

[0111] 401E-3: second extension portion

[0112] 401P: peripheral portion

[0113] 401SW-1: first planar sidewall

[0114] 401SW-3: second planar sidewall

[0115] 403A: intermediate isolation layer

[0116] 403P: intermediate isolation layer

[0117] 405A: upper conductive layer

[0118] 405P: upper conductive layer

[0119] 407: barrier layer

[0120] 409: adjustment layer

[0121] 601: first sacrificial oxide layer

[0122] 603: sacrificial nitride layer

[0123] 605: second sacrificial oxide layer

[0124] 607: recessed dopant source pad

[0125] 609: recessed dopant source pad

[0126] 611: first dummy layer

[0127] 613: recessed dummy layer

[0128] 615: first isolation pad

[0129] 615BS: bottom surface

[0130] 617: annular isolation pad

[0131] 617BS: bottom surface

[0132] 619: second isolation pad

[0133] 621: recessed second isolation pad

[0134] 623: first conductive material

[0135] 625: second conductive material

[0136] 627: overlying isolation pad

[0137] 629: first mask layer

[0138] 629CSW-1: first curved sidewall

[0139] 629CSW-3: second curved sidewall

[0140] 629O: mask opening

[0141] 701: first trench

[0142] 703: widened trench

[0143] AR: array region

[0144] D1: distance

[0145] D2: distance

[0146] D3: Distance

[0147] D4: Distance

[0148] PP: Surrounding area

[0149] S11: Steps

[0150] S13: Steps

[0151] S15: Steps

[0152] S17: Steps

[0153] S19: Steps

[0154] S21: Steps

[0155] S23: Steps

[0156] S25: Steps

[0157] S27: Steps

[0158] Z: Direction Detailed Implementation

[0159] The following describes specific examples of components and configurations to simplify embodiments of this disclosure. Of course, these embodiments are merely illustrative and are not intended to limit the scope of this disclosure. For example, in the description, a first component is formed on top of a second component, which may include embodiments where the first and second components are in direct contact, or embodiments where an additional component is formed between the first and second components such that the first and second components do not directly contact each other. Furthermore, reference numerals and / or letters may be repeated in many examples of embodiments of this disclosure. These repetitions are for simplicity and clarity and, unless specifically stated herein, do not in themselves represent a specific relationship between the various embodiments and / or the configurations discussed.

[0160] Furthermore, for ease of explanation, spatial relative terms such as "beneath," "below," "lower," "above," and "upper" may be used herein to describe the relationship between one element or feature shown in the figures and another element or feature. These spatial relative terms are intended to encompass different orientations of the elements in use or operation, in addition to those shown in the figures. The device may have other orientations (rotated 90 degrees or in other orientations), and the spatial relative descriptions used herein can be interpreted accordingly.

[0161] It should be understood that when a part is referred to as being on, connected to, coupled to, or part of another part, it can be directly on, connected to, coupled to, or part of the other part, or an intermediate part can be present. For example, first and second parts can be directly connected, connected through one or more intermediaries, or connected through one or more intermediaries and one or more intervening parts.

[0162] It should be understood that, although the terms first, second, third, etc. can be used herein to describe various elements, components, regions, layers and / or sections, these elements, components, regions, layers and / or sections should not be limited by these terms. Rather, these terms are only used to distinguish one element, component, region, layer or section from another region, layer or section. Thus, a first element, component, region, layer or section discussed below could be termed a second element, component, region, layer or section without departing from the teachings of the present disclosure.

[0163] Unless otherwise indicated herein, when terms such as "same," "equal," "planar," or "coplanar" are used herein, they are not necessarily intended to mean an exact, complete identical orientation, layout, location, shape, size, amount, or other measure, but rather an orientation, layout, location, shape, size, amount, or other measure that is within acceptable variation, including variation that can occur, for example, due to manufacturing processes. The term "substantially" can be used herein to convey this meaning. For example, substantially the same, substantially equal, or substantially planar can be exact, equal, or planar, or can be within acceptable variation, including variation that can occur, for example, due to manufacturing processes.

[0164] In the present disclosure, a semiconductor device generally means a device that can operate by utilizing semiconductor characteristics, and an electro-optic device, a light-emitting display device, a semiconductor circuit, and an electronic device are included in the category of semiconductor devices.

[0165] It should be understood that in the description of the present disclosure, above (or up) corresponds to the direction of the Z-direction arrow, and below (or down) corresponds to the opposite direction of the Z-direction arrow.

[0166] FIG. 1 A flowchart illustrating a method 10 of manufacturing a semiconductor device 1A according to an embodiment of the present disclosure is shown in FIG. 1. FIGS. 2-22 A cross-sectional view illustrating a part of the flow of manufacturing a semiconductor device 1A according to an embodiment of the present disclosure is shown in FIG. 2.

[0167] Referring to FIG. 1, FIGS. 1-8 In step S11, a substrate 101 can be provided, a plurality of first trenches 701 can be formed in the substrate 101, buried plates 201-1, 201-3 can be formed in the substrate 101, and a plurality of annular isolation spacers 617 can be formed on the buried plates 201-1, 201-3 and in the substrate 101.

[0168] Referring to FIG. 1, FIG. 2 The substrate 101 can include an array region AR and a peripheral region PP. In a top view (not shown), the peripheral region PP can be disposed around the array region AR. The substrate 101 can be a bulk semiconductor substrate. For example, the bulk semiconductor substrate can include an elemental semiconductor such as silicon or germanium, or a compound semiconductor such as silicon germanium, silicon carbide, gallium arsenide, gallium phosphide, indium phosphide, indium arsenide, indium antimonide, or other III-V compound semiconductor or II-VI compound semiconductor.

[0169] In some embodiments, the substrate 101 can comprise a semiconductor-on-insulator structure, which consists of, from bottom to top, a handle substrate, an insulator layer, and an uppermost semiconductor material layer. The handle substrate and the uppermost semiconductor material layer comprise the same materials as the aforementioned bulk semiconductor substrate. The insulator layer can be a crystalline or non-crystalline dielectric material, such as an oxide and / or a nitride. For example, the insulator layer can be a dielectric oxide, such as silicon oxide. As another example, the insulator layer can be a dielectric nitride, such as silicon nitride or boron nitride. As yet another example, the insulator layer can comprise a stack of a dielectric oxide and a dielectric nitride, such as a stack of silicon oxide and silicon nitride or boron nitride in any order. The insulator layer can have a thickness between about 10 nm and about 200 nm.

[0170] It should be understood that the peripheral region PP can comprise a portion of the substrate 101 and a space above the portion of the substrate 101. Describing an element disposed on the peripheral region PP means that the element is disposed on an upper surface of the portion of the substrate 101. Describing an element disposed in the peripheral region PP means that the element is disposed in the portion of the substrate 101; however, an upper surface of the element can be flush with an upper surface of the portion of the substrate 101. Describing an element disposed above the peripheral region PP means that the element is disposed above the upper surface of the portion of the substrate 101. Accordingly, the array region AR can comprise other portions of the substrate 101 and a space above the other portions of the substrate 101.

[0171] Referring to FIG. 2 A first sacrificial oxide layer 601, a sacrificial nitride layer 603, and a second sacrificial oxide layer 605 can be sequentially formed on the substrate 101. For example, the first sacrificial oxide layer 601 can comprise silicon oxide. For example, the sacrificial nitride layer 603 can comprise silicon nitride. For example, the second sacrificial oxide layer 605 can comprise silicon oxide. A lithography process and a subsequent etching process can be performed to form a plurality of first trenches 701 along the second sacrificial oxide layer 605, the sacrificial nitride layer 603, the first sacrificial oxide layer 601, and into the substrate 101. It should be understood that, for clarity, only two first trenches 701 are shown in the array region AR and the peripheral region PP, respectively. The number of the first trenches 701 in the array region AR and the peripheral region PP can be more than one.

[0172] Referring to FIG. 3A dopant source liner 607 can be conformally formed to align with an upper surface of the second sacrificial oxide layer 605 and the plurality of first trenches 701. For example, the dopant source liner 607 can include arsenic silicate glass and can function as a dopant source for forming the embedded plate 201-1, 201-3, which will be described later. A first dummy layer 611 can be formed to fill the plurality of first trenches 701 and cover the dopant source liner 607. For example, the first dummy layer 611 can include undoped polysilicon or a material having etch selectivity with respect to the dopant source liner 607.

[0173] Referring to FIG. 4 An isotropic dry etch process can be performed to recess the first dummy layer 611. After the isotropic dry etch process, the first dummy layer 611 can be converted to a plurality of recessed dummy layers 613. During the isotropic dry etch process, the etch rate ratio of the first dummy layer 611 to the dopant source liner 607 can be between about 100: 1 and about 1.05: 1, between about 15: 1 and about 2: 1, or between about 10: 1 and about 2: 1. An upper surface of each of the plurality of recessed dummy layers 613 can be located at a vertical level below an upper surface of the substrate 101.

[0174] Referring to FIG. 5 An isotropic wet etch process can be performed to recess the dopant source liner 607. After the isotropic wet etch process, the dopant source liner 607 can be converted to a plurality of recessed dopant source liners 609. During the isotropic wet etch process, the etch rate ratio of the dopant source liner 607 to the plurality of recessed dopant source liners 609 can be between about 100: 1 and about 1.05: 1, between about 15: 1 and about 2: 1, or between about 10: 1 and about 2: 1. An upper surface of each of the plurality of recessed dopant source liners 609 can be substantially coplanar with the plurality of recessed dummy layers 613.

[0175] Referring to FIG. 6A first isolation liner 615 can be conformally formed on the upper surface of the second sacrificial oxide layer 605 and in the plurality of first trenches 701. The first isolation liner 615 can cover the upper surfaces of the plurality of recessed dummy layers 613 and the upper surfaces of the plurality of recessed doped source liners 609. The portions of the plurality of first trenches 701 that are below the lower surface 615BS of the first isolation liner 615 can be denoted as lower portions of the plurality of first trenches 701. The portions of the plurality of first trenches 701 that are above the lower surface 615BS of the first isolation liner 615 can be denoted as upper portions of the plurality of first trenches 701. In some embodiments, for example, the first isolation liner 615 can include silicon oxide, silicon nitride, silicon oxynitride, nitrided silicon oxide, or the like. In some embodiments, for example, the first isolation liner 615 can include an isolation material having a dielectric constant of about 4.0 or greater. The isolation material can be hafnium oxide, zirconium oxide, aluminum oxide, titanium oxide, lanthanum oxide, strontium titanate, lanthanum aluminate, yttrium oxide, gallium(III)trioxide, gadolinium gallium oxide, lead zirconium titanate, barium strontium titanate, or mixtures thereof.

[0176] Referring to FIG. 7 An annealing process can be performed to diffuse out the plurality of recessed doped source liners 609 and form embedded plates 201-1, 201-3 in the regions surrounding the lower portions of the plurality of first trenches 701.

[0177] Referring to FIG. 8 An anisotropic dry etching process can be performed to remove the first isolation liner 615 on the upper surface of the second sacrificial oxide layer 605 and on the upper surfaces of the plurality of recessed dummy layers 613. The etch selectivity of the first isolation liner 615 to the plurality of recessed dummy layers 613 can be between about 15: 1 and about 2: 1 or between about 10: 1 and about 2: 1 during the anisotropic dry etching process. After the anisotropic dry etching process, the first isolation liner 615 can be converted to a plurality of annular isolation liners 617. The plurality of annular isolation liners 617 can align only the sidewalls of the upper portions of the plurality of first trenches 701. The upper surfaces of the plurality of recessed dummy layers 613 can be exposed.

[0178] Referring to FIG. 8An isotropic dry etching process can be performed to remove the plurality of recessed dummy layers 613. During the isotropic dry etching process, the etch rate ratio of the plurality of recessed dummy layers 613 to the plurality of annular isolation spacers 617 can be between about 15: 1 and about 2: 1 or between about 10: 1 and about 2: 1. Next, a wet etching process can be performed to remove the plurality of recessed dopant source spacers 609. During the wet etching process, the etch rate ratio of the plurality of recessed dopant source spacers 609 to the plurality of annular isolation spacers 617 can be between about 15: 1 and about 2: 1 or between about 10: 1 and about 2: 1. After the wet etching process, the sidewalls of the lower portions of the plurality of first trenches 701 can be exposed. Conversely, the sidewalls of the upper portions of the plurality of first trenches 701 can still be covered by the plurality of annular isolation spacers 617.

[0179] Referring to FIG. 1 and FIG. 9 At step S13, a wet bottle etching can be performed to convert the plurality of first trenches 701 into a plurality of widened trenches 703.

[0180] Referring to FIG. 9 The wet bottle etching process can widen the plurality of first trenches 701 to form the plurality of widened trenches 703. It should be understood that only the lower portions of the plurality of first trenches 701 are widened. Due to the coverage of the plurality of annular isolation spacers 617, the upper portions of the plurality of first trenches 701 can not be affected. During the wet bottle etching process, the etch rate ratio of the substrate 101 to the plurality of annular isolation spacers 617 can be between about 15: 1 and about 2: 1 or between about 10: 1 and about 2: 1. The portions of the plurality of widened trenches 703 that are higher than the lower surfaces 617BS of the plurality of annular isolation spacers 617 can represent the upper portions of the plurality of widened trenches 703. The portions of the plurality of widened trenches 703 that are lower than the lower surfaces 617BS of the plurality of annular isolation spacers 617 can represent the lower portions of the plurality of widened trenches 703.

[0181] Referring to FIG. 1 and FIGS. 10-20 At step S15, a first decoupling unit 200P and a storage unit 200A can be formed in the plurality of widened trenches 703.

[0182] Referring to FIG. 10A second isolation liner 619 can be conformally formed on the upper surface of the second sacrificial oxide layer 605 and in the plurality of widened trenches 703 by a deposition process, such as chemical vapor deposition or atomic layer deposition. In some embodiments, the second isolation liner 619 can comprise silicon oxide, silicon nitride, silicon oxynitride, nitrided silicon oxide, fluorine-doped silicate, or the like, for example. In some embodiments, the second isolation liner 619 can comprise an isolation material having a dielectric constant of about 4.0 or greater, for example.

[0183] Referring to FIG. 11 , a layer of first conductive material 623 is formed to fill the plurality of widened trenches 703 and cover the second isolation liner 619. In some embodiments, the first conductive material 623 can be polysilicon, doped polysilicon, polysilicon germanium, doped polysilicon germanium, the like, or combinations thereof, for example. In some embodiments, the first conductive material 623 can be a material having etch selectivity to the plurality of annular isolation liners 617 and the second isolation liner 619.

[0184] In some embodiments, the first conductive material 623 can be a material comprising a class of metal borides, metal phosphides, and metal antimonides of transition metals from Groups IV, V, and VI of the periodic table. The plurality of transition metals can be titanium, zirconium, hafnium, vanadium, niobium, tantalum, chromium, molybdenum, or tungsten. In some embodiments, the material can be titanium diboride, zirconium diboride, hafnium diboride, titanium phosphide, zirconium phosphide, hafnium phosphide, titanium antimonide, zirconium antimonide, or hafnium antimonide. The aforementioned materials can have a high thermal stability and excellent electrical conductivity, with a specific electrical resistance of less than 20 μΩcm.

[0185] In some embodiments, a conductive layer (not shown in FIG. 11 ) comprising titanium phosphide and titanium nitride can be disposed between the second isolation liner 619 and the layer of first conductive material 623 to improve the thermal stability and electrical conductivity of the layer of first conductive material 623.

[0186] Referring to FIG. 12A planarization process, such as chemical mechanical polishing, can be performed until the upper surface of the second sacrificial oxide layer 605 is exposed to remove excess material, provide a substantially planar surface for subsequent processing steps, and simultaneously convert the second spacer liners 619 to recessed second spacer liners 621. The upper surfaces of the recessed second spacer liners 621, the upper surfaces of the annular spacer liners 617, and the upper surface of the second sacrificial oxide layer 605 can be substantially coplanar.

[0187] Referring to FIG. 13 An etch back process can be performed to recess the layer of first conductive material 623. The etch rate ratio of the first conductive material 623 to the recessed second spacer liners 621 during the etch back process can be between about 15: 1 and about 2: 1, or between about 10: 1 and about 2: 1. The etch rate ratio of the first conductive material 623 to the annular spacer liners 617 during the etch back process can be between about 15: 1 and about 2: 1, or between about 10: 1 and about 2: 1.

[0188] After the etch back process, the layer of first conductive material 623 can be converted to inner conductive layers 203-1, 203-3. The inner conductive layer 203-1 can be formed in the widened trenches 703 in the peripheral region PP. The inner conductive layer 203-1 can include a lower portion 203B-1 and an annular portion 203C-1. The inner conductive layer 203-3 can be formed in the widened trenches 703 in the array region AR. The inner conductive layer 203-3 can include a lower portion 203B-3 and an annular portion 203C-3. The lower portion 203B-1 can be formed in a lower portion of the widened trenches 703 in the peripheral region PP. The annular portion 203C-1 can be formed on the lower portion 203B-1. The lower portion 203B-3 can be formed in a lower portion of the widened trenches 703 in the array region AR. The annular portion 203C-3 can be formed on the lower portion 203B-3. The upper surfaces of the annular portions 203C-1, 203C-3 can be located at a vertical level between the upper surface of the substrate 101 and the lower surfaces 617BS of the annular spacer liners 617. The widths of the lower portions 203B-1, 203B-3 can be greater than the widths of the annular portions 203C-1, 203C-3.

[0189] Referring to FIG. 14A wet etch process can be performed to remove some portions of the plurality of annular isolation spacers 617 and some portions of the plurality of recessed second isolation spacers 621. After the wet etch process, the plurality of annular isolation spacers 617 can be converted into recessed annular dielectric layers 207-1, 207-3. The plurality of recessed second isolation spacers 621 can be converted into capacitor dielectric layers 205-1, 205-3. During the wet etch process, the plurality of annular isolation spacers 617 can have an etch selectivity ratio to the ring portions 203C-1, 203C-3 of about 15: 1 to about 2: 1, or about 10: 1 to about 2: 1. During the wet etch process, the plurality of second isolation spacers 621 can have an etch selectivity ratio to the ring portions 203C-1, 203C-3 of about 15: 1 to about 2: 1, or about 10: 1 to about 2: 1.

[0190] Referring to FIG. 14 The upper surfaces of the capacitor dielectric layers 205-1, 205-3 and the upper surfaces of the recessed annular dielectric layers 207-1, 207-3 can be substantially coplanar. The upper surfaces of the ring portions 203C-1, 203C-3 can be located at a vertical level higher than the upper surfaces of the capacitor dielectric layers 205-1, 205-3 and the upper surfaces of the recessed annular dielectric layers 207-1, 207-3. The capacitor dielectric layers 205-1, 205-3 can prevent leakage current from occurring between the buried plates 201-1, 201-3 and the contact portions 213-1, 213-3 to be described later.

[0191] Referring to FIG. 15 A layer of second conductive material 625 can be formed to fill the upper portions of the plurality of widened trenches 703 and cover the upper surfaces of the second sacrificial oxide layers 605. Next, a planarization process, such as chemical mechanical polishing, can be performed until the upper surfaces of the sacrificial nitride layers 603 are exposed to remove excess material and provide a substantially planar surface for subsequent processing steps. The second conductive material 625 is doped polysilicon, doped polysilicon germanium, or the like.

[0192] Referring to FIG. 16 A non-isotropic etch process can be performed to recess the layer of second conductive material 625. After the non-isotropic etch process, the layer of second conductive material 625 is converted into strip-shaped conductive layers 209-1, 209-3. The upper surfaces of the strip-shaped conductive layers 209-1, 209-3 can be located at a vertical level lower than the upper surface of the substrate 101.

[0193] Referring to FIG. 17A conformal covering isolation liner 627 can be formed conformally on the upper surface of the sacrificial nitride layer 603 and in the upper portions of the plurality of widened trenches 703. The thickness of the covering isolation liner 627 can be greater than a vertical gap between the upper surface of the substrate 101 and the upper surfaces of the band-like conductive layers 209-1, 209-3. In some embodiments, the covering isolation liner 627 can include silicon oxide, silicon nitride, silicon oxynitride, silicon nitride oxide, a high dielectric constant dielectric material, or a combination thereof, for example. The high dielectric constant dielectric material can be hafnium oxide, hafnium silicon oxide, lanthanum oxide, zirconium oxide, zirconium silicon oxide, tantalum oxide, titanium oxide, barium strontium titanium oxide, barium titanium oxide, strontium titanium oxide, lithium oxide, aluminum oxide, lead scandium tantalum oxide, lead zinc niobate, or a combination thereof.

[0194] Referring to FIG. 18 A planarization process, such as chemical mechanical polishing, can be performed until the upper surface of the substrate 101 is exposed to remove excess material, provide a substantially planar surface for subsequent processing steps, and simultaneously convert the covering isolation liner 627 into the covering isolation layers 211-1, 211-3. The upper surfaces of the covering isolation layers 211-1, 211-3 can be substantially coplanar with the upper surface of the substrate 101.

[0195] Referring to FIG. 9 The insulating layer 103 can be formed in the substrate 101. The fabrication techniques of the substrate 101 can include removing portions of the covering isolation layers 211-1 and 211-3, portions of the band-like conductive layers 209-1 and 209-3, and portions of the ring portions 203C-1 and 203C-3. During subsequent semiconductor processing, the insulating layer 103 can prevent the band-like conductive layers 209-1, 209-3 or the ring portions 203C-1, 203C-3 from diffusing toward adjacent regions that can affect the reliability of the semiconductor device 1A.

[0196] Referring to FIG. 20 The dopants in the band-like conductive layers 209-1, 209-3 can be diffused via an annealing process to form the interface portions 213-1 and 213-3. In some embodiments, the interface portions 213-1 and 213-3, the band-like conductive layers 209-1 and 209-3, the ring portions 203C-1 and 203C-3, and the lower portions 203B-1 and 203B-3 can have the same conductivity type.

[0197] The buried plate 201-1, the inner conductive layer 203-1, the capacitor dielectric layer 205-1, the recessed ring dielectric layer 207-1, the strip conductive layer 209-1, the covering isolation layer 211-1, and the interface portion 213-1 are configured together as a first decoupling unit 200P in the peripheral region PP. The buried plate 201-3, the inner conductive layer 203-3, the capacitor dielectric layer 205-3, the recessed ring dielectric layer 207-3, the strip conductive layer 209-3, the covering isolation layer 211-3, and the interface portion 213-3 are configured together as a memory unit 200A in the array region AR. The first decoupling unit 200A and the memory unit 200P can be a plurality of trench capacitors. For clarity, only one first decoupling unit 200P and one memory unit 200P are shown in the peripheral region PP and the array region AR, respectively. The number of memory units 200A in the array region AR and the number of first decoupling units 200P in the peripheral region PP can be greater than one.

[0198] Generally, when the transition time of a transient current is particularly short, or when the parasitic inductance or the parasitic resistance of a power supply line is large, a voltage on the power supply line can fluctuate. To improve this situation, the first decoupling unit 200P can serve as a temporary charge reservoir to avoid momentary fluctuations in the supply voltage. In addition, the first decoupling unit 200P is formed in the substrate 101 to free up the surface of the substrate for more logic elements.

[0199] Referring to FIG. 1 and FIG. 21 In step S17, a first switching unit 300P and a second switching unit 300A can be formed on the substrate 101.

[0200] Referring to FIG. 21 The first switching unit 300P can be formed on the peripheral region PP of the substrate 101 and can be electrically coupled to the first decoupling unit 200P via the interface portion 213-1. The second switching unit 300A can be formed on the array region AR of the substrate 101 and can be electrically coupled to the memory unit 200A via the interface portion 213-3. The first switching unit 300P and the second switching unit 300A can include a gate dielectric layer 301-1 and 301-3, a lower gate conductive layer 303-1 and 303-3, an upper gate conductive layer 305-1 and 305-3, a gate gap sub-layer 307-1 and 307-3, and an impurity region 309-1 and 309-3.

[0201] Please refer to FIG. 21 Gate dielectric layers 301-1 and 301-3 may be formed on the peripheral region PP and the array region AR of the substrate 101, respectively. For example, gate dielectric layers 301-1 and 301-3 may comprise silicon oxide, silicon nitride, silicon oxynitride, silicon oxynitride, or an isolation material having a dielectric constant of approximately 4.0 or greater.

[0202] Please refer to FIG. 21 The gate conductive layers 303-1 and 303-3 may be formed on the gate dielectric layers 301-1 and 301-3. For example, the gate conductive layers 303-1 and 303-3 may comprise polysilicon, doped polysilicon, polysilicon germanium, doped polysilicon germanium, the like, or combinations thereof.

[0203] Please refer to FIG. 21 The gate conductive layers 305-1 and 305-3 may be formed on the gate conductive layers 303-1 and 303-3. For example, the gate conductive layers 305-1 and 305-3 may comprise titanium silicide, nickel silicide, nickel platinum silicide, tantalum silicide, or cobalt silicide.

[0204] Please refer to FIG. 21 Gate spacers 307-1 and 307-3 may be formed on the sidewalls of the upper gate conductive layers 305-1 and 305-3, on the sidewalls of the lower gate conductive layers 303-1 and 303-3, and on the sidewalls of the gate dielectric layers 301-1 and 301-3. For example, gate spacers 307-1 and 307-3 may comprise silicon oxide, silicon nitride, or the like.

[0205] Please refer to FIG. 21 The plurality of impurity regions 309-1 may be formed on both sides adjacent to the gate dielectric layer 301-1 and in the surrounding region PP of the substrate 101. One of the impurity regions 309-1 may be electrically connected to the connector 213-1. The plurality of impurity regions 309-3 may be formed on both sides adjacent to the gate dielectric layer 301-3 and in the array region AR of the substrate 101. One of the impurity regions 309-3 may be electrically connected to the connector 213-3. The impurity regions 309-1 and 309-3 may be doped with a dopant, such as phosphorus, arsenic, antimony, or boron. The plurality of impurity regions 309-1 and 309-3 may have the same conductivity type as the plurality of connectors 213-1 and 213-3.

[0206] In some embodiments, by changing the voltage applied to the conductive layer 305-1 on the gate, the first switching unit 300P can be used to control an operating state (e.g., On or Off) of the first decoupling unit 200P. By changing the voltage applied to the conductive layer 305-3 on the gate, the second switching unit 300A can be used to control an operating state (e.g., On or Off) of the memory unit 200A.

[0207] FIG. 23 A top view schematic diagram illustrating an intermediate semiconductor element according to an embodiment of the present disclosure. FIG. 24 An embodiment of this disclosure is illustrated along the edge FIG. 23 A cross-sectional view of section line A-A'.

[0208] Please refer to FIG. 1 and FIGS. 22-24 In step S19, pads 109A and 109P may be formed on substrate 101, an upper passivation layer 111 may be formed on pads 109A and 109P, and a plurality of upper passivation layer openings 111O may be formed to expose pads 109A and 109P.

[0209] Please refer to FIG. 22 An inner connection layer 105 may be formed on the substrate 101 and may cover the first switching unit 300P and the second switching unit 300A. The inner connection layer 105 may include a plurality of dielectrics, a plurality of isolation layers, and a plurality of conductive features. For example, the plurality of dielectrics or the plurality of isolation layers may include a semiconductor oxide, a semiconductor nitride, a semiconductor oxynitride, a semiconductor carbide, a tetraethyl orthosilicate oxide, a phosphosilicate glass, a borophosphosilicate glass, a fluorinated silicate glass, carbon-doped silicon oxide, amorphous fluorinated carbon, or a combination thereof. The plurality of conductive features may be a plurality of conductive lines, a plurality of conductive vias, or the like. The plurality of dielectrics or the plurality of isolation layers may act as an insulator, supporting and electrically insulating the plurality of conductive features.

[0210] Please refer to FIG. 22A lower passivation layer 107 can be formed on the inner connection layer 105. In some embodiments, for example, the lower passivation layer 107 can include silicon oxide or phosphosilicate glass. The lower passivation layer 107 can act as a stress buffer between the inner connection layer 105 and an upper passivation layer 111, which will be described later. In some embodiments, for example, the lower passivation layer 107 can include silicon oxide, silicon nitride, silicon oxynitride, silicon oxynitride, polyimide, polybenzoxazole, phosphosilicate glass, undoped silica glass, or fluoride silicate glass. A plurality of lower passivation layer openings 107O can be formed along the lower passivation layer 107 to expose some portions of the upper surface of the inner connection layer 105.

[0211] In some embodiments, a cleaning process and a passivation process can be performed on the plurality of lower passivation layer openings 107O. The cleaning process can remove oxides from the upper surface of the uppermost conductive feature of the inner connection layer 105 without damaging it, which results from oxidation by oxygen in air. The cleaning process can include applying a mixture of hydrogen and argon as a remote plasma source to the plurality of lower passivation layer openings 107O. A process temperature of the cleaning process can be between about 250 °C and about 350 °C. A process pressure of the cleaning process can be between about 1 Torr and about 10 Torr. A bias energy can be applied to the apparatus performing the cleaning process. The bias energy can be between about 0 W and about 200 W.

[0212] The passivation process can include soaking the intermediate semiconductor element with a precursor, such as dimethylaminotrimethylsilane, tetramethylsilane, or the like, at a process temperature between about 200 °C and about 400 °C. An ultraviolet radiation can be used to facilitate the passivation process. The passivation process can passivate the lower passivation layer 107 by sealing surface pores of the lower passivation layer 107 and passivating the sidewalls of the lower passivation layer 107 exposed via the plurality of lower passivation layer openings 107O. The passivation process can reduce unintended sidewall growth, which can affect the electrical properties of the semiconductor element 1A. As a result, the performance and reliability of the semiconductor element 1A can be improved.

[0213] Please refer to FIG. 23 and FIG. 24In some embodiments, the pad layer 109P can be electrically coupled to the first decoupling unit 200P via the plurality of conductive features of the inner connection layer 105 and the first switching unit 300P. The pad layer 109A can be formed in the lower passivation layer openings 107O located on the array region AR of the substrate 101. In some embodiments, the pad layer 109A can be electrically coupled to the memory unit 200A via the plurality of conductive features of the inner connection layer 105 and the second switching unit 300A. In some embodiments, the pad layers 109A, 109P can be stack layers including a plurality of lower layers and a plurality of upper layers. The plurality of lower layers can be formed on the inner connection layer 105 and can include nickel. The plurality of upper layers can be formed on the plurality of lower layers and can include palladium, cobalt, or a combination thereof.

[0214] Referring to FIG. 23 and FIG. 24 The upper passivation layer 111 can be formed on the lower passivation layer 107. The plurality of upper passivation layer openings 111O can be formed along the upper passivation layer 111 by a lithography process and a continued etching process. Some portions of the upper surface of the pad layers 109A, 109P can be exposed via the plurality of upper passivation layer openings 111O. In some embodiments, the plurality of upper passivation layer openings 111O can include a plurality of tapered sidewalls 111SW. In some embodiments, each tapered sidewall 111SW can extend from a lower edge 111BE of the plurality of upper passivation layer openings 111O to an upper edge 111TE of the plurality of upper passivation layer openings 111O in a cross-sectional view. In a top view, each lower edge 111BE of the plurality of upper passivation layer openings 111O can have a rectangular shape, and each upper edge 111TE of the plurality of upper passivation layer openings 111O can also have a rectangular shape. Each lower edge 111BE of the plurality of upper passivation layer openings 111O can define an exposed area of the upper surface of the pad layers 109A, 109P.

[0215] FIG. 25 A top view schematic diagram of an intermediate semiconductor element illustrating an embodiment of the present disclosure. FIG. 26 A cross-sectional view schematic diagram of the intermediate semiconductor element along a cross-sectional line A-A’ illustrating an embodiment of the present disclosure. FIG. 25 A cross-sectional view schematic diagram of the intermediate semiconductor element along a cross-sectional line A-A’ illustrating an embodiment of the present disclosure.

[0216] Referring to FIG. 1 and FIG. 25 and FIG. 26 At step S21, a pad dielectric layer 113 can be formed on the upper passivation layer 111 to expose the pad layers 109A, 109P.

[0217] Referring to FIG. 25 and FIG. 26The pad dielectric layer 113 may be conformally formed on the upper passivation layer 111 to expose the exposed upper surfaces of the pads 109A and 109P. The pad dielectric layer 113 may conformally cover the plurality of tapered sidewalls 111SW to form corresponding tapered sidewalls 113SW. The lower edges 113BE of the pad dielectric layer 113 may extend to cover the lower edges 111E of the plurality of upper passivation layer openings 111O and contact the edges of the plurality of exposed upper surfaces of the pads 109A and 109P. In some embodiments, the pad dielectric layer 113 may be formed to include a photosensitive polymer material, such as a polyimide material. In some embodiments, for example, the pad dielectric layer 113 may comprise silicon oxide, silicon nitride, silicon nitride carbon, silicon nitride oxide, or silicon oxynitride. The pad dielectric layer 113 can provide additional electrical insulation or isolation to the plurality of conductive features beneath it and the plurality of conductive features above it.

[0218] FIG. 27 A top view schematic diagram illustrating an intermediate semiconductor element according to an embodiment of the present disclosure. FIG. 28 An embodiment of this disclosure is illustrated along the edge FIG. 27 A cross-sectional view of section line A-A'. FIG. 29 An embodiment of this disclosure is illustrated along the edge FIG. 27 A sectional view along section line B-B'. For clarity, in... FIG. 29 Some components are omitted.

[0219] Please refer to FIG. 1 and FIGS. 27-29 In step S23, a first mask layer 629 may be formed on the pad dielectric layer 113, and a mask opening 629O may be formed along the first mask layer 629.

[0220] Please refer to FIGS. 27-29 The first mask layer 629 may be a photoresist layer. The mask opening 629O may define a pattern of a redistribution structure 401, which will be described in detail later. In a top view, the mask opening 629O may have a dumbbell shape.

[0221] Please refer to FIGS. 27-29 In the top view, each end of the masking opening 509O may include a horizontally disposed first curved sidewall 629CSW-1 and a second curved sidewall 629CSW-3. The first curved sidewall 629CSW-1 may have a convex shape. The second curved sidewall 629CSW-3 may have a concave shape. The vertical distance between the first curved sidewall 629CSW-1 and the second curved sidewall 629CSW-3, parallel to the Y direction, may vary between a relatively narrow distance D1 and a relatively wide distance D2 along the X direction, which is perpendicular to the Y direction.

[0222] The portions of the mask openings 629O having a relatively narrow distance Dl can provide additional structural support to the first mask layer 629 to prevent collapse or deformation. Conversely, the portions of the mask openings 629O having a relatively wide distance D2 can have a lower resistance to collapse or deformation. That is, the portions of the mask openings 629O having a relatively wide distance D2 can be relatively weak. However, the aforementioned structural support can compensate for the relatively weak portions, which can inhibit or reduce collapse or deformation of the first mask layer 629. That is, the first mask layer 629 and the mask openings 629O can be a stable structure even though some portions of the mask openings 629O are located on the tapered sidewalls 113SW of the pad dielectric layer 113 as shown. FIG. 29

[0223] FIG. 30 A top view schematic diagram of an intermediate semiconductor element according to an embodiment of the present disclosure is shown. FIG. 31 A cross-sectional view schematic diagram of the intermediate semiconductor element along the cross-sectional line A-A’ according to an embodiment of the present disclosure is shown. FIG. 30 A cross-sectional view schematic diagram of the intermediate semiconductor element along the cross-sectional line B-B’ according to an embodiment of the present disclosure is shown. For clarity, some elements are omitted in the following figures. FIG. 32 A cross-sectional view schematic diagram of the intermediate semiconductor element along the cross-sectional line B-B’ according to an embodiment of the present disclosure is shown. For clarity, some elements are omitted in the following figures. FIG. 30 A cross-sectional view schematic diagram of the intermediate semiconductor element along the cross-sectional line B-B’ according to an embodiment of the present disclosure is shown. For clarity, some elements are omitted in the following figures. FIG. 32 A cross-sectional view schematic diagram of the intermediate semiconductor element along the cross-sectional line B-B’ according to an embodiment of the present disclosure is shown. For clarity, some elements are omitted in the following figures.

[0224] Referring to FIG. 1 and FIGS. 30-32 At step S25, the redistribution structure 401 can be formed in the mask openings 629O.

[0225] Referring to FIGS. 30-32 , the redistribution structure 401 can be formed in the mask openings 629O and electrically coupled to the pad layers 109A, 109P. After the redistribution structure 401 is formed, the first mask layer 629 can be removed. For example, the redistribution structure 401 can include tungsten, titanium, tin, nickel, copper, gold, aluminum, platinum, cobalt, or a combination thereof. In a top view, the redistribution structure 401 can be a conductive pattern extending from the array region AR to the peripheral region PP. In some embodiments, the redistribution structure 401 can include a peripheral portion 401P, a connection portion 401C, and an array portion 401A. The peripheral portion 401P can be formed on the peripheral region PP of the substrate 101. The array portion 401A can be formed on the array region AR of the substrate 101. The connection portion 401C can connect the peripheral portion 401P and the array portion 401A.

[0226] Referring to FIGS. 30-32 ​In the top view, the peripheral portion 401P can include a first curved sidewall 401CSW-1, a second curved sidewall 401CSW-3, a first flat sidewall 401SW-1, and a second flat sidewall 401SW-3. The first curved sidewall 401CSW-1 can be horizontally disposed and can have a convex shape. The second curved sidewall 401CSW-3 can be disposed opposite the first curved sidewall 401CSW-1 and can have a concave shape. A vertical distance between the first curved sidewall 401CSW-1 and the second curved sidewall 401CSW-3, parallel to the direction Y, can vary between a relatively narrow distance D3 and a relatively wide distance D4 along the direction X. The first flat sidewall 401SW-1 can connect a first edge of the first curved sidewall 401CSW-1 to a first edge of the second curved sidewall 401CSW-3. The second flat sidewall 401SW-3 can connect a second edge of the first curved sidewall 401CSW-1 to a second edge of the second curved sidewall 401SW-3. The first flat sidewall 401SW-1 and the second flat sidewall 401SW-3 can be parallel to the direction Y. The connection portion 401C can be connected to the second flat sidewall 401SW-3.

[0227] Referring to FIGS. 30-32 In the cross-sectional view, the first curved sidewall 401CSW-1 can be located at an overlap with the plurality of tapered sidewalls 113SW between the upper edge 111TE and the lower edge 111BE. Although a majority of the first curved sidewall 401CSW-1 is formed to overlap the plurality of tapered sidewalls 113SW, both the first edge and the second edge of the first curved sidewall 401SW-1 can be located outside the upper edge 111TE to overlap the flat upper surface of the pad dielectric layer 113.

[0228] Referring to FIG. 31 The peripheral portion 401P can include a first extension portion 401E-1 extending from a lower portion 401B of the peripheral portion 401P to the first flat sidewall 401SW-1. The first extension portion 401E-1 can extend onto an outer side region of the plurality of tapered sidewalls 113SW to overlap the flat upper surface of the pad dielectric layer 113. The lower portion 401B can be a portion of the peripheral portion 401P directly contacting the pad layer 109P.

[0229] Referring to FIG. 32 In the cross-sectional view, the peripheral portion 401P can include a second extension portion 401E-3 extending from the lower portion 401B of the peripheral portion 401P to the first curved sidewall 401CSW-1.

[0230] Referring to FIGS. 30-32Both the first extension 401E-1 and the second extension 401E-3 can cover the lower edge 113BE and the lower edge 111BE. Therefore, even if the surrounding portion 401P shifts from its normal position due to a process variation or the like, the pad 109P can still be covered by the surrounding portion 401P. That is, an overlap boundary between the surrounding portion 401P and the pad 109P can be increased to significantly suppress or reduce the failure of the pad 109P being exposed after the formation of the surrounding portion 401P. It should be understood that the array portion 401A may have a structure similar to that of the surrounding portion 401P.

[0231] FIG. 33 This illustration shows a portion of the process for fabricating a semiconductor device 1A according to an embodiment of the present disclosure. FIG. 30 A cross-sectional view of section line A-A'.

[0232] Please refer to FIG. 1 and FIG. 33 In step S27, an intermediate isolation layer 403P may be formed on the redistribution structure 401, and an upper conductive layer 405P may be formed on the intermediate isolation layer 403P.

[0233] Please refer to FIG. 33 An intermediate isolation layer 403P may be formed on the periphery 401P of the redistribution structure 401. The intermediate isolation layer 403P may have a thickness between approximately 5 nm and approximately 100 nm. For example, the intermediate isolation layer 403P may comprise silicon oxide, silicon nitride, silicon oxynitride, silicon nitride oxide, hafnium oxide, hafnium silicon oxide, hafnium silicon oxynitride, lanthanum oxide, lanthanum aluminum oxide, zirconium oxide, zirconium silicon oxide, zirconium silicon oxynitride, aluminum oxide, or combinations thereof.

[0234] Please refer to FIG. 33 The upper conductive layer 405P may be formed on the intermediate insulating layer 403P. The width of the upper conductive layer 405P may be equal to the width of the intermediate insulating layer 403P. In some embodiments, for example, the upper conductive layer 405P may comprise silicon, germanium, doped silicon, doped silicon-germanium, tungsten, cobalt, zirconium, tantalum, titanium, aluminum, ruthenium, copper, metal carbides (e.g., tantalum carbide, titanium carbide, magnesium tantalum carbide), metal nitrides (e.g., titanium nitride), transition metal aluminum nitrides, or combinations thereof.

[0235] Please refer to FIG. 33The redistribution structure 401, the intermediate isolation layer 403P, and the upper conductive layer 405P together form a second decoupling unit 400P. In some embodiments, the peripheral portion 401P of the redistribution structure 401, the intermediate isolation layer 403P, and the upper conductive layer 405P together form the second decoupling unit 400P. In some embodiments, the second decoupling unit 400P can be electrically coupled to the first switching unit 300P via the pad layer 109P and the plurality of conductive features of the inner connection layer 105. In some embodiments, the second decoupling unit 400P can be electrically coupled to the first decoupling unit 200P via the pad layer 109P, the plurality of conductive features of the inner connection layer 105, and the first switching unit 300P. The second decoupling unit 400P can be used as a temporary charge reservoir to avoid momentary fluctuations under voltage conditions. Therefore, the reliability of the semiconductor device 1A can be improved.

[0236] FIGS. 34-38 A cross-sectional schematic diagram illustrating a process for fabricating semiconductor devices 1B, 1C, 1D, 1E, and 1F according to some embodiments of this disclosure.

[0237] Please refer to FIG. 34 Semiconductor element 1B may have similar characteristics to, for example... FIG. 33 A structure. In FIG. 34 The same or similar FIG. 33 The components in the document have been identified with similar component numbers, and their redundant descriptions have been omitted.

[0238] Please refer to FIG. 34 The redistribution structure 401 may be a stacked layer, including a seed layer 401-1 and a plating layer 401-3. The seed layer 401-1 may be conformally disposed on the pad layers 109A and 109P and on the pad dielectric layer 113. The plating layer 401-3 may be disposed on the seed layer 401-1. For example, the plating layer 401-3 may contain tungsten, titanium, tin, nickel, copper, gold, aluminum, platinum, cobalt, or combinations thereof.

[0239] Please refer to FIG. 35 Semiconductor element 1C may have similar characteristics to, for example FIG. 33 A structure. In FIG. 35 The same or similar FIG. 33 The components in the document have been identified with similar component numbers, and their redundant descriptions have been omitted.

[0240] Please refer to FIG. 35A heat release layer 115 may be formed on the redistribution structure 401. In some embodiments, the heat release layer 115 may be formed on the array portion 401A of the redistribution structure 401. The heat release layer 115 may comprise a carbon material filled with a flexible material, such as a polymer matrix. For example, the heat release layer 115 may comprise graphite, typically vertically oriented, and a plurality of carbon nanotubes filled with a fluoropolymer rubber matrix. The aspect ratio of the plurality of carbon nanotubes may be between approximately 1:1 and approximately 1:100. As another example, the heat release layer 115 may comprise graphitic carbon.

[0241] In some embodiments, with a thickness between approximately 250 and approximately 450, the thermal resistance of the heat release layer 115 can be less than 0.2 °C / cm. 2 / Watt. In some embodiments, the thermal resistance of the heat release layer 115 may be between approximately 0.04°C / cm. 2 / Watt to approximately 0.25℃cm 2 Between / Watt. The heat release layer 115 can improve the heat dissipation capability of the redistribution structure 401. In some embodiments, the heat release layer 115 may be formed on the upper conductive layer 405P and may provide heat dissipation capability for the second decoupling unit 400P.

[0242] Please refer to FIG. 36 Semiconductor element 1D can have similar characteristics to, for example... FIG. 33 A structure. In FIG. 36 The same or similar FIG. 33 The components in the document have been identified with similar component numbers, and their redundant descriptions have been omitted.

[0243] Please refer to FIG. 36 Multiple upper spacers 117 may be formed on the sidewalls of the upper conductive layer 405P, the sidewalls of the intermediate insulating layer 403P, and the sidewalls of the redistribution structure 401. For example, the multiple upper spacers 117 may comprise silicon oxide, silicon nitride, silicon nitride carbon, silicon nitride oxide, or silicon oxynitride. The multiple upper spacers 117 may provide additional electrical insulation or isolation between the redistribution structure 401 and the second decoupling unit 400P.

[0244] Please refer to FIG. 37 Semiconductor element 1E may have similar characteristics to, for example FIG. 33 A structure. In FIG. 37 The same or similar FIG. 33 The components in the document have been identified with similar component numbers, and their redundant descriptions have been omitted.

[0245] Please refer toFIG. 37 An intermediate isolation layer 403A can be formed on the array portion 401 A of the redistribution structure 401. An upper conductive layer 405A can be formed on the intermediate isolation layer 403A. The intermediate isolation layer 403A can comprise the same material as the intermediate isolation layer 403P. The upper conductive layer 405A can comprise the same material as the upper conductive layer 405P. The array portion 401 A of the redistribution structure 401, the intermediate isolation layer 403A, and the upper conductive layer 405A together form a third decoupling unit 400A. The third decoupling unit 400A can act as temporary charge reservoirs to avoid momentary fluctuation under a supply voltage condition. Thus, the reliability of the semiconductor device 1E can be improved.

[0246] Referring to FIG. 38 , the semiconductor device 1F can have a structure similar to that of the semiconductor device 1E as shown in FIG. 1E. Elements in FIG. 1F that are the same as or similar to those in FIG. 1E are designated by like reference numbers, and repetitive description thereof is omitted. FIG. 33 FIG. 38 FIG. 33

[0247] Referring to FIG. 38 , a barrier layer 407 can be formed between the pad dielectric layer 113 and the redistribution structure 401, and between the redistribution structure 401 and the pad layer 109A, 109P. In some embodiments, the barrier layer 407 can have a thickness between about 1 A and about 1000 A. For example, the barrier layer 407 can comprise titanium, titanium nitride, titanium silicon nitride, tantalum, tantalum nitride, tantalum silicon nitride, or a combination thereof. The barrier layer 407 can act as an adhesion layer between the pad layer 109A, 109P and the redistribution structure 401.

[0248] Referring to FIG. 38 , an adjustment layer 409 can be formed between the barrier layer 407 and the redistribution structure 401. In some embodiments, for example, the adjustment layer 409 can comprise graphene, graphite, or the like. In some embodiments, for example, the adjustment layer 409 can comprise graphene. When the adjustment layer 409 comprising graphene has an excellent electrical conductivity, the electrical resistance between the redistribution structure 401 and the pad layer 109A, 109P can be reduced. Thus, the power loss for the semiconductor device 1F can be reduced.

[0249] ​​​​​One embodiment of this disclosure provides a semiconductor device having a substrate including an array region and a surrounding region disposed adjacent to the array region; a first decoupling unit located in the surrounding region of the substrate; a memory cell located in the array region of the substrate; a redistribution structure located on the surrounding region and the array region of the substrate; an intermediate isolation layer located on the redistribution structure on the surrounding region; and an upper conductive layer located on the intermediate isolation layer. The redistribution structure located on the surrounding region, the intermediate isolation layer, and the upper conductive layer are together configured as a second decoupling unit.

[0250] Another embodiment of this disclosure provides a method for fabricating a semiconductor device, including providing a substrate, the substrate including an array region and a surrounding region, the surrounding region being disposed adjacent to the array region; simultaneously forming a first decoupling unit in the surrounding region of the substrate and a memory unit in the array region of the substrate; forming a redistribution structure on the surrounding region of the substrate and on the array region of the substrate; forming an intermediate isolation layer on the redistribution structure, the redistribution structure being formed on the surrounding region of the substrate; and forming an upper conductive layer on the intermediate isolation layer. The redistribution structure formed on the surrounding region, the intermediate isolation layer, and the upper conductive layer are together configured as a second decoupling unit.

[0251] Due to the design of the semiconductor device disclosed herein, the first decoupling unit 200P and the second decoupling unit 400P can be used as temporary charge reservoirs to avoid momentary fluctuations under voltage conditions. Therefore, the reliability of the semiconductor device 1A can be improved.

[0252] While this disclosure and its advantages have been described in detail, it should be understood that various changes, substitutions, and alternatives can be made without departing from the concept and scope of this disclosure as defined in the claims. For example, many of the processes described above can be implemented using different methods, and other processes or combinations thereof can be substituted for many of the processes described above.

[0253] Furthermore, the scope of this disclosure is not limited to the specific embodiments of the processes, machinery, manufacturing, material compositions, means, methods, and steps described in the specification. Those skilled in the art will understand from the content of this disclosure that existing or future processes, machinery, manufacturing, material compositions, means, methods, or steps that have the same function or achieve substantially the same results as the corresponding embodiments described herein can be used based on this disclosure. Accordingly, such processes, machinery, manufacturing, material compositions, means, methods, or steps are included within the scope of the claims of this disclosure.

Claims

1. A semiconductor element, comprising: A substrate includes an array region and a surrounding region disposed adjacent to the array region; A first decoupling unit is located in the surrounding region of the substrate; A storage cell located in the array region of the substrate; A redistributed structure is located on the surrounding region and the array region of the substrate; An intermediate isolation layer is located on the redistribution structure in the surrounding area; as well as A conductive layer is located on the intermediate isolation layer; The redistribution structure, the intermediate isolation layer, and the upper conductive layer in the surrounding area are configured together as a second decoupling unit.

2. The semiconductor device of claim 1, wherein the first decoupling unit and the storage unit are a plurality of trench capacitors.

3. The semiconductor device of claim 1, wherein the first decoupling unit includes an inner conductive layer located in the substrate; a buried plate disposed around a lower portion of the inner conductive layer; a capacitor dielectric layer located between the lower portion of the inner conductive layer and the buried plate; a strip conductive layer located on the inner conductive layer; a covering isolation layer located on the strip conductive layer; and a connector located adjacent to the strip conductive layer.

4. The semiconductor device of claim 3, wherein the inner conductive layer comprises a lower portion and a ring portion, the lower portion being surrounded by the embedded plate, the ring portion being located on the lower portion, and the strip conductive layer being located on the ring portion.

5. The semiconductor device of claim 4, wherein the junction portion and the strip conductive layer have the same conductivity type.

6. The semiconductor device of claim 5 further includes a recessed annular dielectric layer disposed around a lower portion of the annular portion of the inner conductive layer.

7. The semiconductor device of claim 6, wherein the recessed annular dielectric layer comprises silicon oxide, silicon nitride, or silicon oxynitride.

8. The semiconductor device of claim 7, further comprising a first switching unit located on the surrounding area of ​​the substrate and adjacent to the junction of the first decoupling unit, wherein, The first switching unit and the first decoupling unit are electrically coupled.

9. The semiconductor device of claim 8, wherein the thickness of the intermediate isolation layer is between 5 nm and 100 nm.

10. The semiconductor device of claim 9, wherein the intermediate isolation layer comprises silicon oxide, silicon nitride, silicon oxynitride, hafnium oxide, hafnium silicon oxide, hafnium silicon oxynitride, lanthanum oxide, aluminum lanthanum oxide, zirconium oxide, zirconium silicon oxide, zirconium silicon oxynitride, aluminum oxide, or a combination thereof.

11. The semiconductor device of claim 10, further comprising a pad layer located under the redistribution structure and electrically connected to the redistribution structure.

12. The semiconductor device of claim 10, wherein the redistribution structure includes a seed layer and a plating layer, the seed layer being located on the surrounding region and the array region, and the plating layer being located on the seed layer.

13. The semiconductor device of claim 11, further comprising a barrier layer located between the pad layer and the redistribution structure, wherein, The barrier layer comprises titanium, titanium nitride, titanium silicon nitride, tantalum, tantalum nitride, tantalum silicon nitride, or a combination thereof.

14. The semiconductor device of claim 13, wherein the thickness of the barrier layer is between arrive between.

15. The semiconductor device of claim 14, further comprising an adjustment layer located between the barrier layer and the redistribution structure, wherein, The adjustment layer contains graphene or graphite.

16. The semiconductor device of claim 10, wherein the redistribution structure includes a peripheral region, an array region, and a connection region, the peripheral region being located on the peripheral region, the array region being located on the array region, the connection region connecting the peripheral region and the array region, and the intermediate isolation layer being located on the peripheral region.

17. The semiconductor device of claim 16, further comprising a heat-relieving layer located on the array portion of the redistribution structure, wherein, The heat release layer is configured to maintain a thermal resistance between 0.04 °C / cm². 2 / Watt to 0.25℃cm 2 Between / Watt.

18. The semiconductor device of claim 17, wherein the heat release layer comprises an organic material, the organic material being porously mixed with a plurality of carbon nanotubes.

19. A method for fabricating a semiconductor element, comprising: A substrate is provided, the substrate including an array region and a surrounding region disposed adjacent to the array region; Simultaneously, a first decoupling unit is formed in the surrounding area of ​​the substrate and a storage unit is formed in the array area of ​​the substrate; A redistributed structure is formed on the surrounding area of ​​the substrate and on the array area of ​​the substrate; An intermediate isolation layer is formed on the redistribution structure in the surrounding area; as well as A conductive layer is formed on the intermediate insulating layer; The redistribution structure, the intermediate isolation layer, and the upper conductive layer formed on the surrounding area are configured together as a second decoupling unit.

20. The method for fabricating a semiconductor element as claimed in claim 19, wherein the first decoupling unit and the storage unit are a plurality of trench capacitors.

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