Semiconductor Package

Abstract

A semiconductor package includes a flexible carrier, a first chip, a second chip, a first mold sealing layer, a first adhesive layer and a second mold sealing layer. The flexible carrier includes a flexible folding layer having a patterned build-up layer circuit and being soft, and a rigid layer combined on a portion of the surface of the flexible folding layer. The portion of the flexible folding layer combined with the rigid layer forms a first bearing portion and a second bearing portion, and the portion of the flexible folding layer between the first bearing portion and the second bearing portion where the rigid layer is not combined forms a first flexible folding portion. The first chip is flip-chip bonded to the first bearing portion, and the second chip is flip-chip bonded to the second bearing portion. The first mold sealing layer covers the first chip, and the second mold sealing layer covers the second chip. The first adhesive layer combines the first mold sealing layer and the second bearing portion.

Description

Technical Field

[0001] The invention relates to a semiconductor package, and in particular to a package structure of a system integrated package. Background Art

[0002] Technology is changing with each passing day, and semiconductor chips have been widely used in daily life. With the evolution of semiconductor processes and packaging technology, the size of chips has been gradually reduced, and a system consisting of multiple chips or other components can be integrated into a single package, which is called "system in package" (SIP). Among the various system integration packages in the prior art, there are packaging structures of different states, such as: two-dimensional (2-dimension, 2D) packaging structure, two and a half dimensional (2.5-dimension, 2.5D) packaging structure, stacked (package on package, POP) packaging structure and three-dimensional (3-dimenison, 3D) packaging structure, etc.

[0003] Figure 1A and Figure 1B They are respectively a top view and a cross-sectional view of the packaging structure of the two-dimensional packaging component 1 of the prior art. Figure 1A As shown, in the two-dimensional package 1, a plurality of chips 14-1 to 14-5 are arranged in a horizontal direction (along the direction of the connection line AA'). In other words, the chips 14-1 to 14-5 are located in the same plane and are arranged on the same carrier 10; the chips 14-1 to 14-5 are arranged together with the carrier 10 on a circuit board 15 (e.g., a printed circuit board).

[0004] Furthermore, if Figure 1B (along Figure 1A As shown in the cross-sectional view of the connecting line AA', the chip 14-1 and the chip 14-2 (the cross-sectional view of the connecting line AA' does not include the chips 14-3 to 14-5) are set on the carrier 10 through the solder ball 131, and the carrier 10 is set on the circuit board 15. Since the carrier 10 must carry the chips 14-1 to 14-5 ( Figure 1B Only the chip 14-1 and the chip 14-2 are shown in the figure. The carrier 10 must have a larger length w1 in the horizontal direction, which results in the packaging volume of the two-dimensional package 1 being too large. In addition, in order to transmit the signals of the chips 14-1 to 14-5 across the chips, the lengths of the conductive layer 11 of the carrier 10 in the horizontal direction (especially the length w2 of a portion 111 of the conductive layer 11) must also be increased, resulting in increased power consumption. Moreover, since more than two chips 14-1 to 14-5 are carried at the same time, the carrier 10 is prone to warping, resulting in a decrease in the pass rate. The above are the technical problems of the two-dimensional package 1 of the prior art.

[0005] Figure 2A and Figure 2B They are respectively a top view and a cross-sectional view of the packaging structure of a 2.5D package 2 of the prior art. Figure 2A As shown, the 2.5D package 2 is further provided with a silicon interposer 16 to increase the overall rigidity, which is disposed between the chips 14 - 1 to 14 - 5 and the carrier 10 .

[0006] Furthermore, if Figure 2B (along Figure 2A As shown in the cross-sectional view along the connecting line AA′, the silicon interposer 16 is disposed between the chip 14 - 1 and the chip 14 - 2 (the cross-sectional view along the connecting line AA′ does not include the chips 14 - 3 to 14 - 5 ) and the carrier 10 , and includes a plurality of conductive pillars 17 .

[0007] The chip 14-1 and the chip 14-2 are disposed on the silicon interposer 16 through the solder balls 132, and are electrically connected to the conductive pillars 17, and then transferred to the carrier 10. Through the transfer of the silicon interposer 16, the equivalent area of ​​the electrical connection pads of the chip 14-1 and the chip 14-2 can be enlarged, for example: the width w3 of the electrical connection pad 142 of the chip 14-2 is equivalently enlarged to the width w4. However, the additional provision of the silicon interposer 16 will lead to additional material costs and packaging processes, which is a technical problem of the 2.5D package 2 of the prior art.

[0008] Figure 3A and Figure 3B They are respectively a top view and a cross-sectional view of the packaging structure of the stacked package 3 of the prior art. Figure 3A As shown, the stacked package 3 includes two carriers 10 and 18, and a plurality of chips 14-1 to 14-3 are arranged in a vertical direction. Among them, the chips 14-2 and 14-3 are stacked on the carrier 18; and the chip 14-1 is arranged on the carrier 10 and located below the carrier 18.

[0009] Furthermore, if Figure 3B (along Figure 3AAs shown in the cross-sectional view taken along the connecting line AA' in the figure, the chip 14-1 and the chip 14-2 are respectively arranged on the carrier 10 and the carrier 18 in a flip-chip manner; wherein the electrical connection pad 141 of the chip 14-1 is electrically connected to the carrier 10 through the solder ball 133, and the electrical connection pad 142 of the chip 14-2 is electrically connected to the carrier 18 through the solder ball 134. On the other hand, the chip 14-3 is arranged on the chip 14-2 through the adhesive layer 19, and the electrical connection pad 143 of the chip 14-3 is electrically connected to the carrier 18 through the lead 20 in a wire bonding process. In the above manner, the chips 14-1 to 14-3 are stacked in the vertical direction; however, the above stacking arrangement will make it difficult for the chips 14-1 to 14-3 to dissipate heat and generate high temperature.

[0010] In addition, since the chip 14-1 occupies part of the space below the carrier 18, the carrier 18 must increase the extra width w5 to set the solder ball 135, so as to facilitate the output of the input / output port (I / O) of the carrier 18, and then electrically connect to the carrier 10. However, the size of the solder ball 135 is much larger than the solder ball 133 and the solder ball 134, which increases the difficulty of packaging; and due to improper warping of the carrier 18 and the carrier 10, the solder ball 135 and the contact 136 of the carrier 18 and the carrier 10 may be broken or separated. The above is the technical problem of the stacked package 3 of the prior art.

[0011] on the other hand, Figure 3C FIG. 2 is a cross-sectional schematic diagram of a packaging structure of a stacked package 3a in another state of the prior art. Figure 3C As shown, in the stacked package 3a, the conductive pillars 137 (e.g., copper pillars) are used instead of the solder balls 135 as the electrical connection paths between the carrier 18 and the carrier 10. However, the conductive pillars 137 also inevitably increase the lateral area (the area in the horizontal direction) of the stacked package 3a, which is a technical problem of the stacked package 3a in the prior art.

[0012] Figure 4A and Figure 4B They are respectively a top view and a cross-sectional view of the packaging structure of the three-dimensional packaging component 4 of the prior art. Figure 4A As shown, in the three-dimensional package 4, the chip 14-1 and the chip 14-2 are firstly arranged horizontally on the silicon interposer 16. Then, the chip 14-3 is arranged vertically relative to the chip 14-1, and the chip 14-4 and the chip 14-5 are arranged vertically relative to the chip 14-2.

[0013] Furthermore, if Figure 4B (along Figure 4AAs shown in the cross-sectional view of the connecting line AA' in the figure, conductive pillars 21 are set or formed in the chips 14-1 and 14-2 respectively by through-silicon via (TSV) process, so that the chip 14-3 is directly electrically connected to the chip 14-1 through the conductive pillars 21, and the chips 14-4 and 14-5 are directly electrically connected to the chip 14-2 through the conductive pillars 21. In this way, the upper chips 14-3, 14-4 and 14-5 can be directly stacked on the lower chips 14-1 and 14-2, so there is no need to set Figure 3B However, in order to set the conductive pillars 21 in the silicon via process, the internal circuit layout of the chip 14-1 and the chip 14-2 must be redesigned; this increases the process and cost of the wafer process, and also increases the complexity of the packaging process and affects the pass rate. The above are the technical problems of the three-dimensional package 4 in the prior art.

[0014] In view of the above technical problems existing in various packages in the prior art, it is necessary to propose an improved packaging structure which can have the space utilization of a three-dimensional stacking arrangement and can also take into account the overall rigidity of the package and the simplicity of the packaging process, which is the purpose of the present invention. Summary of the invention

[0015] Therefore, an object of the present invention is to provide a package with an improved stacked package structure, which can achieve space utilization, overall structural rigidity and packaging process simplification.

[0016] To achieve the above-mentioned purpose, the present invention provides a semiconductor package, including a flexible carrier, a first chip, a second chip, a first mold sealing layer, a first adhesive layer and a second mold sealing layer. The flexible carrier includes a flexible folding layer having a patterned build-up layer circuit and being soft, and a rigid layer combined on a part of the surface of the flexible folding layer; the part of the flexible folding layer combined with the rigid layer forms a first bearing part and a second bearing part, and the flexible folding layer between the first bearing part and the second bearing part without the rigid layer is formed as a first flexible folding part. The first chip has an active surface and a back surface opposite thereto, and is flip-chip bonded to the first bearing part with the active surface side. The first mold sealing layer is arranged on the first bearing part and covers the first bearing part and the first chip. The first adhesive layer is arranged on the first mold sealing layer so that the second bearing part can be combined with the first mold sealing layer, wherein the first flexible folding part connecting the second bearing part and the first bearing part is bent at least 180°. The second chip has an active surface and an opposite back surface, and is flip-chip-bonded on the second carrier part with the active surface side. The second mold sealing layer is arranged on the second carrier part and covers the second carrier part and the second chip.

[0017] In one embodiment, the first carrying portion and the second carrying portion are electrically connected via a patterned build-up circuit in the carrier.

[0018] In one embodiment, the bottom of the first carrying portion is electrically connected to a circuit board.

[0019] In one embodiment, the semiconductor package further includes a sixth chip embedded in the first mold layer and having an active surface and an opposite back surface. The back surface of the sixth chip is bonded to the back surface of the first chip through a fourth adhesive layer, wherein the active surface of the sixth chip is electrically connected to the first carrier portion through a lead.

[0020] In one embodiment, the semiconductor package further includes a third chip, which is embedded in the second molding layer and has an active surface and a corresponding back surface. The third chip is bonded to the back surface of the second chip via a second adhesive layer via the back surface, wherein the active surface of the third chip is electrically connected to the second supporting portion via a lead.

[0021] In one embodiment, the flexible carrier of the semiconductor package further includes a second flexible portion and a third bearing portion. The second flexible portion has only a flexible layer, and the third bearing portion has a flexible layer and a rigid layer. The third bearing portion is connected to the second bearing portion through the second flexible portion, and the third bearing portion and the first bearing portion are arranged on the same plane. In addition, the semiconductor package further includes a fourth chip and a third mold sealing layer. The fourth chip has an active surface and an opposite back surface, and is placed on the third bearing portion with the active surface flip-chip. The third mold sealing layer is arranged on the third bearing portion and covers the third bearing portion and the fourth chip.

[0022] In one embodiment, the first carrying portion, the second carrying portion and the third carrying portion are electrically connected through the patterned build-up layer circuit in the flexible carrier.

[0023] In one embodiment, the bottom of the third carrying portion is electrically connected to a circuit board.

[0024] In one embodiment, the semiconductor package further includes a fifth chip embedded in the third molding layer and having an active surface and an opposite back surface. The back surface of the fifth chip is bonded to the back surface of the fourth chip through a third adhesive layer. And the active surface of the fifth chip is electrically connected to the third supporting portion through a lead.

[0025] In one embodiment, it further includes:

[0026] a fifth chip embedded in the third molding layer and having an active surface and an opposite back surface, the back surface of the fifth chip being bonded to the back surface of the fourth chip via a third adhesive layer, wherein the active surface of the fifth chip is electrically connected to the third supporting portion via a lead; and

[0027] A third chip is embedded in the second molding layer and has an active surface and an opposite back surface. The back surface of the third chip is combined with the back surface of the second chip through a second adhesive layer, wherein the active surface of the third chip is electrically connected to the second supporting part through a lead.

[0028] In one embodiment, it further includes:

[0029] a fifth chip embedded in the third mold encapsulation layer and having an active surface and an opposite back surface, the back surface of the fifth chip being bonded to the back surface of the fourth chip through a third adhesive layer, wherein the active surface of the fifth chip is electrically connected to the third supporting portion through a lead;

[0030] a sixth chip embedded in the first mold encapsulation layer and having an active surface and an opposite back surface, the back surface of the sixth chip being bonded to the back surface of the first chip via a fourth adhesive layer, wherein the active surface of the sixth chip is electrically connected to the first carrying portion via a lead; and

[0031] A third chip is embedded in the second molding layer and has an active surface and an opposite back surface. The back surface of the third chip is combined with the back surface of the second chip through a second adhesive layer, wherein the active surface of the third chip is electrically connected to the second supporting part through a lead.

[0032] A semiconductor package disclosed in the present invention utilizes a flexible portion that can be bent at least 180 degrees to connect chips, modules or heat sinks of different heights without having to connect circuits through a circuit board or an interposer, thereby greatly improving the freedom of package design, reducing the size of the circuit board, and reducing the cost increased by using a silicon interposer. BRIEF DESCRIPTION OF THE DRAWINGS

[0033] The present invention will be further described in detail below in conjunction with the accompanying drawings and specific embodiments.

[0034] Figure 1A and Figure 1B They are respectively a top view and a cross-sectional view of a packaging structure of a two-dimensional packaging component in the prior art;

[0035] Figure 2A and Figure 2B They are respectively a top view and a cross-sectional view of a packaging structure of a two-and-a-half-dimensional package in the prior art;

[0036] Figure 3A and Figure 3B They are respectively a top view and a cross-sectional view of a packaging structure of a stacked package in the prior art;

[0037] Figure 3CA schematic cross-sectional view of a packaging structure of a stacked package in another state of the prior art;

[0038] Figure 4A and Figure 4B They are respectively a top view and a cross-sectional view of a packaging structure of a three-dimensional packaging component in the prior art;

[0039] Figure 5A is a schematic top view of a semiconductor package according to a first embodiment of the present invention;

[0040] Figure 5B is a cross-sectional schematic diagram of a flexible carrier of a semiconductor package according to a first embodiment of the present invention;

[0041] Figure 5C is a cross-sectional schematic diagram of a semiconductor package according to a first embodiment of the present invention;

[0042] Figure 5D A cross-sectional view of a semiconductor package of the first embodiment of the present invention, in which two chips are arranged back-to-back in both the bottom packaging part and the upper packaging part;

[0043] Fig. 6A is a schematic top view of a semiconductor package according to a second embodiment of the present invention;

[0044] Figure 6B is a cross-sectional schematic diagram of a flexible carrier of a semiconductor package according to a second embodiment of the present invention;

[0045] Figure 6C is a cross-sectional schematic diagram of a semiconductor package according to a second embodiment of the present invention;

[0046] Fig.6D FIG. 4 is a cross-sectional schematic diagram of a semiconductor package in another implementation state of the second embodiment of the present invention.

[0047] Description of Reference Numerals

[0048] 1-4: package; 5, 6, 6a: semiconductor package; 10, 18: carrier; 30, 30a: flexible carrier; 11, W01-W04: conductive layer; 111: part of the conductive layer; 131-135, 361-365: solder ball; 136: contact; 14-1-14-5, 37-1-37-6: chip; 141-143, 371-375: electrical connection pad; 3711, 3721, 3731, 3741, 3751: active surface; 3722, 3732: back surface; 15, 45, 45a: circuit board; 16: silicon interposer; 17, 21, 137, P01-P06: conductive pillar; 19, 40, 41, 55: adhesive layer; 20, 38, 5 6: lead; 31: flexible layer; 311: patterned build-up circuit; 32: rigid layer; 321: first rigid layer; 322: second rigid layer; 33: first bearing part; 331: first side of first bearing part; 332: second side of first bearing part; 34: second bearing part; 341: first side of second bearing part; 342: second side of second bearing part; 35: first flexible part; 42, 43, 48, 48a: molding layer; 46: second flexible part; 47: third bearing part; 471: first side of third bearing part; 51: bottom packaging part; 52: upper packaging part; 53, 53a: lateral packaging part; w1, w2, w6, w7: length; w3, w4, w5: width; AA': connecting line. DETAILED DESCRIPTION

[0049] The technical scheme in the embodiment of the present invention is described clearly and completely below in conjunction with the accompanying drawings in the embodiment of the present invention. In the following description, many specific details are set forth to facilitate a full understanding of the present invention, but the present invention can also be implemented in other ways different from those described herein, and those skilled in the art can make similar generalizations without violating the connotation of the present invention, so the present invention is not limited by the specific embodiments disclosed below.

[0050] FIG. 5A to FIG. 5C 1 and 2 are respectively a top view and a cross-sectional view of the packaging structure of the semiconductor package 5 according to the first embodiment of the present invention. Figure 5A As shown, the semiconductor package 5 is disposed on a circuit board 45, and a flexible carrier 30 that can be bent or folded is used to replace the rigid carrier of the prior art (for example, to replace the Figure 3A The carrier board 10 and the carrier board 18 are shown).

[0051] like Figure 5BAs shown, the flexible carrier 30 mainly includes a flexible folding layer 31 having a patterned build-up layer circuit 311 and being soft, and a rigid layer 32 combined on a part of the surface of the flexible folding layer 31; wherein the part of the flexible folding layer 31 combined with the rigid layer 32 can be formed into a first bearing portion 33 and a second bearing portion 34, and the part of the flexible folding layer 31 between the first bearing portion 33 and the second bearing portion 34 without the rigid layer 32 is formed into a first flexible folding portion 35. Further, the rigid layer 32 also includes a first rigid layer 321 and a second rigid layer 322, which are respectively disposed on opposite surfaces of the flexible folding layer 31.

[0052] In this embodiment, the first supporting portion 33 and the second supporting portion 34 are inflexible and have considerable rigidity, so that they can be flat in the horizontal direction, which is conducive to the flip chip bonding of the chip. The first flexible portion 35 is bent 180 degrees, so that the second supporting portion 34 can be flipped and arranged above the first supporting portion 33, and the second supporting portion 34 is parallel to the first supporting portion 33. Figure 5A The second carrying portion 34 is connected to the first carrying portion 33 through the first flexible portion 35 , and the second carrying portion 34 is located above the first carrying portion 33 .

[0053] The first supporting portion 33 has a first side 331 and a second side 332 disposed opposite to each other, and the second supporting portion 34 also has a first side 341 and a second side 342 disposed opposite to each other. The first flexible portion 35 is flexed in the reverse direction so that the second side 342 of the second supporting portion 34 faces the first side 331 of the first supporting portion 33.

[0054] The patterned build-up circuit 311 includes multiple conductive layers W01-W04 and multiple conductive pillars P01-P04. The conductive layers W01-W04 are patterned conductive layers with predetermined circuit patterns, which serve as horizontal electrical connection paths and signal transmission paths. The conductive pillars P01-P04 serve as vertical electrical connection paths and signal transmission paths.

[0055] The material of the first rigid layer 321 and the second rigid layer 322 is, for example, FR4 glass fiber dielectric material, which can function as a substrate of a traditional rigid circuit board to provide sufficient support to carry active and passive electronic components including chips.

[0056] Also see Figure 5C As shown (along Figure 5A The semiconductor package 5 further includes a first chip 37 - 1 , a second chip 37 - 2 , a third chip 37 - 3 , a plurality of molding layers 42 and 43 , and a plurality of adhesive layers 40 and 41 .

[0057] The first chip 37-1, the second chip 37-2 and the third chip 37-3 are respectively arranged at different parts or different relative positions of the flexible carrier 30. The flexible carrier 30 of this embodiment can also be stacked in a three-dimensional direction to arrange the first chip 37-1, the second chip 37-2 and the third chip 37-3, so that the space can be effectively utilized. The first chip 37-1 is arranged between the first supporting portion 33 and the second supporting portion 34 of the flexible carrier 30. In detail, the active surface 3711 of the first chip 37-1 faces downward, and is placed on the first side 331 of the first supporting portion 33 in a flip chip manner. Among them, the electrical connection pad 371 (also called metal pad or metal electrode pad) arranged on the active surface 3711 is fixed on the first rigid layer 321 through a solder ball (also called tin-lead bump) 361 (also called tin-lead bump), and is further electrically connected to the conductive column P01 inside the first supporting part 33, and then electrically connected to the conductive layers W01~W04 inside the first supporting part 33.

[0058] The mold sealing layer 42 is disposed on the first carrier 33. The mold sealing layer 42 is formed on the first rigid layer 321 of the first side 331 of the first carrier 33 and completely covers the first chip 37-1 and the solder ball 361. The mold sealing layer 42 can be formed by a molding process, and its material is a molding compound, such as a phenolic resin, an epoxy resin, or a silicone resin. In addition, the adhesive layer 40 is disposed or formed on the mold sealing layer 42 so that the second carrier 34 can be combined with the mold sealing layer 42 with its second side 342.

[0059] As described above, the first carrier portion 33 of the flexible carrier 30, the first chip 37-1 and the molding layer 42 constitute the bottom packaging portion 51 of the semiconductor package 5. The bottom packaging portion 51 is disposed on the circuit board 45 through the solder balls 363. That is, the bottom packaging portion 51 is connected to the circuit board 45 by the second side 332 of the first carrier portion 33 through the solder balls 363.

[0060] On the other hand, the second chip 37-2 and the third chip 37-3 are stacked in a vertical direction on the second carrier portion 34. The active surface 3721 of the second chip 37-2 faces downward and is placed on the first side 341 of the second carrier portion 34 in a flip-chip manner. The electrical connection pad 372 disposed on the active surface 3721 is electrically connected to the conductive pillar P02 inside the second carrier portion 34 through the solder ball 362, and is further electrically connected to the conductive layer W01~W04 inside the second carrier portion 34. In other words, the active surface 3721 of the second chip 37-2 is electrically connected to the first side 341 of the second carrier portion 34 in a flip-chip manner.

[0061] In addition, the active surface 3731 of the third chip 37-3 faces upward, and its back surface 3732 is bonded to the back surface 3722 of the second chip 37-2 through the adhesive layer 41. In other words, the second chip 37-2 and the third chip 37-3 are stacked in a back-to-back manner in a vertical direction. The electrical connection pad 373 arranged on the active surface 3731 of the third chip 37-3 is also electrically connected to the conductive column P03 inside the second carrier part 34 through the lead 38 in a wire bonding manner, and then electrically connected to the conductive layer W01~W04 inside the second carrier part 34. In other words, the active surface 3731 of the third chip 37-3 is electrically connected to the first side 341 of the second carrier part 34 in a wire bonding manner.

[0062] The mold layer 43 is formed by a molding process and is made of a molding compound. The mold layer 43 is formed on the second rigid layer 322 of the first side 341 of the second carrier 34 and completely covers the second chip 37 - 2 , the third chip 37 - 3 , the leads 38 and the solder balls 362 .

[0063] As mentioned above, the second supporting portion 34 of the flexible carrier 30, the second chip 37-2, the third chip 37-3 and the molding layer 43 constitute the upper packaging portion 52 of the semiconductor package 5. The upper packaging portion 52 is electrically connected to the bottom packaging portion 51 through the first flexible portion 35. Therefore, the signal transmission between the upper packaging portion 52 and the bottom packaging portion 51 can be completed through the conductive layers W2 and W3 inside the first flexible portion 35, which is equivalent to being completed through the patterned build-up circuit 311. In other words, in this embodiment, the first flexible portion 35 of the flexible carrier 30 replaces the solder balls or conductive pillars of the prior art (for example, replacing the conductive pillars of the first flexible portion 35). Figure 3B Solder ball 135 as shown, or Figure 3C The conductive pillars 137 shown in the figure serve as electrical connection paths and signal transmission paths between the upper packaging portion 52 and the lower packaging portion 51.

[0064] Since the space between the second carrier portion 34 and the first carrier portion 33 does not need to be provided with solder balls or conductive pillars (the space can be fully provided for the chip 37-1), the length w6 of the flexible carrier 30 in the horizontal direction can be reduced, thereby reducing the packaging volume of the semiconductor package 5. In addition, the present embodiment uses the adhesive layer 40 to firmly connect the upper packaging portion 52 to the bottom packaging portion 51, thereby improving the overall structural strength of the semiconductor package 5. The above is the technical effect of the first embodiment of the present invention.

[0065] In addition, it is worth mentioning that Figure 5C In the embodiment, the bottom packaging part 51 is provided with a first chip 37-1, and the upper packaging part 52 is provided with a second chip 37-2 and a third chip 37-3. However, in other implementations, other numbers of chips may be provided, for example, the bottom packaging part 51 is provided with another sixth chip 37-6 on the first chip 37-1 in a back-to-back manner, and the upper packaging part 52 is provided with only a second chip 37-2. Or as Figure 5D As shown, two chips are disposed in a back-to-back manner in both the bottom packaging portion 51 and the upper packaging portion 52 .

[0066] FIG. 6A to FIG. 6C 1 and 2 are respectively a top view and a cross-sectional view of the packaging structure of a semiconductor package 6 according to a second embodiment of the present invention. Fig. 6A As shown, compared with the semiconductor package 5 of the first embodiment, in addition to the first carrying portion 33, the first flexible portion 35 and the second carrying portion 34, the flexible carrier 30a of the semiconductor package 6 of the present embodiment further includes a second flexible portion 46 and a third carrying portion 47. In addition, in addition to the first chip 37-1, the second chip 37-2 and the third chip 37-3, the semiconductor package 6 of the present embodiment further includes a fourth chip 37-4, which is disposed on the third carrying portion 47.

[0067] like Figure 6B As shown, the flexible carrier 30a is further extended to form a second flexible portion 46 and a third bearing portion 47. Therefore, compared with the flexible carrier 30 of the first embodiment, the flexible carrier 30a of this embodiment has a larger length w7 in the horizontal direction. Among them, the second flexible portion 46 only has a flexible layer 31, and the third bearing portion 47 has a flexible layer 31 and a rigid layer 32. In addition, the third bearing portion 47 is connected to the second bearing portion 34 through the second flexible portion 46; and the second flexible portion 46 is arbitrarily bent, so that the third bearing portion 47 and the first bearing portion 33 are arranged on the same or different planes of the circuit board (this embodiment is as shown in FIG. Figure 6C The same plane circuit board 45a is shown.

[0068] For example Figure 6C (along Fig. 6A As shown in the cross-sectional view along the connecting line AA' in the middle, in the semiconductor package 6 of the present embodiment, like the first chip 37-1 and the second chip 37-2, the fourth chip 37-4 is also disposed on the first side 471 of the third carrier portion 47 in a flip-chip manner. In detail, the active surface 3741 of the fourth chip 37-4 faces downward, and the electrical connection pad 374 disposed on the active surface 3741 is electrically connected to the conductive pillar P05 inside the third carrier portion 47 through the solder ball 364, and then electrically connected to the conductive layer W01-W04 inside the third carrier portion 47. In other words, the active surface 3741 of the fourth chip 37-4 is electrically connected to the first side 471 of the third carrier portion 47 in a flip-chip manner.

[0069] In addition, like the mold layers 42 and 43, the semiconductor package 6 further includes a mold layer 48, which is also disposed or formed on the second rigid layer 322 of the first side 471 of the third carrier 47 through a molding process. The mold layer 48 completely covers the fourth chip 37-4 and the solder balls 364.

[0070] As mentioned above, the third carrying portion 47 of the flexible carrier 30a, the fourth chip 37-4 and the molding layer 48 constitute the lateral packaging portion 53 of the semiconductor package 6, which is connected to the upper packaging portion 52 through the second flexible folding portion 46 of the flexible carrier 30a. Therefore, the signal transmission between the lateral packaging portion 53 and the upper packaging portion 52 can be completed through the conductive layers W02 and W03 inside the second flexible folding portion 46.

[0071] In this embodiment, the height difference of the vertically arranged positions of different components is overcome directly by bending the flexible carrier 30a (i.e., the second flexible portion 46 is bent at will) to complete the electrical connection between the lateral packaging portion 53 and the upper packaging portion 52. Furthermore, the connection between the lateral packaging portion 53 and the upper packaging portion 52 does not need to be transferred through any interposer (especially a hard silicon interposer), nor does it need to be electrically connected through any conductive pillars (copper pillars) or solder balls. Therefore, this embodiment can simplify the packaging process and improve the structural strength and reliability of the semiconductor package 6 and the flexibility of the packaging design.

[0072] In addition, since the second flexible folding portion 46 of the flexible carrier 30a can be folded downward, the lateral packaging portion 53 can be set at an appropriate position on the same plane as the bottom packaging portion 51, and electrically connected to the circuit board 45a through the solder ball 365, so that the space above the lateral packaging portion 53 can accommodate other components, thereby greatly improving the space utilization and the flexibility of the packaging design. In other words, the flexible carrier 30a of this embodiment has greater setting flexibility and space utilization in both the horizontal and vertical directions, so that the packaging size of the semiconductor package 6 in both the horizontal and vertical directions can be reduced. The above is the technical effect of the second embodiment of the present invention.

[0073] As described above, since there is still sufficient space above the lateral packaging portion 53, another fifth chip 37-5 can be further stacked on the fourth chip 37-4 to form a Fig.6D The semiconductor package 6a is shown.

[0074] Fig.6D FIG. 6 is a cross-sectional schematic diagram of a packaging structure of a semiconductor package 6a according to another implementation state of the second embodiment of the present invention. Fig.6D As shown, the fifth chip 37-5 is disposed on the fourth chip 37-4 in a back-to-back manner through an adhesive layer 55. The active surface 3751 of the fifth chip 37-5 faces upward, and the electrical connection pad 375 disposed on the active surface 3751 is electrically connected to the conductive pillar P06 inside the third carrier part 47 through the lead 56, and then electrically connected to the conductive layer W01~W04 inside the third carrier part 47. In other words, the active surface 3751 of the fifth chip 37-5 is electrically connected to the first side 471 of the third carrier part 47 by wire bonding.

[0075] In addition, the molding layer 48a completely covers the fourth chip 37-4, the fifth chip 37-5, the leads 56 and the solder balls 364. The third supporting portion 47 of the flexible carrier 30a, the fourth chip 37-4, the fifth chip 37-5, the leads 56 and the molding layer 48a constitute the lateral packaging portion 53a of the semiconductor package 6a.

[0076] In summary, the semiconductor package disclosed in the present invention utilizes a flexible portion that can be bent at least 180 degrees to connect chips, modules or heat sinks of different heights without having to connect circuits through a circuit board or an interposer, thereby greatly improving the freedom of package design, reducing the size of the circuit board, and reducing the cost increased by using a silicon interposer.

[0077] The above description is only a preferred embodiment of the present invention. Obviously, the described embodiment is only a part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of the present invention.

Claims

1. A semiconductor package, characterized in that: include: A flexible carrier includes a flexible folding layer having a patterned build-up circuit and being soft, and a rigid layer combined on a portion of the surface of the flexible folding layer; the portion of the flexible folding layer combined with the rigid layer forms a first bearing portion and a second bearing portion, and the portion of the flexible folding layer between the first bearing portion and the second bearing portion where the rigid layer is not combined forms a first flexible folding portion; A first chip having an active surface and an opposite back surface, and flip-chip-bonded on the active surface side on the first carrier; A first mold sealing layer is disposed on the first carrying portion and covers the first carrying portion and the first chip; A first adhesive layer is disposed on the first mold sealing layer to allow the second supporting part to be combined with the first mold sealing layer, wherein the first bending part connecting the second supporting part and the first supporting part is bent at least 180°; A second chip having an active surface and an opposite back surface, and flip-chip-bonded on the second supporting portion with the active surface side; and A second mold sealing layer is disposed on the second supporting portion and covers the second supporting portion and the second chip; The first carrying portion and the second carrying portion are electrically connected via the patterned build-up layer circuit in the flexible carrier.

2. The semiconductor package according to claim 1, wherein: The lower side of the first carrying portion is electrically connected to a circuit board.

3. The semiconductor package according to claim 1, wherein: Also includes: A sixth chip is embedded in the first molding layer and has an active surface and an opposite back surface. The back surface of the sixth chip is combined with the back surface of the first chip through a fourth adhesive layer, wherein the active surface of the sixth chip is electrically connected to the first supporting part through a lead.

4. The semiconductor package according to claim 1, wherein: Also includes: A third chip is embedded in the second molding layer and has an active surface and an opposite back surface. The back surface of the third chip is combined with the back surface of the second chip through a second adhesive layer, wherein the active surface of the third chip is electrically connected to the second supporting part through a lead.

5. The semiconductor package according to claim 1, wherein: Also includes: a sixth chip embedded in the first mold encapsulation layer and having an active surface and an opposite back surface, the back surface of the sixth chip being bonded to the back surface of the first chip via a fourth adhesive layer, wherein the active surface of the sixth chip is electrically connected to the first carrying portion via a lead; as well as A third chip is embedded in the second molding layer and has an active surface and an opposite back surface. The back surface of the third chip is combined with the back surface of the second chip through a second adhesive layer, wherein the active surface of the third chip is electrically connected to the second supporting part through a lead.

6. The semiconductor package according to claim 1, wherein: The flexible carrier also includes a second flexible portion having only a flexible folding layer, and a third bearing portion having a flexible folding layer and a rigid layer, wherein the third bearing portion is connected to the second bearing portion through the second flexible folding portion, and the third bearing portion and the first bearing portion are arranged on the same plane; a fourth chip having an active surface and an opposite back surface, and flip-chip-bonded on the third supporting portion with the active surface; and a third mold sealing layer, disposed on the third supporting portion and covering the third supporting portion and the fourth chip; The first carrying portion, the second carrying portion and the third carrying portion are electrically connected via the patterned build-up layer circuit in the flexible carrier.

7. The semiconductor package according to claim 6, wherein: The lower side of the third carrying portion is electrically connected to a circuit board.

8. The semiconductor package according to claim 6, wherein: Also includes: A fifth chip is embedded in the third molding layer and has an active surface and an opposite back surface. The back surface of the fifth chip is combined with the back surface of the fourth chip through a third adhesive layer, wherein the active surface of the fifth chip is electrically connected to the third supporting part through a lead.

9. The semiconductor package according to claim 6, wherein: Also includes: a fifth chip embedded in the third mold encapsulation layer and having an active surface and an opposite back surface, the back surface of the fifth chip being bonded to the back surface of the fourth chip through a third adhesive layer, wherein the active surface of the fifth chip is electrically connected to the third supporting portion through a lead; as well as A third chip is embedded in the second molding layer and has an active surface and an opposite back surface. The back surface of the third chip is combined with the back surface of the second chip through a second adhesive layer, wherein the active surface of the third chip is electrically connected to the second supporting part through a lead.

10. The semiconductor package according to claim 6, wherein: Also includes: a fifth chip embedded in the third mold encapsulation layer and having an active surface and an opposite back surface, the back surface of the fifth chip being bonded to the back surface of the fourth chip through a third adhesive layer, wherein the active surface of the fifth chip is electrically connected to the third supporting portion through a lead; a sixth chip embedded in the first mold encapsulation layer and having an active surface and an opposite back surface, the back surface of the sixth chip being bonded to the back surface of the first chip via a fourth adhesive layer, wherein the active surface of the sixth chip is electrically connected to the first carrying portion via a lead; as well as A third chip is embedded in the second molding layer and has an active surface and an opposite back surface. The back surface of the third chip is combined with the back surface of the second chip through a second adhesive layer, wherein the active surface of the third chip is electrically connected to the second supporting part through a lead.

Images