Semiconductor device

Abstract

The present invention relates to a semiconductor device. The semiconductor device includes: a substrate having a first region and a second region; a device layer formed on the first region; and a dummy structure formed on the second region, wherein the dummy structure includes a first helical dummy layer and a second helical dummy layer nested with each other. In this way, the dummy structure formed on the semiconductor device can not only be used to equalize the chip layout density, but also be used as a storage capacitor.

Description

Technical Field

[0001] The present invention relates to the field of semiconductor manufacturing, and particularly to semiconductor devices with virtual structures. Background Art

[0002] In the integrated circuit process, due to the different pattern densities in the wafer, pattern effects, i.e., microloading effects, will occur. The microloading effect is a phenomenon that occurs when exposing, etching, and / or polishing simultaneously on higher density patterns and lower density patterns. Due to the difference in exposure / etching / polishing rates between different positions on the thin film, the reaction amount generated by exposure / etching / polishing will become locally dense or sparse, and cause non-uniformity in etching / polishing rate or pattern size after exposure. Excessive density differences in effective patterns may cause significant and adverse effects. For example, during the chemical mechanical polishing (CMP) process, the polishing rate in the low pattern density area is higher than that in the high pattern density area. Therefore, areas with different pattern densities obtain different thicknesses after the chemical mechanical polishing (CMP) process, that is, an uneven surface is obtained. In addition to different thicknesses, the uneven substrate surface further causes serious problems such as pattern size errors and poor critical dimension uniformity in the subsequent formed patterns.

[0003] To counteract this effect, a layout design called virtual fill has been developed. During virtual fill, the circuit layout is adjusted and virtual patterns are filled into positions with low pattern density. The filling of virtual patterns helps to achieve a uniform effective pattern density on the wafer, thus avoiding the occurrence of pattern effect problems. The prior art usually uses rectangular virtual patterns and places them in a floating electrical characteristic state, but such a method is difficult to efficiently utilize the precious space on the semiconductor chip.

[0004] Therefore, there is still a need in the semiconductor process for a semiconductor device with a new virtual structure that can more efficiently utilize space to reduce the size of the semiconductor device. Summary of the Invention

[0005] A brief overview of one or more aspects is given below to provide a basic understanding of these aspects. This overview is not an exhaustive survey of all contemplated aspects, and is neither intended to identify key or decisive elements of all aspects nor to define the scope of any or all aspects. Its sole purpose is to present some concepts of one or more aspects in a simplified form as a prelude to the more detailed description that follows.

[0006] The present invention aims to overcome the above and / or other problems in the prior art, and particularly provides a virtual structure formed on a semiconductor device, which can not only be used to equalize the chip layout density, but also be used as a storage capacitor, thereby obtaining additional capacitance and efficiently utilizing space.

[0007] Accordingly, an exemplary embodiment of the present invention provides a semiconductor device, comprising: a substrate having a first region and a second region; a device layer formed on the first region; and a dummy structure formed on the second region, wherein the dummy structure includes a first spiral dummy layer and a second spiral dummy layer nested with each other.

[0008] Preferably, the first spiral dummy layer and the second spiral dummy layer are adjacent to each other at a predetermined interval.

[0009] Preferably, a first DC voltage is applied to the first spiral dummy layer, and a second DC voltage is applied to the second spiral dummy layer, and the first DC voltage is greater than the second DC voltage. Preferably, one of the first DC voltage and the second DC voltage is a ground voltage. In this way, a storage capacitor is realized by making the two nodes of the power supply and the ground into a spiral shape instead of a dummy structure with a rectangular floating level; the storage capacitor can reduce the chip size by effectively utilizing the space and help stabilize the entire chip through the shielding effect formed by replacing the floating node with a power supply node.

[0010] Preferably, the first spiral dummy layer and the second spiral dummy layer are formed of polysilicon and / or metal.

[0011] Preferably, the first spiral dummy layer and the second spiral dummy layer have a square spiral pattern, and the square spiral pattern is a broken line formed by line segments connected end to end.

[0012] Preferably, in the square spiral pattern, the included angle between two line segments connected end to end is 90°.

[0013] Preferably, each of the first spiral dummy layer and the second spiral dummy layer includes: a first sub-layer extending along all line segments of the square spiral pattern; an insulating layer formed on one side of the first sub-layer facing the same direction; and a second sub-layer formed on the side of the insulating layer opposite to the first sub-layer, wherein the insulating layer electrically isolates the first sub-layer and the second sub-layer.

[0014] Preferably, at least a part of the first spiral dummy layer and the second spiral dummy layer are centrosymmetric with each other in the dummy structure.

[0015] Preferably, the semiconductor device further includes a MOS transistor formed on the second region, and the dummy structure is adjacent to the gate of the MOS transistor.

[0016] Other features and aspects will become apparent through the following detailed description, the accompanying drawings, and the claims. BRIEF DESCRIPTION OF THE DRAWINGS

[0017] The present invention may be better understood by describing exemplary embodiments of the present invention in conjunction with the accompanying drawings, in which:

[0018] Figure 1 A schematic diagram illustrating a semiconductor device is shown;

[0019] Figure 2 Shown filled with dummy structures Figure 1 A schematic diagram of a semiconductor device;

[0020] Figure 3 shows an example of a virtual structure according to an embodiment of the present invention;

[0021] Figure 4A and Figure 4B Exploded views respectively showing a first spiral virtual layer and a second spiral virtual layer of a virtual structure according to an exemplary embodiment of the present invention;

[0022] Figure 5 An exemplary schematic diagram showing that different voltages are applied to the first spiral virtual layer and the second spiral virtual layer of the virtual structure;

[0023] Figure 6 A schematic diagram showing a virtual structure according to another exemplary embodiment of the present invention;

[0024] Figure 7 An example of a high-voltage MOS capacitor using the same process is shown; and

[0025] Figure 8 Schematic diagram showing the combination of a spiral dummy structure and a MOS transistor to increase capacitance. DETAILED DESCRIPTION

[0026] The specific embodiments of the present invention will be described below. It should be noted that in the specific description of these embodiments, for the sake of concise description, this specification cannot describe all features of the actual embodiments in detail. It should be understood that in the actual implementation process of any one of the embodiments, just as in the process of any engineering project or design project, in order to achieve the specific goals of the developer and to meet system-related or business-related restrictions, various specific decisions are often made, and these will also change from one embodiment to another. In addition, it can also be understood that although the efforts made in this development process may be complex and lengthy, for those of ordinary skill in the art related to the content disclosed in the present invention, some design, manufacturing, or production changes based on the technical content disclosed in this disclosure are only conventional technical means and should not be understood as the content of this disclosure being insufficient.

[0027] Unless otherwise defined, the technical terms or scientific terms used in the claims and the specification should have the ordinary meaning understood by those of ordinary skill in the technical field to which the present invention belongs. The terms "first", "second" and similar terms used in the specification and claims of this patent application for the present invention do not denote any order, quantity or importance, but are only used to distinguish different components. The terms such as "a" or "one" do not denote a quantity limitation, but mean that there is at least one. The terms such as "comprising" or "including" mean that the elements or items appearing before "comprising" or "including" cover the elements or items listed after "comprising" or "including" and their equivalent elements, and do not exclude other elements or items. The terms such as "connected" or "coupled" are not limited to physical or mechanical connections, nor are they limited to direct or indirect connections. The phrase "A is substantially equal to B" is intended to take into account the tolerances in manufacturing processes, that is, the values of A and B can be within ±10% of each other. The phrase "X is substantially perpendicular to Y" is intended to take into account the tolerances in manufacturing processes, that is, the included angle between X and Y can be between 80° and 100°.

[0028] In this application, if there is no special indication, all the embodiments and preferred embodiments mentioned herein can be combined with each other to form new technical solutions. In this application, if there is no special indication, all the technical features and preferred features mentioned herein can be combined with each other to form new technical solutions.

[0029] In the description of the embodiments of the present application, the term "and / or" is merely a description of the association relationship of associated objects, indicating that there can be three relationships. For example, A and / or B can represent three situations: A exists alone, A and B exist simultaneously, and B exists alone. Additionally, in this text, the character " / " generally represents an "or" relationship between the preceding and following associated objects.

[0030] Figure 1 FIG. shows a schematic diagram of a semiconductor device 10 according to an embodiment of the present invention. Refer to Figure 1 , the semiconductor device 10 may include a substrate 100 and one or more device layers 110 formed on the device region of the substrate 100. The one or more device layers 110 may be a material stack, such as for forming an active circuit pattern of the semiconductor device 10. As Figure 1 shown, the pattern distribution of the device layer 10 on the substrate 100 is not uniform, and there are obvious low-density regions (e.g., blank regions). Therefore, for the uniformity of subsequent semiconductor processes (e.g., CMP), it is necessary to fill the virtual structures in these low-density regions so that the pattern distribution on the substrate 100 is more uniform.

[0031] Refer to Figure 2 , which shows a schematic diagram of the semiconductor device 10 filled with the virtual structure 120. As Figure 1 shown, the semiconductor device 10 includes one or more virtual structures 120 formed on the blank regions of the substrate 100. The virtual structure 120 may include a first spiral virtual layer and a second spiral virtual layer nested with each other. The first spiral virtual layer and the second spiral virtual layer are independent of each other and do not intersect. For example, the first spiral virtual layer and the second spiral virtual layer may be adjacent to each other at a predetermined interval. Figure 2 shown, the semiconductor device 10 includes one or more virtual structures 120 formed on the blank regions of the substrate 100. The virtual structure 120 may include a first spiral virtual layer and a second spiral virtual layer nested with each other. The first spiral virtual layer and the second spiral virtual layer are independent of each other and do not intersect. For example, the first spiral virtual layer and the second spiral virtual layer may be adjacent to each other at a predetermined interval.

[0032] Refer to Figure 3 , which shows an exemplary embodiment of the virtual structure 120. The virtual structure 120 includes a first spiral virtual layer 121 and a second spiral virtual layer 122 nested with each other. In this example, the first spiral virtual layer 121 and the second spiral virtual layer 122 may have a square spiral pattern, and the square spiral pattern is a broken line formed by line segments connected end to end. The two line segments connected end to end in the square spiral pattern may be substantially perpendicular, or may have other included angle sizes. The advantage of using a broken line is to facilitate pattern layout. For example, compared with a curve, it simplifies the complexity of pattern layout calculation. Nevertheless, the present invention is not limited to the square spiral pattern. For example, a circular spiral pattern may be adopted.

[0033] Figure 4A and Figure 4BExploded views of a first helical virtual layer 121 and a second helical virtual layer 122 of a virtual structure 120 according to an exemplary embodiment of the present invention are shown respectively. As Figure 4A shown, the first helical virtual layer 121 of the virtual structure 120 may be formed by connecting a plurality of line segments (a1, b1, c1, d1, e1, f1, g1, h1, i1, j1, and k1) end to end. As Figure 4B shown, the second helical virtual layer 122 of the virtual structure 120 may be formed by connecting a plurality of line segments (a2, b2, c2, d2, e2, f2, g2, h2, i2, and j2) end to end. At least a part of the first helical virtual layer 121 (for example, the part except the line segment k1) may be centrosymmetric with the second helical virtual layer 122 in the virtual structure 120. Note that the lengths and numbers of the line segments constituting the first helical virtual layer 121 and the second helical virtual layer 122 may be determined according to needs and the morphology of the low-density region on the semiconductor device, and the present application does not aim to limit this.

[0034] In Figure 4A and Figure 4B the shown exemplary embodiment, the included angle between two adjacent line segments in the square helical pattern of the first helical virtual layer 121 and the second helical virtual layer 122 is 90°. The first helical virtual layer 121 and the second helical virtual layer 122 may be adjacent to each other at a predetermined interval in the virtual structure 120. Referring back to Figure 3 if the interval between the first helical virtual layer 121 and the second helical virtual layer 122 is uniform and each has a uniform width, then the formed virtual structure 120 may present a rectangular shape on the substrate surface.

[0035] In this way, the virtual structure 120 on the semiconductor device 10 can not only be used to equalize the layout density, but also be used as a storage capacitor, thereby obtaining additional capacitance and efficiently utilizing space.

[0036] When used as a storage capacitor, the first helical virtual layer 121 may be applied with a first DC voltage (for example, connected to a first power supply), and the second helical virtual layer 122 may be applied with a second DC voltage (for example, connected to a second power supply). The first DC voltage is different from the second DC voltage. The first helical virtual layer 121 and the second helical virtual layer 122 may comprise the same metal material or different metal materials. Alternatively, the first helical virtual layer 121 and the second helical virtual layer 122 may also comprise polysilicon.

[0037] Referring to Figure 5, an exemplary schematic diagram showing that different voltages are applied to the first helical virtual layer 121 and the second helical virtual layer 122 of the virtual structure 120 respectively. In this example, the first helical virtual layer 121 can be grounded, while the second helical virtual layer 122 can have a high level VDD. In this way, due to the repeated helical structure of adjacent power nodes (VDD) and ground nodes (GND), a large capacitance can be generated between the first helical virtual layer 121 and the second helical virtual layer 122.

[0038] Figure 6 A schematic diagram showing the virtual structure 120 according to another exemplary embodiment of the present invention. In this example, each of the first helical virtual layer 121 and the second helical virtual layer 122 can include a first sub-layer 131, an insulating layer 132, and a second sub-layer 133. As Figure 6 shown, the first sub-layer 131 can extend along all line segments of the square helical pattern of its helical virtual layer; the insulating layer 132 can be formed on one side of the first sub-layer 131 facing the same direction (for example, Figure 6 facing the left side in the figure). The second sub-layer 133 can be formed on the side of the insulating layer 132 opposite to the first sub-layer 131. The insulating layer 132 can electrically isolate the first sub-layer 131 and the second sub-layer 133. The first sub-layer 131 and the second sub-layer 133 can be formed of polysilicon or metal. In this way, the first sub-layer 131 of one of the first helical virtual layer 121 and the second helical virtual layer 122 can be used together with the second sub-layer 133 of the other of the first helical virtual layer 121 and the second helical virtual layer 122 facing the first sub-layer 131 to form a capacitance.

[0039] For example, the insulating layer 132 can extend along the line segments with the same orientation among all line segments of the square helical pattern ( Figure 4A and Figure 4B the line segments b1, b2, d1, d2, f1, f2, h1, h2, and j2 shown in the figure), and is provided at the ends of the first helical virtual layer 121 and the second helical virtual layer 122 facing the same direction, for example, provided at the end of the line segment a2 shown in Figure 4B the figure, so as to allow a capacitance to be formed with the first sub-layer 131 located at the line segment b1. As Figure 6 shown, for example, the first sub-layer 131 can be connected to a first power supply (for example, having a ground voltage GND), while the second sub-layer 133 is connected to a second power supply (having a level VDD) to form a capacitance between the first sub-layer 131 and the second sub-layer 133.

[0040] Table 1 shows the capacitance result test of the dummy structure 120 according to the example of the present invention. Three samples 1-3 were created by using the current process to extract the capacitance. The dummy structures of sample 1, sample 2 and sample 3 have the same area (10μm×10μm), wherein the first spiral dummy layer 121 and the second spiral dummy layer 122 of the dummy structure 120 have a width W=0.18μm, and the spacing S between the first spiral dummy layer 121 and the second spiral dummy layer 122 is 0.12μm. The dummy structure 120 of sample 1 is Figure 5 As shown, the first spiral virtual layer 121 and the second spiral virtual layer 122 are both made of metal aluminum, and the capacitance of one of them is measured. The virtual structure 120 of sample 2 is Figure 5 As shown, the first spiral virtual layer 121 and the second spiral virtual layer 122 are both made of copper, and the capacitance of one of them is measured. The virtual structure 120 of sample 3 is Figure 6 As shown, the first sub-layer 131 includes metal copper (connected to VDD), and the second sub-layer 133 includes metal aluminum (connected to ground), and the capacitance at one of the locations is measured.

[0041]

[0042] Table 1: Capacitance of each sample

[0043] Note that the above samples 1-3 merely illustrate examples of the dummy structure 120 according to the present invention and are not intended to limit the material, width, and spacing of the first spiral dummy layer 121 and the second spiral dummy layer 122. If the process permits, it is desirable that the width and spacing of the first spiral dummy layer 121 and the second spiral dummy layer 122 be as small as possible to achieve the maximum capacitance value.

[0044] For comparison, Figure 7 An example of a high-voltage MOS capacitor under the same process is shown. Assuming the conditions of this example high-voltage transistor are: the gate is formed of tungsten, the electrode is formed of metal aluminum, the thickness is 40nm, the width is 10μm, and the length is 10μm, then

[0045] C=ε r ε o A / d=3.9×(8.854×10 -12 F / m)×100×10 -12 m 2 / (40×10 -9 m)=86fF.

[0046] A simple comparison shows that the additional capacitance obtained by the spiral virtual layer is not small.

[0047] Alternatively, as Figure 8As shown, the capacitance can be increased by combining a spiral virtual structure and a MOS transistor used as a capacitor. For example, the virtual structure 120 can be arranged adjacent to the gate of the MOS transistor. In one example, the virtual structure can be formed on the gate of the MOS transistor, between the source and the drain, i.e., Figure 8 the black box area in. In this way, a further coupling capacitance can be formed between the gate and the adjacent spiral virtual layer.

[0048] The semiconductor device according to an exemplary embodiment of the present invention has been described in detail above. The advantages of the present invention are as follows: 1) The space that is only used as a virtual structure to increase the density ratio in the prior art can be used as a storage capacitor. Thus, additional capacitance can be obtained and the space can be effectively utilized; 2) Due to the shielding effect, replacing the virtual structure from the floating level to the DC level helps to stabilize the entire chip; 3) Combining the spiral virtual structure and the MOS capacitor can additionally obtain a large amount of capacitance.

[0049] It should be understood that the above description is illustrative and not restrictive. For example, the above embodiments (and / or aspects thereof) can be used in combination with each other. In addition, many modifications can be made without departing from the scope of the present invention to adapt a particular situation or material to the teachings of the various embodiments of the present invention. Although the dimensions and types of the materials described herein are used to define the parameters of the various embodiments of the present invention, the various embodiments are not meant to be restrictive, but rather are exemplary embodiments. Many other embodiments will be apparent to those skilled in the art upon reading the above description. Therefore, the scope of the various embodiments of the present invention should be determined with reference to the appended claims and the full scope of the equivalents claimed thereby.

Claims

1. A semiconductor device, comprising: A substrate having a first region and a second region; A device layer formed on the first region; And A dummy structure formed on the second region, Wherein the dummy structure includes a first spiral dummy layer and a second spiral dummy layer nested with each other, Wherein a first DC voltage is applied to the first spiral dummy layer, a second DC voltage is applied to the second spiral dummy layer, and the first DC voltage is greater than the second DC voltage, Wherein the first spiral dummy layer and the second spiral dummy layer are adjacent to each other at a predetermined interval, and a capacitance is formed between the first spiral dummy layer and the second spiral dummy layer through the predetermined interval and the voltage difference, Wherein the first spiral dummy layer and the second spiral dummy layer have a square spiral pattern, and the square spiral pattern is a broken line formed by line segments connected end to end.

2. The semiconductor device according to claim 1, wherein One of the first DC voltage and the second DC voltage is a ground voltage.

3. The semiconductor device according to claim 1, wherein The first spiral dummy layer and the second spiral dummy layer are formed of polysilicon and / or metal.

4. The semiconductor device according to claim 1, wherein, In the square spiral pattern, the included angle between two line segments connected end to end is 90°.

5. The semiconductor device according to claim 1, wherein Each of the first spiral dummy layer and the second spiral dummy layer includes: A first sub-layer extending along all line segments of the square spiral pattern; An insulating layer formed on one side of the first sub-layer facing the same direction; and A second sub-layer formed on the side of the insulating layer opposite to the first sub-layer, Wherein the insulating layer electrically isolates the first sub-layer and the second sub-layer.

6. The semiconductor device according to claim 1, characterized in that, At least a part of the first spiral dummy layer and the second spiral dummy layer are centrosymmetric to each other in the dummy structure.

7. The semiconductor device according to claim 1, characterized in that, The semiconductor device further includes a MOS transistor formed on the second region, wherein the dummy structure is adjacent to the gate of the MOS transistor.

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