Trench gate power devices

Abstract

The present invention discloses a trench-gate power device, comprising a plurality of gate trenches formed on a semiconductor substrate, with each gate trench and each mesa region arranged alternately. A first conductive material layer is formed in the gate trench, and a first through-hole contacting a source region is disposed at the top of the mesa region. The first conductive material layer on a first side of the first through-hole is connected to the gate electrode, and the top of the first conductive material layer on a second side of the first through-hole is connected to the source electrode. The first through-hole and the gate trench on the first side have a first spacing, and the gate trench on the second side have a second spacing, the second spacing being smaller than the first spacing. The present invention, by combining the electrode connection arrangement of the first conductive material layer of the trench gate and the through-hole arrangement at the top of the source region of the mesa region, can reduce the minimum achievable width of the mesa region, thereby reducing the width of the mesa region and thereby reducing the stepping distance between the gate trench and the mesa region, thereby improving device performance.

Description

Technical Field

[0001] The present invention relates to a semiconductor integrated circuit, in particular to a trench gate power device. Background Art

[0002] Currently, power devices fall into two main categories. One is unipolar devices, exemplified by MOSFETs, characterized by fast switching speeds. The other is bipolar devices, exemplified by IGBTs. When the device is on, the concentration of electrons and holes in the drift region is significantly increased due to the conductivity modulation effect. When the device is off, the excess carriers must be removed, resulting in slow switching speeds.

[0003] The development trend of power devices is to continuously increase their current density. In this way, when the current capacity is the same, the area of the power device is smaller, the corresponding capacitance is lower, and the switching speed is faster.

[0004] Power devices are typically composed of multiple unit cells connected in parallel. The most important way to increase their power density is to reduce the device pitch, which is the width of the unit cell structure. For power devices with trench gate structures, the device pitch is the sum of the gate trench width and spacing.

[0005] The shielded gate trench MOSFET is a trench gate MOSFET in which active polysilicon is formed in the gate trench. The source polysilicon acts as a source field plate to shield the polysilicon gate. Figure 1 FIG. 1 is a schematic diagram of the structure of an existing SGT MOSFET. In the existing SGT MOSFET, a plurality of gate trenches are formed on a semiconductor substrate 1. The semiconductor substrate 1 between the gate trenches forms a mesa region. The gate trenches and the mesa regions are alternately arranged. A gate trench and an adjacent mesa region form a unit structure. Figure 1 In the figure, the gate trench formation area is shown as the double-arrow line corresponding to the mark 101, and the gate trench is also represented by Trench; the mesa region formation area is shown as the double-arrow line corresponding to the mark 102, and the mesa region is also represented by Mesa.

[0006] A gate conductive material layer such as a polysilicon gate 6 is formed in the gate trench, and a gate dielectric layer 5 is spaced between the gate conductive material layer 6 and the side surface of the gate trench.

[0007] A channel region 7 is formed on the surface of the semiconductor substrate 1 in each of the mesa regions, and each of the gate trenches passes through the channel region 7;

[0008] The source region 8 is formed on the surface of the channel region 7 .

[0009] The interlayer film 11 covers the surface of the mesa region where the source region 8 is formed and the surface of the gate trench region where the gate conductive material layer 6 is formed.

[0010] A through hole (CT) is formed in the interlayer film 11 so as to pass through the interlayer film 11 .

[0011] A gate electrode and a source electrode are formed on the surface of the interlayer film 11 after patterning the front metal layer 10 .

[0012] The through hole includes a first through hole 9 provided on the top of the mesa region, the bottom of the first through hole 9 contacts the source region 8 and the bottom of the first through hole 9 passes through the source region 8 and contacts the channel region 7, and the top of the first through hole 9 is connected to the source. Figure 1 As shown in the figure, the first through hole 9 is set in the center of the mesa area, that is, when the layout is designed, the middle position of the first through hole 9 is aligned with the middle position of the mesa area, the distances d102 and d103 between the two sides of the first through hole 9 and the corresponding gate trench are equal, and the width of the first through hole 9 is d101. Such a symmetrically arranged structure can make Figure 1 The step of the structure shown is minimized, that is, both d102 and d103 can be taken as the minimum values that meet the requirements.

[0013] The spacings d102 and d103 are limited by the alignment process deviations between the first through-hole 9 and the corresponding gate trench, as well as the minimum spacing between the first through-hole 9 and the corresponding gate trench. Typically, a heavily doped contact region with a doping type opposite that of the channel region 7 is implanted at the bottom of the first through-hole 9. If the spacing between the first through-hole 9 and the gate trench is too small, the doping of the contact region can affect the doping of the channel region 7, thereby affecting the threshold voltage of the device. When the spacings d102 and d103 are greater than the minimum spacing value, the threshold voltage of the channel region 7 on the side of the gate trench corresponding to the first through-hole 9 is unaffected. The layout design values of the spacings d102 and d103 are greater than or equal to the sum of the alignment process deviations between the first through-hole 9 and the gate trench on the first side and the minimum spacing value.

[0014] The width of the mesa region is the sum of the intervals d102 and d103 and the width d101 of the first through hole 9 .

[0015] A first epitaxial layer 2 is further formed on the semiconductor substrate 1, and the gate trench is formed in the first epitaxial layer 2. The gate dielectric layer 5 includes an oxide layer.

[0016] The drain region is formed on the back side of the semiconductor substrate 1. Typically, the semiconductor substrate 1 is a heavily doped silicon substrate, and the drain region is directly formed by thinning the semiconductor substrate 1; alternatively, the drain region is formed by heavily doping the back side of the thinned semiconductor substrate 1 through a drain implantation process.

[0017] The first epitaxial layer 2 on the surface of the semiconductor substrate 1 between the drain region and the channel region 7 forms a drift region.

[0018] An active conductive material layer such as source polysilicon 4 and a shielding dielectric layer 3 are also formed in the gate trench. The shielding dielectric layer 3 is isolated between the source conductive material layer 4 and the inner surface of the corresponding gate trench.

[0019] The gate conductive material layer 6 and the source conductive material layer 4 form a top-bottom structure. The gate conductive material layer 6 is located on top of the source conductive material layer 4 and a conductive material interlayer dielectric layer is separated therebetween.

[0020] Taking an N-type device as an example, the semiconductor substrate 1 has N-type heavy doping; the first epitaxial layer 2 has N-type light doping, the channel region 7 is P-type doping, the source region 8 is N-type heavy doping, and P-type heavy doping is also formed at the bottom of the first contact hole 9a.

[0021] Figure 1 In FIG, the width of the gate trench corresponding to mark 101 and the width of the mesa region corresponding to mark 102 are .

[0022] To reduce back-diffusion of the semiconductor substrate 1, an arsenic substrate is typically selected. However, because the lowest resistivity currently achievable with phosphorus substrates is lower than that of arsenic substrates, phosphorus substrates are often used in applications where substrate resistance is relatively high, such as low-voltage devices below 40V. A thinner substrate not only improves heat dissipation for the device but also significantly reduces substrate resistance.

[0023] The biggest difference between SGT MOSFET and traditional Trench MOSFET is that a longitudinal source field plate, namely source polysilicon 4, is inserted laterally into the drift region 2.

[0024] The shielding dielectric layer 3 realizes the isolation between the source polysilicon 4 and the drift region 2. The shielding dielectric layer 3 needs to withstand the breakdown voltage of the device, and the voltage it can withstand can be roughly Make an estimate.

[0025] Here E crit ε is the critical electric field strength of silicon material, which is related to the width of Mesa. The wider the Mesa, the lower the corresponding critical electric field strength, and the narrower the Mesa, the higher the critical electric field strength.si is the dielectric constant of silicon material, ε dielectric is the dielectric constant of the insulating layer. ox is the thickness of the shielding dielectric layer 3. Selecting a shielding dielectric layer 3 with a lower dielectric constant can reduce its thickness, thereby lowering the device's pitch. Currently, the shielding dielectric layer 3 is most commonly made of silicon dioxide, but can also be a "sandwich" structure of silicon dioxide, silicon nitride, and silicon dioxide.

[0026] The source polysilicon 4 laterally depletes the drift region 2, significantly increasing the drift region's doping concentration without reducing the device's breakdown voltage. However, if the drift region's doping concentration is too high, the lateral electric field cannot completely deplete the drift region, resulting in a decrease in breakdown voltage. The doping concentration is inversely proportional to the width of the Mesa. Therefore, to improve power device performance, the Mesa width must be continuously reduced.

[0027] The specific on-resistance of a device is mainly composed of the following four parts:

[0028] Channel resistance.

[0029] Diffusion resistance mainly refers to the current of MOSFET spreading from along the channel surface to the entire drift region.

[0030] Both A and B can be reduced by reducing the thickness of the gate dielectric layer 5 and increasing the density of the channel. Reducing the width of Mesa can effectively reduce the pitch, thereby increasing the channel density.

[0031] The resistance of the drift region mainly depends on the doping concentration and thickness of the drift region. The thickness of the drift region is proportional to the breakdown voltage, and the doping concentration of the drift region is inversely proportional to the width of the Mesa.

[0032] Substrate resistance.

[0033] It can be seen that one of the most critical factors in reducing the resistance of MOSFET is to reduce the width of Mesa.

[0034] However, in practice, the width of Mesa is limited by the following aspects:

[0035] A. The width d101 of the first through hole 9 depends on the accuracy of the photolithography and the corresponding etching capability. Because the first through hole 9 needs to be etched through the interlayer film 11, the thickness of the interlayer film 11 is usually At the same time, in order to better prevent the parasitic transistor from turning on, it is necessary to continue etching the silicon downwards, that is, through the source region 8. The etching depth is usually The minimum width d101 of the first through hole 9 that can be achieved in the current process is usually around 0.15 μm.

[0036] B. The minimum distance between the first through hole 9 and the gate trench. This is because in order to achieve a better ohmic contact between the first through hole 9 and the channel region 7. After the first through hole 9 is formed, a high concentration through hole injection is usually required. The dose of the through hole injection is very high at 1e15 / cm 3 This is much larger than the current injection dose in the channel region. The injection dose in the channel region 7 is 1e12 to 1e13 / cm 3 To prevent through-hole injection from affecting the threshold voltage, a minimum distance between the two is required, usually around 0.1μm.

[0037] C. Alignment accuracy of the first through-hole 9. This is more pronounced for SGT MOSFETs. This is because the gate trench of SGT MOSFETs is relatively deep, and the shielding dielectric layer 3 is relatively thick. This results in high in-plane stress in the wafer and severe warping of the wafer surface. This significantly complicates alignment. Currently, CT alignment accuracy is typically controlled to around 0.1 μm.

[0038] Therefore, the width of Mesa is usually designed to be greater than 0.55μm, that is, (A+2B+2C), which makes it more difficult to further reduce the pitch of MOSFET.

[0039] The existing self-aligned through-hole technology can effectively avoid the deviation of CT alignment accuracy, but it increases the complexity of the process.

[0040] like Figure 2 As shown, it is a schematic diagram of the structure of an existing trench gate IGBT; a plurality of gate trenches are formed on a semiconductor substrate, and the semiconductor substrate between each of the gate trenches forms a mesa region, and each of the gate trenches and each of the mesa regions are arranged alternately, because one gate trench and an adjacent mesa region form a unit structure. Figure 2 In the figure, the gate trench formation area is shown as the double-arrow line corresponding to the mark 301, and the gate trench is also represented by Trench; the mesa region formation area is shown as the double-arrow line corresponding to the mark 302, and the mesa region is also represented by Mesa.

[0041] A first conductive material layer is formed in the gate trench. Figure 2 As shown by marks 206a and 206b, a gate dielectric layer 205 is spaced between the first conductive material layer and the side surface of the gate trench.

[0042] A channel region 207 is formed on the surface of the semiconductor substrate in each of the mesa regions, and each of the gate trenches passes through the channel region 207;

[0043] The source region 208 is formed on the surface of the channel region 207. The source region 208 is also generally referred to as an emitter region in an IGBT.

[0044] The interlayer film 211 covers the surface of the mesa region where the source region 208 is formed and the gate trench region where the first conductive material layer is formed.

[0045] A through hole is formed in the interlayer film 211 so as to pass through the interlayer film 211 .

[0046] A gate and a source are formed on the surface of the interlayer film 211 after patterning the front metal layer 210 .

[0047] The through hole includes a first through hole 209 arranged on the top of the mesa region, the bottom of the first through hole 209 contacts the source region 208 and the bottom of the first through hole 209 passes through the source region 208 and contacts the channel region 207, and the top of the first through hole 209 is connected to the source.

[0048] Each of the first through holes 209 has a first conductive material layer on both sides, the top of the first conductive material layer 206a on the first side of the first through hole 209 is connected to the gate through the corresponding through hole (not shown), and the top of the first conductive material layer 206b on the second side of the first through hole 209 is connected to the source through the corresponding through hole (not shown).

[0049] In the existing trench gate IGBT, the first through hole 209 is arranged in the middle of the mesa region and has a symmetrical structure on both sides, that is, the distances between the two sides of the first through hole 209 and the corresponding gate trench are equal. Figure 1 Like the conventional SGTMOSFET shown, Figure 2 The size limitation of the distance between the two sides of the first through hole 209 makes it impossible to further reduce the mesa area.

[0050] The semiconductor substrate includes a silicon substrate.

[0051] A first epitaxial layer 202 is further formed on the semiconductor substrate, and the gate trench is formed in the first epitaxial layer 202. The material of the first conductive material layer includes polysilicon. The gate dielectric layer 205 includes an oxide layer.

[0052] The collector region 201 is formed on the back side of the semiconductor substrate. Typically, the collector region 201 is formed by heavily doping the thinned semiconductor substrate with ions implanted on the back side.

[0053] The drift region is formed by the semiconductor substrate between the collector region 201 and the channel region 207. Typically, a buffer layer 203 is formed between the collector region 201 and the drift region.

[0054] A carrier storage (CS) layer 204 is further formed at the bottom of the channel region 207 .

[0055] Taking an N-type device as an example, the collector region 201 has a heavy P-type doping; the first epitaxial layer 202 has a light N-type doping, the channel region 207 is a P-type doping, the source region 208 is a heavy N-type doping, and a P-type heavy doping is also formed at the bottom of the first contact hole 209a.

[0056] like Figure 2 As shown, it is a schematic diagram of the structure of an existing trench gate IGBT; a plurality of gate trenches are formed on a semiconductor substrate, and the semiconductor substrate between each of the gate trenches forms a mesa region, and each of the gate trenches and each of the mesa regions are arranged alternately, because one gate trench and an adjacent mesa region form a unit structure. Figure 2 In the figure, the gate trench formation area is shown as the double-arrow line corresponding to the mark 301, and the gate trench is also represented by Trench; the mesa region formation area is shown as the double-arrow line corresponding to the mark 302, and the mesa region is also represented by Mesa.

[0057] A gate conductive material layer is formed in the gate trench, and the gate conductive material layer is as follows: Figure 2 As shown by marks 206a and 206b, a gate dielectric layer 205 is spaced between the gate conductive material layer and the side surface of the gate trench.

[0058] A channel region 207 is formed on the surface of the semiconductor substrate in each of the mesa regions, and each of the gate trenches passes through the channel region 207;

[0059] The source region 208 is formed on the surface of the channel region 207. The source region 208 is also generally referred to as an emitter region in an IGBT.

[0060] The interlayer film 211 covers the surface of the mesa region where the source region 208 is formed and the surface of the gate trench region where the gate conductive material layer is formed.

[0061] A through hole is formed in the interlayer film 211 so as to pass through the interlayer film 211 .

[0062] A gate and a source are formed on the surface of the interlayer film 211 after patterning the front metal layer 210 .

[0063] The through hole includes a first through hole 209 arranged on the top of the mesa region, the bottom of the first through hole 209 contacts the source region 208 and the bottom of the first through hole 209 passes through the source region 208 and contacts the channel region 207, and the top of the first through hole 209 is connected to the source.

[0064] Each of the first through holes 209 has a gate conductive material layer on both sides, the top of the gate conductive material layer 206a on the first side of the first through hole 209 is connected to the gate through the corresponding through hole (not shown), and the top of the gate conductive material layer 206b on the second side of the first through hole 209 is connected to the source through the corresponding through hole (not shown).

[0065] In the existing trench gate IGBT, the first through hole 209 is arranged in the middle of the mesa region and has a symmetrical structure on both sides, that is, the distances between the two sides of the first through hole 209 and the corresponding gate trench are equal. Figure 1 Like the conventional SGTMOSFET shown, Figure 2 The size limitation of the distance between the two sides of the first through hole 209 makes it impossible to further reduce the mesa area.

[0066] The semiconductor substrate includes a silicon substrate.

[0067] A first epitaxial layer 202 is further formed on the semiconductor substrate, and the gate trench is formed in the first epitaxial layer 202. The gate conductive material layer includes polysilicon. The gate dielectric layer 205 includes an oxide layer.

[0068] The collector region 201 is formed on the back side of the semiconductor substrate. Typically, the collector region 201 is formed by heavily doping the thinned semiconductor substrate with ions implanted on the back side.

[0069] The drift region is formed by the semiconductor substrate between the collector region 201 and the channel region 207. Typically, a buffer layer 203 is formed between the collector region 201 and the drift region.

[0070] A carrier storage (CS) layer 204 is further formed at the bottom of the channel region 207 .

[0071] Taking an N-type device as an example, the collector region 201 has a P-type heavy doping; the first epitaxial layer 202 has an N-type light doping, the channel region 207 is a P-type doping, the source region 208 is an N-type heavy doping, and a P-type heavy doping is also formed at the bottom of the first contact hole 209a, and the carrier storage layer 204 is an N-type heavy doping.

[0072] The carrier storage layer 204 acts as a barrier to hole diffusion when the IGBT is turned on. The hole doping concentration in the CS layer 204 increases rapidly due to the impedance of the built-in electric field, thereby increasing the hole concentration and reducing the voltage drop when the IGBT is turned on. The higher the doping concentration of the CS layer 204, the more pronounced the carrier storage effect. However, if the doping concentration of the CS layer 204 is too high, it cannot be completely depleted, resulting in a decrease in breakdown voltage. The maximum doping concentration that can be achieved in the CS layer 204 is inversely proportional to the width of the Mesa. Therefore, reducing the width of the Mesa, that is, reducing the pitch, has always been a continuous effort of the IGBT.

[0073] Because IGBT has a conductivity modulation effect when it is turned on, the current is large when the drain load is short-circuited. Currently, IGBT is generally required to have a short-circuit capability of 10μs. This requires reducing the current of IGBT when it is short-circuited. A common method is to use a dummy gate. The so-called dummy gate method is to connect part of the gate conductive material layer to the source. Figure 2 The gate conductive material layer 206a is partially connected to the gate. Figure 2 The gate conductive material layer 206b is connected to the source to ensure that the channel will not be turned on, thereby significantly reducing the current of the IGBT when the load is short-circuited.

[0074] exist Figure 2 The middle gate conductive material layer 206b is an Active Gate, the gate conductive material layer 206a is a Non-Active Gate, and the ratio of Active Gate to Non-Active Gate is 1:1. To further reduce the saturation current of the load short circuit, the ratio of Active Gate to Non-Active Gate can be 1:2, or even 1:3.

[0075] Reducing the width of Mesa can improve the performance of IGBT.

[0076] However, like the MOSFET described above, its Mesa width is also affected by the width of the first through hole 209 , the distance between the first through hole 209 and the gate trench, and the alignment accuracy.

[0077] IGBTs are more difficult to control in terms of alignment accuracy than MOSFETs. This is because IGBTs typically use melt-zone (FZ) single-crystal silicon substrate wafers, which are more susceptible to warping. Alignment accuracy is typically controlled to 0.2μm. This makes it very difficult to reduce the Mesa requirement for IGBTs. Summary of the Invention

[0078] The technical problem to be solved by the present invention is to provide a trench gate power device. Combined with the electrode connection arrangement of the first conductive material layer of the trench gate and the arrangement of the through hole at the top of the source region of the mesa region, the minimum value that the width of the mesa region can reach can be reduced, thereby reducing the width of the mesa region and thereby reducing the step formed by the gate trench and the mesa region, thereby improving the performance of the device.

[0079] In order to solve the above technical problems, in the trench gate power device provided by the present invention, a plurality of gate trenches are formed on the semiconductor substrate, the semiconductor substrate between each of the gate trenches constitutes a mesa region, and each of the gate trenches and each of the mesa regions are arranged alternately, because one gate trench and an adjacent mesa region constitute a unit structure.

[0080] A first conductive material layer is formed in the gate trench, and a gate dielectric layer is spaced between the first conductive material layer and a side surface of the gate trench.

[0081] A channel region is formed on the surface of the semiconductor substrate in each of the mesa regions, and each of the gate trenches passes through the channel region;

[0082] The source region is formed on the surface of the channel region.

[0083] An interlayer film covers the surface of the mesa region where the source region is formed and the surface of the gate trench region where the first conductive material layer is formed.

[0084] A through hole is formed in the interlayer film so as to pass through the interlayer film.

[0085] A gate electrode and a source electrode are formed on the surface of the interlayer film after patterning the front metal layer.

[0086] The through hole includes a first through hole arranged on the top of the mesa region, the bottom of the first through hole contacts the source region and the bottom of the first through hole passes through the source region and contacts the channel region, and the top of the first through hole is connected to the source electrode.

[0087] Each of the first through holes has a first conductive material layer on both sides, the top of the first conductive material layer on the first side of the first through hole is connected to the gate through the corresponding through hole, and the top of the first conductive material layer on the second side of the first through hole is connected to the source through the corresponding through hole.

[0088] The first through hole and the gate trench on the first side have a first distance, and the first through hole and the gate trench on the second side have a second distance, and the second distance is smaller than the first distance.

[0089] The first spacing is limited by the alignment process deviation between the first through hole and the gate trench on the first side, and the first spacing is limited by the minimum spacing value between the first through hole and the gate trench on the first side. When the first spacing is greater than the minimum spacing value, the threshold voltage of the channel region on the side of the gate trench on the first side of the first through hole is not affected; the layout design value of the first spacing is greater than or equal to the sum of the alignment process deviation between the first through hole and the gate trench on the first side and the minimum spacing value.

[0090] The second spacing is not limited by the minimum spacing value between the first through hole and the gate trench on the second side. The second spacing ensures that after alignment deviation occurs between the first through hole and the gate trench on the second side, the first side of the first through hole is located in the mesa area and the second side of the first through hole is located in the formation area of the gate trench on the mesa area or the second side of the first through hole.

[0091] The width of the mesa region is the sum of the first spacing, the width of the first through hole, and the second spacing. The width of the mesa region is reduced by reducing the second spacing, thereby reducing the step of the unit structure.

[0092] A further improvement is that the semiconductor substrate includes a silicon substrate or a silicon carbide substrate.

[0093] A further improvement is that a first epitaxial layer is further formed on the semiconductor substrate, and the gate trench is formed in the first epitaxial layer.

[0094] A further improvement is that the material of the first conductive material layer includes polysilicon.

[0095] A further improvement is that the gate dielectric layer includes an oxide layer.

[0096] A further improvement is that the trench gate power device is a trench gate MOSFET;

[0097] The drain region is formed on the back side of the semiconductor substrate.

[0098] The semiconductor substrate between the drain region and the channel region forms a drift region.

[0099] A further improvement is that the trench gate MOSFET is an SGT MOSFET.

[0100] An active conductive material layer and a shielding dielectric layer are also formed in the gate trench. The shielding dielectric layer is isolated between the source conductive material layer and the inner surface of the corresponding gate trench.

[0101] A further improvement is that the first conductive material layer and the source conductive material layer form a top-bottom structure, the first conductive material layer is located on top of the source conductive material layer and a conductive material dielectric layer is separated therebetween.

[0102] A further improvement is that the first through holes on both sides of the first conductive material layer connected to the source are connected to form an integral structure.

[0103] A further improvement is that the first conductive material layer and the source conductive material layer form a left-right structure;

[0104] The top surface of the source conductive material layer is exposed from the top surface of the gate trench. The first conductive material layer is located on the left and right sides of the source conductive material layer. A conductive material interlayer is interposed between the source conductive material layer and the first conductive material layer.

[0105] A further improvement is that the first conductive material layers on the left and right sides of the source conductive material layer located in the same gate trench are both connected to the source, or both connected to the gate, or one is connected to the source and the other is connected to the gate.

[0106] A further improvement is that when the first conductive material layers on the left and right sides of the source conductive material layer in the corresponding gate trench are connected to the source electrode, the first through holes on both sides of the gate trench are connected to form an integral structure.

[0107] A further improvement is that the trench gate power device is a trench gate IGBT;

[0108] A collector region is formed on the back side of the semiconductor substrate;

[0109] The semiconductor substrate between the collector region and the channel region forms a drift region.

[0110] A further improvement is that the first through holes on both sides of the first conductive material layer connected to the source are connected to form an integral structure.

[0111] A further improvement is that a carrier storage layer is formed at the bottom of the channel region.

[0112] A further improvement is that the source conductive material layer is made of polysilicon; and the shielding dielectric layer is made of silicon dioxide or silicon nitride.

[0113] The present invention makes a special arrangement for the electrode connection of the first conductive material layer in the gate trench on both sides of the first contact hole corresponding to the source region in the alternating arrangement structure formed by the gate trench and the mesa region, and sets the spacing between the first contact hole and the corresponding gate trench according to the electrode connection setting of the first conductive material layer on both sides, that is, the first spacing and the second spacing. The second spacing is not limited by the minimum spacing value of the first through hole and the gate trench on the second side, and the second side of the first through hole can be offset into the area of the gate trench. Therefore, the second spacing only needs to ensure that the first side of the first through hole is located at the gate trench after the alignment deviation occurs between the first through hole and the gate trench on the second side. The mesa region can be sufficient, and the second side of the first through hole can be located in the mesa region and in the formation region of the gate trench on the second side of the first through hole. Therefore, the second spacing of the present invention can be greatly reduced or even negative. The negative value of the second spacing indicates that the second side of the first through hole is located on the formation region of the gate trench. In this way, the width of the mesa region is only limited by the width of the first through hole itself and the first spacing, and is basically not limited by the second spacing. Therefore, the present invention can reduce the minimum value that the width of the mesa region can reach, thereby reducing the width of the mesa region and thereby reducing the step of forming the gate trench and the mesa region, thereby improving the performance of the device.

[0114] The present invention is well-suited for use in SGT MOSFETs. Due to the reduced stepping of the gate trench and mesa region, the device's specific on-resistance can be significantly reduced, primarily by reducing the drift region resistance. Although the first conductive material layer on the second side of the first through-hole is connected to the source, reducing the channel density and increasing the device's channel resistance and diffusion resistance, the reduced drift region resistance can compensate for the increased channel resistance and diffusion resistance. The first conductive material layer connected to the source can significantly reduce the device's gate capacitance, which can lower the MOSFET's figure of merit (FOM), i.e., Rsp*Qg. Rsp represents the device's specific on-resistance, and Qg represents the gate charge. Due to the reduced gate capacitance, Qg is reduced. This reduced FOM helps increase the MOSFET's switching speed and reduces losses during switching.

[0115] The present invention is well-suited for trench-gate IGBTs. Compared with MOSFETs, the alignment accuracy between the through-holes and gate trenches of IGBTs is more difficult to control. This is because the semiconductor substrate commonly used in IGBTs is an FZ wafer, which is more prone to warping. This increases the alignment accuracy range, i.e., the alignment process deviation, which greatly increases the difficulty in reducing the width of the mesa region of the IGBT. The present invention, by separately setting the first and second spacings of the through-holes, easily reduces the width of the mesa region, thereby improving the device performance of the IGBT. For example, after the width of the mesa region is reduced, the doping concentration of the carrier storage layer can be increased, thereby increasing the number of carrier storage layers and reducing the voltage drop when the IGBT is turned on. BRIEF DESCRIPTION OF THE DRAWINGS

[0116] The present invention will be further described in detail below with reference to the accompanying drawings and specific embodiments:

[0117] Figure 1 This is a schematic diagram of the structure of an existing SGT MOSFET;

[0118] Figure 2 It is a schematic diagram of the structure of an existing trench gate IGBT;

[0119] Figure 3 1 is a schematic structural diagram of an SGT MOSFET according to a first embodiment of the present invention;

[0120] Figure 4 1 is a schematic structural diagram of an SGT MOSFET according to a second embodiment of the present invention;

[0121] Figure 5 FIG. 1 is a schematic structural diagram of a trench gate IGBT according to a fifth embodiment of the present invention. DETAILED DESCRIPTION

[0122] The first embodiment of the present invention is an SGT MOSFET:

[0123] like Figure 3 2 is a schematic structural diagram of an SGT MOSFET according to a first embodiment of the present invention. The trench gate power device according to the first embodiment of the present invention is an SGT MOSFET, and is therefore also referred to as an SGT MOSFET according to the first embodiment of the present invention. A plurality of gate trenches are formed on a semiconductor substrate 1, and the semiconductor substrate 1 between the gate trenches forms a mesa region. The gate trenches and the mesa regions are alternately arranged, and a gate trench and an adjacent mesa region form a unit structure. Figure 3 In the figure, the gate trench formation area is shown as the double-arrow line corresponding to the mark 101, and the gate trench is also represented by Trench; the mesa region formation area is shown as the double-arrow line corresponding to the mark 102, and the mesa region is also represented by Mesa.

[0124] A first conductive material layer is formed in the gate trench. Figure 3 As shown by marks 6a and 6b, a gate dielectric layer 5 is spaced between the first conductive material layer and the side surface of the gate trench.

[0125] A channel region 7 is formed on the surface of the semiconductor substrate 1 in each of the mesa regions, and each of the gate trenches passes through the channel region 7;

[0126] The source region 8 is formed on the surface of the channel region 7 .

[0127] An interlayer film 11 covers the surface of the mesa region where the source region 8 is formed and the surface of the gate trench region where the first conductive material layer is formed.

[0128] A through hole is formed in the interlayer film 11 so as to pass through the interlayer film 11 .

[0129] A gate electrode and a source electrode are formed on the surface of the interlayer film 11 after patterning the front metal layer 10 .

[0130] The through hole includes a first through hole 9a arranged on the top of the mesa area, the bottom of the first through hole 9a contacts the source area 8 and the bottom of the first through hole 9a passes through the source area 8 and contacts the channel area 7, and the top of the first through hole 9a is connected to the source.

[0131] Each of the first through holes 9a has a first conductive material layer on both sides, the top of the first conductive material layer 6a on the first side of the first through hole 9a is connected to the gate through the corresponding through hole (not shown), and the top of the first conductive material layer 6b on the second side of the first through hole 9a is connected to the source through the corresponding through hole (not shown).

[0132] The first through hole 9a and the gate trench on the first side have a first distance d2, and the first through hole 9a and the gate trench on the second side have a second distance d3, wherein the second distance d3 is smaller than the first distance d2. The width of the first through hole 9a is d1.

[0133] The first spacing d2 is limited by the alignment process deviation between the first through hole 9a and the gate trench on the first side, and the first spacing d2 is limited by the minimum spacing value between the first through hole 9a and the gate trench on the first side. When the first spacing d2 is greater than the minimum spacing value, the threshold voltage of the channel region 7 on the side of the gate trench on the first side of the first through hole 9a is not affected; the layout design value of the first spacing d2 is greater than or equal to the sum of the alignment process deviation between the first through hole 9a and the gate trench on the first side and the minimum spacing value.

[0134] The second spacing d3 is not limited by the minimum spacing between the first through hole 9a and the gate trench on the second side. The second spacing d3 ensures that, after the first through hole 9a and the gate trench on the second side are misaligned, the first side of the first through hole 9a is located in the mesa region and the second side of the first through hole 9a is located in the formation region of the gate trench on the mesa region or the second side of the first through hole 9a. That is, in the first embodiment of the present invention, the first through hole 9a can move laterally toward the gate trench on its second side, and the second side of the first through hole 9a can also move to the formation region of the gate trench. It is only necessary to ensure that the first side of the first through hole 9a remains located in the mesa region and contacts the source region 8 after the first through hole 9a is misaligned toward its second side.

[0135] The width of the mesa region is the sum of the first distance d2, the width d1 of the first through-hole 9a, and the second distance d3. By reducing the second distance d3, the width of the mesa region is reduced, thereby reducing the stepping of the cell structure. The second distance d3 can also be a negative value, that is, the distance between the second side of the first through-hole 9a and the corresponding side of the gate trench when the second side of the first through-hole 9a moves to the region of the gate trench.

[0136] In the first embodiment of the present invention, the semiconductor substrate 1 includes a silicon substrate or a silicon carbide substrate.

[0137] A first epitaxial layer 2 is further formed on the semiconductor substrate 1, and the gate trench is formed in the first epitaxial layer 2. The material of the first conductive material layer includes polysilicon. The gate dielectric layer 5 includes an oxide layer.

[0138] The drain region is formed on the back side of the semiconductor substrate 1. In the first embodiment of the present invention, the semiconductor substrate 1 is heavily doped, and the drain region is directly formed by thinning the semiconductor substrate 1; or, the drain region is formed by heavily doping the back side of the thinned semiconductor substrate 1 through drain implantation.

[0139] The semiconductor substrate 1 between the drain region and the channel region 7 forms a drift region.

[0140] An active conductive material layer 4 and a shielding dielectric layer 3 are also formed in the gate trench. The shielding dielectric layer 3 isolates the source conductive material layer 4 from the inner surface of the corresponding gate trench. The source conductive material layer 4 is made of polysilicon, and the shielding dielectric layer 3 is made of silicon dioxide or silicon nitride.

[0141] The first conductive material layer and the source conductive material layer 4 form a top-bottom structure. The first conductive material layer is located on top of the source conductive material layer 4 and a conductive material dielectric layer is separated therebetween.

[0142] Taking an N-type device as an example, the semiconductor substrate 1 is heavily N-type doped; the first epitaxial layer 2 is lightly N-type doped; the channel region 7 is P-type doped; the source region 8 is heavily N-type doped; and a heavily P-type doped region is also formed at the bottom of the first contact hole 9a. A P-type device can be obtained by swapping the N-type and P-type doping types described above.

[0143] In the first embodiment of the present invention, in the alternating arrangement structure formed by the gate trench and the mesa region, a special arrangement is made for the electrode connection of the first conductive material layer in the gate trench on both sides of the first contact hole corresponding to the source region 8, and the spacing between the first contact hole and the corresponding gate trench, namely the first spacing d2 and the second spacing d3, is set according to the electrode connection arrangement of the first conductive material layer on both sides. The second spacing d3 is not limited by the minimum spacing value of the first through hole 9a and the gate trench on the second side, and the second side of the first through hole 9a can be offset into the area of the gate trench. Therefore, the second spacing d3 only needs to ensure that the first through hole 9a of the first through hole 9a is aligned with the gate trench on the second side after the first through hole 9a and the gate trench on the second side have an alignment deviation. The second side of the first through hole 9a can be located in the mesa area, and the second side of the first through hole 9a can be located in the mesa area and in the formation area of the gate trench on the second side of the first through hole 9a. Therefore, the second spacing d3 of the present invention can be greatly reduced or even negative. The negative value of the second spacing d3 indicates that the second side of the first through hole 9a is located on the formation area of the gate trench. In this way, the width of the mesa area is only limited by the width of the first through hole 9a itself and the first spacing d2, and is basically not limited by the second spacing d3. Therefore, the present invention can reduce the minimum value that the width of the mesa area can reach, thereby reducing the width of the mesa area and thereby reducing the step of forming the gate trench and the mesa area, thereby improving the performance of the device.

[0144] In the first embodiment of the SGT MOSFET of the present invention, the reduction in the step size of the gate trench and mesa region significantly reduces the device's specific on-resistance, primarily by reducing the drift region resistance. Although the first conductive material layer on the second side of the first through-hole 9a is connected to the source, reducing the channel density and increasing the device's channel resistance and diffusion resistance, the reduced drift region resistance compensates for the increased channel resistance and diffusion resistance. The first conductive material layer connected to the source significantly reduces the device's gate capacitance, which can lower the MOSFET's figure of merit (FOM), namely, Rsp*Qg. Rsp represents the device's specific on-resistance, and Qg represents the gate charge. Due to the reduced gate capacitance, Qg is reduced. This reduced FOM helps increase the MOSFET's switching speed and reduces losses during switching.

[0145] and Figure 1 Compared with the existing structure shown, in the first embodiment of the present invention, the first conductive material layer is no longer connected to the gate and serves as a gate conductive material layer such as a polysilicon gate. Instead, the first conductive material layer 6a is connected to the gate and the first conductive material layer 6b is connected to the source.

[0146] At the same time, the first through hole 9a is not in the middle of the Mesa, but is close to the first conductive material layer 6b and far from the first conductive material layer 6a.

[0147] The benefits of doing this are:

[0148] 1. The minimum distance between the first through hole 9a and the gate trench, or the minimum spacing value, such as the previously mentioned 0.1 μm, only needs to be considered on one side. This is the distance between the first through hole 9a and the first conductive material layer 6a. The distance between the first through hole 9a and the first conductive material layer 6b can be very close because there is no channel there, and there is no need to worry about the impact of the through hole injection of the first through hole 9a on the threshold voltage.

[0149] 2. The deviation of the alignment accuracy of the first through hole 9a will cause the actual position of the first through hole 9a to deviate from the original design value. Figure 3 In this structure, only the process variations between the first through-hole 9a and the first conductive material layer 6a need to be considered, and not the process variations between the first through-hole 9a and the first conductive material layer 6b. Even in the worst case, it does not matter if the first through-hole 9a contacts the first conductive material layer 6b, because the first conductive material layer 6b is already connected to the source electrode, and they are at the same potential.

[0150] Therefore and Figure 1 Compared with the corresponding existing structure, under the process conditions of the first embodiment of the present invention, the minimum width of the Mesa is 0.55 μm. By adopting this structure, the minimum width of the Mesa can be greatly reduced.

[0151] One possible implementation is to reduce the width of Mesa to 0.4μm, and the distance between the first through-hole 9a and the first conductive material layer 6a to 0.2μm. Considering the alignment accuracy of the first through-hole 9a of 0.1μm and the fact that the through-hole injection of the first through-hole 9a has the least impact on the threshold of 0.1μm, the width of the first through-hole 9a itself is 0.15μm, and the distance between the first through-hole 9a and the first conductive material layer 6b is 0.05μm. The distance between the first through-hole 9a and the first conductive material layer 6b is only 0.05μm. Thus, in the worst case scenario of the alignment accuracy of the first through-hole 9a, 0.1μm of the first through-hole 9a will fall above Mesa, and another 0.05μm will fall above the gate dielectric layer 5 of the gate trench. If the gate dielectric layer 5 is relatively thin, it may even fall above the first conductive material layer 6b. However, this has no impact on the device.

[0152] Another benefit of doing this is:

[0153] A portion of the first conductive material layer 6b is connected to the source. This will increase the channel resistance and diffusion resistance due to the reduction in channel density. However, the reduction in Mesa width will reduce the Pitch, which can compensate for the deterioration of the on-resistance caused by the increase in channel resistance. More importantly, the first conductive material layer 6b is connected to the source, which can greatly reduce the gate capacitance of the MOSFET, which will bring about the MOSFET FOM value R sp *Q g This helps to increase the switching speed of the MOSFET and reduce the loss of the MOSFET during the switching process.

[0154] The second embodiment of the present invention is an SGTMOSFET:

[0155] The difference between the SGTMOSFET device of the second embodiment of the present invention and the SGTMOSFET of the first embodiment of the present invention is that the SGTMOSFET device of the second embodiment of the present invention has the following features:

[0156] like Figure 4 , which is a schematic structural diagram of an SGTMOSFET according to a second embodiment of the present invention, wherein the first through holes 9b on both sides of the first conductive material layer 6b connected to the source are connected to form an integral structure.

[0157] That is to say Figure 3 The second sides of the first through holes 9a of the two adjacent mesa regions extend toward the formation area of the adjacent first conductive material layer 6b and merge together to form Figure 4 The first through hole 9b does not need to be set Figure 3The second spacing d3 in the table area can further reduce the width of the mesa area. Figure 4 The width d4 of the first through hole 9b is greater than Figure 3 The width d1 of the first through hole 9b in the embodiment of the present invention can reduce the complexity of the process of forming the first through hole 9b, thereby reducing the cost.

[0158] The third embodiment of the present invention is an SGT MOSFET:

[0159] The SGT MOSFET device according to the third embodiment of the present invention differs from the SGT MOSFET according to the first embodiment of the present invention in that the SGT MOSFET device according to the third embodiment of the present invention has the following features:

[0160] The first conductive material layer and the source conductive material layer 4 form a left-right structure;

[0161] The top surface of the source conductive material layer 4 is exposed from the top surface of the gate trench. The first conductive material layer is located on the left and right sides of the source conductive material layer 4. A conductive material dielectric layer is interposed between the source conductive material layer 4 and the first conductive material layer.

[0162] The first conductive material layers on the left and right sides of the source conductive material layer 4 located in the same gate trench are both connected to the source, or both connected to the gate, or one is connected to the source and the other is connected to the gate.

[0163] SGT MOSFET according to the fourth embodiment of the present invention:

[0164] The SGT MOSFET device according to the fourth embodiment of the present invention differs from the SGT MOSFET according to the third embodiment of the present invention in that the SGT MOSFET device according to the fourth embodiment of the present invention has the following features:

[0165] Based on the third embodiment of the present invention, the first conductive material layers on the left and right sides of the source conductive material layer 4 in the corresponding gate trench are connected to the source electrode, and the first through holes on both sides of the gate trench are connected into an integral structure. The first through hole in the fourth embodiment of the present invention is also the same as the first through hole 9b in the second embodiment of the present invention. Figure 4 The structure of the fourth embodiment of the present invention can be obtained by changing the upper and lower structure composed of the first conductive material layer and the source conductive material layer 4 into a left and right structure.

[0166] The fifth embodiment of the present invention IGBT:

[0167] Figure 51 is a schematic structural diagram of a trench gate IGBT according to a fifth embodiment of the present invention. The trench gate power device according to the fifth embodiment of the present invention is an IGBT, and is therefore also referred to as the IGBT according to the fifth embodiment of the present invention. A plurality of gate trenches are formed on a semiconductor substrate, and the semiconductor substrate between the gate trenches constitutes a mesa region. The gate trenches and the mesa regions are alternately arranged, and a gate trench and an adjacent mesa region constitute a unit structure. Figure 5 In the figure, the gate trench formation area is shown as the double-arrow line corresponding to the mark 301, and the gate trench is also represented by Trench; the mesa region formation area is shown as the double-arrow line corresponding to the mark 302, and the mesa region is also represented by Mesa.

[0168] A first conductive material layer is formed in the gate trench. Figure 5 As shown by marks 206a and 206b, a gate dielectric layer 205 is spaced between the first conductive material layer and the side surface of the gate trench.

[0169] A channel region 207 is formed on the surface of the semiconductor substrate in each of the mesa regions, and each of the gate trenches passes through the channel region 207;

[0170] The source region 208 is formed on the surface of the channel region 207. The source region 208 is also generally referred to as an emitter region in an IGBT.

[0171] The interlayer film 211 covers the surface of the mesa region where the source region 208 is formed and the gate trench region where the first conductive material layer is formed.

[0172] A through hole is formed in the interlayer film 211 so as to pass through the interlayer film 211 .

[0173] A gate and a source are formed on the surface of the interlayer film 211 after patterning the front metal layer 210 .

[0174] The through hole includes a first through hole 209a arranged on the top of the mesa region, the bottom of the first through hole 209a contacts the source region 208 and the bottom of the first through hole 209a passes through the source region 208 and contacts the channel region 207, and the top of the first through hole 209a is connected to the source.

[0175] Each of the first through holes 209a has a first conductive material layer on both sides, the top of the first conductive material layer 206a on the first side of the first through hole 209a is connected to the gate through the corresponding through hole (not shown), and the top of the first conductive material layer 206b on the second side of the first through hole 209a is connected to the source through the corresponding through hole (not shown).

[0176] The first through hole 209a and the gate trench on the first side have a first distance, and the first through hole 209a and the gate trench on the second side have a second distance, and the second distance is smaller than the first distance.

[0177] The first spacing is limited by the alignment process deviation between the first through hole 209a and the gate trench on the first side, and the first spacing is limited by the minimum spacing value between the first through hole 209a and the gate trench on the first side. When the first spacing is greater than the minimum spacing value, the threshold voltage of the channel region 207 on the side of the gate trench on the first side of the first through hole 209a is not affected; the layout design value of the first spacing is greater than or equal to the sum of the alignment process deviation between the first through hole 209a and the gate trench on the first side and the minimum spacing value.

[0178] The second spacing is not limited by the minimum spacing between the first through hole 209a and the gate trench on the second side. The second spacing ensures that, after the first through hole 209a and the gate trench on the second side are misaligned, the first side of the first through hole 209a is located in the mesa region and the second side of the first through hole 209a is located in the formation region of the gate trench on the mesa region or the second side of the first through hole 209a. That is, in the fifth embodiment of the present invention, the first through hole 209a can move laterally toward the gate trench on its second side, and the second side of the first through hole 209a can also move to the formation region of the gate trench. It is only necessary to ensure that the first side of the first through hole 209a can still be located in the mesa region and contact the source region 208 after the first through hole 209a is misaligned toward its second side.

[0179] The width of the mesa region is the sum of the first spacing, the width of the first through-hole 209a, and the second spacing. By reducing the second spacing, the width of the mesa region is reduced, thereby reducing the stepping of the cell structure. The second spacing can also be a negative value, that is, the spacing between the second side of the first through-hole 209a and the corresponding side of the gate trench when the second side of the first through-hole 209a moves to the region of the gate trench.

[0180] In a fifth embodiment of the present invention, the semiconductor substrate includes a silicon substrate or a silicon carbide substrate.

[0181] A first epitaxial layer 202 is further formed on the semiconductor substrate, and the gate trench is formed in the first epitaxial layer 202. The material of the first conductive material layer includes polysilicon. The gate dielectric layer 205 includes an oxide layer.

[0182] The collector region 201 is formed on the back side of the semiconductor substrate. In the fifth embodiment of the present invention, the collector region 201 is formed by heavily doping ions by implanting the thinned semiconductor substrate into the back side.

[0183] The drift region is formed by the semiconductor substrate between the collector region 201 and the channel region 207. Typically, a buffer layer 203 is formed between the collector region 201 and the drift region.

[0184] A carrier storage layer 204 is further formed at the bottom of the channel region 207 .

[0185] Taking an N-type device as an example, the collector region 201 is heavily P-type doped; the first epitaxial layer 202 is lightly N-type doped; the channel region 207 is P-type doped; the source region 208 is heavily N-type doped; the carrier storage layer 204 is heavily N-type doped; and a heavily P-type doped region is also formed at the bottom of the first contact hole 209a. A P-type device can be obtained by swapping the N-type and P-type doping types described above.

[0186] Compared with MOSFET, the alignment accuracy between the through hole 209a and the gate trench of the IGBT in the fifth embodiment of the present invention is more difficult to control. This is because the semiconductor substrate commonly used in the IGBT is an FZ wafer, which is more prone to warping, resulting in a larger alignment accuracy range, that is, alignment process deviation. This makes it very difficult to reduce the width of the mesa region of the IGBT. The fifth embodiment of the present invention can easily reduce the width of the mesa region by separately setting the first and second spacings of the through holes, thereby improving the device performance of the IGBT. For example, after the width of the mesa region is reduced, the doping concentration of the carrier storage layer can be increased, thereby increasing the number of carrier storage layers and reducing the voltage drop when the IGBT is turned on.

[0187] The sixth embodiment of the present invention is an IGBT:

[0188] The difference between the IGBT of the sixth embodiment of the present invention and the IGBT of the fifth embodiment of the present invention is that the IGBT of the sixth embodiment of the present invention has the following features:

[0189] The first through holes 209a on both sides of the first conductive material layer 206b connected to the source are connected to form an integral structure.

[0190] The present invention has been described in detail above by means of specific embodiments, but these do not constitute limitations of the present invention. Without departing from the principles of the present invention, those skilled in the art may make many variations and improvements, which should also be considered as the scope of protection of the present invention.

Claims

1. A trench gate power device, characterized in that: A plurality of gate trenches are formed on a semiconductor substrate, wherein the semiconductor substrate between the gate trenches forms a mesa region, the gate trenches and the mesa regions are alternately arranged, and a unit structure is formed by one gate trench and an adjacent mesa region; A first conductive material layer is formed in the gate trench, and a gate dielectric layer is spaced between the first conductive material layer and a side surface of the gate trench; A channel region is formed on the surface of the semiconductor substrate in each of the mesa regions, and each of the gate trenches passes through the channel region; A source region is formed on the surface of the channel region; An interlayer film covers the surface of the mesa region where the source region is formed and the surface of the gate trench region where the first conductive material layer is formed; forming a through hole in the interlayer film and passing through the interlayer film; A gate electrode and a source electrode are formed on the surface of the interlayer film after patterning the front metal layer; The through hole includes a first through hole provided on the top of the mesa region, the bottom of the first through hole contacts the source region and the bottom of the first through hole passes through the source region and contacts the channel region, and the top of the first through hole is connected to the source electrode; Each of the first through holes has a first conductive material layer on both sides, the top of the first conductive material layer on the first side of the first through hole is connected to the gate through the corresponding through hole, and the top of the first conductive material layer on the second side of the first through hole is connected to the source through the corresponding through hole; The first through hole and the gate trench on the first side have a first distance, the first through hole and the gate trench on the second side have a second distance, and the second distance is smaller than the first distance; The first spacing is limited by an alignment process deviation between the first through hole and the gate trench on the first side, and the first spacing is limited by a minimum spacing value between the first through hole and the gate trench on the first side. When the first spacing is greater than the minimum spacing value, the threshold voltage of the channel region on the side of the gate trench on the first side of the first through hole is not affected. A layout design value of the first spacing is greater than or equal to the sum of the alignment process deviation between the first through hole and the gate trench on the first side and the minimum spacing value. The second distance is not limited by a minimum distance between the first through hole and the gate trench on the second side, and the second distance ensures that, after an alignment deviation occurs between the first through hole and the gate trench on the second side, the first side of the first through hole is located in the mesa region and the second side of the first through hole is located in a formation region of the gate trench in the mesa region or on the second side of the first through hole; The width of the mesa region is the sum of the first spacing, the width of the first through hole, and the second spacing. The width of the mesa region is reduced by reducing the second spacing, thereby reducing the step of the unit structure.

2. The trench gate power device according to claim 1, wherein: The semiconductor substrate includes a silicon substrate or a silicon carbide substrate.

3. The trench gate power device according to claim 2, wherein: A first epitaxial layer is further formed on the semiconductor substrate, and the gate trench is formed in the first epitaxial layer.

4. The trench gate power device according to claim 2, wherein: The first conductive material layer is made of polysilicon.

5. The trench gate power device according to claim 2, wherein: The gate dielectric layer includes an oxide layer.

6. The trench gate power device according to claim 1, 2 or 3, wherein: The trench gate power device is a trench gate MOSFET; A drain region is formed on the back side of the semiconductor substrate; The semiconductor substrate between the drain region and the channel region forms a drift region.

7. The trench gate power device according to claim 6, wherein: The trench gate MOSFET is an SGTMOSFET; An active conductive material layer and a shielding dielectric layer are also formed in the gate trench. The shielding dielectric layer is isolated between the source conductive material layer and the inner surface of the corresponding gate trench.

8. The trench gate power device according to claim 7, wherein: The first conductive material layer and the source conductive material layer form a top-bottom structure. The first conductive material layer is located on top of the source conductive material layer and a conductive material dielectric layer is separated therebetween.

9. The trench gate power device according to claim 8, wherein: The first through holes on both sides of the first conductive material layer connected to the source are connected to form an integral structure.

10. The trench gate power device according to claim 7, wherein: The first conductive material layer and the source conductive material layer form a left-right structure; The top surface of the source conductive material layer is exposed from the top surface of the gate trench. The first conductive material layer is located on the left and right sides of the source conductive material layer. A conductive material interlayer is interposed between the source conductive material layer and the first conductive material layer.

11. The trench gate power device according to claim 10, wherein: The first conductive material layers on the left and right sides of the source conductive material layer located in the same gate trench are both connected to the source, or both connected to the gate, or one is connected to the source and the other is connected to the gate.

12. The trench gate power device according to claim 11, wherein: When the first conductive material layers on the left and right sides of the source conductive material layer in the corresponding gate trench are connected to the source electrode, the first through holes on both sides of the gate trench are connected into an integral structure.

13. The trench gate power device according to claim 1, 2 or 3, wherein: The trench gate power device is a trench gate IGBT; A collector region is formed on the back side of the semiconductor substrate; The semiconductor substrate between the collector region and the channel region forms a drift region.

14. The trench gate power device according to claim 13, wherein: The first through holes on both sides of the first conductive material layer connected to the source are connected to form an integral structure.

15. The trench gate power device according to claim 13, wherein: A carrier storage layer is also formed at the bottom of the channel region.

16. The trench gate power device according to claim 7, wherein: The material of the source conductive material layer includes polysilicon; the material of the shielding dielectric layer includes silicon dioxide or silicon nitride.

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