A power semiconductor device and an electronic apparatus

Abstract

The application provides a power semiconductor device and an electronic device. The power semiconductor device comprises an epitaxial layer and two field effect transistors. The epitaxial layer is provided with a groove, and the two field effect transistors are mirror-symmetrical. Each field effect transistor comprises a first MOS structure and a second MOS structure connected in series. The first channel of the first MOS structure and the second channel of the second MOS structure are arranged at intervals along the depth direction of the groove; and the first gate of the first MOS structure and the second gate of the second MOS structure are arranged at intervals along the depth direction of the groove. In the above technical solution, the first gate and the second gate are arranged longitudinally along the depth direction of the groove, thereby reducing the size of the field effect transistor occupied in the transverse direction. The first MOS structure and the second MOS structure share a drift region, thereby reducing the resistance of the drift region; and the two identical field effect transistors are symmetrically connected in parallel back-to-back, thereby reducing the specific on-resistance of the power semiconductor device per unit area.

Description

TECHNICAL FIELD

[0001] The present application relates to the technical field of circuit, in particular to a power semiconductor device and electronic equipment. BACKGROUND

[0002] With the development of power integrated circuit and equipment towards miniaturization, as one of the core electronics of power integrated circuit, power semiconductor devices also show the development requirements of high integration, miniaturization, high performance and low cost. For example, as the core component of the battery management and charging system protection circuit in electronic equipment, the power semiconductor device can effectively protect the battery and charging load from over-discharge, over-charge and over-current, and realize output short circuit protection.

[0003] The power semiconductor device in the battery management and charging system protection circuit is mainly a switching device of metal oxide semiconductor field effect transistor (MOSFET) prepared by silicon material. And the field effect transistor applied in the battery management and charging system protection circuit needs to have bidirectional blocking and bidirectional conduction function to bidirectionally protect lithium battery and load circuit. The common solution in the industry is to symmetrically connect two MOSFETs with the same structure in series at the common drain to form a common drain type power semiconductor device. Figure 1 It is a semiconductor device with two MOSFETs connected in series at the common drain in a vertical type. The main structure of the power semiconductor device includes a substrate 4 and an epitaxial layer 3 arranged on the substrate 4. The substrate 4 is a silicon substrate, and the epitaxial layer 3 is a silicon epitaxial layer. Each MOSFET structure includes a gate 1 and a source 2 arranged on the surface of the epitaxial layer 3, and a channel (not shown in the figure) located in the epitaxial layer 3. A back metal is arranged at the bottom of the substrate as a common drain electrode of the two MOSFETs. A drift region (not shown in the figure) corresponding to each MOSFET is arranged in the epitaxial layer 3. Among them, the two sources 2 are respectively the input end and the output end of the power semiconductor device, and the two gates 1 control the conduction or turn-off of the input end MOSFET and the output end MOSFET.

[0004] In the off state, the gate of the output end (or input end) MOSFET is at a high level, the input end (or output end) MOSFET is turned on, but the gate of the input end (or output end) MOSFET is at a low level, the input end (or output end) MOS structure is turned off, realizing bidirectional blocking voltage resistance between the source of one MOSFET (output end) and the source of another MOSFET (input end). In the on state, the gates of the input end MOSFET and the output end MOSFET are at a high level at the same time, and the input end MOSFET and the output end MOSFET are turned on at the same time. For example Figure 1The current flows from the source 2 of one MOSFET through the channel, the drift region (located in the epitaxial layer 3, not shown in the figure), and then flows through the substrate 4, the drift region and the channel of another MOSFET, and then flows to the source 2 of the other MOSFET, as indicated by the arrowed lines in the figure.

[0005] In the on state of the power semiconductor device, the current flows through the drift region in the epitaxial layer 3 twice and the substrate 4 once in the current flow path, and the resistance of the drift region in the epitaxial layer 3 and the substrate resistance of the substrate 4 increase the on-resistance of the overall power semiconductor device. As the process size of the metal-oxide-semiconductor field-effect transistor continues to shrink, the proportion of the resistance of the drift region and the substrate in the total resistance also increases. In addition, the gate 1, the source 2, and other structures are arranged on the surface of the epitaxial layer and arranged laterally, which wastes the chip area of the power semiconductor device, further increases the on-resistance per unit area and the cost per unit area of the device, and makes it difficult to miniaturize the power semiconductor device. In the same device area, the loss and temperature rise of the battery management and charging system protection circuit will be increased, and the charging efficiency will be reduced. SUMMARY

[0006] The present application provides a power semiconductor device and an electronic device, which are used to improve the on-resistance per unit area of the device and make the power semiconductor device develop towards miniaturization under the condition of meeting certain voltage withstand requirements of the power semiconductor device.

[0007] In a first aspect, a power semiconductor device is provided, which includes a first doped type epitaxial layer and two common-drain metal oxide semiconductor field effect transistors; wherein the first doped type epitaxial layer is provided with a trench; and the two common-drain metal oxide semiconductor field effect transistors are symmetrically back-to-back connected in parallel to form a cell. Each common-drain metal oxide semiconductor field effect transistor includes a first metal oxide semiconductor structure and a second metal oxide semiconductor structure arranged along the depth direction of the trench, and the first metal oxide semiconductor structure and the second metal oxide semiconductor structure are connected in series in common drain. The first metal oxide semiconductor structure includes a first source, a first channel and a first gate. The first channel is provided in the first doped type epitaxial layer, the first source is connected to the first channel, and the first source and the first channel are located on the same side of the trench. The first channel is a second doped type region provided in the first doped type epitaxial layer. The first gate is provided in the trench and is used to control the conduction of the first channel. The second metal oxide semiconductor structure includes a second source, a second channel and a second gate. The second source is located at the bottom of the trench, the second channel is located in the first doped type epitaxial layer and connected to the second channel. The second channel is a second doped type region provided in the first doped type epitaxial layer. The second gate is provided in the trench and is used to control the conduction of the second channel. In the specific arrangement of the above structure, the first channel and the second channel are longitudinally spaced along the depth direction of the trench, and the part of the first doped type epitaxial layer between the first channel and the second channel is a drift region. The drift region is located on the same side of the trench as the first channel and is arranged vertically longitudinally with the first channel. The second gate and the first gate are longitudinally spaced along the depth direction of the trench. When the first gate and the second gate control the conduction of the first channel and the second channel respectively, the current flows along the arrangement direction of the first source, the first channel, the part of the first doped type epitaxial layer (drift region) between the first channel and the second channel, the second channel and the second source, or in the opposite direction. In addition, in the specific arrangement of the two common-drain metal oxide semiconductor field effect transistors, the second sources of the two common-drain metal oxide semiconductor field effect transistors are shared, and the two first channels of the two common-drain metal oxide semiconductor field effect transistors are arranged on opposite sides of the trench; and the two first sources are arranged on opposite sides of the trench. In the above technical solution, the first gate and the second gate are longitudinally arranged along the depth direction of the trench, thereby reducing the size of the common-drain metal oxide field effect transistor occupied in the lateral direction. In addition, the first metal oxide semiconductor structure and the second metal oxide semiconductor structure share the drift region, which reduces the resistance of the drift region, and further reduces the specific on-resistance per unit area of the power semiconductor device.

[0008] In one embodiment, the first gate oxide layer and the second gate oxide layer are disposed on sidewalls of the trench. The first gate oxide layer is disposed on the sidewalls of the trench to form a first gate structure along the depth of the trench, thereby reducing the lateral dimension of the power semiconductor device.

[0009] In one embodiment, the first gate oxide layer and the second gate oxide layer are disposed on sidewalls of the trench. The first gate oxide layer is disposed on the sidewalls of the trench to form a first gate structure along the depth of the trench, thereby reducing the lateral dimension of the power semiconductor device.

[0010] In one embodiment, the trench is filled with a filling layer wrapping the first gate, the second gate and the second source. The first gate, the second gate and the second source are isolated by the filling layer.

[0011] In one embodiment, the second source is exposed outside the filling layer, and the portion of the second source exposed outside the filling layer serves as a connection terminal. This facilitates connection with external circuits.

[0012] In one embodiment, the first source is partially exposed outside the first doped type epitaxial layer, and the portion of the first source exposed outside the first doped type epitaxial layer serves as a connection terminal. This facilitates connection with external circuits.

[0013] In one embodiment, the first doped type epitaxial layer is provided with a first source contact region, and the first channel is connected to the first source through the first source contact region. The first source contact region improves the contact effect between the first source and the first channel.

[0014] In one embodiment, the first source contact region comprises a heavily doped region of the first doped type and a heavily doped region of the second doped type.

[0015] In one embodiment, the first doped type epitaxial layer is provided with a second source contact region, and the second channel is connected to the second source through the second source contact region. The second source contact region improves the contact effect between the second source and the second channel.

[0016] In one embodiment, the second source contact region comprises a heavily doped region of the first doped type and a heavily doped region of the second doped type.

[0017] In one specific implementation, the heavily doped region of the second doping type of the second source contact region is located below the bottom of the second source, and the heavily doped region of the first doping type of the second source contact region is located on one side of the second source.

[0018] In one specific implementation, the trench is a straight trench, and the first gate and the second gate are longitudinally arranged along the depth direction of the trench. The size of the common-drain metal oxide semiconductor field effect transistor is reduced, and the arrangement density of the device is improved.

[0019] In one specific implementation, the first gate and the second gate are staggered along the depth direction of the trench. The first gate oxide layer, the second gate oxide layer, the first gate and the second gate are conveniently arranged.

[0020] In one specific implementation, the trench is a T-shaped trench, the second gate is arranged at the bottom of the T-shaped trench, and the first gate is arranged on the step surface of the T-shaped trench. The first gate and the second gate are conveniently arranged.

[0021] In a second aspect, an electronic device is provided, which includes a battery and a charging protection circuit connected with the battery, and the charging protection circuit includes the power semiconductor device of any one of the above technical solutions. In the above technical solution, the drift region, the first gate and the second gate are longitudinally arranged along the depth direction of the trench, thereby reducing the size of the common-drain metal oxide semiconductor field effect transistor in the lateral direction, and in addition, the first metal oxide semiconductor structure and the second metal oxide semiconductor structure share the drift region, which reduces the resistance of the drift region, and further reduces the specific on-resistance of the power semiconductor device per unit area. BRIEF DESCRIPTION OF DRAWINGS

[0022] Figure 1 A structural schematic diagram of a power semiconductor device in the prior art;

[0023] Figure 2 An application scenario schematic diagram of the power semiconductor device provided by the embodiment of the present application;

[0024] Figure 3 A sectional view of the power semiconductor device provided by the embodiment of the present application;

[0025] Figure 4 A top view of the power semiconductor device provided by the embodiment of the present application;

[0026] Figure 5 A current schematic diagram of the power semiconductor device provided by the embodiment of the present application;

[0027] Figure 6An application scenario diagram of a power semiconductor device provided by an embodiment of the present application is shown in FIG. 1.

[0028] Figure 7 A simulation structure diagram of a power semiconductor device provided by an embodiment of the present application is shown in FIG. 2.

[0029] Figure 8a Breakdown characteristics of a second MOS structure to a first MOS structure provided by an embodiment of the present application are shown in FIG. 3.

[0030] Figure 8b Breakdown characteristics of a first MOS structure to a second MOS structure provided by an embodiment of the present application are shown in FIG. 4.

[0031] Figure 9a Transfer switch characteristics of a second MOS structure to a first MOS structure provided by an embodiment of the present application are shown in FIG. 5.

[0032] Figure 9b Transfer switch characteristics of a first MOS structure to a second MOS structure provided by an embodiment of the present application are shown in FIG. 6.

[0033] Figure 10 A cross-sectional view of a power semiconductor device provided by an embodiment of the present application is shown in FIG. 7.

[0034] Figure 11 A top view of a power semiconductor device provided by an embodiment of the present application is shown in FIG. 8.

[0035] Figure 12 A current diagram of a power semiconductor device provided by an embodiment of the present application is shown in FIG. 9.

[0036] Figure 13 A simulation structure diagram of a power semiconductor device provided by an embodiment of the present application is shown in FIG. 10.

[0037] Figure 14a Breakdown characteristics of a second MOS structure to a first MOS structure provided by an embodiment of the present application are shown in FIG. 11.

[0038] Figure 14b Breakdown characteristics of a first MOS structure to a second MOS structure provided by an embodiment of the present application are shown in FIG. 12.

[0039] Figure 15a Transfer switch characteristics of a second MOS structure to a first MOS structure provided by an embodiment of the present application are shown in FIG. 13.

[0040] Figure 15b Transfer switch characteristics of a first MOS structure to a second MOS structure provided by an embodiment of the present application are shown in FIG. 14. DETAILED DESCRIPTION

[0041] The embodiments of the present application will be further described below with reference to the accompanying drawings.

[0042] For the convenience of understanding the power semiconductor device used in the embodiments of the present application, first, the application scenario of the power semiconductor device provided by the embodiments of the present application is described. The power semiconductor device provided by the embodiments of the present application can be applied to the battery management and charging protection system of a portable electronic device such as a smart phone, a smart watch, a tablet computer, or the like, or can also be applied to different scenarios such as a protection current conversion system, a power IC, and the like. As shown in a battery protection system scenario Figure 2 The battery 5 is used to supply power to the load 6, and a protection circuit is arranged between the battery 5 and the load 6. The protection circuit is composed of a power semiconductor device 7 and a control chip 8. The power semiconductor device 7 is composed of two MOS structures 9 connected in series. In use, the conduction of the two MOS structures 9 can be controlled by the control chip 4008. The above-mentioned power semiconductor device 7 can effectively protect the battery from over-discharge, over-charge, and over-current (current exceeding the designed range). However, the power semiconductor device in the prior art has the problems of too large size and too large characteristic on-resistance per unit area. Therefore, the embodiments of the present application provide a power semiconductor device to improve the structure and layout of the power semiconductor device, facilitate the miniaturization of the power semiconductor device, and improve the characteristic on-resistance per unit area. The specific embodiments will be described in detail below in combination with specific drawings and embodiments.

[0043] For the convenience of understanding the power semiconductor device provided by the embodiments of the present application, the terms related to the present application are first described below.

[0044] PN junction: By using different doping processes, P-type semiconductor and N-type semiconductor are made on the same semiconductor (usually silicon or germanium) substrate through diffusion, and a space charge region called PN junction is formed at their interface. The PN junction has unidirectional conductivity.

[0045] Channel: Refers to a thin semiconductor layer between the source region and the drain region in a field power semiconductor device.

[0046] Drift region: Refers to a high-resistance region in a power semiconductor device where the number of carriers is very small under the dual influence of drift motion and diffusion.

[0047] Epitaxial layer: Refers to a semiconductor layer epitaxially grown on a substrate.

[0048] On-resistance: Refers to the resistance value of the power semiconductor device working in the linear region.

[0049] Threshold voltage: Usually refers to the input voltage corresponding to the midpoint of the transition zone where the output current changes sharply with the input voltage in the transfer characteristic curve of the power semiconductor device.

[0050] The first and second doping types involved in the embodiments of the present application are P-type and N-type respectively. For example, if the power semiconductor device is of electron conduction type, the first doping type is N-type, and the second doping type is P-type. If the power semiconductor device is of hole conduction type, the first doping type is P-type, and the second doping type is N-type. In the following examples of the present application, the first doping type is N-type, and the second doping type is P-type. The same applies to the examples of the present application when the first doping type is P-type, and the second doping type is N-type.

[0051] For the convenience of understanding the power semiconductor device provided by the embodiments of the present application, the lateral direction and the longitudinal direction are defined. The longitudinal direction refers to the stacking direction of the layer structure of the power semiconductor device, which can also be referred to as the thickness direction of the power semiconductor device. The lateral direction refers to the direction perpendicular to the longitudinal direction and parallel to the arrangement direction of the two common-drain metal oxide semiconductor field effect transistors in the power semiconductor device.

[0052] Reference Figure 3 , Figure 3 A cross-sectional view of the power semiconductor device is shown. The power semiconductor device at least includes a substrate 11 and an epitaxial layer 12 arranged on the substrate 11, and the substrate 11 and the epitaxial layer 12 are two main layer structures of the power semiconductor device. The power semiconductor device provided by the embodiments of the present application can also include other conventionally arranged layer structures (such as passivation layer, interconnection metal, back metal layer, etc.). For the convenience of describing the structure of the power semiconductor device, other layer structures are omitted in the present application.

[0053] The substrate 11 and the epitaxial layer 12 are arranged along the longitudinal direction, wherein the substrate 11 is a first-doping-type substrate, and the epitaxial layer 12 is a first-doping-type epitaxial layer. The epitaxial layer 12 is provided with a trench 31, and the depth of the trench 31 extends along the longitudinal direction (the thickness direction of the power semiconductor device). The above-mentioned substrate 11 and epitaxial layer 12 form the device body of the power semiconductor device, and the epitaxial layer 12 serves as the main structural part of the power semiconductor device.

[0054] According to the functional division, the power semiconductor device provided by the embodiments of the present application includes two common-drain metal oxide semiconductor field effect transistors (referred to as field effect transistors for short), which are named as a first field effect transistor 100 and a second field effect transistor 101 for the convenience of description. As an example, when the first field effect transistor 100 and the second field effect transistor 101 are arranged, the first field effect transistor 100 and the second field effect transistor 101 are arranged in a symmetrical manner along the center line of the trench 31, and the first field effect transistor 100 and the second field effect transistor 101 are connected in parallel to form a cell structure of the power semiconductor device (not marked in the figure). Figure 3 It should be understood that the same applies to the embodiments of the present application when the first field effect transistor 100 and the second field effect transistor 101 are arranged in a non-symmetrical manner along the center line of the trench 31. Figure 3Although only one cell structure is shown, the power semiconductor device provided in the embodiments of the present application can contain multiple cells, and the multiple cells can be arranged periodically. In the embodiments of the present application, only one cell is taken as an example for description.

[0055] The first field effect transistor 100 and the second field effect transistor 101 are of a symmetrical structure, and thus the first field effect transistor 100 is taken as an example for description.

[0056] Referring to Figure 3 , the field effect transistor 100 includes a first metal-oxide-semiconductor structure (1 st Metal-Oxide-Semicondcutor Structure, referred to as the first MOS structure) and a second metal-oxide-semiconductor structure (2 nd Metal-Oxide-Semicondcutor Structure, referred to as the second MOS structure), and the first MOS structure 10 and the second MOS structure 20 are connected in series. When the first MOS structure 10 and the second MOS structure 20 are arranged, the first MOS structure 10 and the second MOS structure 20 are arranged in a longitudinal direction, and a part of the first doped type epitaxial layer is arranged between the first MOS structure 10 and the second MOS structure 20, which is used as a drift region 30 and is shared by the first MOS structure 10 and the second MOS structure 20.

[0057] The first MOS structure 10 includes a first gate 51, a first source 61 and a first channel 21. The first gate 51 is used as a control component of the first MOS structure 10, and is connected to a control chip. Under the control of the control chip, the first gate 51 is used to control the first channel 21 to be turned on or turned off.

[0058] The first source 61 of the first MOS structure 10 is used as a connection terminal of the first MOS structure 10, and can be made of metal or metalloid (such as TiN, Si compound, etc.). When arranged, the first source 61 can be arranged on the surface of the epitaxial layer 12, or can be partially embedded or entirely embedded in the epitaxial layer 12. Figure 3 In the embodiment, only a structure schematic diagram in which the first source 61 is entirely embedded in the epitaxial layer 12 is shown, and other modes are not shown one by one. When the first source 61 is entirely embedded in the epitaxial layer 12, a surface of the first source 61 is exposed outside the epitaxial layer 12, and the surface is used as a connection surface of the first source 61, so as to be connected to other metal layers or interconnection metal layers (not shown). Figure 3

[0059] ​The first channel 21 is disposed in the epitaxial layer 12, and the first channel 21 is on the same side of the first source 61 as the trench 31. The first channel 21 is close to the sidewall of the trench 31, and the first source 61 is away from the sidewall of the trench 31.

[0060] The first channel 21 is a second-doped-type region. In forming the first channel 21, a doped region of the second-doped-type is disposed in the epitaxial layer 12 on the sidewall of the trench 31 to form the first channel 21. The first channel 21 extends along the sidewall of the trench 31 in the longitudinal direction and contacts the drift region 30. Since the first channel 21 is a second-doped-type region and the drift region 30 is a first-doped-type region, the drift region 30 and the first channel 21 can form a PN junction. When the first gate 51 is not applied with a voltage, or is applied with a voltage of 0 or negative voltage relative to the first source 61, the PN junction between the first channel 21 and the drift region 30 is not conductive, so that the conductive path from the first source 61 to the first channel 21 to the drift region 30 is closed. Under the action of the voltage applied by the first gate 51, the part of the first channel 21 close to the sidewall of the trench 31 forms an inversion layer, which can be converted from the second-doped-conductive-type to the first-doped-conductive-type, so that the conductive path from the first channel 21 to the drift region 30 is conductive. At this time, the first source 61, the first channel 21 and the drift region 30 are conductive.

[0061] The first gate 51 is disposed in the trench 31 and opposite to the first channel 21. When the first gate 51 is applied with a voltage, the conduction of the first channel 21 can be controlled.

[0062] As an optional solution, the first MOS structure 10 further comprises a first gate oxide layer 41 for isolating the first channel 21 from the first gate 51. The first gate oxide layer 41 is disposed on the sidewall of the trench 31 and between the first gate 51 and the first channel 21. The first gate oxide layer 41 can be provided to inhibit the increase of leakage current between the first channel 21 and the first gate 51 and improve the gate withstand voltage capability.

[0063] As an optional solution, the epitaxial layer 12 further comprises a first source contact region (not shown in the figure), and the first source 61 is connected to the first channel 21 through the first source contact region. The first source contact region comprises a heavily doped region 13 of the first-doped-type and a heavily doped region 23 of the second-doped-type.

[0064] The heavily doped region 13 of the first doping type is arranged in the epitaxial layer 12 and is located between the first source 61 and the trench 31 and between the first source 61 and the first channel 21. The heavily doped region 13 of the first doping type is in contact with the first source 61 and the first channel 21 respectively and forms a conductive channel composed of the first source 61, the heavily doped region 13 of the first doping type, the first channel 21 and the drift region 30. The doping concentration of the heavily doped region 13 of the first doping type is generally at least one order of magnitude higher than the doping concentration of other doped regions (such as the epitaxial layer 12), so as to improve the resistance when the metal and the semiconductor are connected. When the heavily doped region 13 of the first doping type is connected with the first source 61 and the first channel 21 respectively, the ohmic contact resistance between the first source 61 and the epitaxial layer 12 can be reduced through the heavily doped region 13 of the first doping type.

[0065] The heavily doped region 23 of the second doping type is arranged in the epitaxial layer 12 and is located between the first source 61 and the first channel 21 and is not in contact with the trench 31. The heavily doped region 23 of the second doping type is in contact with the first source 61 and the first channel 21 respectively. The doping concentration of the heavily doped region 23 of the second doping type is generally at least one order of magnitude higher than the doping concentration of other doped regions (such as the first channel 21). The contact between the first source 61 and the first channel 21 can be improved through the heavily doped region 23 of the second doping type.

[0066] The second MOS structure 20 is arranged along the longitudinal direction with the first MOS structure 10. The second MOS structure 20 comprises a second gate 52, a second source 62 and a second channel 22. The second gate 52 is used as a control component of the second MOS structure 20 and is used to control the second channel. Under the control of the control chip, the second gate 52 is used to control the second channel 22 to be turned on and turned off.

[0067] The second source 62 of the second MOS structure 20 is used as a terminal of the second MOS structure 20 and can be made of metal or metal-like material. When the second source 62 is arranged, the second source 62 is arranged in the trench 31 and extends along the bottom of the trench 31 to the outside of the trench 31 so as to be exposed on the surface of the epitaxial layer 12. The second source 62 extends to the surface of the epitaxial layer 12 as a connecting surface of the second source 62.

[0068] The second channel 22 is a region of the second doping type. In forming the second channel 22, a doped region of the second doping type is provided in the epitaxial layer 12 under the bottom of the trench 31, thereby forming the second channel 22. Since the second channel 22 is a region of the second doping type and the drift region 30 is a region of the first doping type, the drift region 30 and the second channel 22 form a PN junction. When the second gate 52 is not applied with a voltage, or is applied with a voltage of 0 or negative voltage relative to the second source 62, the PN junction between the second channel 22 and the drift region 30 is not conductive, thereby closing the conductive path from the second source 62 to the second channel 22 to the drift region 30. Under the action of the voltage applied by the second gate 52, the portion of the second channel 22 near the bottom and sidewall of the trench 31 forms an inversion layer, which is converted from the second doping conductivity type to the first doping conductivity type, thereby making the conductive path from the second source 62 to the second channel 22 to the drift region 30 conductive. The first MOS structure 10 is combined with the case when the first channel 21 is conductive. When the first gate 51 controls the first channel 21 to be conductive and the second gate 52 controls the second channel 22 to be conductive, the conductive path of the first source 61, the first channel 21, the drift region 30, the second channel 22, and the second source 62 is formed.

[0069] The second gate 52 is disposed in the trench 31 and opposite to the second channel 22. When the second gate 52 is applied with a voltage, the conduction of the second channel 22 can be controlled.

[0070] As an optional solution, the second MOS structure 20 further comprises a second gate oxide layer 43 for isolating the second channel 22 from the second gate 52. The second gate oxide layer 43 is disposed on the sidewall and bottom of the trench 31 and between the second gate 52 and the second channel 22. The second gate oxide layer 42 is provided to inhibit the increase of leakage current between the second channel 22 and the second gate 52 and improve the gate withstand voltage capability.

[0071] As an optional solution, the epitaxial layer 12 further comprises a second source contact region (not shown in the figure), and the second source 62 is connected to the second channel 22 through the second source contact region. The second source contact region comprises a heavily doped region 14 of the first doping type and a heavily doped region 24 of the second doping type.

[0072] The heavily doped region 14 of the first doping type is arranged in the epitaxial layer 12 at the bottom of the trench 31 and is located at one side of the second source 62. The heavily doped region 14 of the first doping type is in contact with the second source 62 and the second channel 22 respectively and forms a conductive channel composed of the second source 62, the heavily doped region 14 of the first doping type, the second channel 22 and the drift region 30. The doping concentration of the heavily doped region 14 of the first doping type is at least one order of magnitude higher than that of other doped regions (such as the epitaxial layer 12) so as to improve the resistance when the metal and the semiconductor are connected. When the heavily doped region 14 of the first doping type is connected with the second source 62 and the second channel 22 respectively, the ohmic contact resistance between the second source 62 and the epitaxial layer 12 can be reduced through the heavily doped region 14 of the first doping type.

[0073] The heavily doped region 24 of the second doping type of the second source contact region is arranged below the bottom of the second source 62 and is in contact with the second source 62 and the second channel 22 respectively. The doping concentration of the heavily doped region 24 of the second doping type is at least one order of magnitude higher than that of other doped regions (such as the second channel 22). The contact between the second source 62 and the second channel 22 can be improved through the heavily doped region 24 of the second doping type.

[0074] As an optional solution, the trench 31 is filled with a filling layer 42 which wraps the first gate 51, the second gate 52 and the second source 62 so as to isolate and protect the above-mentioned components. It should be understood that when the filling layer 42 is provided, the second source 62 is exposed outside the filling layer so as to facilitate the connection with other circuits.

[0075] Reference Figure 3 It can be seen that when the first MOS structure 10 and the second MOS structure 20 are arranged, the first MOS structure 10 and the second MOS structure 20 are arranged in a longitudinal manner so as to reduce the lateral size of the field effect transistor. In addition, the first gate 51 and the second gate 52 are arranged longitudinally along the depth direction of the trench 31 so that the first MOS structure 10 and the second MOS structure 20 can share the longitudinally arranged drift region 30. In addition, the drift region 30 is located between the first channel 21 and the second channel 22 and does not occupy the lateral size of the power semiconductor device, which can further reduce the size of the power semiconductor device and improve the arrangement density of the device.

[0076] In addition, the structure of the second field effect transistor 101 is the same as that of the first field effect transistor 100. The two first channels of the two common-drain metal oxide semiconductor field effect transistors are arranged on opposite sides of the trench and the two first sources are arranged on opposite sides of the trench. As an optional solution, in order to reduce the device settings, part of the components of the first field effect transistor 100 and the second field effect transistor 101 are shared. For example,Figure 3 As shown in FIG. 2, the two field effect transistors share the second source 62. In addition, the second channels 22 of the two first field effect transistors 100 can be in communication with each other, but are controlled separately by the two different second gates 52.

[0077] Reference will now be made to the drawings and specific language will be used to describe the application. Figure 4 , Figure 4 A top view of the power semiconductor device is shown. In conjunction with Figure 3 and Figure 4 It can be seen that the components of the power semiconductor device are arranged laterally, and adjacent first field effect transistors 100 and second field effect transistors 200 are mirror-symmetrical (along the center line of the trench). On the surface of the epitaxial layer 12 in the lateral direction, the first source 61, the heavily doped region 13 of the first doping type, the first gate oxide layer 41, the filling layer 42, and the second source 62 are arranged in sequence. Adjacent two field effect transistors are mirror-symmetrical and form a cell. When there are multiple cells, the multiple cells can be arranged periodically in the lateral direction.

[0078] Reference will now be made to the drawings and specific language will be used to describe the application. Figure 5 , Figure 5 A current schematic diagram of the power semiconductor device provided by the embodiments of the present application is shown. Figure 5 Reference can be made to the same reference numerals in Figure 3 The first gate 51 and the second gate 52 are control ports of the power semiconductor device, the first source 61 is an output port of the power semiconductor device, and the second source 62 is an input port of the power semiconductor device. When a positive voltage is applied to the first gate 51 and the second gate 52, the level of the first gate 51 and the second gate 52 is high relative to the level of the first source 61 and the second source 62, and the first channel 21 and the second channel 22 are both open. As shown by the dashed arrow in Figure 5 , the current can flow along a first path, which is a path passing through the first source 61, the first channel 21, the drift region between the first channel 21 and the second channel 22, the second channel 22, and the second source 62 in sequence; or as shown by the solid arrow in Figure 5 , the current flows along a second path, which is a path passing through the second source 62, the second channel 22, the drift region between the first channel 21 and the second channel 22, the first channel 21, and the first source 61 in sequence. When no positive voltage is applied to the first gate 51, the level of the first gate 51 is low relative to the first source 61, and the first channel 21 is closed; when no positive voltage is applied to the second gate 52, the level of the second gate 52 is low relative to the first source 61, and the second channel 22 is closed.

[0079] As can be seen from the above description, in the power semiconductor device provided by the embodiment of the present application, the first MOS structure 10 and the second MOS structure 20 are structures sharing a drift region, and the two second-doping-type body regions (the first channel 21 and the second channel 22) and the intermediate first-doping-type drift region can form a P-N-P common cathode back-to-back diode, so that the first MOS structure 10 and the second MOS structure 20 form a common-drain metal oxide semiconductor field effect transistor and can realize bidirectional voltage resistance. The power semiconductor device provided by the embodiment of the present application adopts a structure design of a longitudinal drift region and two vertically arranged upper and lower gates, thereby reducing the size of the field effect transistor occupied in the lateral direction. In addition, the first MOS structure 10 and the second MOS structure 20 share a longitudinal drift region, so that the current does not flow through the substrate when flowing, and thus the power semiconductor device has a smaller channel resistance and no substrate resistance when turned on, thereby reducing the resistance of the power semiconductor device.

[0080] Reference Figure 6 , Figure 6 An application scenario schematic diagram of the power semiconductor device provided by the embodiment of the present application is shown. The cathode of a battery 300 is connected to a load 300 through a battery management and charging protection circuit. The power semiconductor device provided by the embodiment of the present application is arranged on the circuit as a structure for protecting the battery 300. The first field effect transistor 100 and the second field effect transistor 101 of the power semiconductor device are connected in parallel in the circuit, and the first MOS structure 10 and the second MOS structure 20 of the first field effect transistor 100 are connected in series. The first MOS structure 10 and the second MOS structure 20 are both controlled by a control chip 400. The control chip 400 controls the conduction and turn-off of the first MOS structure 10 and the second MOS structure 20 by controlling the levels of the first gate and the second gate.

[0081] In addition, the power semiconductor device provided by the embodiment of the present application adopts a planar device structure (as shown in FIG. 1) and the second MOS structure 20 can adopt a structure design of LDMOS (Laterally Diffused Metal Oxide Semiconductor) to realize WLCSP (Wafer Level Chip Scale Packaging) packaging. Figure 4

[0082] To verify the technical effects of the power semiconductor device provided by the embodiment of the present application, the power semiconductor device provided by the embodiment of the present application is simulated by a semiconductor TCAD (Technology Computer Aided Design, which refers to a semiconductor process simulation and device simulation tool).

[0083] ​A common-drain N-type field-effect transistor with a bidirectional blocking voltage of 15V is used as an example for simulation. The structural parameters of the field-effect transistor are shown in Table 1. Figure 7 As shown: The lateral dimension of a single common-drain transistor is 1 μm, which is 0.5 μm, meaning the cell size of a power semiconductor device is 1 μm, at a concentration of 1.8e19 cm⁻¹. -3 On an N-type substrate with a thickness of 2 1 μm, a doping concentration of 1.3e17 cm⁻¹ is formed. -3 A 3µm thick N-type epitaxial layer forms the body of the power semiconductor device. A trench with a depth of 1µm and a half-width of 0.35µm is formed on the surface of the field-effect transistor body. A first P-type channel (first channel) with a potential well depth of 0.28µm and a potential well width of 0.16µm is formed on the device body surface by P-type ion implantation, with an implantation dose of 1.35e13cm. -3 An N-type heavily doped region with a depth of 0.15 μm and a width of 0.1 μm (8) was formed using N-type ion implantation and etching. A P-type heavily doped region with a depth of 0.15 μm and a width of 0.1 μm (11) was formed using P-type ion implantation and etching. A second P-type channel (second channel) with a potential well depth of 0.45 μm (5), a potential well half-width of approximately 0.35 μm (13), and a channel length of 0.18 μm (7) was formed at the bottom of the trench using P-type ion implantation, with an implantation dose of 1.2e13cm. -3 and 6e13cm -3 A thickness () is provided on the inner sidewall of the trench. Figure 7 (Unmarked, located between G1 / G2 and the trench sidewall) A gate oxide layer is formed; and polysilicon layers with a depth of 14 (0.35 μm), a width of 16 (0.18 μm), a depth of 15 (0.18 μm), and a width of 10 (0.18 μm) are filled to form gate G1 (first gate) and gate G2 (second gate), respectively; gate G1 and gate G2 are isolated by a fill layer with a thickness of 17 (0.3 μm). The threshold voltage of a power field-effect transistor (FET), i.e., a power semiconductor device, depends on the gate oxide thickness and the concentration of the P-type channel. The breakdown voltage and on-resistance of a power field-effect transistor, i.e., a power semiconductor device, are determined by factors such as the concentration, depth, and length of the N-type drift region, the concentration and length of the P-type channel region, the oxide thickness, and the trench depth, respectively.

[0084] Table 1: Structural Parameters of Field-Effect Transistors

[0085] Reference Structure Name Parameter Value Reference Structure Name (Units) Parameter Value 1 Field Effect Transistor Size 0.5um 10 N-type Heavily Doped Region Width 0.1um 2 N-type Substrate Thickness 1um 11 P-type Heavily Doped Region Width 0.1um 3 N-type Epitaxial Layer Thickness 3um 12 Trench Depth 1um 4 P-type First Well Region Depth 0.28um 13 Trench Width 0.35um 5 First P-type Channel Depth 0.45um 14 First Gate Depth 0.35um 6 First P-type Channel Width 0.16um 15 Second Gate Depth 0.18um 7 Second P-type Channel Width 0.18um 16 Gate Width 0.18um 8 N-type Heavily Doped Region Depth 0.15um 17 Fill Layer Depth 0.3um 9 P-type Heavily Doped Region Depth 0.15um

[0086] The power semiconductor devices in Table 1 above were simulated, and the simulation results are as follows: Figure 8a and Figure 8b As shown. Figure 8a andFigure 8b The simulation curve of the breakdown voltage of the device is shown. When the potentials of the first gate and the first source (source S1) are both low, the voltage of the second source and the second gate is gradually increased from 0 V, and the current of the second source (source S2) is gradually read. When the current of the second source suddenly changes to 1 uA / mm, the corresponding voltage of the second source is the breakdown voltage of the second MOS structure, i.e., the breakdown voltage from the second source to the first source, which is Figure 8a It can be seen that the breakdown voltage of the second MOS structure is 15 V. Similarly, the breakdown voltage of the first MOS structure, i.e., the breakdown voltage from the first source to the second source, is Figure 8b It can be seen that the breakdown voltage of the first MOS structure is 15 V.

[0087] Figure 9a and Figure 9b The simulation curve of the transfer switch characteristic of the power semiconductor device is shown. When the potential of the first source is low and the second source is connected to a fixed voltage of 0.1 V, the first gate and the second gate are gradually increased from 0 V and 0.1 V, respectively, and the current of the second source is gradually read. When the current of the second source suddenly increases to 1 uA / mm, the corresponding first gate voltage is the threshold voltage of the first MOS structure, as shown in Figure 9a It can be seen that the threshold voltage of the first MOS structure is 0.8 V. When the current of the first source suddenly increases to 1 uA / mm, the corresponding second gate voltage is the threshold voltage of the second MOS structure, as shown in Figure 9b It can be seen that the threshold voltage of the second MOS structure is 0.8 V.

[0088] In addition, as shown in Figure 9a and Figure 9b When the gate-source bias voltage of the power semiconductor device is 3.1 V, the characteristic on-resistance of the common-drain power semiconductor device in the embodiment of the present application is only about 5 mΩ·mm 2 .

[0089] Through the above experimental verification, it can be seen that the power semiconductor device provided by the embodiment of the present application, when the first MOS structure and the second MOS structure share the longitudinal drift region and the first gate and the second gate are longitudinally distributed, the breakdown characteristics of the device can meet 15 V, and the unit on-resistance is only 5 mΩ·mm 2 . However, the power semiconductor device of the two MOSFETs in back-to-back common-drain series adopted by the industry at present has a unit area characteristic on-resistance of 10.6 mΩ·mm 2(Data source: Panasonic product data in 2016, "FCAB21490L - Gate resistor installed Dual N-channel MOSFET For lithium-ion secondary battery protection circuits"), therefore, the unit area on-resistance of the power semiconductor device provided by the embodiments of the present application can be reduced by 53% compared with the unit area on-resistance of the existing power semiconductor device, and the breakdown voltage can also be increased to 15V and above.

[0090] To facilitate the understanding of the above-mentioned power semiconductor device provided by the embodiments of the present application, the preparation process thereof is described in detail below. For example, to form a field effect transistor, the preparation can be based on the traditional discrete Trench MOS or integrated BCD (Bipolar CMOS DMOS, Bipolar Transistor Complementary Metal Oxide Semiconductor Double Diffusion Metal Oxide Semiconductor) process technology, combined with the structure shown in Figure 3 The specific preparation method is as follows:

[0091] An N-type epitaxial layer 12 with a certain doping concentration is epitaxially grown on an N-type substrate 11; a trench 31 is etched on the epitaxial layer 12.

[0092] By ion implantation, a P-type doping region is formed in the epitaxial layer 12 below the bottom of the trench 31 to form a second channel 22, and a P-type doping region is formed in the epitaxial layer 12 outside the upper part of the trench 31 to form a first channel 21.

[0093] By thermal oxidation growth, a gate oxide layer is formed in the trench 31, which covers the bottom and sidewall of the trench 31.

[0094] The trench is filled with polysilicon, and a second gate 52 is formed by etching process, which is opposite to the second channel 22 so as to control the conduction of the second channel 22. In addition, the part of the gate oxide layer that separates the second gate 52 and the second channel 22 is the second gate oxide layer 43.

[0095] By ion implantation, an N-type heavily doped region 13 and an N-type heavily doped region 14 are formed in the epitaxial layer 12. A filling layer 42 is deposited in the trench 31 by chemical vapor deposition, and only the filling layer 42 in the trench is filled by CMP (chemical mechanical polishing) process. For example, the filling layer 42 can be an oxide layer.

[0096] Part of the filling layer 42 is etched away, and the surface of the filling layer left after etching is the surface bearing the first gate 51. When etching the filling layer 42, part of the gate oxide layer will also be etched away.

[0097] A gate oxide layer, known as the first gate oxide layer 41, is regenerated on the sidewall of trench 31 through thermal oxidation growth. The thickness of the first gate oxide layer 41 is substantially the same as that of the second gate oxide layer 43. When the first gate oxide layer 41 is attached to the sidewall of trench 13, it can be used to isolate the first gate 51 from the first channel 21.

[0098] Polysilicon is deposited on the fill layer retained after etching, and the first gate 51 is formed by etching. The fill layer is then deposited in the trench by chemical vapor deposition and etching.

[0099] The filling layer above the ohmic contact region in the trench is removed by etching, and P-type heavily doped region 23 and P-type heavily doped region 24 are formed on the surface of epitaxial layer 12 and at the bottom of trench 31 by ion implantation, respectively; finally, metal is deposited to form the first source 61 and the second source 62.

[0100] A P-type heavily doped region 23 is formed at the ohmic contact region on the surface of the epitaxial layer 12 by ion implantation; finally, metal is deposited to form the first source electrode 61.

[0101] like Figure 10 As shown, Figure 10 A schematic diagram of another power semiconductor device provided in an embodiment of this application is shown. Figure 10 The power semiconductor device shown is Figure 3 The power semiconductor devices shown have similar structures, differing only in the arrangement of their internal structures.

[0102] Figure 10 The middle part of the labeling can be used as a reference. Figure 3 The same labels in the text will not be repeated here. Figure 10 The trench shown is a T-shaped trench, which includes a first trench 32 and a second trench 33. The second gate 52 is disposed at the bottom of the T-shaped trench (the bottom of the second trench 33); the first gate 51 is disposed at the stepped surface of the T-shaped trench (the bottom of the first trench 32).

[0103] Depend on Figure 10 It can be seen that the first gate 51 and the second gate 52 are offset along the depth direction of the trench, and... Figure 3 Compared to the power semiconductor device shown, the first gate 51 can be directly disposed at the bottom of the first trench 32, thereby facilitating the positioning of the first gate 51 during placement and improving the accuracy of the first gate 51 placement. Furthermore, when using… Figure 10 When the trench shown is prepared, the first gate 51 and the second gate 52 can be formed simultaneously by a single polysilicon etching process during the preparation of the gate oxide layer, which simplifies the preparation process.

[0104] refer to Figure 11 , Figure 11 A top view of a power semiconductor device is shown. (Combined with...) Figure 10 and Figure 11 As can be seen, the multiple components of the power semiconductor device are arranged laterally, with adjacent first field-effect transistors 100 and second field-effect transistors 101 being mirror-symmetrical (along the center line of the trench). On the surface of the epitaxial layer 12, along the lateral direction, are sequentially distributed a first source 61, a heavily doped region 13 of a first doping type, a first gate oxide layer 41, a fill layer 42, and a second source 62. Adjacent field-effect transistors are mirror-symmetrically arranged to form a cell. When there are multiple cells, these cells can be periodically repeated along the lateral direction.

[0105] refer to Figure 12 , Figure 12 A current schematic diagram of the power semiconductor device provided in an embodiment of this application is shown. The first gate 51 and the second gate 52 are control ports of the power semiconductor device, the first source 61 is the input port of the power semiconductor device, and the second source 62 is the output port of the power semiconductor device. When a voltage is applied to the first gate 51 and the second gate 52, the voltage levels of the first gate 51 and the second gate 52 are high relative to the voltage levels of the first source 61 and the second source 62, and both the first channel 21 and the second channel 22 are turned on. Figure 5 As shown by the dashed arrow, current can flow along the first path, which refers to the path that sequentially passes through the first source 61, the first channel 21, the drift region between the first channel 21 and the second channel 22, the second channel 22, and the second source 62; or as... Figure 5 As shown by the solid arrow, current flows along the second path, which refers to the path that sequentially passes through the second source 62, the second channel 22, the drift region between the first channel 21 and the second channel 22, the first channel 21, and the first source 61. When no positive voltage is applied to the first gate 51, the level of the first gate 51 is low relative to the first source 61, and the first channel 21 is turned off; when no positive voltage is applied to the second gate 52, the level of the second gate 52 is low relative to the first source 61, and the second channel 22 is turned off.

[0106] To verify the technical effects of the present invention, the device structure and performance parameters of the embodiments of this application were simulated using semiconductor TCAD. The structural parameters of the field-effect transistor are shown in Table 2 and... Figure 13 As shown: at a concentration of 1.8e19cm -3 On an N-type substrate, a doping concentration of 1.3e17cm is formed. -3, a N-type epitaxial layer with a thickness of 3um forms a device body. A first trench with a depth of 0.6um and a width of 0.55um is formed on the surface of the device body. The first trench is further etched to form a second trench with a depth of 0.3um and a width of 0.35um. A first P-type channel (first channel) with a potential well depth of 0.28um and a channel length of 14um is formed on the surface of the device body by P-type ion implantation. The implantation dose is 1.35e13cm -3 A first heavily doped region of a first doping type with a depth of 0.15um and a width of 0.1um is formed by N-type ion implantation. A second heavily doped region of a second doping type with a depth of 0.15um and a width of 0.1um is formed by P-type ion implantation. A second P-type channel (second channel) with a potential well depth of 0.55um and a channel length of 0.21um is formed on the bottom of the second trench by P-type ion implantation. A gate oxide layer with a thickness of A first gate (gate G1) and a second gate (gate G2) are formed by filling the first trench and the second trench with polysilicon with a depth of 0.4um and a width of 0.18um, and a depth of 0.2um and a width of 0.18um, respectively. The threshold voltage of the power semiconductor device depends on the thickness of the gate oxide layer and the concentration of the P-type well region. The breakdown voltage and the on-resistance of the device are determined by the concentration, depth and length of the N-type drift region, the concentration and length of the P-type channel region, the thickness of the oxide layer, the trench depth, and other factors.

[0107] Table 2: Field effect transistor structure parameters

[0108]

[0109]

[0110] The power semiconductor device in Table 2 above is simulated, and the simulation results are shown in Figure 14a and Figure 14b The breakdown voltage simulation curve of the power semiconductor device is shown in Figure 14a and Figure 14b When the first gate and the first source (source S1) have the same low voltage, the voltage of the second source and the second gate is gradually increased from 0V, and the current of the second source (source S2) is gradually read. When the second source current suddenly changes to 1uA / mm, the corresponding second source voltage is the breakdown voltage of the second MOS structure, i.e. the breakdown voltage from the second source to the first source, which can be seen from Figure 14a The breakdown voltage of the second MOS structure is 15V. Similarly, the breakdown voltage of the first MOS structure, i.e. the breakdown voltage from the first source to the second source, can be seen from Figure 14b The breakdown voltage of the first MOS structure is 15V.

[0111] Figure 15a and Figure 15b Fig. 6 shows a simulation curve of the transfer characteristic of the power semiconductor device. When the first source electrode is at low level and the second source electrode is fixed at 0.1 V, the first gate electrode and the second gate electrode are gradually increased from 0 V and 0.1 V respectively, and the current of the second source electrode is gradually read. The first gate voltage corresponding to the sudden increase of the second source current to 1 uA / mm is the threshold voltage of the first MOS structure, as shown in Fig. 7. The simulation result of the threshold voltage of the first MOS structure is 0.9 V. Figure 15a Fig. 8 shows a simulation curve of the transfer characteristic of the power semiconductor device. The second gate voltage corresponding to the sudden increase of the second source current to 1 uA / mm is the threshold voltage of the second MOS structure, as shown in Fig. 9. The simulation result of the threshold voltage of the second MOS structure is 0.9 V. Figure 15b Fig. 10 shows a simulation curve of the transfer characteristic of the power semiconductor device. The second gate voltage corresponding to the sudden increase of the second source current to 1 uA / mm is the threshold voltage of the second MOS structure, as shown in Fig. 9. The simulation result of the threshold voltage of the second MOS structure is 0.9 V.

[0112] In addition, under the condition that the breakdown voltage of the power semiconductor device is 15 V and the gate-source bias voltage is 3.1 V, the characteristic on-resistance of the first MOS structure and the second MOS structure in the embodiment of the present application is only about 7 mΩ·mm 2 .

[0113] It can be seen from the above experimental verification that the power semiconductor device provided by the embodiment of the present application has a unit on-resistance of 7 mΩ·mm 2 when two MOS structures share the longitudinal drift region, the first gate electrode and the second gate electrode are distributed in a staggered manner, and the lateral trench structure is adopted. However, the unit area characteristic on-resistance of the power semiconductor device in which two MOS structures are connected in series with back-to-back and common drain in the industry is 10.6 mΩ·mm 2 (data source: product data of Panasonic in 2016, “FCAB21490L-Gate resistor installed Dual N-channel MOSFET For lithium-ion secondary battery protection circuits”), therefore, the unit area on-resistance of the power semiconductor device provided by the embodiment of the present application can be reduced by 33% compared with the unit area on-resistance of the existing power semiconductor device in the industry, and the breakdown voltage can also be increased to 15 V and above. In addition, the staggered arrangement of the first gate electrode and the second gate electrode can simplify the preparation process and improve the production efficiency.

[0114] The embodiment of the present application also provides an electronic device, such as a notebook computer, a mobile phone, a wearable device, a tablet computer and the like. The electronic device comprises a battery and an output circuit connected with the battery, and the output circuit comprises the power semiconductor device of any one of the above. In the above technical solution, the first gate and the second gate are arranged longitudinally along the depth direction of the trench, thereby reducing the size of the lateral occupation of the common-drain metal oxide field effect transistor. In addition, the first metal oxide semiconductor structure and the second metal oxide semiconductor structure share the drift region, thereby reducing the resistance of the drift region. The two identical common-drain metal oxide semiconductor field effect transistors are symmetrically connected in parallel back-to-back, so that the resistance of the power semiconductor device is half of the resistance when the power semiconductor device adopts a single common-drain metal oxide semiconductor, thereby reducing the specific on-resistance per unit area of the power semiconductor device.

[0115] Obviously, various modifications and variations of the present application can be made by those skilled in the art without departing from the spirit and scope of the application. Thus, it is intended that the present application cover modifications and variations of this application provided they come within the scope of the appended claims and their equivalents.

Claims

1. A power semiconductor device, characterized by, The power semiconductor device comprises a first doped type epitaxial layer and two common-drain metal oxide semiconductor field effect transistors; the first doped type epitaxial layer is provided with a groove; Each common-drain metal oxide semiconductor field effect transistor comprises a first metal oxide semiconductor structure and a second metal oxide semiconductor structure arranged along the depth direction of the groove; The first metal oxide semiconductor structure comprises a first channel provided in the first doped type epitaxial layer, and a first source connected to the first channel; the first source and the first channel are located on the same side of the groove, and the first source is connected to the first channel; the first channel is a second doped type region provided in the first doped type epitaxial layer; The first metal oxide semiconductor structure further comprises a first gate provided in the groove and used for controlling the first channel to be turned on; The second metal oxide semiconductor structure comprises a second source and a second channel; the second source is provided in the groove and extends along the depth direction of the groove and is located at the bottom of the groove; the second channel is located in the first doped type epitaxial layer and connected to the second source; the second channel is a second doped type region provided in the first doped type epitaxial layer; The second metal oxide semiconductor structure further comprises a second gate provided in the groove and used for controlling the second channel to be turned on; The first channel and the second channel are arranged in intervals along the depth direction of the groove; the second gate and the first gate are arranged in intervals along the depth direction of the groove; When the first gate and the second gate control the first channel and the second channel to be turned on respectively, current flows along the arrangement direction of the first source, the first channel, the part of the first doped type epitaxial layer between the first channel and the second channel, the second channel, and the second source, or in the opposite direction; The second sources of the two common-drain metal oxide semiconductor field effect transistors are shared, and the two first channels of the two common-drain metal oxide semiconductor field effect transistors are arranged on opposite sides of the groove; the two first sources are arranged on opposite sides of the groove.

2. The power semiconductor device according to claim 1, characterized in that, Each common-drain metal oxide semiconductor field effect transistor further comprises: A first gate oxide layer isolating the first channel and the first gate; A second gate oxide layer isolating the second channel and the second gate.

3. The power semiconductor device according to claim 2, characterized in that, The first gate oxide layer and the second gate oxide layer are provided on the sidewall of the groove.

4. The power semiconductor device according to claim 3, characterized in that, The groove is filled with a filling layer wrapping the first gate, the second gate, and the second source.

5. The power semiconductor device according to any one of claims 1 to 4, characterized in that, The first doped type epitaxial layer is provided with a first source contact region, and the first channel is connected to the first source through the first source contact region.

6. The power semiconductor device according to claim 5, characterized in that, The first source contact region comprises a heavily doped region of a first doped type and a heavily doped region of a second doped type.

7. The power semiconductor device according to any one of claims 1 to 4, characterized in that, The first doped type epitaxial layer is provided with a second source contact region, and the second channel is connected to the second source through the second source contact region.

8. The power semiconductor device according to claim 7, characterized in that, The second source contact region comprises a heavily doped region of a first doping type and a heavily doped region of a second doping type.

9. The power semiconductor device according to any one of claims 1 to 4, characterized in that, The trench is a straight trench; the first gate and the second gate are arranged longitudinally along the depth direction of the trench.

10. The power semiconductor device according to any one of claims 1 to 4, characterized in that, The first gate and the second gate are arranged in a staggered manner along the depth direction of the trench.

11. The power semiconductor device according to claim 10, characterized in that, The trench is a T-shaped trench; the second gate is arranged at the bottom of the T-shaped trench; and the first gate is arranged at the step surface of the T-shaped trench.

12. An electronic device, comprising: The power semiconductor device according to any one of claims 1 to 11.

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