Three-dimensional memory and manufacturing method thereof, storage system and electronic device

Abstract

The present application relates to a kind of three-dimensional memory and its manufacturing method, storage system and electronic equipment, by forming stop layer on substrate;Forming a stack structure on the stop layer;Forming channel hole in the stack structure, channel hole penetrates stack structure and stop layer, and extends into substrate;The first hole section of channel hole penetrates stop layer and is blocked, forms separation layer;Forming channel structure in the second hole section of channel hole, second hole section is located at the side of separation layer away from substrate, so that channel structure is located at the side of stop layer away from substrate, so when removing substrate and the part of bottom of channel structure, it can avoid that reaction liquid (such as, grinding reaction liquid) enter channel structure inside along the gap or interstice inside channel structure and destroy storage cell in channel structure, realizes that channel structure and bottom source electrode layer in three-dimensional memory are well connected, and improve the yield and stability of three-dimensional memory.

Description

[Technical Field]

[0001] This invention relates to the field of memory technology, specifically to a three-dimensional memory, its fabrication method, storage system, and electronic device. [Background Technology]

[0002] With the development of technology, the semiconductor industry is constantly seeking new production methods to enable each memory die in memory devices to have a greater number of memory cells. Among them, 3D NAND flash memory has become a cutting-edge and highly promising memory technology due to its advantages such as high storage density and low cost.

[0003] However, how to achieve a good electrical connection between the channel structure and the bottom source layer in a three-dimensional memory is a rather troublesome problem in current memory technology, and new methods to solve this problem are urgently needed. [Summary of the Invention]

[0004] This invention provides a three-dimensional memory and its fabrication method, storage system, and electronic device to achieve good electrical connection between the channel structure and the bottom source layer in the three-dimensional memory, and to improve the yield and stability of the three-dimensional memory.

[0005] To at least partially solve the above problems, embodiments of the present invention provide a method for fabricating a three-dimensional memory. The method includes: forming a stop layer on a substrate; forming a stacked structure on the stop layer; forming a channel hole in the stacked structure, the channel hole penetrating the stacked structure and the stop layer and extending into the substrate; sealing a first segment of the channel hole penetrating the stop layer to form a separator layer; and forming a channel structure in a second segment of the channel hole, the second segment being located on the side of the separator layer away from the substrate.

[0006] Specifically, the process of sealing the first section of the channel hole that penetrates the stop layer to form a separation layer includes: oxidizing the inner wall of the first section so that the exposed part of the stop layer on the inner wall of the first section is oxidized into oxide, and the oxide extends from the unoxidized remaining stop layer in the stop layer into the first section to form a separation layer.

[0007] The substrate includes a substrate, and the method further includes: while oxidizing the inner wall of the first hole segment, simultaneously oxidizing the substrate exposed through the bottom of the channel hole, and the rate at which the substrate is oxidized is less than the rate at which the stop layer is oxidized.

[0008] Specifically, the first section of the channel hole that penetrates the stop layer is sealed to form a separation layer, which includes growing a separation layer on the inner wall of the first section.

[0009] Specifically, forming a channel structure in the second section of the channel hole includes: forming a channel structure including a channel layer on the inner wall of the second section; and after forming the channel structure in the second section of the channel hole, further including: removing the substrate and the separator layer to expose the end of the channel layer; and forming a common source electrode layer covering and connecting the end of the channel layer on the side of the stop layer away from the stacked structure.

[0010] The channel structure further includes a storage functional layer, which is formed sequentially on the inner wall of the second via segment. The substrate includes a substrate and a sacrificial layer formed on the substrate. A stop layer is formed on the sacrificial layer. Removing the substrate and the separator layer to expose the end of the channel layer specifically includes: removing the substrate to expose the sacrificial layer; selectively etching away the sacrificial layer, the separator layer, and the storage functional layer located at the end of the channel structure in contact with the separator layer relative to the stop layer to expose the end of the stop layer and the channel layer.

[0011] The process of forming a stacked structure on the stop layer specifically includes: forming a first stacked structure on the stop layer; forming a first channel hole that penetrates the first stacked structure and the stop layer and extends into the substrate; forming a sacrificial material layer in the first channel hole; forming a second stacked structure on the first stacked structure and the sacrificial material layer to obtain a stacked structure including the first stacked structure and the second stacked structure; and forming a channel hole specifically includes: forming a second channel hole that penetrates the second stacked structure and exposes the sacrificial material layer; and removing the sacrificial material layer through the second channel hole to obtain a channel hole including the first channel hole and the second channel hole.

[0012] To at least partially solve the above problems, embodiments of the present invention provide a three-dimensional memory, the three-dimensional memory comprising: a common source layer; a stacked structure located on one side of the common source layer; a channel structure passing through a portion of the stacked structure, the channel structure including a channel layer; wherein, the common source layer protrudes on one side of the stacked structure relative to the channel structure to form a boss, the boss passing through the remaining portion of the stacked structure and connected to the end of the channel layer.

[0013] The three-dimensional memory includes gaps that are sealed within a channel structure.

[0014] The stacked structure includes a first stack structure and a second stack structure arranged sequentially in the direction away from the common source layer, and the gap is located in a partial channel structure arranged parallel to the first stack structure.

[0015] The channel layer has a bottom wall opposite to the boss, and the bottom wall of the channel layer is in contact with the boss.

[0016] The three-dimensional memory also includes a stop layer located between the common source layer and the stacked structure, with a boss penetrating the stop layer.

[0017] In this case, the area of ​​the end face of the channel structure that contacts the boss is smaller than the area of ​​the surface of the boss that contacts the channel structure.

[0018] The channel structure also includes a storage function layer. The storage function layer and the channel layer have sidewalls extending from the boss in a direction away from the common source layer. The sidewalls of the storage function layer are arranged around the sidewalls of the channel layer and are in contact with the boss.

[0019] To at least partially solve the above problems, embodiments of the present invention also provide a three-dimensional memory, which is manufactured using any of the three-dimensional memory manufacturing methods described above.

[0020] To at least partially solve the above problems, embodiments of the present invention also provide a storage system, which includes a controller and a three-dimensional memory as described above, wherein the controller is coupled to the three-dimensional memory and is used to control the storage of data in the three-dimensional memory.

[0021] To at least partially solve the above problems, embodiments of the present invention also provide an electronic device that includes the above-described storage system.

[0022] The electronic devices include at least one of the following: mobile phones, desktop computers, tablet computers, laptops, servers, in-vehicle equipment, wearable devices, and power banks.

[0023] The three-dimensional memory, its fabrication method, storage system, and electronic device provided in this invention form a stop layer on a substrate and a stacked structure on the stop layer. A channel hole is then formed within the stacked structure, penetrating the stacked structure and the stop layer and extending into the substrate. The first segment of the channel hole penetrating the stop layer is then sealed to form a separator layer. Subsequently, a channel structure is formed in a second segment of the channel hole, located on the side of the separator layer away from the substrate. This ensures that the channel structure is located only on the side of the stop layer away from the substrate. Therefore, during the removal of part of the bottom of the substrate and the channel structure, reactive liquids (e.g., grinding reactive liquids) can be prevented from entering the channel structure along gaps or voids and damaging the storage cells within the channel structure. This achieves a good electrical connection between the channel structure and the bottom source layer in the three-dimensional memory and improves the yield and stability of the three-dimensional memory. [Attached Image Description]

[0024] To more clearly illustrate the technical solutions in the embodiments of the present invention, the accompanying drawings used in the description of the embodiments will be briefly introduced below. Obviously, the accompanying drawings described below are only some embodiments of the present invention. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0025] Figure 1This is a flowchart illustrating the method for fabricating a three-dimensional memory provided in an embodiment of the present invention;

[0026] Figure 2 This is a cross-sectional structural diagram after step S11 is completed according to an embodiment of the present invention;

[0027] Figure 3 This is a cross-sectional structural diagram after step S12 is completed according to an embodiment of the present invention;

[0028] Figure 4 This is a cross-sectional structural diagram after step S13 is completed according to an embodiment of the present invention;

[0029] Figure 5 This is a cross-sectional structural diagram after step S14 is completed according to an embodiment of the present invention;

[0030] Figure 6 This is another cross-sectional structural diagram after step S14 is completed, as provided in the embodiment of the present invention;

[0031] Figure 7 This is a cross-sectional structural diagram after step S15 is completed according to an embodiment of the present invention;

[0032] Figure 8 This is another cross-sectional structural diagram after step S15 is completed, as provided in the embodiment of the present invention;

[0033] Figure 9 This is a schematic cross-sectional view of the semiconductor structure obtained after forming the channel structure, provided in another embodiment;

[0034] Figure 10 This is a cross-sectional view of the semiconductor structure obtained after bonding the peripheral circuit chip to the first interconnect layer, as provided in an embodiment of the present invention.

[0035] Figure 11 This is a cross-sectional structural diagram after step S161 is completed according to an embodiment of the present invention;

[0036] Figure 12 This is a cross-sectional structural diagram after step S162 is completed according to an embodiment of the present invention;

[0037] Figure 13 This is another cross-sectional structural diagram after step S17 is completed, as provided in the embodiment of the present invention;

[0038] Figure 14 This is a schematic cross-sectional view of the semiconductor structure obtained after forming the second interconnect layer, provided in an embodiment of the present invention.

[0039] Figure 15 This is a schematic diagram of the structure of the storage system provided in an embodiment of the present invention;

[0040] Figure 16 This is a schematic diagram of the structure of the electronic device provided in an embodiment of the present invention.

Detailed Implementation Methods

[0041] The embodiments of the present invention will be further described in detail below with reference to the accompanying drawings and examples. It should be particularly noted that the following embodiments are only used to illustrate the embodiments of the present invention and do not limit the scope of the embodiments of the present invention. Similarly, the following embodiments are only some embodiments of the embodiments of the present invention, and not all embodiments. All other embodiments obtained by those skilled in the art without creative effort are within the protection scope of the embodiments of the present invention.

[0042] Furthermore, the directional terms mentioned in the embodiments of this invention, such as [up], [down], [front], [back], [left], [right], [inner], [outer], and [side], are only for reference to the accompanying drawings. Therefore, the directional terms used are for illustrating and understanding the embodiments of this invention, and not for limiting the embodiments of this invention. In the various drawings, structurally similar units are represented by the same reference numerals. For clarity, the various parts in the drawings are not drawn to scale. In addition, some well-known parts may not be shown in the drawings.

[0043] The embodiments of the present invention may be presented in various forms, and some examples will be described below.

[0044] Please see Figure 1 , Figure 1 This is a schematic flowchart of a method for fabricating a three-dimensional memory according to an embodiment of the present invention. The specific process of the method for fabricating the three-dimensional memory is as follows:

[0045] Step S11: Form a stop layer on the substrate.

[0046] The cross-sectional structure diagram after step S11 is shown below. Figure 2 As shown.

[0047] The substrate 11 is used to support the device structure thereon and may include semiconductor materials such as silicon, germanium or silicon-on-insulator (SOI).

[0048] In one embodiment, such as Figure 2 As shown, the substrate 11 may include a substrate 111 and a sacrificial layer 112. Specifically, the sacrificial layer 112 may be formed on the substrate 111 using a thin film deposition process (e.g., chemical vapor deposition process) to obtain the aforementioned substrate 11.

[0049] The substrate 111 can be made of semiconductor materials such as silicon, germanium, or silicon-on-insulator (SOI). The sacrificial layer 112 can be made of insulating materials such as silicon oxide, and the sacrificial layer 112 can be used to protect the substrate 111 from damage in subsequent process steps.

[0050] In this embodiment, the stop layer 12 can be formed on the substrate 11 using a thin film deposition process (e.g., chemical vapor deposition). Furthermore, when the substrate 11 includes a substrate 111 and a sacrificial layer 112, the stop layer 12 can be specifically formed on the side of the sacrificial layer 112 facing away from the substrate 111.

[0051] The stop layer 12 may be made of, but is not limited to, polysilicon. In some embodiments, the stop layer 12 and the substrate 111 may be made of the same material, that is, they may be prepared using the same material.

[0052] Step S12: Form a stacked structure on the stop layer.

[0053] The cross-sectional structure diagram after step S12 is shown below. Figure 3 As shown.

[0054] The stacked structure 13 may include a plurality of gate sacrificial layers 131 and interlayer insulating layers 132 alternately stacked in a longitudinal direction Z perpendicular to the substrate 11. Specifically, methods such as physical vapor deposition, chemical vapor deposition, atomic layer deposition, and laser-assisted deposition can be used to form the gate sacrificial layer 131 and interlayer insulating layer 132 of the stacked structure 13 on the stop layer 12. The gate sacrificial layer 131 may be, but is not limited to, silicon nitride, and the interlayer insulating layer 132 may be, but is not limited to, silicon oxide, thereby forming a silicon nitride / silicon oxide stacked structure 13. Furthermore, in subsequent process steps, the gate sacrificial layer 131 may be replaced by a replacement process, and a conductive material (e.g., tungsten) may be filled at the same location to form a gate layer.

[0055] In a three-dimensional memory, the number of layers in the stacked structure 13 determines the number of storage cells it contains in the vertical direction (that is, the longitudinal direction Z perpendicular to the substrate 11). For example, the stacked structure 13 can have 32, 64, 96, or 128 layers, and the more layers the stacked structure 13 has, the higher the integration of the corresponding three-dimensional memory.

[0056] Step S13: Forming a channel hole that penetrates the stacked structure and the stop layer and extends into the substrate.

[0057] The cross-sectional structure diagram after step S13 is shown below. Figure 4 As shown.

[0058] Specifically, an anisotropic etching process (e.g., dry etching) can be used to sequentially etch the aforementioned stacked structure 13, stop layer 12, and substrate 11 from top to bottom, forming a channel hole 14 that penetrates the stacked structure 13, stop layer 12, and part of the substrate 11 from top to bottom. The channel hole 14 extends into the substrate 11 and forms a groove 143 within the substrate 11. Furthermore, when the substrate 11 includes a substrate 111 and a sacrificial layer 112, the aforementioned channel hole 14 can penetrate the sacrificial layer 112 in the substrate 11 and extend into the interior of the substrate 111 in the substrate 11, so as to form a notch 111A on the substrate 111 (that is, the bottom of the aforementioned groove 143).

[0059] Step S14: Seal the first section of the channel hole that penetrates the stop layer to form a separation layer.

[0060] The cross-sectional structure diagram after step S14 is shown below. Figure 5 As shown.

[0061] The partition layer 15 can separate the second hole segment 142 of the channel hole 14 located on the side of the partition layer 15 away from the substrate 11 from the groove 143. That is, the partition layer 15 can isolate the channel hole 14, and after the partition layer 15 isolates the channel hole 14, the second hole segment 142 of the channel hole 14 located above the partition layer 15 is no longer connected to the groove 143 located below the partition layer 15. Therefore, when forming the channel structure in subsequent process steps, the channel structure can be formed only in the second hole segment 142 located above the partition layer 15.

[0062] In one embodiment, such as Figure 5 As shown, to form the aforementioned separator layer 15, step S14 may specifically include: oxidizing the inner wall 141A (i.e., sidewall 141A) of the first hole segment 141 through which the channel hole 14 penetrates the stop layer 12, so that the exposed portion of the stop layer on the sidewall 141A is oxidized into a first oxide 16. The first oxide 16 extends from the unoxidized remaining stop layer in the stop layer 12 into the first hole segment 141 and connects to form a single unit, thereby filling the interior of the first hole segment 141 and obtaining the separator layer 15. The first oxide 16 and the unoxidized remaining stop layer in the stop layer 12 are arranged side-by-side and in contact on the substrate 11. Furthermore, the separator layer 15 may be the portion of the first oxide 16 extending into the first hole segment 141. Specifically, the material of the stop layer 12 may be polycrystalline silicon, and the material of the first oxide 16 may be silicon oxide.

[0063] It should be noted that the stop layer 12 (e.g., a polysilicon layer) expands after oxidation. That is, after the portion of the stop layer exposed through the sidewall 141A of the first aperture segment 141 in the stop layer 12 is oxidized to the first oxide 16, the volume of the first oxide 16 will be larger than the volume of the oxidized portion of the stop layer. Furthermore, since the oxidation direction is from the sidewall 141A of the first aperture segment 141 towards the interior of the stop layer 12, meaning the stop layer material closer to the sidewall 141A is oxidized earlier than the stop layer material farther from the sidewall 141A, the oxidized stop layer material expands from the interior of the stop layer 12 towards the first aperture segment 141, thus entering the interior of the first aperture segment 141. Moreover, when the oxidized stop layer material reaches a certain amount, it completely fills the first aperture segment 141, resulting in the aforementioned separator layer 15 composed of the oxidized stop layer material.

[0064] Furthermore, in specific implementation, a thermal oxidation process (e.g., a wet oxidation process) can be used to oxidize the material of the stop layer 12 exposed through the sidewall 141A of the first hole segment 141 to form the first oxide 16.

[0065] In one specific embodiment, the surrounding sidewalls 141A of the first hole segment 141 can be oxidized to transform the portion of the stop layer with an annular cross-section columnar shape exposed through the surrounding sidewalls 141A of the first hole segment 141 into the corresponding first oxide 16. The first oxide 16 can be a solid column, and the outer sidewall of the solid column is adjacent to and in contact with the remaining unoxidized stop layer in the stop layer 12.

[0066] In some embodiments, such as Figure 5 As shown, the substrate 11 may include a substrate 111, and the bottom of the channel hole 14 (e.g., the groove 143) may expose the substrate 111. For example, the channel hole 14 may penetrate the sacrificial layer 112 in the substrate 11 in a direction perpendicular to the substrate Z and extend into the substrate 111 to form a notch 111A on the substrate 111. Furthermore, the method for fabricating the three-dimensional memory may further include oxidizing the substrate 111 exposed through the bottom of the channel hole 14. Specifically, during the oxidation process of the sidewall 141A of the first hole segment 141, the substrate 111 exposed through the bottom of the channel hole 14 may be oxidized simultaneously.

[0067] Specifically, the material (e.g., single-crystal silicon) of the portion of the substrate 111 exposed via the inner wall of the bottom of the channel hole 14 (i.e., the recess 111A) can be oxidized to a corresponding oxide to obtain a second oxide 17. This second oxide 17 can extend from the unoxidized remaining substrate in the substrate 111 toward the recess 111A and protrude into the recess 111A. The second oxide 17 can fill all or part of the space inside the recess 111A.

[0068] In some embodiments, under the same conditions, the oxidation rate of the substrate 111 may be less than the oxidation rate of the stop layer 12. For example, the substrate 111 may be a monocrystalline silicon layer, and the stop layer 12 may be a p-doped polycrystalline silicon layer, wherein, under the same conditions, the oxidation rate of the monocrystalline silicon layer is less than that of the p-doped polycrystalline silicon layer.

[0069] Thus, when oxidizing the stop layer 12 exposed through the sidewall 141A of the first hole segment 141, the amount of substrate 111 exposed through the bottom of the channel hole 14 or the inner wall of the notch 111A can be reduced. This reduces the problem of increased difficulty in chemical mechanical polishing due to some substrate being oxidized into oxides that are difficult to polish and remove in subsequent process steps.

[0070] Furthermore, in the above embodiments, the stop layer 12 and the stacked structure 13 can be formed by using appropriate materials so that the material of the stop layer 12 exposed through the sidewall of the channel hole 14 will not be oxidized during the oxidation of the material of the stop layer 12 exposed through the sidewall of the channel hole 14.

[0071] In some alternative embodiments, such as Figure 6 As shown, the aforementioned separating layer 15 can specifically be an epitaxial portion 10. Furthermore, to form this epitaxial portion 10, step S14 can specifically include: growing the epitaxial portion 10 on the sidewall 141A of the first hole segment 141 through the stop layer 12 in the channel hole 14. The epitaxial portion 10 extends from the sidewall 141A of the first hole segment 141 inwards into the first hole segment 141 and is integrally connected to fill the interior of the first hole segment 141. The epitaxial portion 10 and the stop layer 12 are arranged side-by-side and in contact on the substrate 11.

[0072] The material of the epitaxial portion 10 may be, but is not limited to, monocrystalline silicon or polycrystalline silicon, and the material of the epitaxial portion 10 may be the same as or different from that of the stop layer 12. Specifically, the epitaxial portion 10 may be epitaxially grown on the surface of the stop layer 12 exposed on the sidewall 141A of the first via 141 by means of a selective epitaxial growth (SEG) process.

[0073] It should be noted that, compared with the method of obtaining the above-mentioned separation layer 15 by growing the epitaxial portion 10 on the sidewall 141A of the first hole segment 141, the method of obtaining the above-mentioned separation layer 15 by oxidizing the sidewall 141A of the first hole segment 141 is less difficult and more conducive to reducing production costs.

[0074] Step S15: Form a channel structure in the second segment of the channel hole, the second segment being located on the side of the separator layer away from the substrate.

[0075] The cross-sectional structure diagram after step S15 is shown below. Figure 7 As shown.

[0076] The channel structure 18 may include a storage function layer 181 and a channel layer 182 sequentially formed on the sidewall of the second hole segment 142 and the surface of the partition layer 15.

[0077] Specifically, a storage function layer 181 and a channel layer 182 can be sequentially formed on the sidewall of the second hole segment 142 and the surface of the separator layer 15. Then, a dielectric material (e.g., silicon oxide) is filled into the channel hole 14 where the storage function layer 181 and the channel layer 182 are formed to form an insulating filling layer 183 to fill the remaining space in the second hole segment 142, thereby obtaining the channel structure 18.

[0078] The channel structure 18 includes an insulating filler layer 183, a channel layer 182, and a storage function layer 181, and is located only on the side of the separator layer 15 facing away from the substrate 11. Furthermore, due to the different deposition rates of dielectric materials on different material surfaces, air gaps (or voids or slits) 18A may be formed inside the insulating filler layer 183 (i.e., inside the channel structure 18).

[0079] It should be noted that although the aforementioned air cavity gap 18A may be formed inside the channel structure 18 in the second hole segment 142 of each channel hole 14, in practice, only some of the channel structures 18 in the second hole segment 142 of the channel hole 14 may have the aforementioned air cavity gap 18A formed, or all of the channel structures 18 in the second hole segment 142 of the channel hole 14 may have the aforementioned air cavity gap 18A formed, or none of the channel structures 18 in the second hole segment 142 of the channel hole 14 may have the aforementioned air cavity gap 18A formed (that is, the second hole segment 142 of each channel hole 14 may be completely filled by the corresponding channel structure 18, so as not to form the aforementioned air cavity gap 18A). Furthermore, it is understood that the aforementioned air cavity gap 18A is not expected to be formed within the aforementioned channel structure 18.

[0080] The aforementioned storage functional layer 181 may include a charge blocking layer, a charge trapping layer, and a tunneling layer sequentially formed on the sidewalls and bottom surfaces of the second via segment 142. Specifically, the charge blocking layer, charge trapping layer, tunneling layer, and the aforementioned channel layer 182 may be made of silicon oxide, silicon nitride, silicon oxide, and polysilicon, respectively, corresponding to the aforementioned channel structure 18 as an "ONOP" structure. Furthermore, it is understood that although the storage functional layer exemplified here is an ONO structure composed of an oxide layer, a nitride layer, and another oxide layer, other possible structures are also possible.

[0081] In the above embodiments, in order to increase the storage density of the three-dimensional memory by increasing the number of layers of the stacked structure 13 without increasing the difficulty of the etching process for forming the above-mentioned channel hole 14, the stacked structure 13 may include multiple stacked structures stacked in the longitudinal Z direction, and the channel hole 14 through the stacked structure 13 can be formed by multiple etching processes.

[0082] Specifically, such as Figure 8 As shown, the aforementioned stacked structure 13 may include a first stacked structure 13A and a second stacked structure 13B stacked in the longitudinal direction Z. Accordingly, step S12 may specifically include: forming the first stacked structure 13A on the stop layer 12; forming a first channel hole 14A, the first channel hole 14A penetrating the first stacked structure 13A and the stop layer 12, and extending into the substrate 11; forming a sacrificial material layer in the first channel hole 14A; and forming a second stacked structure 13B on the first stacked structure 13A and the sacrificial material layer to obtain a stacked structure 13 including the first stacked structure 13A and the second stacked structure 13B. Step S13 may specifically include: forming a second channel hole 14B penetrating the second stacked structure 13B, the second channel hole 14B exposing the sacrificial material layer; and removing the sacrificial material layer through the second channel hole 14B to obtain a channel hole 14 including the first channel hole 14A and the second channel hole 14B.

[0083] The first stack structure 13A and the second stack structure 13B in the stacked structure 13 can both include multiple layers of gate sacrificial layers 131 and interlayer insulating layers 132 alternately stacked in the longitudinal direction Z perpendicular to the substrate 11. Furthermore, the number of layers in the second stack structure 13B can be the same as or different from the number of layers in the first stack structure 13A.

[0084] The first channel hole 14A can penetrate the first stack structure 13A and the stop layer 12 in a longitudinal direction Z perpendicular to the substrate 11, and extend into the interior of the substrate 111 to form a notch 111A on the substrate. The second channel hole 14B can penetrate the second stack structure 13B in a longitudinal direction Z perpendicular to the substrate 11, and the bottom of the second channel hole 14B exposes the top surface of the sacrificial material layer in the first channel hole 14A.

[0085] The aforementioned sacrificial material layer can be formed by depositing and filling the sacrificial material in the first channel hole 14A using a chemical vapor deposition process, and then removing the sacrificial material located outside the first channel hole 14A using chemical mechanical planarization. The sacrificial material can be any one of polycrystalline silicon, carbon, and tungsten.

[0086] The aforementioned via 14 includes a first via 14A and a second via 14B that are interconnected. After the second via 14B is formed, a selective etchant can be used to selectively etch away the sacrificial material layer relative to the first stack structure 13A and the second stack structure 13B via the second via 14B to obtain the aforementioned via 14. Subsequently, a separator layer 15 can be formed in the first via segment 141 of the via 14 adjacent to the stop layer 12, separating the via 14. Then, the aforementioned channel structure 18 is formed in the second via segment 142 of the via 14 located above the separator layer 15.

[0087] like Figure 9 As shown, according to another method for fabricating a three-dimensional memory, after forming the via 24, a channel structure 28 is formed throughout the via 24. The channel structure 28 penetrates the stacked structure 23 and the stop layer 22 and extends into the interior of the substrate 21. Since the via 24, where the storage functional layer 281 and the channel layer 282 are formed, is filled with a dielectric material (e.g., silicon oxide), an air cavity gap 28A is formed inside the resulting insulating filling layer 283. This air cavity gap 28A extends from the stacked structure 23 toward the substrate 21 to the side of the stop layer 22 away from the stacked structure 23. Therefore, when the substrate 21 is removed in subsequent process steps, the reaction solution used to remove the substrate 21 (e.g., the polishing reaction solution used to remove the substrate 11 by chemical mechanical polishing) will enter the interior of the channel structure 28 along the air cavity gap 28A from the side of the stop layer 22 away from the stacked structure 23, leading to defects in the memory cells within the channel structure 28.

[0088] The inventors discovered that, as Figure 9As shown, when the stacked structure 23 includes a first stacked structure 23A and a second stacked structure 23B stacked in the longitudinal direction Z, the small aperture of the channel holes at the connection between the first stacked structure 23A and the second stacked structure 23B will cause the lower channel hole 24A in the stacked structure (i.e., the first stacked structure 23A) near the substrate 21 to be sealed prematurely when the channel hole 24 (including the lower channel hole 24A and the upper channel hole 24B) forming the storage functional layer 281 and the channel layer 282 is filled with dielectric material (e.g., silicon oxide) to form an insulating filling layer 283. This will result in a large void 28A forming inside the channel structure segment of the channel structure 28 that penetrates the first stacked structure 23A. The presence of these voids 28A will cause the reaction liquid to enter the interior of the channel structure 28 during the subsequent removal of the substrate 21, which will seriously affect the performance of the memory cells in the channel structure 28.

[0089] Furthermore, compared to the scheme of not sealing the first hole segment 241 through the stop layer 22 of the channel hole 24, that is, forming a channel structure 28 in the entire channel hole 24 and extending the channel structure 28 to the side of the stop layer 22 away from the stacked structure 23, this embodiment forms a separator layer 15 by sealing the first hole segment 141 through the stop layer 12 of the channel hole 14, and forms a channel structure 18 only in the second hole segment 142 above the separator layer 15 of the channel hole 14. This makes the channel structure 18 only located on the side of the stop layer 12 away from the substrate 11. Therefore, in the subsequent process step of removing the substrate 11, the reaction liquid can be prevented from entering the interior of the channel structure through the pores inside the channel structure, thus affecting the quality of the memory cells in the channel structure 18.

[0090] In some specific embodiments, such as Figure 10 As shown, after forming the aforementioned channel structure 18, the fabrication method of the aforementioned three-dimensional memory may further include: forming a gate line gap that penetrates the stacked structure 13 and extends to the stop layer 12; removing the gate sacrificial layer 131 in the aforementioned stacked structure 13 through the gate line gap to form a sacrificial gap; forming a gate layer 131 within the sacrificial gap (in this case, the gate layer and the gate sacrificial layer are represented by the same reference numerals); and filling the gate line gap with an insulating material (e.g., oxide) and / or a conductive material (e.g., titanium, polysilicon, and / or tungsten) to form a gate line gap structure 19.

[0091] In some embodiments, such as Figure 10 As shown, the width of each gate layer 131 at at least one end of the above-mentioned stacked structure 13 can be successively reduced in the direction away from the substrate 11 to form a stepped structure 13C. Furthermore, after forming the above-mentioned gate gap structure 19, the above-mentioned method for manufacturing the three-dimensional memory may further include: forming a plurality of word line contacts 32A, which are electrically connected to the gate layer 131 at the positions of the stepped structure 13C.

[0092] Specifically, the aforementioned plurality of letter contacts 32A can be perpendicular to the base 11 and can extend longitudinally in the Z direction to the multiple steps of the stepped structure 13C. In one embodiment, as Figure 10 As shown, while forming the multiple word line contacts 32A, peripheral pad contacts 32B can also be formed around the periphery of the stacked structure 13. The peripheral pad contacts 32B are used for electrical connection with peripheral circuits, and their number and arrangement can be prepared according to actual needs. The materials of the word line contacts 32A and the peripheral pad contacts 32B can be conductive materials, such as tungsten.

[0093] In some specific embodiments, such as Figure 10 As shown, after forming the word line contact 32A and the peripheral pad contact 32B, the fabrication method of the three-dimensional memory may further include: forming a first interlayer dielectric layer 33 on the stacked structure 13; forming a plurality of first conductive contacts 34 penetrating the first interlayer dielectric layer 33; and forming a first interconnect layer 35 on the first interlayer dielectric layer 33. The first interlayer dielectric layer 33 may be made of an insulating material such as silicon oxide. The first interconnect layer 35 may be made of a conductive material such as tungsten.

[0094] Specifically, the plurality of first conductive contacts 34 may include bit line contacts, which may extend in a direction Z perpendicular to the substrate 11, with one end electrically connected to the channel structure 18 and the other end electrically connected to a corresponding conductive trace in the first interconnect layer 35. In some embodiments, the plurality of first conductive contacts 34 may further include peripheral circuit contacts, which may extend in a direction Z perpendicular to the substrate 11, with one end electrically connected to a corresponding peripheral circuit contact 32B and the other end electrically connected to a corresponding conductive trace in the first interconnect layer 35.

[0095] In some specific embodiments, such as Figure 10 As shown, after forming the first interconnect layer 35, the fabrication method of the three-dimensional memory may further include: providing a peripheral circuit chip 36 and bonding the peripheral circuit chip 36 to the first interconnect layer 35 using a bonding structure. Furthermore, the peripheral circuit chip 36 and the bonding structure can be found in specific embodiments of peripheral circuit chips and bonding structures in the prior art, and therefore will not be described in detail here.

[0096] In the above embodiments, after step S15, the following may also be included:

[0097] Step S16: Remove the substrate and separator layer to expose the ends of the channel layer.

[0098] Specifically, the substrate 11 includes a substrate 111 and a sacrificial layer 112 formed on the substrate 111, the stop layer 12 is formed on the sacrificial layer 112, and step S16 may specifically include:

[0099] Step S161: Remove the substrate to expose the sacrificial layer.

[0100] The cross-sectional structural diagram after step S161 can be as follows: Figure 11 As shown.

[0101] Specifically, the semiconductor structure obtained after the preceding steps can be flipped 180°, and then the substrate 111 can be polished using the sacrificial layer 112 as the polishing stop layer until the sacrificial layer 112 is exposed.

[0102] Step S162: Selectively etch away the sacrificial layer, the separator layer, and the storage function layer located at the end of the channel structure in contact with the separator layer relative to the stop layer, so as to expose the end of the stop layer and the channel layer.

[0103] The cross-sectional structure diagram after step S162 can be as follows: Figure 12 As shown.

[0104] Specifically, a selective etchant can be used, with the end 182A of the channel layer 182 as the etching stop layer, to selectively etch away the sacrificial layer 112, the separation layer 15, and the storage function layer 181 located at the end 18B of the channel structure 18 in contact with the separation layer 15, relative to the stop layer 12, until the stop layer 12 and the end 182A of the channel layer 182 are exposed.

[0105] In some embodiments, when the partition layer 15 is obtained by oxidizing the sidewall 141A of the first hole segment 141 adjacent to the stop layer 12 of the channel hole 14, that is, when the partition layer 15 is a portion of the first oxide 16 extending into the first hole segment 141, during the selective etching removal of the sacrificial layer 112 and the partition layer 15, the remaining first oxide in the first oxide 16 located around the partition layer 15 is simultaneously etched away to form a through hole 121 on the stop layer 12 with a diameter larger than that of the first hole segment 141. Further, during the selective etching removal of the storage function layer 181 located at the end 18B of the channel structure 18 in contact with the partition layer 15, a portion of the stacked structure 13 located around the end 18B of the channel structure 18 and exposed through the through hole 121 is simultaneously removed to form a bottom recess 13D, thereby obtaining an opening 20 including the through hole 121 and the bottom recess 13D.

[0106] The end 182A of the channel layer 182 exposed through the opening 20 and the end 181A of the storage function layer 181 exposed through the opening 20 can be flush. That is, the end face of the end 182A of the channel layer 182, the end face of the end 181A of the storage function layer 181, and the bottom surface of the opening 20 can be located in the same horizontal plane.

[0107] It should be noted that, compared with the method of removing the substrate and sacrificial layer by grinding, this embodiment removes the sacrificial layer by etching, which saves the process steps of removing the sacrificial layer by grinding and helps to reduce production costs.

[0108] Step S17: A common source electrode layer is formed on the side of the stop layer away from the stacked structure, covering and connecting the end of the channel layer.

[0109] The cross-sectional structure diagram after step S17 is completed can be shown as follows: Figure 13 As shown.

[0110] Specifically, a common source layer 30 covering the end 182A of the channel layer 182 can be formed on the side of the stop layer 12 facing away from the stacked structure 13. The common source layer 30 may include polysilicon. For example, the common source layer 30 may include P-type doped polysilicon.

[0111] In some embodiments, such as Figure 14 As shown, after step S17, the fabrication method of the three-dimensional memory may further include: forming a second interlayer dielectric layer 31 on the side of the common source layer 30 away from the stacked structure 13; forming a plurality of second conductive contacts 37 penetrating the second interlayer dielectric layer 31; and forming a second interconnect layer 38 on the side of the second interlayer dielectric layer 31 away from the common source layer 30.

[0112] Specifically, the plurality of second conductive contacts 37 may include source contacts that extend longitudinally in the Z direction, with one end electrically connected to the common source layer 30 and the other end electrically connected to the second interconnect layer 38. In some embodiments, the plurality of second conductive contacts 37 may further include peripheral circuit contacts that extend longitudinally in the Z direction, with one end electrically connected to the peripheral circuit contact 32B and the other end electrically connected to the second interconnect layer 38.

[0113] The fabrication method of the three-dimensional memory in this embodiment involves forming a stop layer on a substrate, forming a stacked structure on the stop layer, and then forming a channel hole that penetrates the stacked structure and the stop layer and extends into the substrate. Next, the first segment of the channel hole penetrating the stop layer is sealed to form a separator layer. Then, a channel structure is formed in the second segment of the channel hole, located on the side of the separator layer away from the substrate. This ensures that the channel structure is located on the side of the stop layer away from the substrate. Therefore, during the removal of the substrate and the bottom of the channel structure, it is possible to prevent the reaction liquid (e.g., grinding reaction liquid) from entering the channel structure along the gaps or voids inside the channel structure and damaging the memory cells within the channel structure. This achieves a good electrical connection between the channel structure and the bottom source layer in the three-dimensional memory and improves the yield and stability of the three-dimensional memory.

[0114] The three-dimensional memory fabricated according to the above method embodiments of the present invention is as follows: Figure 14 As shown, the three-dimensional memory may include:

[0115] The three-dimensional memory fabricated according to the above method embodiments of the present invention is as follows: Figure 14 As shown, the three-dimensional memory may include: a common source layer 30, a stacked structure 13 located on one side of the common source layer 30, and a channel structure 18 passing through a portion of the stacked structure 13. The channel structure 18 includes a channel layer 182. Furthermore, a boss 301 protrudes from the side of the common source layer 30 facing the stacked structure 13 at a position relative to the channel structure 18. The boss 301 extends from the surface of the common source layer 30 toward the channel structure 18, passes through the remaining portion of the stacked structure 13, and connects to the end 182A of the channel layer 182.

[0116] In one embodiment, the aforementioned three-dimensional memory may further include a gap 18A, which is sealed within the channel structure 18. This avoids the problem in existing three-dimensional memories where a gap is formed inside the channel structure during its formation, and this gap is exposed from the back side of the substrate during substrate removal, allowing the reaction liquid used to remove the substrate to enter the channel structure along the exposed gap, leading to defective memory cells in the channel structure. In other words, even if a gap 18A is formed inside the channel structure 18 during its formation in this embodiment, because the channel structure 18 is only formed on the side of the stop layer 12 away from the substrate, the gap 18A is always sealed within the channel structure 18 during substrate removal and is not exposed. This prevents the reaction liquid used to remove the substrate from entering the channel structure through the gap and affecting the quality of the memory cells in the channel structure.

[0117] In one specific embodiment, the aforementioned stacked structure 13 may include a first stacked structure (such as...) arranged sequentially in a direction away from the common source layer 30. Figure 8 The first stack structure 13A shown) and the second stack structure (as shown) Figure 8 The second stack structure 13B shown in the figure, and the aforementioned gap 18A may be located in a portion of the channel structure 18 arranged parallel to the first stack structure.

[0118] In one embodiment, the channel layer 182 may have a bottom wall opposite to the boss 301, and the bottom wall of the channel layer 182 is in contact with the boss 301, thereby increasing the contact area and improving electrical performance.

[0119] In one embodiment, the three-dimensional memory may further include a stop layer 12 located between the common source layer 30 and the stacked structure 13. The boss 301 extends through the stop layer 12.

[0120] In one embodiment, the area of ​​the end face of the channel structure 18 that contacts the boss 301 can be smaller than the area of ​​the surface of the boss 301 that contacts the channel structure 18, thereby further increasing the contact area and further improving the electrical performance.

[0121] In one embodiment, the channel structure 18 may further include a storage function layer 181, and both the storage function layer 181 and the channel layer 182 have sidewalls extending from the protrusion 301 in a direction away from the common source layer 30. The sidewall of the storage function layer 181 surrounds the sidewall of the channel layer 182 and contacts the protrusion 301. It should be noted that, unlike the channel layer 182 which has a bottom wall opposite to the protrusion 301, the storage function layer 181 may not have a bottom wall opposite to the protrusion 301, or it may have a bottom wall opposite to the protrusion 301 and have a window, to ensure that the bottom wall of the channel layer 182 located inside the storage function layer 181 can be exposed.

[0122] Specifically, the end 182A of the aforementioned channel layer 182 can be flush with the end 181A of the storage function layer 181. The end 182A of the channel layer 182 is the end of the channel layer 182 in the aforementioned channel structure 18 that contacts the aforementioned boss 301, and the end 181A of the storage function layer 181 is the end of the storage function layer 181 in the aforementioned channel structure 18 that contacts the aforementioned boss 301.

[0123] It should be noted that the various structures of the three-dimensional memory in this embodiment can refer to the specific implementation methods described in the above method embodiments, so they will not be repeated here.

[0124] The three-dimensional memory provided in this embodiment, by placing the channel structure only on the side of the stop layer away from the substrate, can prevent the reaction liquid (e.g., grinding reaction liquid) from entering the interior of the channel structure along the gaps or voids inside the channel structure and damaging the memory cells in the channel structure during the process of removing part of the bottom of the substrate and the channel structure. This achieves good electrical connection between the channel structure and the bottom source layer in the three-dimensional memory and improves the yield and stability of the three-dimensional memory.

[0125] Accordingly, such as Figure 15 As shown, this embodiment of the invention also provides a storage system 40, which includes a controller 41 and a three-dimensional memory 42. The controller 41 is coupled to the three-dimensional memory 42 and is used to control the three-dimensional memory 42 to store data.

[0126] The three-dimensional memory 42 may be the same as the three-dimensional memory described in any of the embodiments above, and therefore will not be repeated here. The controller 41 controls the three-dimensional memory 42 via channel CH, and the three-dimensional memory 42 can perform operations based on the control of the controller 41 in response to requests from the host 50. The three-dimensional memory 42 receives commands CMD and addresses ADDR from the controller 41 via channel CH and accesses the region selected from the memory cell array in response to that address. In other words, the three-dimensional memory 42 can perform internal operations corresponding to commands on the region selected by the address.

[0127] In some implementations, the storage system 40 may be implemented as a Universal Flash Storage (UFS) device, a Solid State Drive (SSD), a Multimedia Card in the form of MMC, eMMC, RS-MMC, and Micro MMC, a Secure Digital Card in the form of SD, Mini SD, and Micro SD, a PCMCIA card type storage device, a Peripheral Component Interconnect (PCI) type storage device, a High Speed ​​PCI (PCI-E) type storage device, a Compact Flash (CF) card, a Smart Media Card, or a Memory Stick, etc.

[0128] Specifically, the aforementioned storage system 40 can be used in terminal products such as computers, televisions, set-top boxes, and in-vehicle systems.

[0129] The storage system provided in this embodiment, by placing the channel structure only on the side of the stop layer away from the substrate, can prevent the reaction liquid (e.g., grinding reaction liquid) from entering the interior of the channel structure along the seams or gaps inside the channel structure and damaging the storage cells in the channel structure during the process of removing part of the bottom of the substrate and the channel structure. This achieves good electrical connection between the channel structure and the bottom source layer in the three-dimensional memory and improves the yield and stability of the three-dimensional memory.

[0130] Accordingly, such as Figure 16As shown, this embodiment of the invention also provides an electronic device 60, which includes the storage system 61 provided in this embodiment of the invention. Specifically, the electronic device 60 can be any device capable of storing data, such as a mobile phone, desktop computer, tablet computer, laptop computer, server, vehicle-mounted device, wearable device, or power bank.

[0131] An electronic device provided in this embodiment of the invention has the same beneficial effects as the storage system described above due to the inclusion of the storage system provided in this embodiment of the invention.

[0132] The above description is only a preferred embodiment of the present invention and is not intended to limit the present invention. Any modifications, equivalent substitutions, and improvements made within the spirit and principles of the present invention should be included within the protection scope of the present invention.

Claims

1. A method for fabricating a three-dimensional memory, characterized in that, include: A stop layer is formed on the substrate; A stacked structure is formed on the stop layer; A channel hole is formed, which penetrates the stacked structure and the stop layer and extends into the substrate; The first section of the channel hole penetrating the stop layer is sealed to form a separation layer; A channel structure is formed in the second segment of the channel hole, the second segment being located on the side of the separator layer opposite to the substrate.

2. The method for manufacturing a three-dimensional memory according to claim 1, characterized in that, The step of sealing the first section of the channel hole that penetrates the stop layer to form a separation layer specifically includes: The inner wall of the first hole segment is oxidized so that the exposed portion of the stop layer on the inner wall of the first hole segment is oxidized into an oxide. The oxide extends from the remaining unoxidized stop layer into the first hole segment to form the separator layer.

3. The method for manufacturing a three-dimensional memory according to claim 2, characterized in that, The substrate includes a substrate, and the method further includes: When the inner wall of the first hole is oxidized, the substrate exposed through the bottom of the channel hole is also oxidized, and the rate at which the substrate is oxidized is less than the rate at which the stop layer is oxidized.

4. The method for manufacturing a three-dimensional memory according to claim 1, characterized in that, The step of sealing the first section of the channel hole that penetrates the stop layer to form a separation layer specifically includes: The separator layer is grown on the inner wall of the first hole segment.

5. The method for manufacturing a three-dimensional memory according to any one of claims 1 to 4, characterized in that, The formation of the channel structure in the second section of the channel hole specifically includes: A channel structure including a channel layer is formed on the inner wall of the second hole section; Furthermore, after the channel structure is formed in the second section of the channel hole, it also includes: Remove the substrate and the separator layer to expose the ends of the channel layer; A common source electrode layer is formed on the side of the stop layer opposite to the stacked structure, covering and connecting the end of the channel layer.

6. The method for manufacturing a three-dimensional memory according to claim 5, characterized in that... The channel structure further includes a storage functional layer, which is sequentially formed on the inner wall of the second via segment along with the channel layer. The substrate includes a substrate and a sacrificial layer formed on the substrate. The stop layer is formed on the sacrificial layer. The step of removing the substrate and the separator layer to expose the end of the channel layer specifically includes: Remove the substrate to expose the sacrificial layer; Relative to the stop layer, the sacrificial layer, the separator layer, and the storage function layer located at the end of the channel structure in contact with the separator layer are selectively etched away to expose the ends of the stop layer and the channel layer.

7. The method for manufacturing a three-dimensional memory according to claim 1, characterized in that, The formation of a stacked structure on the stop layer specifically includes: A first stack structure is formed on the stop layer; A first channel hole is formed, which penetrates the first stack structure and the stop layer and extends into the substrate; A sacrificial material layer is formed in the first channel hole; A second stack structure is formed on the first stack structure and the sacrificial material layer to obtain the stacked structure including the first stack structure and the second stack structure; The formation of the channel hole specifically includes: A second channel hole is formed through the second stack structure, the second channel hole exposing the sacrificial material layer; The sacrificial material layer is removed via the second channel hole to obtain the channel hole including the first channel hole and the second channel hole.

8. A three-dimensional memory, characterized in that, include: Common source pole layer; A stacked structure located on one side of the common source electrode layer; A channel structure passing through a portion of the stacked structure, the channel structure comprising a channel layer; In this configuration, the common source electrode layer protrudes to one side of the stacked structure relative to the channel structure to form a boss, which passes through the remaining portion of the stacked structure and connects to the end of the channel layer.

9. The three-dimensional memory according to claim 8, characterized in that, The three-dimensional memory includes a gap that is sealed within the channel structure.

10. The three-dimensional memory according to claim 9, characterized in that, The stacked structure includes a first stack structure and a second stack structure arranged sequentially in a direction away from the common source layer, and the gap is located in a portion of the channel structure arranged parallel to the first stack structure.

11. The three-dimensional memory according to claim 8, characterized in that, The channel layer has a bottom wall opposite to the boss, and the bottom wall of the channel layer is in contact with the boss.

12. The three-dimensional memory according to claim 8, characterized in that, The three-dimensional memory also includes: A stop layer is located between the common source electrode layer and the stacked structure, and the boss penetrates the stop layer.

13. The three-dimensional memory according to claim 8, characterized in that, The area of ​​the end face of the channel structure that contacts the boss is smaller than the area of ​​the surface of the boss that contacts the channel structure.

14. The three-dimensional memory according to claim 8, characterized in that, The channel structure further includes a storage function layer, the storage function layer and the channel layer having sidewalls extending from the boss in a direction away from the common source layer, the sidewalls of the storage function layer being disposed around the sidewalls of the channel layer and in contact with the boss.

15. A three-dimensional memory, characterized in that, The three-dimensional memory is manufactured using the method described in any one of claims 1 to 7.

16. A storage system, characterized in that, The storage system includes a controller and a three-dimensional memory as described in any one of claims 8 to 15, wherein the controller is coupled to the three-dimensional memory and is used to control the storage of data in the three-dimensional memory.

17. An electronic device, characterized in that, Includes the storage system described in claim 16.

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