Display panel and its manufacturing method

Abstract

This application discloses a display panel and its fabrication method. The display panel includes a substrate, a transistor layer, and pixel electrodes. The transistor layer is disposed on the substrate, and an induced crystallization portion is disposed on the side of the transistor layer away from the substrate. The pixel electrodes are disposed on the transistor layer and located on the induced crystallization portion. In this application, by providing an induced crystallization portion on the transistor layer to induce crystallization of the pixel electrodes located on the induced crystallization portion, the exposure process is eliminated during the fabrication of the pixel electrodes, thereby reducing the number of exposure processes in the display panel and simplifying the fabrication process of the display panel.

Description

Technical Field

[0001] This application relates to the field of display technology, specifically to a display panel and its manufacturing method. Background Technology

[0002] In manufacturing, streamlining production processes and reducing production costs are timeless pursuits; this is also true in the display panel industry. Currently, the most widely used display technology, Thin Film Transistor (TFT) display panels, suffer from increasingly complex processes and higher costs due to the precision of the exposure process and the high price of exposure equipment. More exposure steps mean greater process complexity and higher manufacturing costs. In existing display panels, the fabrication of pixel electrodes and passivation layers typically requires two exposure processes, further increasing the panel's manufacturing cost. Summary of the Invention

[0003] This application provides a display panel and a method for manufacturing the same, thereby reducing the manufacturing cost of the display panel.

[0004] This application provides a display panel, including:

[0005] Substrate;

[0006] A transistor layer, wherein the transistor layer is disposed on the substrate, and an induced crystallization portion is disposed on the side of the transistor layer away from the substrate; and

[0007] A pixel electrode is disposed on the transistor layer and located on the induced crystallization portion, wherein the pixel electrode is a crystallized pixel electrode.

[0008] Optionally, in some embodiments of this application, the induced crystallization portion includes a first induced crystallization portion and a second induced crystallization portion, and the transistor layer includes a transistor and a passivation layer disposed on the transistor;

[0009] The transistor includes a first electrode, and the first induced crystallization portion is disposed on the side of the first electrode away from the substrate;

[0010] The passivation layer includes a via that penetrates the passivation layer to expose the first induced crystallization portion. The second induced crystallization portion is disposed on the side of the passivation layer away from the substrate, and the second induced crystallization portion is disposed around the via.

[0011] Optionally, in some embodiments of this application, the first induced crystallization portion is a first rough surface, and the second induced crystallization portion is a second rough surface.

[0012] Optionally, in some embodiments of this application, the roughness of both the first rough surface and the second rough surface is greater than or equal to 10 nanometers.

[0013] Optionally, in some embodiments of this application, the roughness of the first rough surface is greater than the roughness of the second rough surface.

[0014] Optionally, in some embodiments of this application, the passivation layer has a plurality of second induced crystallization portions spaced apart on the side away from the substrate.

[0015] Accordingly, this application also provides a method for manufacturing a display panel, comprising:

[0016] Provide a substrate;

[0017] A transistor layer material is disposed on the substrate, and the transistor layer material is patterned to form a transistor layer. An induced crystallization portion is disposed on the side of the transistor layer away from the substrate.

[0018] A pixel electrode is formed on the transistor layer, and the pixel electrode is located on the induced crystallization portion, wherein the pixel electrode is a crystallized pixel electrode.

[0019] Optionally, in some embodiments of this application, the transistor layer includes a transistor and a passivation layer disposed on the transistor, the transistor including a first electrode, and the step of forming the transistor layer by patterning the transistor layer material on the substrate includes:

[0020] A conductive layer for transistors is formed on the substrate;

[0021] A passivation layer material is disposed on the transistor and patterned, wherein the passivation layer material forms a passivation layer and the conductive layer forms a first electrode;

[0022] Wherein, a first induced crystallization portion is formed on the side of the first electrode away from the substrate, the passivation layer includes a via through the passivation layer to expose the first induced crystallization portion, and a second induced crystallization portion is formed on the surface of the passivation layer away from the substrate.

[0023] Optionally, in some embodiments of this application, the transistor layer includes an amorphous region and crystalline regions disposed on both sides of the amorphous region, the conductive layer is located in the crystalline region, a passivation layer material is disposed on the transistor and patterned, the passivation layer material forms a passivation layer, and the step of forming the first electrode with the conductive layer includes:

[0024] A passivation layer material is disposed on the transistor layer;

[0025] A photoresist layer is provided, the photoresist layer being disposed on the passivation layer material and located in the amorphous region;

[0026] The passivation layer material is subjected to a first patterning process to form a passivation intermediate layer with through holes, the through holes penetrating the passivation intermediate layer to expose the conductive layer;

[0027] The passivation intermediate layer is subjected to a second patterning process, the conductive layer forms a first electrode, the side of the first electrode away from the substrate forms a first induced crystallization portion, the passivation intermediate layer forms a passivation layer, the side of the passivation layer away from the substrate forms a second induced crystallization portion, the second induced crystallization portion is disposed around the through hole, and the first induced crystallization portion and the second induced crystallization portion are located in the crystallization region;

[0028] Remove the photoresist layer.

[0029] Optionally, in some embodiments of this application, the step of providing a pixel electrode on the passivation layer, the pixel electrode being disposed in the second induced crystallization portion, and extending into the via to contact the first induced crystallization portion includes:

[0030] A pixel electrode material is disposed on the passivation layer and processed by wet etching to form a pixel electrode. The pixel electrode is located in the second induced crystallization part and extends into the through hole to contact the first induced crystallization part.

[0031] This application discloses a display panel and its fabrication method. The display panel includes a substrate, a transistor layer, and pixel electrodes. The transistor layer is disposed on the substrate, and an induced crystallization portion is disposed on the side of the transistor layer away from the substrate. The pixel electrodes are disposed on the transistor layer and located on the induced crystallization portion. In this application, by providing an induced crystallization portion on the transistor layer to induce crystallization of the pixel electrodes located on the induced crystallization portion, the exposure process is eliminated during the fabrication of the pixel electrodes, thereby reducing the number of exposure processes in the display panel and simplifying the fabrication process of the display panel. Attached Figure Description

[0032] To more clearly illustrate the technical solutions in the embodiments of this application, the accompanying drawings used in the description of the embodiments will be briefly introduced below. Obviously, the accompanying drawings described below are only some embodiments of this application. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0033] Figure 1 This is a schematic diagram of the structure of the display panel provided in the embodiment of this application.

[0034] Figure 2 This is a schematic diagram of the process steps of the method for manufacturing a display panel provided in the embodiments of this application.

[0035] Figures 3-9 This is a schematic diagram of the process steps of the method for manufacturing a display panel provided in the embodiments of this application. Detailed Implementation

[0036] The technical solutions in the embodiments of this application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of this application, and not all embodiments. Based on the embodiments in this application, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of this application. Furthermore, it should be understood that the specific embodiments described herein are only for illustration and explanation of this application and are not intended to limit this application. In this application, unless otherwise stated, directional terms such as "upper" and "lower" generally refer to the upper and lower positions of the device in actual use or operation, specifically the drawing directions in the accompanying drawings; while "inner" and "outer" refer to the outline of the device. In this application, "reaction" can be a chemical reaction or a physical reaction.

[0037] This application discloses a display panel and its fabrication method. The display panel includes a substrate, a transistor layer and a pixel electrode. The transistor layer is disposed on the substrate, and an induced crystallization portion is disposed on the side of the transistor layer away from the substrate. The pixel electrode is disposed on the transistor layer and located on the induced crystallization portion.

[0038] In this application, by providing an induced crystallization section on the transistor layer, the pixel electrode located on the induced crystallization section is induced to crystallize, thereby eliminating the need for an exposure process during the preparation of the pixel electrode, thus reducing the number of exposure processes in the display panel and simplifying the preparation process of the display panel.

[0039] Please see Figure 1 This application provides a display panel 10. The display panel 10 includes a substrate 100, a transistor layer 200, and pixel electrodes 300.

[0040] A transistor layer 200 is disposed on a substrate 100, and an induced crystallization portion 201 is disposed on the side of the transistor layer 200 away from the substrate 100. Specifically, the induced crystallization portion 201 is used to induce crystallization of the pixel electrode 300. The induced crystallization portion 201 includes a first induced crystallization portion 202 and at least one second induced crystallization portion 203. The transistor layer 200 includes an amorphous region 204 and crystalline regions 205 disposed on both sides of the amorphous region 204. The transistor layer 200 includes at least one transistor and a passivation layer 260 disposed on the transistor. The transistor is a bottom-gate transistor. Each transistor includes a gate 210, a gate insulating layer 220, an active layer 230, a first electrode 240, and a second electrode 250. The gate 210 is disposed on the substrate 100. The gate insulating layer 220 is disposed on the substrate 100 and the gate 210. The active layer 230 is disposed on the gate insulating layer 220. The active layer 230 is located directly above the gate 210. The active layer 230 includes either a metal oxide active layer or a silicon-based active layer. A first electrode 240 is disposed on one side of the gate insulating layer 220 and the active layer 230. A first induced crystallization portion 202 is disposed on the side of the first electrode 240 away from the substrate 100. The first induced crystallization portion 202 is located in the crystallization region 205. The first induced crystallization portion 202 is used to induce crystallization of the pixel electrode 300 located on the first induced crystallization portion 202. Further, the first induced crystallization portion 202 is a first rough surface. A second electrode 250 is disposed on the other side of the active layer 230. The first electrode 240 and the second electrode 250 are disposed at intervals. The first electrode 240 is either a source or a drain. The second electrode 250 is either a source or a drain. A passivation layer 260 is disposed on the gate insulating layer 220, the active layer 230, the first electrode 240, and the second electrode 250. The passivation layer 260 has a via 261. A via 261 penetrates the passivation layer 260 to expose a first induced crystallization portion 202. The first induced crystallization portion 202 is located only in the region of the first electrode 240 exposed by the via 261. A second induced crystallization portion 203 is disposed on the side of the passivation layer 260 away from the substrate 100. The second induced crystallization portion 203 is disposed around the via 261. The second induced crystallization portion 203 is located in the crystallization region 205. The second induced crystallization portion 203 is used to induce crystallization of the pixel electrode 300 located on the second induced crystallization portion 203. The second induced crystallization portion 203 has a second rough surface.

[0041] In the prior art, the pixel electrode 300 must be subjected to high temperatures to crystallize. However, in this application, a first crystallization-inducing portion 202 is provided on the first electrode 240, and a second crystallization-inducing portion 203 is provided on the passivation layer 260. The first crystallization-inducing portion 202 is a first rough surface. This increases the contact area between the pixel electrode 300 and the first electrode 240 and the passivation layer 260. Simultaneously, the protrusions on the rough surface act as crystal nuclei, which can lower the crystallization temperature of the pixel electrode 300, thus reducing the energy required for crystallization and allowing the pixel electrode 300 to crystallize more efficiently. During the deposition process, crystallization occurs, while the pixel electrode 300 on the amorphous region 204 does not crystallize. This means that when the pixel electrode 300 is etched in the subsequent etching process, the etching rate of the crystallized pixel electrode 300 is lower than that of the amorphous pixel electrode 300. As a result, the amorphous pixel electrode 300 is etched, while the crystallized pixel electrode 300 remains on the first electrode 240 and the passivation layer 260. This eliminates the need for an exposure process to form the pixel electrode 300, saving the number of exposures required for the display panel 10. This simplifies the manufacturing process of the display panel 10 and reduces its manufacturing cost.

[0042] In one embodiment, the passivation layer 260 has a plurality of spaced second induced crystallization portions 203 on the side away from the substrate 100.

[0043] In one embodiment, the roughness of both the first rough surface and the second rough surface is greater than or equal to 10 nanometers. Further, the roughness of both the first rough surface and the second rough surface is between 10 nanometers and 100 nanometers. Specifically, the roughness of both the first rough surface and the second rough surface can be 10 nanometers, 15 nanometers, 20 nanometers, 50 nanometers, 80 nanometers, 90 nanometers, or 100 nanometers, etc.

[0044] In this application, the roughness of both the first rough surface and the second rough surface is set to be greater than or equal to 10 nanometers, which further increases the contact area between the pixel electrode 300 and the first electrode 240 and the passivation layer 260, further reducing the energy required for the pixel electrode 300 to crystallize. This allows the pixel electrode 300 to crystallize during the deposition process, while the pixel electrode 300 on the amorphous region 204 does not crystallize. Consequently, when the pixel electrode 300 is etched using an etching process in the subsequent process, the etching rate of the crystallized pixel electrode 300 is further lower than that of the amorphous pixel electrode 300. This results in the amorphous pixel electrode 300 being etched, while the crystallized pixel electrode 300 remains on the first electrode 240 and the passivation layer 260. As a result, the pixel electrode 300 can be formed without the need for an exposure process, saving the number of exposures required for the display panel 10, thereby simplifying the fabrication process of the display panel 10 and reducing the fabrication cost of the display panel 10.

[0045] In one embodiment, the roughness of the first rough surface is greater than the roughness of the second rough surface. In this application, because the pixel electrode 300 located on the first induced crystallization portion 202 is relatively thick, the roughness of the first rough surface is set to be greater than the roughness of the second rough surface, which further increases the contact area between the pixel electrode 300 and the first induced crystallization portion 202, further reduces the energy required for the pixel electrode 300 to crystallize, thereby improving the crystallization performance of the pixel electrode 300.

[0046] The pixel electrode 300 is disposed on the transistor layer 200 and located on the induced crystallization region 201. Specifically, the pixel electrode 300 is disposed on the passivation layer 260 and extends into the via 261 to contact the first electrode 240. The pixel electrode 300 is located in the crystallization region 205.

[0047] In another embodiment, the transistor may be a top-gate transistor.

[0048] In one embodiment, the induced crystallization portion 201 is an adhesive coating, and the visible light transmittance of the coating is greater than 85%. The visible light transmittance of the coating can be greater than 85%, 90%, 95%, or 98%, etc.

[0049] This application also provides a method for manufacturing a display panel 10, comprising:

[0050] B11, Provide a substrate.

[0051] B12. A transistor layer material is disposed on a substrate, and the transistor layer material is patterned to form a transistor layer. An induced crystallization part is formed on the side of the transistor layer away from the substrate.

[0052] B13. A pixel electrode is formed on the transistor layer, and the pixel electrode is located on the induced crystallization part, and the pixel electrode is a crystallized pixel electrode.

[0053] This application provides a method for fabricating a display panel, comprising: providing a substrate; then, depositing a transistor layer material on the substrate, patterning the transistor layer material to form a transistor layer, and forming an induced crystallization portion on the side of the transistor layer away from the substrate; finally, forming a pixel electrode on the transistor layer, wherein the pixel electrode is a crystalline pixel electrode and is located on the induced crystallization portion. In this application, the induced crystallization portion is located on the side of the transistor layer away from the substrate to induce crystallization of the pixel electrode located on the induced crystallization portion, thereby eliminating the need for an exposure process during the fabrication of the pixel electrode, thus reducing the number of exposure processes in the display panel and simplifying the display panel fabrication process.

[0054] Please see Figures 2-9 This application also provides a method for manufacturing a display panel 10, comprising:

[0055] B11, Provide a substrate.

[0056] B12. A transistor layer material is disposed on a substrate, and the transistor layer material is patterned to form a transistor layer. An induced crystallization part is formed on the side of the transistor layer away from the substrate.

[0057] Please see Figure 3 Specifically, the transistor layer 200 includes an amorphous region 204 and crystalline regions 205 disposed on both sides of the amorphous region 204. A gate 210 material is deposited on the substrate 100, and the gate 210 is formed through processes such as exposure, development, and etching. That is, the gate 210 is formed using a first photomask. Then, a gate insulating layer 220 is formed on the substrate 100 and the gate 210. Next, a semiconductor layer and a conductive layer material are stacked on the gate insulating layer 220, and after processes such as exposure, development, and etching, the semiconductor layer forms an active layer 230, and the conductive layer material forms a conductive layer 397 and a second electrode 250 spaced apart on the active layer 230. That is, the active layer 230, the conductive layer 397, and the second electrode 250 are formed using a single photomask. The active layer 230 is located directly above the gate 210. The active layer 230 includes either a metal oxide active layer 230 or a silicon-based active layer 230. The gate 210, the gate insulating layer 220, the active layer 230, the conductive layer 397, and the second electrode 250 constitute the transistor of the transistor layer 200.

[0058] Please see Figure 4 Then, a passivation layer 260 material is disposed on the gate insulating layer 220, the active layer 230, the first electrode 240 and the second electrode 250.

[0059] Please see Figure 5 Then, a photoresist layer 398 is provided. The photoresist layer 398 is disposed on the passivation layer 260 material. The photoresist layer 398 includes a plurality of spaced photoresist portions. The photoresist portions are located in the amorphous region 204. The photoresist layer is photoresist.

[0060] Please see Figure 6 Then, the passivation layer 260 material undergoes a first patterning process to form a passivation intermediate layer with vias 261, which penetrate the passivation intermediate layer to expose the conductive layer 397. Specifically, the passivation layer 260 material is subjected to exposure, development, and etching processes to form the passivation intermediate layer with vias 261, which penetrate the passivation intermediate layer to expose the conductive layer 397. Then, the photoresist layer 398 undergoes an ashing process to reduce its thickness.

[0061] Then, the passivation intermediate layer undergoes a second patterning process. A first electrode 240 is formed on the conductive layer 397. A first induced crystallization portion 202 is formed on the side of the first electrode 240 away from the substrate 100. A passivation layer 260 is formed on the passivation intermediate layer. A second induced crystallization portion 203 is formed on the side of the passivation layer 260 away from the substrate 100. The second induced crystallization portion 203 is disposed around the via 261. The first induced crystallization portion 202 and the second induced crystallization portion 203 are located in the crystallization region 205. Specifically, the passivation intermediate layer undergoes plasma treatment. The first electrode 240 is formed on the conductive layer 397, and the first induced crystallization portion 202 is formed on the side of the first electrode 240 away from the substrate 100. Simultaneously, a passivation layer 260 is formed on the passivation intermediate layer, and the second induced crystallization portion 203 is formed on the side of the passivation layer 260 away from the substrate 100.

[0062] Please see Figure 7 Remove the photoresist layer 398.

[0063] B13. A pixel electrode is formed on the transistor layer, and the pixel electrode is located on the induced crystallization part, and the pixel electrode is a crystallized pixel electrode.

[0064] Please see Figure 8 and Figure 9 Specifically, pixel electrode material 301 is deposited using physical vapor deposition (PVD). Pixel electrode material 301 located in the first induced crystallization region 202 and the second induced crystallization region 203 crystallizes, while pixel electrode material 301 located in the amorphous region 204 does not crystallize. During etching, the etching rate of pixel electrode material 301 in the crystalline region 205 is much lower than that in the amorphous region 204, causing the pixel electrode material 301 in the amorphous region 204 to be etched, while the pixel electrode material 301 in the crystalline region 205 remains on the first electrode 240 and the passivation layer 260, thereby forming pixel electrode 300. Pixel electrode 300 has multiple spaced pixel electrode 300 portions. Pixel electrode 300 and passivation layer 260 are formed using a single photomask. That is, after depositing pixel electrode material 301 using PVD, it is directly etched to form pixel electrode. In other words, the formation of pixel electrode does not require an exposure process, thereby reducing the manufacturing cost of display panel 10.

[0065] In one embodiment, the etching process is either a wet etching process or a dry etching process. Further, the etching solution for the wet etching process is an oxalic acid etching solution or a nitric acid etching solution.

[0066] In one embodiment, the deposition gas in the physical vapor deposition process includes a mixture of water vapor, hydrogen, and oxygen.

[0067] In one embodiment, the temperature of the device is controlled between 0 and 200 degrees Celsius during the deposition of the pixel electrode material 301. Specifically, the temperature of the device can be 0 degrees Celsius, 50 degrees Celsius, 80 degrees Celsius, 150 degrees Celsius, or 200 degrees Celsius, etc.

[0068] In the prior art, the pixel electrode 300 must be subjected to high temperatures to crystallize. However, in this application, a first induced crystallization portion 202 is provided on the first electrode 240, and a second induced crystallization portion 203 is provided on the passivation layer 260. The first induced crystallization portion 202 is a first rough surface. This increases the contact area between the pixel electrode 300 and the first electrode 240 and the passivation layer 260. Simultaneously, the protrusions on the rough surface act as crystal nuclei, which can lower the crystallization temperature of the pixel electrode 300, thus reducing the energy required for crystallization and allowing the pixel electrode 300 to crystallize more efficiently. During the deposition process, crystallization occurs, while the pixel electrode 300 on the amorphous region 204 does not crystallize. This means that when the pixel electrode 300 is etched in the subsequent etching process, the etching rate of the crystallized pixel electrode 300 is lower than that of the amorphous pixel electrode 300. As a result, the amorphous pixel electrode 300 is etched, while the crystallized pixel electrode 300 remains on the first electrode 240 and the passivation layer 260. This eliminates the need for an exposure process to form the pixel electrode 300, saving the number of exposures required for the display panel 10. This simplifies the manufacturing process of the display panel 10 and reduces its manufacturing cost.

[0069] This application provides a display panel 10 and a method for fabricating the same, comprising: providing a substrate 100; then, depositing a transistor layer 200 material on the substrate 100, patterning the transistor layer 200 material to form the transistor layer 200, and forming an induced crystallization portion 201 on the side of the transistor layer 200 away from the substrate 100; finally, forming a pixel electrode 300 on the transistor layer 200, wherein the pixel electrode 300 is a crystalline pixel electrode 300 and is located on the induced crystallization portion 201. In this application, the induced crystallization portion 201 is disposed on the side of the transistor layer 200 away from the substrate 100 to induce crystallization of the pixel electrode 300 located on the induced crystallization portion 201, thereby eliminating the need for an exposure process during the fabrication of the pixel electrode 300, thus reducing the number of exposure processes in the display panel 10 and simplifying the fabrication process of the display panel 10.

[0070] The above provides a detailed description of a display panel and its preparation method according to the embodiments of this application. Specific examples have been used to illustrate the principles and implementation methods of this application. The description of the above embodiments is only for the purpose of helping to understand the method and core ideas of this application. At the same time, for those skilled in the art, there will be changes in the specific implementation methods and application scope based on the ideas of this application. Therefore, the content of this specification should not be construed as a limitation of this application.

Claims

1. A display panel, characterized by, The application relates to a substrate, a transistor layer provided on the substrate, the transistor layer being provided with an induced crystallization part on the side away from the substrate, and a pixel electrode provided on the transistor layer and located on the induced crystallization part, the pixel electrode being a crystalline pixel electrode. The induced crystallization part comprises a first induced crystallization part and a second induced crystallization part, the transistor layer comprises a transistor and a passivation layer provided on the transistor, the transistor comprises a first electrode, the first electrode is provided with the first induced crystallization part on the side away from the substrate, the passivation layer comprises a through hole penetrating through the passivation layer to expose the first induced crystallization part, the passivation layer is provided with the second induced crystallization part on the side away from the substrate, and the second induced crystallization part is arranged around the through hole. The first induced crystallization part is a first rough surface, and the second induced crystallization part is a second rough surface. The roughness of the first rough surface and the second rough surface is greater than or equal to 10 nanometers. The roughness of the first rough surface is greater than the roughness of the second rough surface. The side of the passivation layer away from the substrate has a plurality of second induced crystallization parts arranged at intervals.

2. The display panel of claim 1, wherein, The application relates to a substrate, a transistor layer provided on the substrate, the transistor layer being provided with an induced crystallization part on the side away from the substrate, and a pixel electrode provided on the transistor layer and located on the induced crystallization part, the pixel electrode being a crystalline pixel electrode.

3. The display panel of claim 2, wherein, The transistor layer comprises a transistor and a passivation layer provided on the transistor, the transistor comprises a first electrode, the substrate is provided with a transistor layer material, the transistor layer material is subjected to a patterning process to form a transistor layer, and the transistor layer is provided with an induced crystallization part on the side away from the substrate.

4. The display panel of claim 2, wherein, The transistor layer comprises a transistor and a passivation layer provided on the transistor, the transistor comprises a first electrode, the substrate is provided with a transistor layer material, the transistor layer material is subjected to a patterning process to form a transistor layer, and the transistor layer is provided with an induced crystallization part on the side away from the substrate.

5. The display panel of claim 1, wherein, The transistor layer comprises a transistor and a passivation layer provided on the transistor, the transistor comprises a first electrode, the substrate is provided with a transistor layer material, the transistor layer material is subjected to a patterning process to form a transistor layer, and the transistor layer is provided with an induced crystallization part on the side away from the substrate.

6. A method for manufacturing a display panel, characterized by, The transistor layer comprises a transistor and a passivation layer provided on the transistor, the transistor comprises a first electrode, the substrate is provided with a transistor layer material, the transistor layer material is subjected to a patterning process to form a transistor layer, and the transistor layer is provided with an induced crystallization part on the side away from the substrate. The transistor layer comprises a transistor and a passivation layer provided on the transistor, the transistor comprises a first electrode, the substrate is provided with a transistor layer material, the transistor layer material is subjected to a patterning process to form a transistor layer, and the transistor layer is provided with an induced crystallization part on the side away from the substrate. The transistor layer comprises a transistor and a passivation layer provided on the transistor, the transistor comprises a first electrode, the substrate is provided with a transistor layer material, the transistor layer material is subjected to a patterning process to form a transistor layer, and the transistor layer is provided with an induced crystallization part on the side away from the substrate. The transistor layer comprises a transistor and a passivation layer provided on the transistor, the transistor comprises a first electrode, the substrate is provided with a transistor layer material, the transistor layer material is subjected to a patterning process to form a transistor layer, and the transistor layer is provided with an induced crystallization part on the side away from the substrate. The transistor layer comprises a transistor and a passivation layer provided on the transistor, the transistor comprises a first electrode, the substrate is provided with a transistor layer material, the transistor layer material is subjected to a patterning process to form a transistor layer, and the transistor layer is provided with an induced crystallization part on the side away from the substrate. ​ ​ ​ ​ 7. The method of manufacturing a display panel according to claim 6, wherein ​ ​ ​ ​ The passivation intermediate layer is subjected to a second patterning process, the conductive layer forms a first electrode, the first electrode forms a first induced crystallization portion away from one side of the substrate, the passivation intermediate layer forms a passivation layer, the passivation layer forms a second induced crystallization portion away from one side of the substrate, the second induced crystallization portion is arranged around the through hole, and the first induced crystallization portion and the second induced crystallization portion are located in the crystallization region. The photoresist layer is removed.

8. The method of manufacturing a display panel according to claim 7, wherein, In the step of arranging a pixel electrode on the passivation layer, the pixel electrode is arranged in the second induced crystallization portion and extends into the through hole to contact the first induced crystallization portion, and the step includes: In the step of arranging a pixel electrode material on the passivation layer, the pixel electrode material is processed by a wet etching method, the pixel electrode material forms a pixel electrode, the pixel electrode is located in the second induced crystallization portion and extends into the through hole to contact the first induced crystallization portion.

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