Semiconductor device

Abstract

The present invention provides a semiconductor device that improves the reliability of a semiconductor device including a thin film transistor using an oxide semiconductor. The semiconductor device has a thin film transistor in each pixel. The thin film transistor has: an oxide semiconductor layer; a gate insulating layer; a gate electrode overlapping the oxide semiconductor layer with the gate insulating layer interposed therebetween; a source electrode in contact with the oxide semiconductor layer; a drain electrode in contact with the oxide semiconductor layer; and a first metal layer that is in contact with the oxide semiconductor layer and is disposed between the source electrode and the drain electrode with a space therebetween, spaced apart from the source electrode and the drain electrode.

Description

Technical Field

[0001] One embodiment of the present invention relates to a semiconductor device including thin film transistors in respective pixels. In particular, the present invention relates to a display device including thin film transistors using an oxide semiconductor. Background Art

[0002] In recent years, an oxide semiconductor has attracted attention as a semiconductor for a channel layer of a thin film transistor used in an organic light emitting diode display device (OLED display device). A thin film transistor using an oxide semiconductor has a low leakage current in an off state and can be driven at a low frequency. Therefore, a thin film transistor using an oxide semiconductor can realize a display device with low power consumption.

[0003] Generally, a thin film transistor has a problem that its electrical characteristics deteriorate due to hot carriers generated near the boundary between a channel region and a drain region. Specifically, a problem that a threshold value of Vg-Id characteristics shifts due to hot carriers is known. This problem is not exceptional in a thin film transistor using an oxide semiconductor, and in order to improve reliability, it is preferable to take countermeasures against hot carriers. For example, in Patent Document 1, as a countermeasure against hot carriers, a technique of disposing a buffer region for alleviating electric field concentration between a channel region and a drain region is disclosed.

[0004] Prior Art Documents

[0005] Patent Documents

[0006] Patent Document 1: Japanese Unexamined Patent Application Publication No. 2012-114426. Summary of the Invention

[0007] Problems to be Solved by the Invention

[0008] In the above prior art, the length (L) of a buffer region is determined by controlling the amount of recession when etching a drain electrode isotropically. Therefore, when forming a plurality of thin film transistors on a substrate, a deviation in the distribution of the etching amount within the substrate surface sometimes occurs. In this case, buffer regions of uniform length cannot be formed for the plurality of thin film transistors, and the reliability of the display device may be reduced.

[0009] One object of the present invention is to improve the reliability of a semiconductor device (particularly a display device) including a thin film transistor using an oxide semiconductor.

[0010] Means for Solving the Problems

[0011] A semiconductor device according to an embodiment of the present invention has thin-film transistors in each pixel. The thin-film transistor has: an oxide semiconductor layer; a gate insulating layer; a gate electrode overlapping the oxide semiconductor layer with the gate insulating layer interposed therebetween; a source electrode in contact with the oxide semiconductor layer; a drain electrode in contact with the oxide semiconductor layer; and a first metal layer, which is in contact with the oxide semiconductor layer and is disposed between the source electrode and the drain electrode with a space therebetween from the source electrode and the drain electrode.

[0012] According to the present invention, it is possible to improve the reliability of a semiconductor device (particularly a display device) including a thin-film transistor using an oxide semiconductor. BRIEF DESCRIPTION OF THE DRAWINGS

[0013] Figure 1 It is a top view showing the structure of a display device according to a first embodiment of the present invention.

[0014] Figure 2 It is a circuit diagram showing the circuit structure of a pixel in a display device according to a first embodiment of the present invention.

[0015] Figure 3 It is a cross-sectional view showing the structure of a display section in a display device according to a first embodiment of the present invention.

[0016] Figure 4A It is a cross-sectional view showing the structure of a thin-film transistor used in a display device according to a first embodiment of the present invention.

[0017] Figure 4B It is a top view showing the structure of a thin-film transistor used in a display device according to a first embodiment of the present invention.

[0018] Figure 5A It is a cross-sectional view showing a manufacturing method of a thin-film transistor used in a display device according to a first embodiment of the present invention.

[0019] Figure 5B It is a top view showing a manufacturing method of a thin-film transistor used in a display device according to a first embodiment of the present invention.

[0020] Figure 6A It is a cross-sectional view showing a manufacturing method of a thin-film transistor used in a display device according to a first embodiment of the present invention.

[0021] Figure 6B It is a top view showing a manufacturing method of a thin-film transistor used in a display device according to a first embodiment of the present invention.

[0022] Figure 7AIt is a cross-sectional view showing a method for manufacturing a thin-film transistor used in the display device according to the first embodiment of the present invention.

[0023] Figure 7B It is a top view showing a method for manufacturing a thin-film transistor used in the display device according to the first embodiment of the present invention.

[0024] Figure 8A It is a cross-sectional view showing a method for manufacturing a thin-film transistor used in the display device according to the first embodiment of the present invention.

[0025] Figure 8B It is a top view showing a method for manufacturing a thin-film transistor used in the display device according to the first embodiment of the present invention.

[0026] Figure 9A It is a cross-sectional view showing a method for manufacturing a thin-film transistor used in the display device according to the first embodiment of the present invention.

[0027] Figure 9B It is a top view showing a method for manufacturing a thin-film transistor used in the display device according to the first embodiment of the present invention.

[0028] Figure 10A It is a cross-sectional view showing the structure of a thin-film transistor used in the display device according to the second embodiment of the present invention.

[0029] Figure 10B It is a top view showing the structure of a thin-film transistor used in the display device according to the second embodiment of the present invention.

[0030] Figure 11A It is a cross-sectional view showing the structure of a thin-film transistor used in the display device according to the third embodiment of the present invention.

[0031] Figure 11B It is a top view showing the structure of a thin-film transistor used in the display device according to the third embodiment of the present invention.

[0032] Figure 12A It is a cross-sectional view showing the structure of a thin-film transistor used in the display device according to the fourth embodiment of the present invention.

[0033] Figure 12B It is a top view showing the structure of a thin-film transistor used in the display device according to the fourth embodiment of the present invention.

[0034] Explanation of reference numerals

[0035] 10, 10a to 10c... thin film transistors, 11... gate electrodes, 12, 13... insulating layers, 14... source electrodes, 15... drain electrodes, 16, 17... metal layers, 18, 19... insulating layers, 20... metal layer, 30... oxide semiconductor layer, 31... source region, 32... drain region, 33 to 36... first low-resistance regions, 37, 38... second low-resistance regions, 39... channel region, 41... first low-resistance region, 42... channel region, 51... base layer, 52... gate insulating layer, 53... gate electrode, 54, 55... insulating layers, 56... source electrode, 57... drain electrode, 58, 59... metal layers, 60... oxide semiconductor layer, 61... source region, 62... drain region, 63 to 66... first low-resistance regions, 67, 68... second low-resistance regions, 71, 72... metal layers, 100... display device, 110... substrate, 120... display unit, 121... insulating layer, 122... anode electrode, 123... partition layer, 124... organic layer, 125... cathode electrode, 126... sealing layer, 126a, 126c... inorganic insulating layers, 126b... organic insulating layer, 127... adhesive layer, 128... protective glass, 130... driving circuit unit, 140... terminal unit, 141... terminal, 150... flexible printed circuit board, 160... driving IC chip, 200... pixel, 200R, 200G, 200B... pixels, 300... pixel circuit, 310... selection transistor, 312... gate line, 314... data line, 320... driving transistor, 322... anode power supply line, 324... cathode power supply line, 330... capacitor, 340... light-emitting element. Detailed Embodiments

[0036] Hereinafter, embodiments of the present invention will be described with reference to the drawings and the like. However, the present invention can be implemented in various ways without departing from its gist. The present invention is not to be construed as limited to the description of the embodiments illustrated below. In the drawings, in order to make the description clearer, the width, thickness, shape, etc. of each part are sometimes schematically shown as compared with the actual form. However, the drawings are merely examples and do not limit the interpretation of the present invention.

[0037] In the description of the embodiments of the present invention, the direction from the substrate toward the light-emitting element is defined as "up", and the opposite direction is defined as "down". However, expressions such as "up" or "down" are merely for explaining the upper-lower relationship of each element. For example, the expression of disposing a light-emitting element on a substrate also includes the case where there are other components between the substrate and the light-emitting element. Furthermore, expressions such as "up" or "down" include not only the case where each element overlaps in a top view but also the case where they do not overlap.

[0038] In the description of the embodiments of the present invention, for elements having the same functions as the elements already described, the description may sometimes be omitted by using the same reference numerals or adding notations such as letters to the same reference numerals.

[0039] In the description of the embodiments of the present invention, multiple elements formed by performing processing such as etching on a certain film may sometimes be described as elements having different functions or actions. These multiple elements are composed of the same layer structure and the same material. Therefore, multiple elements formed by a certain film are sometimes referred to as elements provided on the "same layer".

[0040] In the description of the embodiments of the present invention, expressions such as "α includes A, B, or C", "α includes any one of A, B, and C", and "α includes one selected from the group consisting of A, B, and C" do not exclude the case where α includes multiple combinations of A to C unless otherwise specified. Furthermore, these expressions do not exclude the case where α includes other elements.

[0041] In the description of the embodiments of the present invention, a "display device" refers to a device that displays an image. That is, a "display device" includes not only a display panel or a display component but also a device in which other optical components (for example, a polarization component, a touch panel, etc.) are mounted on the display panel or the display component.

[0042] <First Embodiment>

[0043] [Structure of Display Device 100]

[0044] Figure 1 It is a top view showing the structure of a display device 100 according to the first embodiment of the present invention. The display device 100 includes a display unit 120, a driving circuit unit 130, and a terminal unit 140. The display unit 120, the driving circuit unit 130, and the terminal unit 140 are provided on a substrate 110.

[0045] The display unit 120 includes a plurality of pixels 200R, 200G, and 200B. The pixel 200R corresponds to a pixel that emits red light. The pixel 200G corresponds to a pixel that emits green light. The pixel 200B corresponds to a pixel that emits blue light. The display unit 120 displays an image by controlling the light emission and non-light emission of the plurality of pixels 200R, 200G, and 200B. In the present embodiment, when it is not necessary to particularly distinguish each color of RGB, it may sometimes be described only as a pixel 200. The structure of each pixel 200 will be described later.

[0046] The driving circuit unit 130 controls each pixel 200 of the display unit 120. The driving circuit unit 130 includes, for example, a gate line driving circuit, etc. Although in Figure 1The illustration is omitted, but the driving circuit section 130 may also include a data line driving circuit.

[0047] The terminal section 140 functions as a terminal for receiving signals supplied to the display section 120 and the driving circuit section 130 from the outside. The terminal section 140 includes a plurality of terminals 141. The terminal section 140 is connected to the flexible printed circuit board 150, and the plurality of terminals 141 are respectively connected to the corresponding terminals on the flexible printed circuit board 150 side. In the present embodiment, a driving IC chip 160 is provided on the flexible printed circuit board 150. However, this is not limited to this example, and the driving IC chip 160 may be omitted.

[0048] In Figure 1 it is shown in a planar manner the overall structure of the display device 100, but the substrate 110 may be bent between the display section 120 and the terminal section 140. In this case, as the substrate 110, a flexible substrate such as a resin substrate may be used. In the case of adopting such a structure, the terminal section 140 and the flexible printed circuit board 150 can be folded to the back side of the display device 100, and the display device 100 can be miniaturized.

[0049] [Structure of pixel circuit 300]

[0050] Figure 2 is a circuit diagram showing the circuit structure of the pixel 200 in the display device 100 according to the first embodiment of the present invention. The pixel circuit 300 includes a selection transistor 310, a driving transistor 320, a capacitor 330, and a light-emitting element 340.

[0051] The selection transistor 310 is connected to the gate line 312 and the data line 314. Specifically, the gate line 312 is connected to the gate of the selection transistor 310. The data line 314 is connected to the source of the selection transistor 310. The selection transistor 310 functions as a switch for selecting whether to input a data signal (video signal Vs) to the pixel circuit 300. The drain of the selection transistor 310 is connected to the gate of the driving transistor 320 and the capacitor 330.

[0052] The driving transistor 320 is connected to the anode power supply line 322, the light-emitting element 340, and the capacitor 330. Specifically, the anode power supply line 322 is connected to the drain of the driving transistor 320. The light-emitting element 340 is connected to the source of the driving transistor 320. The capacitor 330 is connected between the gate and the source of the driving transistor 320. The driving transistor 320 functions as a valve for controlling the amount of current flowing through the light-emitting element 340. A high-potential power supply voltage (PVDD) is applied to the anode power supply line 322.

[0053] The capacitor 330 functions to hold the data signal input via the selection transistor 310. The voltage corresponding to the data signal held in the capacitor 330 is applied to the gate of the driving transistor 320. Thereby, the amount of current flowing through the driving transistor 320 is controlled according to the data signal.

[0054] The light-emitting element 340 is connected between the driving transistor 320 and the cathode power line 324. Specifically, the anode of the light-emitting element 340 is connected to the source of the driving transistor 320. That is, the anode of the light-emitting element 340 is connected to the anode power line 322 via the driving transistor 320. The cathode of the light-emitting element 340 is connected to the cathode power line 324. A power supply voltage (PVSS) of a low potential is applied to the cathode power line 324.

[0055] In the pixel circuit 300, when the selection transistor 310 becomes conductive, a data signal is input from the data line 314. The voltage corresponding to the input data signal is held by the capacitor 330. Thereafter, during the light-emitting period, the gate of the driving transistor 320 is controlled by the voltage held in the capacitor 330, and a current corresponding to the data signal flows through the driving transistor 320. When current flows through the light-emitting element 340, the light-emitting element 340 emits light with a brightness corresponding to the amount of current.

[0056] [Structure of Pixel 200]

[0057] Figure 3 It is a cross-sectional view showing the structure of the display unit 120 in the display device 100 according to the first embodiment of the present invention. Specifically, Figure 3 The shown cross-sectional structure corresponds to the cross-sectional view of the display unit 120 cut along the single-dot chain line A-A. Figure 1 Since the basic structures of the respective pixels 200R, 200G, and 200B are the same, the pixel 200G that emits green light is described in Figure 3 .

[0058] As shown in Figure 3 , the driving transistor 320 is provided on the substrate 110. Although not shown in Figure 3 , each element constituting the pixel circuit 300 such as the selection transistor 310 and the capacitor 330 is also provided on the substrate 110.

[0059] The driving transistor 320 is covered with an insulating layer 121 including a resin layer. The resin layer included in the insulating layer 121 functions to flatten the unevenness caused by the driving transistor 320 and the like. The insulating layer 121 may have a laminated structure of an inorganic insulating layer and a resin layer. As the material of the inorganic insulating layer, for example, silicon-based inorganic materials such as silicon oxide and silicon nitride can be used. As the material of the resin layer, for example, photosensitive organic materials such as acrylic acid or polyimide can be used.

[0060] An anode electrode 122 is provided on the insulating layer 121. The anode electrode 122 is the anode of the light-emitting element 340 and also functions as the pixel electrode of the pixel 200. The anode electrode 122 is electrically connected to the source electrode of the driving transistor 320 via a contact hole provided in the insulating layer 121. In the present embodiment, the anode electrode 122 is composed of a transparent conductive layer. However, it is not limited to this example, and the anode electrode 122 may be composed of a metal layer or may have a laminated structure of a transparent conductive layer and a metal layer. For example, as the anode electrode 122, a transparent conductive layer containing a metal oxide can be used. In the present embodiment, as the anode electrode 122, a conductive layer formed by laminating a metal layer containing silver and a transparent conductive layer made of ITO (Indium Tin Oxide) is used. In this case, the conductive layer on the side in contact with the organic layer 124 described later is used as the transparent conductive layer.

[0061] A partition layer 123 is provided above the anode electrode 122. The partition layer 123 has an opening to expose a part of the surface of the anode electrode 122. That is, the partition layer 123 is provided so as to cover the end portion of the anode electrode 122. The inner wall of the opening of the partition layer 123 is preferably a gentle conical shape. By forming the inner wall of the opening of the partition layer 123 into a conical shape, it is possible to reduce the coverage failure of the organic layer 124 or the cathode electrode 125 formed on the anode electrode 122. The partition layer 123 is sometimes also referred to as a dam or a rib.

[0062] An organic layer 124 including at least a hole transport layer, a light-emitting layer, and an electron transport layer is provided on the anode electrode 122. In the case of the pixel 200G, the light-emitting layer of the organic layer 124 is composed of an organic material that emits green light. Similarly, in the case of the pixel 200R and the pixel 200B, the light-emitting layers of the organic layer 124 are composed of an organic material that emits red light and an organic material that emits blue light, respectively. The hole transport layer and the electron transport layer included in the organic layer 124 may also be provided in a manner that spans each pixel 200. The organic layer 124 may further include functional layers, such as an electron injection layer, an electron blocking layer, a hole injection layer, or a hole blocking layer.

[0063] A cathode electrode 125 is provided on the organic layer 124. The cathode electrode 125 can also be provided in a manner spanning across each pixel 200. In the present embodiment, the cathode electrode 125 is composed of a metal layer. However, not limited to this example, the cathode electrode 125 can be composed of a transparent conductive layer or can have a laminated structure of a transparent conductive layer and a metal layer. For example, as the cathode electrode 125, a metal layer containing an alkali metal or an alkaline earth metal can be used. In the present embodiment, as the cathode electrode 125, a metal layer composed of a MgAg alloy (an alloy containing magnesium and silver) is used. In this case, the film thickness of the cathode electrode 125 is a thickness that can transmit visible light.

[0064] A sealing layer 126 is provided on the cathode electrode 125. The sealing layer 126 has a structure in which an inorganic insulating layer 126a, an organic insulating layer 126b, and an inorganic insulating layer 126c are laminated, for example. As the materials of the inorganic insulating layer 126a and the inorganic insulating layer 126c, for example, silicon-based inorganic materials such as silicon oxide and silicon nitride can be used. The inorganic insulating layer 126a and the inorganic insulating layer 126c have the function of preventing moisture from invading from the outside. Therefore, as the inorganic insulating layer 126a and the inorganic insulating layer 126c, an insulating layer with a dense film quality is preferably used. As the material of the organic insulating layer 126b, for example, resin materials such as acrylic resin, epoxy resin, polyimide resin, silicone resin, fluororesin, or siloxane resin can be used.

[0065] In the present embodiment, a protective glass 128 is provided on the sealing layer 126 via an adhesive layer 127. Although the illustration is omitted in Figure 3 , optical components such as a polarizing plate or a touch sensor can also be further provided above or below the protective glass 128. The adhesive layer 127 and the protective glass 128 can also be omitted.

[0066] [Structure of thin film transistor 10]

[0067] Figure 4A is a cross-sectional view showing the structure of the thin film transistor 10 used in the display device 100 according to the first embodiment of the present invention. Figure 4B is a top view showing the structure of the thin film transistor 10 used in the display device 100 according to the first embodiment of the present invention. In Figure 4B , for ease of explanation, the illustrations of the insulating layers 18 and 19 shown in Figure 4A are omitted. The thin film transistor 10 can be used for at least one of the selection transistor 310 and the driving transistor 320 shown in Figure 2 . Figure 4A and Figure 4B The thin film transistor 10 shown is an example of a bottom-gate transistor.

[0068] On a substrate 110 having an insulating surface, a gate electrode 11 is provided. As the substrate 110, for example, a light-transmissive substrate made of glass, quartz, sapphire, or the like can be used. However, as the substrate 110, a non-light-transmissive substrate made of silicon, ceramics, or the like can also be used. Further, as the substrate 110, a flexible substrate made of a resin material such as polyimide resin, acrylic resin, silicone resin, or fluororesin can also be used.

[0069] The gate electrode 11 is made of, for example, a metal material such as titanium, tantalum, tungsten, molybdenum, vanadium, aluminum, copper, or niobium, or an alloy material containing these metals. The gate electrode 11 can be a single-layer structure or a stacked structure.

[0070] The gate electrode 11 is covered with insulating layers 12 and 13. In the present embodiment, the insulating layer 12 is a silicon nitride layer. The insulating layer 13 is a silicon oxide layer. In the present embodiment, the insulating layers 12 and 13 are stacked to function as a gate insulating layer. However, not limited to this example, as the gate insulating layer, the insulating layer 13 can also be used alone as a single layer.

[0071] An oxide semiconductor layer 30 is provided on the insulating layer 13. As the material of the oxide semiconductor layer 30, for example, indium gallium zinc oxide (IGZO), indium tin zinc oxide (ITZO), indium aluminum zinc oxide (IAZO), zinc oxide (ZnO), or the like can be used. In addition, the oxide semiconductor layer 30 can be a single layer or a stacked layer. In the present embodiment, indium gallium zinc oxide (IGZO) is used as the oxide semiconductor layer 30. Therefore, the thin-film transistor 10 of the present embodiment operates as an N-channel transistor in which the majority carriers are electrons. Details of the structure of the oxide semiconductor layer 30 will be described later.

[0072] On the oxide semiconductor layer 30, a source electrode 14 and a drain electrode 15 are provided so as to be in contact with the ends of the oxide semiconductor layer 30. Specifically, in a cross-sectional view, the source electrode 14 is provided so as to be in contact with the first end of the oxide semiconductor layer 30, and the drain electrode 15 is provided so as to be in contact with the second end on the opposite side of the first end. In the present embodiment, at the ends of the oxide semiconductor layer 30, the source electrode 14 and the drain electrode 15 are provided so as to cover three sides, but not limited to this example. For example, the source electrode 14 and the drain electrode 15 can also be provided so as to cross the oxide semiconductor layer 30 (that is, so as to cover two sides).

[0073] As materials for the source electrode 14 and the drain electrode 15, they are made of metal materials such as titanium, aluminum, tantalum, tungsten, molybdenum, vanadium, aluminum, copper, or niobium, or alloy materials containing these metals. The source electrode 14 and the drain electrode 15 can be a single-layer structure or a stacked structure. In the present embodiment, as the source electrode 14 and the drain electrode 15, a metal layer having a three-layer structure of titanium / aluminum / titanium is used.

[0074] In the present embodiment, the metal layers 16 and 17 are formed simultaneously with the source electrode 14 and the drain electrode 15. That is, both the metal layers 16 and 17 are provided in the same layer as the source electrode 14 and the drain electrode 15. Therefore, the metal layers 16 and 17 have the same three-layer structure of titanium / aluminum / titanium as the source electrode 14 and the drain electrode 15. However, not limited to this example, the metal layers 16 and 17 can also be formed of metal materials different from those of the source electrode 14 and the drain electrode 15.

[0075] Both the metal layers 16 and 17 are provided in a manner that they are in contact with the oxide semiconductor layer 30. At this time, the metal layers 16 and 17 are arranged at intervals from the source electrode 14 and the drain electrode 15, respectively. Specifically, in the present embodiment, the distance between the source electrode 14 and the metal layer 16 is 1.0 μm or more and 3.0 μm or less (preferably 1.5 μm or more and 2.0 μm or less). The distance between the drain electrode 15 and the metal layer 17 is also 1.0 μm or more and 3.0 μm or less (preferably 1.5 μm or more and 2.0 μm or less).

[0076] In the present embodiment, the metal layers 16 and 17 are electrically floating. That is, the potentials of the metal layers 16 and 17 are not determined. However, not limited to this example, the metal layers 16 and 17 can also be fixed to a fixed potential. The widths of the metal layers 16 and 17 are not particularly limited. In the present embodiment, the widths of the metal layers 16 and 17 are 1.0 μm or more and 3.0 μm or less. However, the lower limit of the widths of the metal layers 16 and 17 can also be the minimum width that can be exposed.

[0077] As Figure 4A shown, an insulating layer 18 and an insulating layer 19 are provided on the source electrode 14, the drain electrode 15, the metal layer 16, and the metal layer 17. The insulating layers 18 and 19 function as passivation layers, respectively. In the present embodiment, a silicon oxide layer is used as the insulating layer 18. In addition, a silicon nitride layer is used as the insulating layer 19. In addition to the function as a passivation layer, the insulating layer 18 also has the function of supplying oxygen to the oxide semiconductor layer 30. Therefore, as the material of the insulating layer 18, materials with a relatively high oxygen content such as silicon oxide and silicon oxynitride are preferably used. In contrast, the insulating layer 19 mainly functions as a passivation layer. Therefore, the insulating layer 19 preferably uses a silicon nitride layer with a dense film quality.

[0078] [Structure of Oxide Semiconductor Layer 30]

[0079] In the thin-film transistor 10 of the present embodiment, the oxide semiconductor layer 30 has a plurality of regions with different resistances (in other words, a plurality of regions with different conductivities). Specifically, the oxide semiconductor layer 30 includes a source region 31, a drain region 32, first low-resistance regions 33 to 36, second low-resistance regions 37 and 38, and a channel region 39.

[0080] The first low-resistance regions 33 to 36 and the second low-resistance regions 37 and 38 both have a lower resistance than the channel region 39. The second low-resistance regions 37 and 38 have a lower resistance than the first low-resistance regions 33 to 36. In addition, the resistances of the second low-resistance regions 37 and 38 are substantially equal to the resistances of the source region 31 and the drain region 32. In the present embodiment, the first low-resistance regions 33 to 36 function as buffer regions for alleviating the electric field concentration near the source region 31 or the drain region 32. Such buffer regions are effective as a countermeasure against hot carriers.

[0081] Since the oxide semiconductor layer 30 of the present embodiment is indium gallium zinc oxide (IGZO), it has the following physical property: when oxygen escapes from the inside of the layer to the outside, the resistance of the part where oxygen escapes decreases. Therefore, when another metal layer comes into contact with the oxide semiconductor layer 30, an oxygen escape phenomenon from the inside of the oxide semiconductor layer 30 is caused along with the oxidation of the other metal layer. That is, the oxide semiconductor layer 30 of the present embodiment has the physical property that the resistance of the part in contact with the other metal layer and its vicinity decreases. Therefore, in the oxide semiconductor layer 30 of the present embodiment, due to the influence of the source electrode 14, the drain electrode 15, the metal layer 16, the metal layer 17, etc., regions with a lower resistance than the channel region 39 are formed.

[0082] Specifically, as Figure 4A shown, the source region 31 and the drain region 32 are respectively formed in the regions of the oxide semiconductor layer 30 that are in contact with the source electrode 14 and the drain electrode 15. The second low-resistance regions 37 and 38 are formed in the regions of the oxide semiconductor layer 30 that are in contact with the metal layers 16 and 17.

[0083] The first low-resistance region 33 is formed between the source region 31 and the second low-resistance region 37. At this time, the region between the source region 31 and the second low-resistance region 37 becomes the first low-resistance region 33 over the entire region. Similarly, the first low-resistance region 34 is formed between the drain region 32 and the second low-resistance region 38. In this case, the region between the drain region 32 and the second low-resistance region 38 also becomes the first low-resistance region 34 over the entire region. The first low-resistance region 35 is formed between the second low-resistance region 37 and the channel region 39. Similarly, the first low-resistance region 36 is formed between the second low-resistance region 38 and the channel region 39.

[0084] As described above, the source region 31, the drain region 32, the first low-resistance regions 33 to 36, and the second low-resistance regions 37 and 38 are formed by oxygen detaching from the inside of the oxide semiconductor layer 30. Therefore, the oxygen concentration in these regions is lower than that in the channel region 39. In addition, the first low-resistance regions 33 to 36 do not directly contact the source electrode 14, the drain electrode 15, the metal layer 16, and the metal layer 17. Therefore, the oxygen concentration in the first low-resistance regions 33 to 36 is higher than that in the source region 31, the drain region 32, and the second low-resistance regions 37 and 38, and lower than that in the channel region 39.

[0085] In addition, the lengths (the lengths along the direction of carrier movement) of the first low-resistance regions 33 to 36 vary according to the conditions of the manufacturing process after the source electrode 14, the drain electrode 15, the metal layer 16, and the metal layer 17 are formed. For example, the lengths of the first low-resistance regions 33 to 36 can be controlled by the process temperature when the insulating layer 18 is formed, or the baking temperature after the insulating layer 18 is formed, etc. In the present embodiment, the process temperature when the insulating layer 18 is formed is controlled so that, for example, the first low-resistance regions 35 and 36 are each 0.5 μm or more and 1.5 μm or less. However, it is not limited to this example, and as long as the lengths of the first low-resistance regions 35 and 36 can be finally made into desired lengths, the control method is not limited.

[0086] In the first low-resistance region 34, oxygen is separated due to the influence of both the drain electrode 15 and the metal layer 17. Therefore, the formation of the first low-resistance region 34 starts from both the region near the drain electrode 15 and the region near the metal layer 17. Thus, for example, when the above process temperature is passed, the length of the first low-resistance region 34 becomes approximately twice the length of the first low-resistance region 36. That is, the length of the first low-resistance region 34 is 1.0 μm or more and 3.0 μm or less. As a result, the length of the buffer region near the drain region 32 substantially becomes the sum of the lengths of the first low-resistance regions 34 and 36. That is, according to the present embodiment, as the buffer region near the drain region 32, a low-resistance region having a length of 1.5 μm or more and 4.5 μm or less (preferably 2.0 μm or more and 3.0 μm or less) can be formed. Here, the vicinity of the drain region 32 has been described, but the vicinity of the source region 31 is the same.

[0087] According to the applicant's understanding, in a thin-film transistor using an oxide semiconductor, the longer the length of the low-resistance region disposed near the drain region, the higher the hot-carrier tolerance. Specifically, the applicant has obtained the following understanding: If the length of the low-resistance region is at least 1.5 μm or more (preferably 2.0 μm or more), the characteristic degradation caused by hot carriers can be effectively suppressed. However, when oxygen is separated from the oxide semiconductor layer 30 only by using the source electrode 14 and the drain electrode 15, it is difficult to form a low-resistance region having a sufficient length.

[0088] In contrast, in the present embodiment, by forming the metal layers 16 and 17 simultaneously with the formation of the source electrode 14 and the drain electrode 15, the total length of the low-resistance region formed can be increased. As described above, according to the present embodiment, the first low-resistance regions 33 to 36 having a sufficient length can be formed without increasing the manufacturing process.

[0089] In addition, since the lengths of the first low-resistance regions 33 to 36 are determined by the heat history after the formation of the source electrode 14, the drain electrode 15, the metal layer 16, and the metal layer 17, etc., the length deviation of the first low-resistance regions 33 to 36 in the plane of the substrate 110 is small. Therefore, buffer regions having a uniform length can be formed for a plurality of thin-film transistors 10.

[0090] Furthermore, according to the present embodiment, buffer regions having a sufficient length can be formed near both the source region 31 and the drain region 32. Therefore, for example, as Figure 2As in the case of the selection transistor 310 shown, in a thin film transistor in which the source and drain are swapped according to the magnitude relationship of the voltages applied to the source region and the drain region, deterioration of characteristics caused by hot carriers can be suppressed regardless of the direction of carrier movement. Even when the source and drain are swapped by AC driving or the like, deterioration of characteristics can be suppressed regardless of the direction of carrier movement.

[0091] As described above, according to the present embodiment, the reliability of the display device 100 including the thin film transistor 10 using the oxide semiconductor can be improved.

[0092] [Manufacturing method of thin film transistor 10]

[0093] Figure 5A 、 Figure 6A 、 Figure 7A 、 Figure 8A and Figure 9A are cross-sectional views showing a manufacturing method of the thin film transistor 10 used in the display device 100 according to the first embodiment of the present invention. Figure 5B 、 Figure 6B 、 Figure 7B 、 Figure 8B and Figure 9B are top views showing a manufacturing method of the thin film transistor 10 used in the display device 100 according to the first embodiment of the present invention.

[0094] First, as shown in Figure 5A and Figure 5B , a gate electrode 11 is formed on the substrate 110. Specifically, a metal layer containing a metal material (in the present embodiment, the metal materials are aluminum and titanium) constituting the gate electrode 11 is formed. Then, the metal layer laminated with aluminum and titanium is etched to form the gate electrode 11.

[0095] Next, as shown in Figure 6A and Figure 6B , insulating layers 12 and 13 are formed so as to cover the gate electrode 11. In the present embodiment, first, a silicon nitride layer is formed as the insulating layer 12. Then, a silicon oxide layer is formed as the insulating layer 13 on the insulating layer 12. After forming the insulating layer 13, an oxide semiconductor layer 30 is formed on the insulating layer 13. In the present embodiment, first, an oxide semiconductor layer made of indium gallium zinc oxide (IGZO) is formed with a thickness of 40 nm or more and 100 nm or less. Then, the oxide semiconductor layer is etched to form the oxide semiconductor layer 30.

[0096] Next, as shown in Figure 7A and Figure 7BAs shown, a metal layer 20 is formed to cover the oxide semiconductor layer 30. The metal layer 20 is formed by laminating a titanium layer, an aluminum layer, and a titanium layer in this order from the lower layer. In the present embodiment, by providing the titanium layer at the lowermost layer, the oxide semiconductor layer 30 and the aluminum layer do not directly contact each other. Thereby, it is possible to prevent excessive oxygen accompanying the oxidation of the aluminum layer from being released from the oxide semiconductor layer 30.

[0097] Next, as Figure 8A and Figure 8B shown, the metal layer 20 is etched to form a source electrode 14, a drain electrode 15, a metal layer 16, and a metal layer 17. At this time, as Figure 8B shown, the metal layers 16 and 17 are formed so as to cross the oxide semiconductor layer 30. In the present embodiment, a distance of 1.0 μm or more and 3.0 μm or less (preferably 1.5 μm or more and 2.0 μm or less) is provided between the source electrode 14 and the metal layer 16, or between the drain electrode 15 and the metal layer 17.

[0098] Next, as Figure 9A and Figure 9B shown, an insulating layer 18 is formed so as to cover the source electrode 14, the drain electrode 15, the metal layer 16, the metal layer 17, and the oxide semiconductor layer 30. In the present embodiment, as the insulating layer 18, a silicon oxide layer is formed with a thickness of 100 nm or more and 300 nm or less. In the present embodiment, during the formation process of the insulating layer 18, a source region 31, a drain region 32, first low-resistance regions 33 to 36, second low-resistance regions 37 and 38, and a channel region 39 are formed in the oxide semiconductor layer 30. It is also possible to perform a baking process on the insulating layer 18 after the insulating layer 18 is formed. The length of the first low-resistance regions 33 to 36 can also be adjusted by the temperature of the baking process of the insulating layer 18.

[0099] In the above-described formation process of the insulating layer 18 and the baking process for the insulating layer 18, oxygen is supplied from the silicon oxide layer as the insulating layer 18 to the channel region 39. Thereby, it is possible to adjust the resistance of the channel region 39 so that the channel region 39 functions properly as a channel. The oxygen released from the insulating layer 18 is also supplied to the first low-resistance regions 33 to 36. However, the oxygen is released from the first low-resistance regions 33 to 36 due to the influence of the metal layers 16 and 17. Therefore, the resistance of the first low-resistance regions 33 to 36 is lower than the resistance of the channel region 39.

[0100] After completing Figure 9A and Figure 9B the processing, an insulating layer 19 is formed on the insulating layer 18. In the present embodiment, as the insulating layer 19, a silicon nitride layer is formed with a thickness of 100 nm or more and 200 nm or less. Thereby, the use of Figure 4A andFigure 4B Thin film transistor 10 with the described structure.

[0101] <Second Embodiment>

[0102] In this embodiment, a display device with a thin film transistor 10a having a structure different from that of the first embodiment will be described. In this embodiment, mainly the parts different from the first embodiment will be described. In the drawings used in the description of this embodiment, the same reference numerals are given to the same structures as those in the first embodiment, and detailed descriptions thereof are omitted.

[0103] Figure 10A It is a cross-sectional view showing the structure of the thin film transistor 10a used in the display device of the second embodiment of the present invention. Figure 10B It is a top view showing the structure of the thin film transistor 10a used in the display device of the second embodiment of the present invention. As Figure 10A and Figure 10B shown, in this embodiment, a structure is adopted in which a metal layer ( Figure 4A and Figure 4B the metal layer 16 shown) is not provided near the source electrode 14.

[0104] In the case of a thin film transistor in which the positional relationship between the source and the drain does not change and carriers always move in a certain direction, it is sufficient to provide a buffer region with a sufficient length only near the drain region. Correspondingly, in this embodiment, only the first low-resistance regions 34 and 36 are provided near the drain region 32. In this case, near the source region 31, only the first low-resistance region 41 formed by the oxidation of the source electrode 14 is formed. Therefore, in this embodiment, the region between the first low-resistance region 41 and the first low-resistance region 36 functions as the channel region 42.

[0105] In this embodiment, it is also possible to form the first low-resistance regions 34 and 36 with a sufficient length near the drain region 32 without increasing the manufacturing process. In addition, as in the first embodiment, the lengths of the first low-resistance regions 34 and 36 can be made uniform among the plurality of thin film transistors 10a. Thus, according to this embodiment, the reliability of the display device including the thin film transistor 10a using an oxide semiconductor can be improved.

[0106] <Third Embodiment>

[0107] In this embodiment, a display device with a thin film transistor 10b having a structure different from that of the first embodiment will be described. In addition, the thin film transistor 10b in this embodiment corresponds to changing the structure of the bottom-gate type thin film transistor 10 described in the first embodiment to a top-gate type thin film transistor.

[0108] Figure 11A FIG. 2 is a cross-sectional view showing the structure of the thin film transistor 10b used in the display device according to the third embodiment of the present invention. Figure 11B FIG. 3 is a top view showing the structure of the thin film transistor 10b used in the display device according to the third embodiment of the present invention. In Figure 11B , for ease of explanation, the illustrations of the gate insulating layer 52, the insulating layer 54, and the insulating layer 55 shown in Figure 11A are omitted. The thin film transistor 10b can be used for at least one of the selection transistor 310 and the driving transistor 320 shown in Figure 2 . Figure 11A and Figure 11B The thin film transistor 10b shown in FIG. 4 is an example of a top gate type transistor.

[0109] An oxide semiconductor layer 60 is provided on the substrate 110 with an underlying layer 51 interposed therebetween. As the underlying layer 51, a silicon oxide layer or an insulating layer having a double layer structure of a silicon nitride layer and a silicon oxide layer can be used. In the case where the underlying layer 51 has a double layer structure, the insulating layer in contact with the oxide semiconductor layer 60 is preferably a silicon oxide layer. Since the material of the substrate 110 is the same as that in the first embodiment, the description thereof is omitted here.

[0110] As the material of the oxide semiconductor layer 60, for example, indium gallium zinc oxide (IGZO), indium tin zinc oxide (ITZO), indium aluminum zinc oxide (IAZO), zinc oxide (ZnO), or the like can be used. In addition, the oxide semiconductor layer 60 can be a single layer or a stacked layer. In the present embodiment, indium gallium zinc oxide (IGZO) is used as the oxide semiconductor layer 60. Therefore, the thin film transistor 10b of the present embodiment operates as an N-channel type transistor in which the majority carriers are electrons.

[0111] The oxide semiconductor layer 60 is covered with a gate insulating layer 52. In the present embodiment, a silicon oxide layer is used as the gate insulating layer 52. However, it is not limited to this example, and as the gate insulating layer 52, an insulating layer having a double layer structure of a silicon nitride layer and a silicon oxide layer can also be used. However, in this case, the insulating layer in contact with the oxide semiconductor layer 60 is preferably a silicon oxide layer.

[0112] A gate electrode 53 is provided on the gate insulating layer 52. Since the material of the gate electrode 53 is the same as that in the first embodiment, the description thereof is omitted here. The gate electrode 53 is covered with insulating layers 54 and 55. In the present embodiment, the insulating layer 54 is a silicon oxide layer. The insulating layer 54 is mainly provided to insulate and separate the gate electrode 53 from the source electrode 56, the drain electrode 57, the metal layer 58, and the metal layer 59. The insulating layer 55 is a silicon nitride layer. The insulating layer 55 functions as a passivation film. However, it is not limited to this example, and the insulating layer 55 can also be omitted.

[0113] An anode electrode 56, a drain electrode 57, a metal layer 58, and a metal layer 59 are provided on the insulating layer 55. In the present embodiment, as the anode electrode 56, the drain electrode 57, the metal layer 58, and the metal layer 59, a metal layer having a three-layer structure of titanium / aluminum / titanium is used in the same manner as in the first embodiment. In the present embodiment, the metal layers 58 and 59 may be electrically floating or fixed to a certain potential. In the present embodiment, the anode electrode 56, the drain electrode 57, the metal layer 58, and the metal layer 59 are formed simultaneously by the same process. That is, the anode electrode 56 and the drain electrode 57 and the metal layers 58 and 59 are elements provided on the same layer. However, the present invention is not limited to this example, and the metal layers 58 and 59 may be formed of a metal material different from that of the anode electrode 56 and the drain electrode 57.

[0114] The anode electrode 56, the drain electrode 57, the metal layer 58, and the metal layer 59 are all connected to the oxide semiconductor layer 60 via contact holes provided in the gate insulating layer 52, the insulating layers 54 and 55. Therefore, as in the first embodiment, as the anode electrode 56, the drain electrode 57, the metal layer 58, and the metal layer 59 are oxidized, oxygen is released from the oxide semiconductor layer 60. As a result, a source region 61, a drain region 62, first low-resistance regions 63 to 66, second low-resistance regions 67 and 68, and a channel region 69 are formed in the oxide semiconductor layer 60. The details of the source region 61, the drain region 62, the first low-resistance regions 63 to 66, and the second low-resistance regions 67 and 68 are the same as those of the source region 31, the drain region 32, the first low-resistance regions 33 to 36, and the second low-resistance regions 37 and 38 described in the first embodiment, respectively, so the description thereof is omitted here.

[0115] The metal layers 58 and 59 are arranged at intervals from the anode electrode 56 and the drain electrode 57, respectively. Specifically, in the present embodiment, the length of the first low-resistance region 63 or the length of the first low-resistance region 64 is designed to be 1.0 μm or more and 3.0 μm or less (preferably 1.5 μm or more and 2.0 μm or less). Therefore, the length of the buffer region near the source region 61 or the drain region 62 (the sum of the lengths of the first low-resistance regions 63 and 65 or the sum of the lengths of the first low-resistance regions 64 and 66) is 1.5 μm or more and 4.5 μm or less (preferably 2.0 μm or more and 3.0 μm or less).

[0116] As described above, according to the present embodiment, it is possible to form the first low-resistance regions 63 to 66 having a sufficient length without adding a manufacturing process. In addition, the lengths of the first low-resistance regions 63 to 66 are determined by the thermal history after forming the source electrode 56, the drain electrode 57, the metal layer 58, and the metal layer 59, etc., so the deviation in the length in the plane of the substrate 110 is small, and it is possible to form buffer regions having a uniform length for a plurality of thin film transistors 10b. Thus, according to the present embodiment, the reliability of a display device including the thin film transistor 10b using an oxide semiconductor can be improved.

[0117] <Fourth Embodiment>

[0118] In the present embodiment, a display device including a thin film transistor 10c having a structure different from that of the third embodiment will be described. In the present embodiment, mainly the parts different from the first embodiment will be described. In the drawings used for the description of the present embodiment, the same reference numerals are given to the same structures as those in the first embodiment, and the detailed description thereof is omitted.

[0119] Figure 12A FIG. is a cross-sectional view showing the structure of the thin film transistor 10c used in the display device according to the fourth embodiment of the present invention. Figure 12B FIG. is a plan view showing the structure of the thin film transistor 10c used in the display device according to the second embodiment of the present invention. As Figure 12A and Figure 12B shown, in the present embodiment, as the metal layers 71 and 72, a metal layer of the same layer as the gate electrode 53 is used.

[0120] In the present embodiment, after forming the gate insulating layer 52, contact holes are formed in the gate insulating layer 52 to expose the regions that will become the second low-resistance regions 67 and 68 later. Thereafter, a metal layer formed by laminating aluminum and titanium is formed, and etching is performed to form the gate electrode 53, the metal layer 71, and the metal layer 72. That is, in the present embodiment, the gate electrode 53, the metal layer 71, and the metal layer 72 are formed simultaneously by the same process. That is, the gate electrode 53 and the metal layers 71 and 72 are elements provided in the same layer. However, this is not limited to this example, and the metal layers 71 and 72 may also be formed of a metal material different from that of the gate electrode 53.

[0121] Both the metal layer 71 and the metal layer 72 are in contact with the oxide semiconductor layer 60 via contact holes provided in the gate insulating layer 52. Therefore, due to the source electrode 56, the drain electrode 57, the metal layer 71, and the metal layer 72, the first low-resistance regions 63 to 66 and the second low-resistance regions 67 and 68 are formed in the oxide semiconductor layer 60. The structure of the oxide semiconductor layer 60 is the same as that of the third embodiment, so the description thereof is omitted here.

[0122] In this embodiment, it is also possible to form the first low-resistance regions 64 and 66 having sufficient lengths near the drain region 62 without adding a manufacturing process. Further, similarly to the third embodiment, it is possible to make the lengths of the first low-resistance regions 64 and 66 uniform for a plurality of thin-film transistors 10c. Thus, according to this embodiment, the reliability of a display device including the thin-film transistors 10c using an oxide semiconductor can be improved.

[0123] In each of the above embodiments, a display device has been described as an example. However, it is not limited to this example, and each embodiment can be applied to all devices including devices using a semiconductor, that is, semiconductor devices. Further, as long as the above-described embodiments as embodiments of the present invention do not contradict each other, they can be appropriately combined and implemented. Based on each embodiment, a structure obtained by appropriately adding, deleting, or changing the design of components by those skilled in the art, or a structure obtained by adding, omitting, or changing conditions of processes, as long as it includes the gist of the present invention, is also included in the scope of the present invention.

[0124] In addition, other effects different from the effects brought about by each of the above embodiments, which are apparent from the description of this specification or can be easily predicted by those skilled in the art, are of course also understood to be brought about by the present invention.

Claims

1. A semiconductor device having thin film transistors in respective pixels, characterized in that: The thin film transistor has: An oxide semiconductor layer; A gate insulating layer; A gate electrode overlapping the oxide semiconductor layer with the gate insulating layer interposed therebetween; A source electrode in contact with the oxide semiconductor layer; A drain electrode in contact with the oxide semiconductor layer; And A first metal layer that is in contact with the oxide semiconductor layer and is disposed between the source electrode and the drain electrode with a space therebetween from the source electrode and the drain electrode; The oxide semiconductor layer has: a channel region; a drain region; and a low resistance region located between the channel region and the drain region and in contact with the channel region and the drain region respectively, at least a part of the low resistance region being in contact with the first metal layer; The oxygen concentration of the low resistance region is lower than that of the channel region.

2. The semiconductor device according to claim 1, characterized in that: The distance between the first metal layer and the drain electrode is 1.0 μm or more and 3.0 μm or less.

3. The semiconductor device according to claim 1, characterized in that: The first metal layer and the drain electrode are provided in the same layer.

4. The semiconductor device according to claim 1, characterized in that: The first metal layer and the drain electrode are made of the same metal material.

5. The semiconductor device according to claim 1, characterized in that: The first metal layer is electrically floating.

6. The semiconductor device according to claim 1, characterized in that: The low resistance region includes: a region in contact with the first metal layer; and a first region, The first region is disposed between the region in contact with the first metal layer and the drain region.

7. The semiconductor device according to claim 6, characterized in that: The low resistance region includes: a region in contact with the first metal layer; and a second region, The second region is disposed between the region in contact with the first metal layer and the channel region.

8. The semiconductor device according to claim 7, characterized in that: The first region and the second region are spaced apart from each other through the region in contact with the first metal layer.

9. The semiconductor device according to claim 1, characterized in that: The first metal layer penetrates through the gate insulating layer to be in contact with the oxide semiconductor layer.

10. The semiconductor device according to claim 1, characterized in that: It further has a second metal layer that is in contact with the oxide semiconductor layer and is disposed between the source electrode and the first metal layer with a space therebetween from the source electrode and the first metal layer.

11. The semiconductor device according to claim 10, characterized in that: The distance between the second metal layer and the source electrode is 1.0 μm or more and 3.0 μm or less.

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