A high-voltage linear charging circuit based on thin gate oxide process with reverse connection protection

Abstract

The application discloses a high-voltage linear charging circuit based on a thin gate oxide process and with reverse connection protection, which comprises a voltage stabilizing module, a PMOS charging tube, a self-turn-off gate voltage clamping circuit, a voltage conversion current circuit with current limiting, a current detection setting circuit and a charging controller; the output end of the voltage stabilizing module is connected with the input ends of the voltage conversion current circuit with current limiting, the current detection setting circuit and the charging controller; the output end of the current detection setting circuit is connected with the input end of the charging controller; the output end of the charging controller is connected with the input end of the voltage conversion current circuit with current limiting; the output end of the voltage conversion current circuit with current limiting is connected with the input end of the self-turn-off gate voltage clamping circuit; and the output end of the self-turn-off gate voltage clamping circuit is connected with the input end of the PMOS charging tube. The application realizes a linear charging circuit which can bear high-voltage input and output and has battery reverse connection protection on the basis of a thin gate oxide process; and the linear charging circuit has the characteristics of high density and easy integration.

Description

Technical Field

[0001] This invention relates to the field of power management integrated circuit technology, specifically to a high-voltage linear charging circuit with reverse connection protection based on thin gate oxide technology. Background Technology

[0002] In recent years, the field of charging electronic devices has developed rapidly. Higher power density and safer performance are important directions for its future development. Battery charging management chips, as a key component, directly determine the power density and safety of electronic devices. Due to increasingly higher and more volatile interface voltages in various electronic devices, and the increasing voltage of battery packs, a battery charging management chip capable of withstanding high input and output voltages is universally needed. To prevent product failure or safety accidents caused by reversed battery polarity during production and use, the battery charging management chip should also have reverse protection functionality. Meanwhile, with the advancement of Moore's Law, thin-gate oxide (LTO) technology, offering higher integration and lower cost, has become the mainstream technology in the semiconductor manufacturing industry. Therefore, developing battery charging circuits with high input voltage ranges and protection using LTO technology is an inevitable requirement.

[0003] Existing Chinese literature, such as the patent with authorization publication number CN100442629, includes known linear chargers (see attached). Figure 5 This structure typically consists of a P-type MOSFET, with M2 as the control transistor and M1 as the output transistor. The source of the PMOS transistor M1 is connected to the power supply VDD, and the drain is connected to the battery terminal VBAT. The gate control voltage is between ground and the power supply VDD. Thin gate oxide technology can only provide devices with high voltage withstand between the source and drain, but not between the source and gate. If the power supply VDD continues to increase, and the voltage between the gate and source exceeds the gate oxide withstand voltage, the MOSFET will be damaged. Therefore, this structure cannot be used for high-voltage input. A similar structure is used in the patent with US10439421, which also uses a P-type MOSFET. If it is used in high-voltage applications, it cannot be processed using thin gate oxide technology. For example, the patent with authorization announcement number CN101431295 / US8248049 uses an N-type MOS transistor structure, where the drain of the N-type MOS transistor is connected to the power supply and the source of the N-type MOS transistor is connected to the battery terminal. However, since there is a diode between the source of the N-type MOS transistor and the P-type substrate, when the battery terminal is reverse-connected, a negative voltage will be applied between the source of the N-type NMOS transistor and ground. The diode will carry a very large current, causing the circuit to burn out. Moreover, if the reverse connection voltage is high enough, the voltage between the gate and source of the N-type NMOS transistor in this structure may exceed the gate oxide breakdown voltage. Summary of the Invention

[0004] The purpose of this invention is to provide a high-voltage linear charging circuit with reverse connection protection based on thin gate oxide technology, so as to solve the problems mentioned in the background art.

[0005] To solve the above-mentioned technical problems, the present invention provides the following technical solution: a high-voltage linear charging circuit based on thin gate oxide technology with reverse connection protection, comprising a voltage regulator module, a PMOS charging transistor, a self-turn-off gate voltage clamping circuit, a voltage-to-current conversion circuit with current limiting, a current detection and setting circuit, and a charging controller. The output terminal of the voltage regulator module is connected to the input terminals of the voltage-to-current conversion circuit with current limiting, the current detection and setting circuit, and the charging controller. The output terminal of the current detection and setting circuit is connected to the input terminal of the charging controller. The output terminal of the charging controller is connected to the input terminal of the voltage-to-current conversion circuit with current limiting. The output terminal of the voltage-to-current conversion circuit with current limiting is connected to the input terminal of the self-turn-off gate voltage clamping circuit. The output terminal of the self-turn-off gate voltage clamping circuit is connected to the input terminal of the PMOS charging transistor.

[0006] Furthermore, the voltage-to-current conversion circuit with current limiting includes MP6, current source I1, MN1 and MN2. MP6 is a PMOS transistor, and MN1 and MN2 are both NMOS transistors. Its function is to limit the amplitude of the output current and prevent the self-turn-off gate voltage clamping circuit from failing due to excessive output current.

[0007] Furthermore, the drain of MN1 is connected to Vg, the gate of MN1 is connected to Vc, the source of MN1 is connected to ground, the drain of MN2 is connected to Vd, the gate of MN2 is connected to Vc, the source of MN2 is connected to ground, the drain of MP6 is connected to ground, the gate of MP6 is connected to Vd, the source of MP6 is connected to Vc, the upper end of the current source I1 is connected to VDD, and the lower end of the current source I1 is connected to Vd.

[0008] Furthermore, the PMOS charging transistor includes MP1 and MP2, both of which are PMOS transistors. The drain of MP1 is connected to the input VIN, and the drain of MP2 is connected to the output VBAT. The source of MP1 is connected to the source of MP2. The gates of both MP1 and MP2 are connected to the Vg output of the self-turn-off gate voltage clamping circuit. Its function is that the high voltage between the output VBAT and the input VIN can be withstood by the withstand voltage between the source and drain of MP1; the high voltage between the input VIN and the output VBAT can be withstood by the withstand voltage between the source and drain of MP2; and the reverse connection of the battery may cause a negative voltage in VBAT, which can be withstood by the withstand voltage between the source and drain of MP2.

[0009] Furthermore, the self-turn-off gate voltage clamping circuit includes resistors R1, MP3, MP4, and MP5. MP3, MP4, and MP5 are all PMOS transistors. Through the self-turn-off gate voltage clamping circuit, the gate voltage Vg and source voltage Vcom of MP1 and MP2 are protected within the withstand voltage range of the thin gate oxide process, and the PMOS charging transistors can be turned on and off normally.

[0010] Furthermore, the source of MP3 is connected to Vcom, the gate and drain of MP3 are connected to the source of MP4, the gate and drain of MP4 are connected to the source of MP5, the gate and drain of MP5 are connected to Vg, one end of resistor R1 is connected to Vcom, and the other end of resistor R1 is connected to Vg.

[0011] Furthermore, the current detection and setting circuit detects the charging current and sets the current by the value of the series resistor R2. Its output control signal Ic is connected to the input terminal of the charging controller. The charging controller outputs a control voltage Vc according to the control signal Ic and the output voltage VBAT.

[0012] Furthermore, the voltage regulator module includes a resistor R3, a Zener diode D1, a capacitor C1, and MN3. MN3 is an NMOS transistor. When the VIN voltage rises, the Zener diode D1 breaks down, generating a constant voltage Vcl. VDD is a voltage lower than Vcl. VDD is used as the power supply for the internal modules, so all modules powered by VDD will not be affected by the high VIN voltage.

[0013] Furthermore, one end of the resistor R3 is connected to the input VIN, the other end of the resistor R3 is connected to Vcl, the negative terminal of the Zener diode D1 is connected to Vcl, the positive terminal of the Zener diode D1 is grounded, the drain of the MN3 is connected to VIN, the source of the MN3 is connected to VDD, the gate of the MN3 is connected to Vcl, the upper plate of the capacitor C1 is connected to VDD, and the lower plate of the capacitor C1 is grounded.

[0014] Compared with the prior art, the beneficial effects achieved by the present invention are:

[0015] This invention realizes a linear charging circuit that can withstand high voltage input and has battery reverse connection protection on the output by using thin gate oxide technology. The linear charging circuit is based on thin gate oxide technology, has the characteristics of high density and easy integration, and can withstand high voltage input and output, and has reliable reverse connection protection function, making it suitable for a wide range of applications. Attached Figure Description

[0016] The accompanying drawings are provided to further illustrate the invention and form part of the specification. They are used in conjunction with embodiments of the invention to explain the invention and do not constitute a limitation thereof. In the drawings:

[0017] Figure 1 This is a circuit diagram of Embodiment 1 of the present invention;

[0018] Figure 2 This is a circuit diagram of Embodiment 2 of the present invention;

[0019] Figure 3 This is a circuit diagram of Embodiment 3 of the present invention;

[0020] Figure 4 This is a circuit diagram of Embodiment 4 of the present invention.

[0021] Figure 5 This is a circuit diagram referenced in the background section of this invention. Detailed Implementation

[0022] The technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of the present invention, and not all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of the present invention.

[0023] Please see Figures 1-5This invention provides a technical solution: a high-voltage linear charging circuit based on thin-gate oxide technology with reverse connection protection, comprising a voltage regulator module, a PMOS charging transistor, a self-turn-off gate voltage clamping circuit, a voltage-to-current conversion circuit with current limiting, a current detection and setting circuit, and a charging controller. The output terminal of the voltage regulator module is connected to the input terminals of the voltage-to-current conversion circuit with current limiting, the current detection and setting circuit, and the charging controller. The output terminal of the current detection and setting circuit is connected to the input terminal of the charging controller. The output terminal of the charging controller is connected to the input terminal of the voltage-to-current conversion circuit with current limiting. The output terminal of the voltage-to-current conversion circuit with current limiting is connected to the input terminal of the self-turn-off gate voltage clamping circuit. The output terminal of the clamping circuit is connected to the input terminal of the PMOS charging transistor. The voltage-to-current conversion circuit with current limiting includes MP6, current source I1, MN1, and MN2. MP6 is a PMOS transistor, and MN1 and MN2 are both NMOS transistors. Its function is to limit the amplitude of the output current to prevent the self-turn-off gate voltage clamping circuit from failing due to excessive output current. The drain of MN1 is connected to Vg, the gate of MN1 is connected to Vc, and the source of MN1 is connected to ground. The drain of MN2 is connected to Vd, the gate of MN2 is connected to Vc, and the source of MN2 is connected to ground. The drain of MP6 is connected to ground, the gate of MP6 is connected to Vd, and the source of MP6 is connected to Vc. The upper current source I1... The lower end of the current source I1 is connected to Vd, and the lower end of the current source I1 is connected to Vd. The PMOS charging transistors include MP1 and MP2, both of which are PMOS transistors. The drain of MP1 is connected to the input VIN, and the drain of MP2 is connected to the output VBAT. The source of MP1 is connected to the source of MP2. The gates of both MP1 and MP2 are connected to the Vg output of the self-turn-off gate voltage clamping circuit. The self-turn-off gate voltage clamping circuit includes resistors R1, MP3, MP4, and MP5, all of which are PMOS transistors. The source of MP3 is connected to Vcom, and the gate and drain of MP3 are connected to the source of MP4. The gate and drain of MP4 are connected to the source of MP4. The source of the MP5 is connected, and the gate and drain of the MP5 are connected to Vg. One end of the resistor R1 is connected to Vcom, and the other end of the resistor R1 is connected to Vg. The function of the current detection and setting circuit is to detect the charging current and set the current by the value of the series-connected resistor R2. Its output control signal Ic is connected to the input terminal of the charging controller. The charging controller outputs a control voltage Vc according to the control signal Ic and the output voltage VBAT. The voltage regulator module includes a resistor R3, a Zener diode D1, a capacitor C1, and MN3. MN3 is an NMOS transistor. When the VIN voltage rises, the Zener diode D1 will break down, generating a constant voltage Vcl, while VDD is a voltage lower than Vcl.VDD is used as the power supply for the internal modules, so all VDD-powered modules are not affected by the high voltage VIN. One end of resistor R3 is connected to the input VIN, and the other end of resistor R3 is connected to Vcl. The cathode of Zener diode D1 is connected to Vcl, and the anode of Zener diode D1 is grounded. The drain of MN3 is connected to VIN, the source of MN3 is connected to VDD, and the gate of MN3 is connected to Vcl. The upper plate of capacitor C1 is connected to VDD, and the lower plate of capacitor C1 is grounded.

[0024] Example 1: Figure 1 This is one embodiment of the present invention:

[0025] In the voltage regulator module, one end of resistor R3 is connected to VIN, and the other end is connected to the N-terminal Vcl of diode D1. The N-terminal of diode D1 is connected to Vcl, and the P-terminal is connected to ground. The drain of NMOS transistor MN3 is connected to VIN, the source is connected to the upper plate VDD of capacitor C1, and the gate is connected to Vcl. The upper plate of capacitor C1 is connected to VDD, and the lower plate is connected to ground. When the voltage VIN rises, the Zener diode will break down, generating a constant voltage Vcl, while VDD is a voltage lower than Vcl. VDD is used as the power supply for the internal modules, so all modules powered by VDD will not be affected by the high voltage VIN.

[0026] The current detection and setting circuit is a VDD power supply module. Its function is to detect the charging current Icharge and set the charging current through the value of resistor R2. Its output control signal Ic is connected to the charging controller module.

[0027] The charging controller is a VDD power supply module, whose input signals are the control signal Ic and the battery voltage VBAT; the output signal is the control voltage Vc.

[0028] The voltage-to-current conversion circuit with current limiting is a VDD power supply module with input signal Vc. NMOS transistor MN1 has its drain connected to Vg, its gate connected to Vc, and its source connected to ground. NMOS transistor MN2 has its drain connected to Vd, its gate connected to Vc, and its source connected to ground. PMOS transistor MP6 has its drain connected to ground, its gate connected to Vd, and its source connected to Vc. Current source I1 has its upper end connected to VDD and its lower end connected to Vd. This circuit converts the control signal Vc into a current signal, which is output from NMOS transistor MN1 to the self-turn-off gate voltage clamping circuit. Its function is to limit the amplitude of the output current, preventing excessive output current from causing the self-turn-off gate voltage clamping circuit to fail.

[0029] In the self-turn-off gate voltage clamping circuit, the source of PMOS transistor MP3 is connected to Vcom, and its gate and drain are connected to the source of PMOS transistor MP4. The source of PMOS transistor MP4 is connected to the gate and drain of PMOS transistor MP3, and its gate and drain are connected to the source of PMOS transistor MP5. The source of PMOS transistor MP5 is connected to the gate and drain of PMOS transistor MP4, and its gate and drain are connected to Vg. One end of resistor R1 is connected to Vcom, and the other end is connected to Vg. Through the self-turn-off gate voltage clamping circuit, the voltages of the gate Vg and source Vcom of PMOS charging transistors MP1 and MP2 are protected within the withstand voltage range of the thin gate oxide process, and the PMOS charging transistors can be turned on and off normally.

[0030] In the PMOS charging transistor, the drain of PMOS transistor MP1 is connected to VIN, the gate is connected to Vg, and the source is connected to the source Vcom of PMOS transistor MP2; the drain of PMOS transistor MP2 is connected to VBAT, the gate is connected to Vg, and the source is connected to the source Vcom of PMOS transistor MP1. Therefore, the high voltage between the output VBAT and the input VIN can be withstood by the breakdown voltage between the source and drain of MP1; the high voltage between the input VIN and the output VBAT can be withstood by the breakdown voltage between the source and drain of MP2; reverse battery connection may cause VBAT to have a negative voltage, which can be withstood by the breakdown voltage between the source and drain of MP2.

[0031] Example 2: Figure 2 This is another embodiment of the present invention, which is similar to... Figure 2 The difference in the embodiment is that in the current detection and setting circuit, the source of PMOS transistor MP7 is connected to Vcom, the gate is connected to Vg, and the drain is connected to Ve; the negative input of amplifier OP1 is connected to VBAT, the positive input is connected to the drain of PMOS transistor MP7 Ve, and the output is connected to Vop; the gate of NMOS transistor MN4 is connected to Vop, the source is connected to Ic, and the drain is connected to Ve; one end of resistor R2 is connected to Ic and the other end is connected to ground; this circuit realizes the sampling of charging current by mirroring PMOS transistor MP7, superimposing it on resistor R2, and setting the charging current by adjusting the resistance value of resistor R2.

[0032] Example 3: Figure 3 This is yet another embodiment of the present invention; this embodiment is similar to... Figure 2 The difference in the embodiment is that in the current detection setting circuit, the negative input of amplifier OP1 is connected to Vcom, the positive input is connected to VIN, and the output is connected to one end Ic of resistor R2; this circuit samples the charging current by directly amplifying the voltage difference across PMOS transistor MP1 and superimposes it onto resistor R2, and sets the charging current by adjusting the resistance value of resistor R2.

[0033] Example 4: Figure 4This is another embodiment of the present invention; in this embodiment, diode D2 is used instead of... Figure 2 In this embodiment, the PMOS transistor MP1 can be placed either inside or outside the chip. This embodiment saves costs and allows for flexible configuration.

[0034] Working principle of the invention:

[0035] The linear charger of this invention uses a current detection and setting circuit to compare the detected charging current with a set charging current, generating a control signal Ic which is sent to the charging controller. The charging controller generates a control signal Vc based on the control signal Ic and the detected VBAT voltage, and then transmits Vc to a self-turn-off gate voltage clamping circuit through a voltage-to-current conversion circuit with current limiting. This generates a gate control signal Vg for the PMOS charging transistor, which controls the PMOS charging transistor to turn on and off, ultimately achieving constant current or constant voltage charging from input VIN to output VBAT. Addressing the problems mentioned in the background, this invention firstly addresses the issue of high-voltage input VIN by converting VIN through a voltage regulator module before powering other internal modules. This prevents internal components from being affected by high VIN voltage. Secondly, this invention also uses a voltage-to-current conversion circuit with current limiting to convert the voltage signal of the control circuit into a... The current limiting signal is transmitted to the PMOS charging transistor, which limits the amplitude of the output current to prevent excessive output current from causing the self-turn-off gate voltage clamping circuit to fail. Furthermore, at the charging transistor, this invention uses two P-type MOS transistors, MP1 and MP2. Since thin-gate oxide technology can only provide devices with high voltage withstand between the source and drain, but not between the source and gate, the high voltage between the output VBAT and the input VIN can be absorbed by the voltage withstand between the source and drain of MP1; the high voltage between the input VIN and the output VBAT can be absorbed by the voltage withstand between the source and drain of MP2; the negative voltage of VBAT after reverse connection of the battery can be absorbed by the voltage withstand between the source and drain of MP2. Finally, the voltage difference between the gate and source of the PMOS charging transistors MP1 and MP2 is protected within the voltage withstand range of the thin-gate oxide technology by the self-turn-off gate voltage clamping circuit of this invention.

[0036] It should be noted that, in this document, relational terms such as "first" and "second" are used only to distinguish one entity or operation from another, and do not necessarily require or imply any such actual relationship or order between these entities or operations. Furthermore, the terms "comprising," "including," or any other variations thereof are intended to cover non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements includes not only those elements but also other elements not expressly listed, or elements inherent to such process, method, article, or apparatus.

[0037] Finally, it should be noted that the above descriptions are merely preferred embodiments of the present invention and are not intended to limit the present invention. Although the present invention has been described in detail with reference to the foregoing embodiments, those skilled in the art can still modify the technical solutions described in the foregoing embodiments or make equivalent substitutions for some of the technical features. Any modifications, equivalent substitutions, improvements, etc., made within the spirit and principles of the present invention should be included within the protection scope of the present invention.

Claims

1. A high-voltage linear charging circuit with reverse connection protection based on thin gate oxide technology, characterized in that: The application relates to a charging circuit, which comprises a voltage stabilizing module, a PMOS charging tube, a self-turn-off gate voltage clamping circuit, a voltage conversion current circuit with current limiting, a current detection setting circuit and a charging controller, wherein the output end of the voltage stabilizing module is connected with the input ends of the voltage conversion current circuit with current limiting, the current detection setting circuit and the charging controller, the output end of the current detection setting circuit is connected with the input end of the charging controller, the output end of the charging controller is connected with the input end of the voltage conversion current circuit with current limiting, the output end of the voltage conversion current circuit with current limiting is connected with the input end of the self-turn-off gate voltage clamping circuit, and the output end of the self-turn-off gate voltage clamping circuit is connected with the input end of the PMOS charging tube; the voltage conversion current circuit with current limiting comprises an MP6, a current source I1, an MN1 and an MN2, the MP6 is a PMOS tube, and the MN1 and the MN2 are NMOS tubes; the PMOS charging tube comprises an MP1 and an MP2, the MP1 and the MP2 are PMOS tubes, the drain of the MP1 is connected with an input VIN, the drain of the MP2 is connected with an output VBAT, the source of the MP1 is connected with the source of the MP2, and the gates of the MP1 and the MP2 are connected with the Vg output of the self-turn-off gate voltage clamping circuit; the self-turn-off gate voltage clamping circuit comprises a resistor R1, an MP3, an MP4 and an MP5, and the MP3, the MP4 and the MP5 are PMOS tubes; the current detection setting circuit detects charging current and sets current through the size of a series-connected resistor R2, and the output control signal Ic of the current detection setting circuit is connected to the input end of the charging controller; the charging controller is a circuit outputting a control voltage; and the voltage stabilizing module comprises a resistor R3, a voltage stabilizing diode D1, a capacitor C1 and an MN3, and the MN3 is an NMOS tube.

2. A high voltage linear charging circuit with reverse connection protection based on thin gate oxide process according to claim 1, characterized in that: The drain of the MN1 is connected with Vg, the gate of the MN1 is connected with Vc, the source of the MN1 is connected with the ground, the drain of the MN2 is connected with Vd, the gate of the MN2 is connected with Vc, the source of the MN2 is connected with the ground, the drain of the MP6 is connected with the ground, the gate of the MP6 is connected with Vd, and the source of the MP6 is connected with Vc.

3. A high voltage linear charging circuit based on thin gate oxide process with reverse connection protection according to claim 1, characterized in that: The source of the MP3 is connected with Vcom, the gate and the drain of the MP3 are connected with the source of the MP4, the gate and the drain of the MP4 are connected with the source of the MP5, the gate and the drain of the MP5 are connected with Vg, one end of the resistor R1 is connected with Vcom, and the other end of the resistor R1 is connected with Vg.

4. The high voltage linear charging circuit with reverse connection protection based on thin gate oxide process according to claim 1, characterized in that: One end of the resistor R3 is connected with the input VIN, the other end of the resistor R3 is connected with Vcl, the negative electrode of the voltage stabilizing diode D1 is connected with Vcl, the positive electrode of the voltage stabilizing diode D1 is connected with the ground, the drain of the MN3 is connected with VIN, the source of the MN3 is connected with VDD, the gate of the MN3 is connected with Vcl, the upper plate of the capacitor C1 is connected with VDD, and the lower plate of the capacitor C1 is connected with the ground.

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