Semiconductor device

Abstract

The present invention relates to a semiconductor device. The semiconductor device according to an embodiment includes: a first circuit configured to generate a first voltage; a second circuit configured to transmit the generated first voltage to a first terminal; and a third circuit configured to generate a first signal that becomes a first level when the voltage of the first terminal is equal to or higher than a threshold voltage and becomes a second level when the voltage of the first terminal is less than the threshold voltage. The second circuit is configured to stop the transmission of the first voltage based on the first signal at the second level.

Description

[0001] This application claims priority based on Japanese Patent Application No. 2020-199676 (filing date: December 1, 2020). This application incorporates the entire contents of the base application by reference thereto. Technical Field

[0002] The embodiment mainly relates to a semiconductor device. Background Art

[0003] Semiconductor devices for supplying voltage to a load are known. Summary of the Invention

[0004] The embodiment provides a semiconductor device capable of suppressing an increase in current caused by a short circuit.

[0005] The semiconductor device of the embodiment includes: a first circuit configured to generate a first voltage; a second circuit configured to transmit the generated first voltage to a first terminal; and a third circuit configured to generate a first signal that becomes a first level when the voltage of the first terminal is equal to or higher than a threshold voltage and becomes a second level when the voltage of the first terminal is less than the threshold voltage. The second circuit is configured to stop the transmission of the first voltage based on the first signal at the second level. Brief Description of the Drawings

[0006] Figure 1 It is a block diagram showing an example of the configuration of the semiconductor device of the embodiment.

[0007] Figure 2 It is a circuit diagram showing an example of the configuration of the drive circuit and the voltage monitoring circuit of the semiconductor device of the embodiment.

[0008] Figure 3 It is a circuit diagram showing an example of the configuration of the output circuit included in the drive circuit of the semiconductor device of the embodiment.

[0009] Figure 4 It is a timing diagram showing an example of the drive operation of the semiconductor device when driving an external switch using the semiconductor device of the embodiment.

[0010] Figure 5 It is a circuit diagram showing an example of the configuration of the voltage monitoring circuit of the semiconductor device of the first modification.

[0011] Figure 6 It is a circuit diagram showing an example of the configuration of the voltage monitoring circuit of the semiconductor device of the second modification.

[0012] Figure 7This is a timing chart showing an example of the driving operation of a semiconductor device when driving an external switch using the second modification example.

[0013] Figure 8 This is a circuit diagram showing an example of the configuration of the voltage monitoring circuit of the semiconductor device according to the third modification example.

[0014] Figure 9 This is a circuit diagram showing an example of the configuration of the output circuit included in the driving circuit of the semiconductor device according to the fourth modification example.

[0015] Figure 10 This is a circuit diagram showing an example of the configuration of the voltage monitoring circuit of the semiconductor device according to the fifth modification example. Detailed Implementation Manner

[0016] Hereinafter, the implementation manner will be described with reference to the accompanying drawings. In addition, in the following description, components having the same functions and configurations are denoted by common reference symbols.

[0017] 1. Implementation Manner

[0018] The semiconductor device of the implementation manner will be described.

[0019] The semiconductor device of the implementation manner is a driver that supplies a voltage for driving a load such as a switching element. The semiconductor device of the implementation manner is, for example, an IC (Integrated Circuit) chip.

[0020] 1.1 Configuration

[0021] The configuration of the semiconductor device of the implementation manner will be described.

[0022] 1.1.1 Overall Configuration of the Semiconductor Device

[0023] Use Figure 1 The configuration of the semiconductor device of the implementation manner will be described. Figure 1 This is a block diagram showing an example of the configuration of the semiconductor device of the implementation manner.

[0024] The semiconductor device 1 is configured to supply a voltage for driving the switch 2 outside the semiconductor device 1.

[0025] The switch 2 includes, for example, two switching elements NTOUT (NTOUT1 and NTOUT2). The switching element NTOUT is an N-channel type MOSFET (Metal-Oxide-Semiconductor Field Effect Transistor). In addition, in Figure 1In the example, switch 2 includes two switching elements NTOUT1 and NTOUT2, but the number of switching elements NTOUT is not limited thereto. Switch 2 may include one or more than three switching elements.

[0026] The first ends of the switching elements NTOUT1 and NTOUT2 are each input with the voltage VIN. The voltage VIN is a voltage supplied from a voltage source outside the semiconductor device 1. The external voltage source supplies the voltage VIN to the first ends of the switching elements NTOUT, for example, via the USB (Universal Serial Bus) terminal of the portable electronic device. As will be described later, the gates of the switching elements NTOUT1 and NTOUT2 are each connected to the semiconductor device 1. Voltages VOUT1 and VOUT2 are respectively output from the second ends of the switching elements NTOUT1 and NTOUT2. The voltages VOUT1 and VOUT2 are respectively supplied to different loads (not shown). The loads are, for example, a battery and a power supply IC, etc.

[0027] The semiconductor device 1 includes terminals PVIN, POUT1, POUT2, and PS.

[0028] The terminal PVIN is input with the voltage VIN.

[0029] The terminal POUT1 connects the semiconductor device 1 to the gate of the switching element NTOUT1. The terminal POUT2 connects the semiconductor device 1 to the gate of the switching element NTOUT2. Voltages for charging the gate of the switching element NTOUT1 and voltages for charging the gate of the switching element NTOUT2 are respectively output from the terminals POUT1 and POUT2.

[0030] The terminal PS receives, for example, a command CMD from outside the semiconductor device 1. The command CMD includes, for example, a command for causing the semiconductor device 1 to drive the switch 2 and a command for causing the semiconductor device 1 to stop driving the switch 2. The semiconductor device 1 drives the switch 2 based on the received command CMD.

[0031] The semiconductor device 1 includes a control circuit 10, an oscillator 11, a boost circuit 12, a drive circuit 13, and a voltage monitoring circuit 14. The drive circuit 13 includes drive circuits 13-1 and 13-2. The voltage monitoring circuit 14 includes voltage monitoring circuits 14-1 and 14-2. In addition, in the following description, the case where the semiconductor device 1 includes two drive circuits 13 and voltage monitoring circuits 14 respectively is taken as an example for description, but it is not limited thereto. The semiconductor device 1 may also include one or more than three drive circuits 13 and voltage monitoring circuits 14 respectively according to the number of switching elements NTOUT included in the switch 2.

[0032] The control circuit 10 receives a command CMD from the outside of the semiconductor device 1 via a terminal PS, for example, and controls the oscillator 11 and the booster circuit 12 based on the received command CMD.

[0033] The oscillator 11 generates a clock signal based on the control of the control circuit 10 and outputs the generated clock signal to the booster circuit 12.

[0034] A voltage VIN is input to the booster circuit 12 from the outside of the semiconductor device 1 via a terminal PVIN. The booster circuit 12 boosts the input voltage VIN to a voltage VCP and outputs it. The voltage VCP of the booster circuit 12 is used to drive the switch 2. In the following description, the operation in which the booster circuit 12 boosts the voltage VIN to the voltage VCP and outputs it is referred to as a boosting operation.

[0035] The voltage VCP of the booster circuit 12 is input to the drive circuits 13-1 and 13-2, respectively. The drive circuits 13-1 and 13-2 drive the switch 2 using the input voltage VCP of the booster circuit 12. More specifically, the drive circuit 13-1 transmits the voltage VCP of the booster circuit 12 to the gate of the switching element NTOUT1 via a terminal POUT1 based on the control of the control circuit 10 and the voltage monitoring circuit 14-1. Thereby, the drive circuit 13-1 charges the gate of the switching element NTOUT1 and drives the switching element NTOUT1. In addition, the drive circuit 13-2 transmits the voltage VCP of the booster circuit 12 to the gate of the switching element NTOUT2 via a terminal POUT2 based on the control of the control circuit 10 and the voltage monitoring circuit 14-2. Thereby, the drive circuit 13-2 charges the gate of the switching element NTOUT2 and drives the switching element NTOUT2.

[0036] The voltage monitoring circuit 14-1 monitors the voltage VG1 of the gate of the switching element NTOUT1. The voltage monitoring circuit 14-1 controls the drive circuit 13-1 together with the control circuit 10 based on the result of monitoring the voltage VG1. The voltage monitoring circuit 14-2 monitors the voltage VG2 of the gate of the switching element NTOUT2. The voltage monitoring circuit 14-2 controls the drive circuit 13-2 together with the control circuit 10 based on the result of monitoring the voltage VG2. In the following description, the voltages VG1 and VG2 are also collectively referred to as the voltage VG.

[0037] 1.1.2 Configuration of Drive Circuit and Voltage Monitoring Circuit

[0038] Use Figure 2 The configuration of the drive circuit 13 and the voltage monitoring circuit 14 of the semiconductor device 1 according to the embodiment will be described. Figure 2This is a circuit diagram showing an example of the configuration of the drive circuit 13 and the voltage monitoring circuit 14 of the semiconductor device 1 for explaining the embodiments. In addition, in Figure 2 it shows the configuration of the drive circuit 13-1 and the voltage monitoring circuit 14-1 together with the control circuit 10, the oscillator 11, and the boost circuit 12. In the following description, the configuration of the drive circuit 13-1 and the voltage monitoring circuit 14-1 will be described together with the control circuit 10, the oscillator 11, and the boost circuit 12. Regarding the configuration of the drive circuit 13-2 and the voltage monitoring circuit 14-2, the description of the same configuration as that of the drive circuit 13-1 and the voltage monitoring circuit 14-1 will be omitted, and mainly the different configuration from the drive circuit 13-1 and the voltage monitoring circuit 14-1 will be described.

[0039] The control circuit 10 generates a signal S1 according to the command CMD and outputs the signal S1 to the oscillator 11 and the drive circuit 13. When the control circuit 10 receives a command to drive the drive switch 2, it changes the signal S1 from the "L" level to the "H" level. When the control circuit 10 receives a command to stop driving the drive switch 2, it changes the signal S1 from the "H" level to the "L" level.

[0040] The oscillator 11 generates a clock signal during the period when the signal S1 of the control circuit 10 is at the "H" level and outputs it to the boost circuit 12.

[0041] The boost circuit 12 performs a boosting operation based on the clock signal of the oscillator 11 and outputs a voltage VCP during the period when the signal S1 of the control circuit 10 is at the "H" level. The boost circuit 12 stops the boosting operation and stops the output of the voltage VCP during the period when the signal S1 is at the "L" level.

[0042] The configuration of the drive circuit 13-1 will be described.

[0043] The drive circuit 13-1 includes a pulse generation circuit 130, an OR circuit 131, an AND circuit 132, and an output circuit 133.

[0044] The pulse generation circuit 130 includes an input terminal and an output terminal. A signal S1 is input to the input terminal of the pulse generation circuit 130. The pulse generation circuit 130 generates a signal S2 based on the signal S1. More specifically, when the signal S1 changes from the "L" level to the "H" level, the pulse generation circuit 130 changes the signal S2 from the "L" level to the "H" level, and after a first period, changes the signal S2 from the "H" level to the "L" level. The first period is, for example, a period longer than the period from when the boost circuit 12 starts boosting until the gate of the switching element NTOUT is fully charged. The drive circuits 13-1 and 13-2 preset the first period in advance based on the configuration of the voltage monitoring circuit 14, for example. The signal S2 is output from the output terminal of the pulse generation circuit 130.

[0045] The OR circuit 131 has a first input terminal, a second input terminal, and an output terminal. The first input terminal of the OR circuit 131 is connected to the output terminal of the pulse generation circuit 130 and receives the signal S2. As will be described later, the second input terminal of the OR circuit 131 is connected to the voltage monitoring circuit 14-1 and receives the signal S3 of the voltage monitoring circuit 14-1. The OR circuit 131 performs an OR operation between the signal S2 input to the first input terminal of the OR circuit 131 and the signal S3 input to the second input terminal of the OR circuit 131, and generates a signal S4. More specifically, when both the signals S2 and S3 are at the "L" level, the OR circuit 131 sets the signal S4 to the "L" level, and when at least one of the signals S2 and S3 is at the "H" level, the OR circuit 131 sets the signal S4 to the "H" level. The signal S4 is output from the output terminal of the OR circuit 131.

[0046] The AND circuit 132 has a first input terminal, a second input terminal, and an output terminal. The signal S1 is input to the first input terminal of the AND circuit 132. The second input terminal of the AND circuit 132 is connected to the output terminal of the OR circuit 131 and receives the signal S4. The AND circuit 132 performs an AND operation between the signal S1 input to the first input terminal of the AND circuit 132 and the signal S4 input to the second input terminal of the AND circuit 132, and generates a signal S5. More specifically, when both the signals S1 and S4 are at the "H" level, the AND circuit 132 sets the signal S5 to the "H" level, and when at least one of the signals S1 and S4 is at the "L" level, the AND circuit 132 sets the signal S5 to the "L" level. The signal S5 is output from the output terminal of the AND circuit 132.

[0047] The output circuit 133 has a first input terminal, a second input terminal, and an output terminal. The first input terminal of the output circuit 133 is connected to the output terminal of the AND circuit 132 and receives the signal S5. The second input terminal of the output circuit 133 is connected to the boost circuit 12 and receives the voltage VCP of the boost circuit 12. The output terminal of the output circuit 133 is connected to the gate of the switching element NTOUT1 via the terminal POUT1. Additionally, although not shown, in the drive circuit 13-2, the output terminal of the output circuit 133 is connected to the gate of the switching element NTOUT2 via the terminal POUT2. When the signal S5 is at the "H" level, the output circuit 133 transfers the voltage VCP of the boost circuit 12 to the gate of the switching element NTOUT. Thus, the gate of the switching element NTOUT is charged. When the signal S5 is at the "L" level, the output circuit 133 stops the transfer of the voltage VCP. Thus, the gate of the switching element NTOUT is grounded. The specific configuration of the output circuit 133 will be described later.

[0048] Next, the configuration of the voltage monitoring circuit 14-1 will be described.

[0049] The voltage monitoring circuit 14-1 includes switching elements NT1, NT2, PT1, and a resistor R1. The switching elements NT1 and NT2 are N-channel MOSFETs. The switching element PT1 is a P-channel MOSFET.

[0050] The first terminal of the switching element NT1 is connected to the node N1. The second terminal of the switching element NT1 is grounded. The gate of the switching element NT1 is connected to the output terminal of the output circuit 133.

[0051] The first terminal of the resistor R1 is connected to the node N1. The voltage VBIAS is input to the second terminal of the resistor R1. The voltage VBIAS is, for example, a voltage supplied from a voltage source (not shown) inside the semiconductor device 1. However, the voltage VBIAS is not limited thereto, and for example, it may also be the voltage VIN.

[0052] The voltage VBIAS is input to the first terminal of the switching element PT1. The second terminal of the switching element NT2 is grounded. The gates of the switching element PT1 and the switching element NT2 are commonly connected to the node N1. The second terminal of the switching element PT1 is commonly connected to the first terminal of the switching element NT2 and the second input terminal of the OR circuit 121. The voltage between the second terminal of the switching element PT1 and the first terminal of the switching element NT2 is input as the signal S3 to the second input terminal of the OR circuit 131.

[0053] With the configuration of the voltage monitoring circuit 14 as described above, when the voltage VG of the switching element NTOUT is equal to or higher than the threshold voltage of the switching element NT1, the voltage of the node N1 becomes the "L" level and the signal S3 becomes the "H" level. When the voltage VG of the switching element NTOUT is less than the threshold voltage of the switching element NT1, the voltage of the node N1 becomes the "H" level and the signal S3 becomes the "L" level.

[0054] 1.1.3 Configuration of the output circuit

[0055] Use Figure 3 The configuration of the output circuit 133 of the drive circuit 13 in the embodiment will be described. Figure 3 It is a circuit diagram showing an example of the configuration of the output circuit 133 included in the drive circuit 13 of the semiconductor device 1 in the embodiment. In addition, Figure 3 The configuration of the output circuit 133 included in the drive circuit 13-1 is shown. In the following description, the configuration of the output circuit 133 included in the drive circuit 13-1 will be described. Regarding the configuration of the output circuit 133 included in the drive circuit 13-2, the description of the same configuration as that of the output circuit 133 included in the drive circuit 13-1 will be omitted, and mainly the configuration different from that of the output circuit 133 included in the drive circuit 13-1 will be described.

[0056] The output circuit 133 includes a constant current source I1, a current mirror CM1, a current mirror CM2, a transmission control circuit SWTC, and a slew rate control circuit STBC.

[0057] The constant current source I1 supplies current to the current mirror CM1. The current mirror CM1 generates a current based on the current of the constant current source I1, and this generated current flows through the current mirror CM2. The current mirror CM2 generates a current based on the current of the current mirror CM1 and supplies current to the output terminal of the output circuit 133. The transmission control circuit SWTC controls the current flowing through the current mirror CM1 and the current mirror CM2 based on the signal S5 input to the output circuit 133, and in addition, controls the voltage at the output terminal of the output circuit 133. The slew rate control circuit STBC supplies a current to the output terminal of the output circuit 133 to stabilize the voltage at the output terminal of the output circuit 133.

[0058] The constant current source I1 is connected to the node N2. For example, a voltage VBIAS is input to the constant current source I1. The constant current source I1 outputs a current based on the input voltage VBIAS to the node N2.

[0059] The current mirror CM1 includes switching elements NT3 and NT4. The switching elements NT3 and NT4 are N-channel MOSFETs.

[0060] The first terminal of the switching element NT3 is connected to the node N2 together with the gate of the switching element NT3. The second terminal of the switching element NT3 is connected to the transmission control circuit SWTC.

[0061] The first terminal of the switching element NT4 is connected to the node N3. The second terminal of the switching element NT4 is connected to the transmission control circuit SWTC. The gate of the switching element NT4 is connected to the node N2.

[0062] Through the configuration of the current mirror CM1 as described above, based on the current of the constant current source I1 flowing in the switching element NT3, the current flowing in the switching element NT4 is generated.

[0063] The current mirror CM2 includes switching elements PT2 and PT3. The switching elements PT2 and PT3 are P-channel MOSFETs.

[0064] The voltage VCP of the boost circuit 12 is input to the first terminal of the switching element PT2. The second terminal of the switching element PT2 and the gate of the switching element PT2 are connected to the node N3 together.

[0065] The voltage VCP of the boost circuit 12 is input to the first terminal of the switching element PT3. The second terminal of the switching element PT3 is connected to the gate of the switching element NTOUT1 via the terminal POUT1. Additionally, although not shown, in the drive circuit 13-2, the second terminal of the switching element PT3 is connected to the gate of the switching element NTOUT2 via the terminal POUT2. The gate of the switching element PT3 is connected to the node N3.

[0066] Through the configuration of the current mirror CM2 as described above, based on the current flowing in the switching element PT2, the current flowing in the switching element PT3 is generated. Thus, the current flowing in the switching element PT3 charges the gate of the switching element NTOUT. In addition, the current flowing in the switching element PT3 is a current based on the voltage VCP of the boost circuit 12. Thus, the voltage VCP of the boost circuit 12 is transmitted to the gate of the switching element NTOUT.

[0067] The transmission control circuit SWTC includes switching elements NT5, NT6, and NT7, a resistor R2, and an inverter circuit INVC1. The switching elements NT5, NT6, and NT7 are N-channel MOSFETs.

[0068] The first terminal of the switching element NT5 is connected to the second terminal of the switching element NT3. The second terminal of the switching element NT5 is grounded. The signal S5 of the circuit 132 is input to the gate of the switching element NT5.

[0069] The first terminal of the switching element NT6 is connected to the second terminal of the switching element NT4. The second terminal of the switching element NT6 is grounded. The gate of the switching element NT6 is input with the signal S5 of the input circuit 132.

[0070] The inverter circuit INVC1 includes an input terminal and an output terminal. The input terminal of the inverter circuit INVC1 is input with the signal S5 of the input circuit 132. The inverter circuit INVC1 generates a signal / S5 that inverts the voltage level (“H” level or “L” level) of the signal S5. More specifically, when the signal S5 is at the “H” level, the inverter circuit INVC1 sets the signal / S5 to the “L” level, and when the signal S5 is at the “L” level, the inverter circuit INVC1 sets the signal / S5 to the “H” level. The signal / S5 is output from the output terminal of the inverter circuit INVC1.

[0071] The first terminal of the switching element NT7 is connected via the resistor R2 to the second terminal (the output terminal of the output circuit 133) of the switching element PT3. The second terminal of the switching element NT7 is grounded. The gate of the switching element NT7 is connected to the output terminal of the inverter circuit INVC1 and is input with the signal / S5.

[0072] With the configuration of the transmission control circuit SWTC as described above, when the signal S5 is at the “H” level, the switching elements NT5 and NT6 are in the on state, and the switching element NT7 is in the off state. As a result, current flows in the current mirrors CM1 and CM2, and the voltage VCP of the boost circuit 12 is transmitted via the terminal POUT to the gate of the switching element NTOUT. When the signal S5 is at the “L” level, the switching elements NT5 and NT6 are in the off state, and the switching element NT7 is in the on state. As a result, the gate of the switching element NOUT is grounded via the switching element NT7, and the voltage VG of the gate of the switching element NOUT becomes the ground voltage VSS.

[0073] The slew rate control circuit STBC includes a switching element NT8 and PT4, a resistor R3, and a delay circuit DLYC. The switching element NT8 is an N-channel MOSFET. The switching element PT4 is a P-channel MOSFET.

[0074] The voltage VCP of the boost circuit 12 is input to the first terminal of the resistor R3. The second terminal of the resistor R3 is connected to the node N4.

[0075] The voltage VCP of the boost circuit 12 is input to the first terminal of the switching element PT4. The second terminal of the switching element PT4 is connected to the second terminal of the switching element PT3 and the first terminal of the resistor R2. The gate of the switching element PT4 is connected to the node N4. The resistance value of the switching element PT4 in the on state is, for example, smaller than the resistance value of the switching element PT3 in the on state. In addition, in the following description, the resistance of the switching element in the on state is referred to as the on-resistance. By setting the switching element PT3 to have a larger on-resistance value than the switching element PT4, the generation of a large current flowing through the switching element PT3 in the current mirror circuit CM2 can be suppressed. In addition, the on-resistance values of the switching elements PT3 and PT4 can be appropriately changed, for example, according to the breakdown voltage characteristics, on-resistance values, etc. of the switching element NTOUT.

[0076] The delay circuit DLYC includes an input terminal and an output terminal. The input terminal of the delay circuit DLYC is input with the signal S5 of the circuit 132. The delay circuit DLYC generates a signal S6 based on the signal S5. More specifically, when the signal S5 changes from the "L" level to the "H" level, the delay circuit DLYC causes the signal S6 to change from the "L" level to the "H" level after a first period. That is, the delay circuit DLYC delays the change of the signal S6 from the "L" level to the "H" level (hereinafter also referred to as rising) by the first period with respect to the rising of the signal S5. The delay circuit DLYC sets the signal S6 to the "L" level when the signal S5 is at the "H" level and the first period has not elapsed and when the signal S5 is at the "L" level. The output terminal of the delay circuit DLYC outputs the signal S6.

[0077] In addition, the delay circuit DLYC may delay the rising of the signal S6 by a second period different from the first period. The second period is, for example, the period from the moment when the signal S5 changes from the "L" level to the "H" level until the gate voltage of the switching element NTOUT becomes a specified voltage by the driving operation of the semiconductor device 1 described later. The specified voltage is a voltage higher than the ground voltage VSS and lower than the voltage VCP. The delay circuit DLYC, for example, presets the specified voltage based on the on-resistance of the switching element PT3, the voltage VCP, etc. In addition, the delay circuit DLYC may, for example, have a configuration for monitoring the gate voltage of the switching element NTOUT. In this case, the second period may also be the period during which the gate voltage of the switching element NTOUT monitored by the delay circuit DLYC becomes equal to or higher than the specified voltage.

[0078] The first terminal of the switching element NT8 is connected to the node N4. The second terminal of the switching element NT8 is grounded. The gate of the switching element NT8 is connected to the output terminal of the delay circuit DLYC and is input with the signal S6.

[0079] With the configuration of the STBC by the conversion rate control circuit as described above, when the gate voltage of the switching element NTOUT is charged to a specified voltage, the switching elements NT8 and PT4 become conductive, and current flows through the switching element PT4. As a result, the current flowing through the switching element PT4, together with the current flowing through the switching element PT3, charges the gate of the switching element NTOUT, and the voltage VCP of the boost circuit 12 is transmitted to the gate of the switching element NTOUT. As described above, the on-resistance of the switching element PT4 is smaller than that of the switching element PT3. Therefore, the current flowing through the switching element PT4 is smaller than the current flowing through the switching element PT3. Thus, the current flowing through the switching element PT4 can suppress, for example, variations in the gate voltages VG1 and VG2 of the switching element NTOUT caused by noise or the like.

[0080] 1.2 Operation

[0081] Use Figure 4 The operation of the semiconductor device 1 of the embodiment will be described. Figure 4 is a timing chart showing an example of the driving operation of the semiconductor device 1 of the embodiment. The driving operation is the operation of the semiconductor device 1 from the command to drive the switch 2 received by the control circuit 10 until the command to stop the driving of the switch 2 is received by the control circuit 10. In Figure 4 it shows the case where a gate short circuit of the switching element NTOUT1 occurs during the driving operation.

[0082] In addition, in the following description, when distinguishing between the signals S3, S4, and S5 of the drive circuit 13-1 and the signals S3, S4, and S5 of the drive circuit 13-2, they are respectively referred to as signals S3_1, S4_1, and S5_1 and signals S3_2, S4_2, and S5_2.

[0083] In addition, in the following description, the case where the threshold voltage VNT1 of the switching element NT1, the threshold voltages of the switching elements NTOUT1 and NTOUT2 are the same is shown as an example. The threshold voltage VNT1 is a voltage higher than the ground voltage VSS. However, it is not limited thereto, and the threshold voltage VNT1 may be higher than the threshold voltage of the switching element NTOUT or may be smaller than the threshold voltage of the switching element NTOUT.

[0084] In addition, in the following description, the case where the boost circuit 12 boosts the voltage VIN to the voltage V1 and outputs it is shown. The voltage V1 is the same as the maximum value of the voltage VCP of the boost circuit 12 and is a voltage higher than the threshold voltage VNT1 of the switching element NT1.

[0085] At time T1, the control circuit 10 receives a command to drive the switch 2. Thus, the driving operation of the semiconductor device 1 starts ( Figure 4 in which the driving operation starts). Based on the received command, the control circuit 10 changes the signal S1 from the "L" level to the "H" level. Further, based on the change in the signal S1, the pulse generation circuit 130 of the driving circuit 13 changes the signal S2 from the "L" level to the "H" level.

[0086] At time T1, the voltage VG1 is lower than the threshold voltage VNT1. Therefore, based on the monitored voltage VG1, the voltage monitoring circuit 14 sets the signal S3 to the "L" level. The OR circuit 131 outputs a signal S4 of the "H" level based on the signal S2 of the "H" level and the signal S3 of the "L" level. The AND circuit 132 outputs a signal S5 of the "H" level based on the signal S1 of the "H" level and the signal S40 of the "H" level.

[0087] The oscillator 11 generates a clock signal based on the signal S1 of the "H" level. Based on the generated clock signal, the booster circuit 12 boosts the voltage VIN to the voltage V1, and the boosted voltage V1 is transmitted to the second input terminal of the output circuit 133 of the driving circuit 13. The output circuit 133 of the driving circuit 13 starts charging the gate of the switching element NTOUT based on the signal S5 of the "H" level ( Figure 4 in which charging starts). Further, before the charging of the gate of the switching element NTOUT is completed, the voltage VCP of the booster circuit 12 is lower than the voltage V1. Further, a current IG1 for charging the gate of the switching element NTOUT1 flows to the output terminal of the output circuit 133 of the driving circuit 13-1. A current IG2 for charging the gate of the switching element NTOUT2 flows to the output terminal of the output circuit 133 of the driving circuit 13-2.

[0088] At time T2, the gate of the switching element NTOUT is charged to the threshold voltage VNT1. Thus, based on the voltage VG, the voltage monitoring circuit 13 changes the signal S3 from the "L" level to the "H" level.

[0089] Further, the switching elements NTOUT1 and NTOUT2 change from the off state to the on state.

[0090] At time T3, the voltages VG1, VG2, and VCP become the voltage V1, and the charging of the gates of the switching elements NTOUT1 and NTOUT2 is completed ( Figure 4 in which the charging is completed). Thus, almost no current IG1 and IG2 flow.

[0091] At time T4, after the first period has elapsed since time T1, the pulse generation circuit 130 of the drive circuit 13 causes the signal S2 to change from the "H" level to the "L" level.

[0092] At time T5, a gate short circuit of the switching element NTOUT1 occurs. Due to the occurrence of the short circuit, a current IG1 flows to the output terminal of the output circuit 133 of the drive circuit 13-1, and a decrease in the voltage VG1 occurs. In addition, as the voltage VG1 decreases, the voltage VCP of the boost circuit 12 and the voltage VG2 also decrease. Furthermore, the ratio of the voltage drop of the voltage VG2 with respect to time is smaller than the ratio of the voltage drop of the voltage VG1 with respect to time.

[0093] At time T6, due to the gate short circuit of the switching element NTOUT1, the voltage VG1 of the gate of the switching element NTOUT1 becomes smaller than the threshold voltage VNT1 of the switching element NT1. Accordingly, the voltage monitoring circuit 13-1 causes the signal S3_1 to change from the "H" level to the "L" level based on the voltage VG1. The OR circuit 131 outputs a signal S4_1 of the "L" level based on the signal S3_1 of the "L" level and the signal S2 of the "L" level. The AND circuit 132 outputs a signal S5_1 of the "L" level based on the signal S1 of the "H" level and the signal S4_1 of the "L" level. Accordingly, the output circuit 133 of the drive circuit 13-1 sets the voltage VG1 of the gate of the switching element NTOUT1 to the ground voltage VSS. Therefore, the supply of the current IG1 stops. Since the current IG1 no longer flows, the voltage VCP of the boost circuit 12 and the voltage VG2 of the gate of the switching element NTOUT2 become the voltage V1 again.

[0094] In addition, the switching element NTOUT1 changes from the on state to the off state. The switching element NTOUT2 maintains the on state.

[0095] At time T7, the control circuit 10 receives a command to stop driving the stop switch 2, and based on the received command, causes the signal S1 to change from the "H" level to the "L" level. Accordingly, the signals S3_2, S4_2, and S5_2 change from the "H" level to the "L" level, and the boosting of the voltage VIN by the boost circuit 12 stops. In addition, the voltages VG2 and VCP become the ground voltage VSS, and the switching element NTOUT2, together with the switching element NTOUT1, becomes the off state. In this way, the driving operation of the semiconductor device 1 ends ( Figure 4 in, the driving operation ends).

[0096] 1.3 Effects of this Embodiment

[0097] According to the embodiment, an increase in current due to a short circuit can be suppressed. Hereinafter, the effects of the embodiment will be described.

[0098] When using an N-channel MOSFET, i.e., an external switching element, on the low-voltage side, a load such as an LED or a solenoid driven by an external power source or the like is connected to the first terminal of the external switching element. The second terminal of the external switching element is grounded, for example. A semiconductor device for driving the external switching element is connected to the gate of the external switching element. The semiconductor device drives the external switching element by inputting a voltage to the gate of the external switching element, whereby the current flowing through the load flows from the first terminal of the external switching element to the second terminal of the external switching element. When driving the external switching element, the semiconductor device outputs a voltage of, for example, 10 V or more and less than 20 V to the gate of the external switching element.

[0099] On the other hand, when an N-channel MOSFET, i.e., an external switching element, is used on the high-voltage side, an external power supply such as a portable electronic device is connected to the first terminal of the external switching element via a USB terminal or the like. The second terminal of the external switching element is connected to, for example, a power supply IC, a battery, etc. that are different from the external power supply connected to the first terminal of the external switching element. A semiconductor device for driving the external switching element is connected to the gate of the external switching element. The external power supply is driven at, for example, 40V to 50V, and a voltage of, for example, 40V is input to the first terminal of the external switching element. Generally, the on-resistance value of the external switching element is, for example, 10 mΩ. When the load current flowing from the external power supply to the first terminal of the external switching element is, for example, 10A, the potential difference between the first terminal and the second terminal of the external switching element is 100 mV, which is sufficiently lower than the voltage input to the first terminal of the external switching element. Thus, the voltage at the second terminal of the external switching element is approximately the same as the voltage at the first terminal of the external switching element (e.g., (40 - 0.1)V). Therefore, when driving the external switching element, the semiconductor device inputs a voltage equal to or higher than the voltage obtained by adding the voltage at the second terminal of the external switching element and the threshold voltage Vth of the external switching element (e.g., a voltage equal to or higher than (40 + Vth)V) to the gate of the external switching element. That is, the voltage input to the gate of the external switching element when the external switching element is used on the high-voltage side is sufficiently larger than the voltage input to the gate of the external switching element when the external switching element is used on the low-voltage side. Therefore, the current flowing from the semiconductor device to the gate of the external switching element due to a gate short circuit or the like of the external switching element when the external switching element is used on the high-voltage side is sufficiently larger than the current flowing from the semiconductor device to the gate of the external switching element due to a gate short circuit or the like of the external switching element when the external switching element is used on the low-voltage side. Thus, when the external switching element is used on the high-voltage side, it is preferable to suppress an increase in the current flowing from the semiconductor device to the gate of the external switching element due to a gate short circuit or the like of the external switching element.

[0100] According to an embodiment, the boost circuit 12 boosts the voltage VIN to the voltage VCP and outputs it to the drive circuit 13-1. The drive circuit 13-1 transmits the voltage VCP to the gate of the external switching element NTOUT1 via the terminal POUT1. Thereby, the drive circuit 13-1 charges the gate of the switching element NTOUT1 and drives the switching element NTOUT1. The voltage monitoring circuit 14-1 monitors the voltage VG1 of the gate of the switching element NTOUT1 charged by the drive circuit 13-1. The voltage monitoring circuit 14-1 generates a signal S3, which becomes the "H" level when the voltage VG1 is equal to or higher than the threshold voltage VNT1 of the switching element NTOUT1 in the voltage monitoring circuit 14-1, and becomes the "L" level when the voltage VG1 is less than the threshold voltage VNT1. Based on the "L" level signal S3, the drive circuit 13-1 stops transmitting the voltage VCP to the gate of the switching element NTOUT1. Thus, in the semiconductor device 1, when the voltage VG1 of the gate of the switching element NTOUT1 becomes less than the threshold voltage VNT1 of the switching element NTOUT1 due to a short circuit of the gate of the switching element NTOUT1, the voltage VCP can be stopped from being transmitted to the gate of the short-circuited switching element NTOUT1 based on the "L" level signal S3. Therefore, an increase in the current flowing through the gate of the short-circuited switching element NTOUT1 can be suppressed. Thus, even when an external switching element is used on the high voltage side, an increase in current due to a short circuit of the gate of the switching element NTOUT can be suppressed. In addition, even when the semiconductor device 1 of the embodiment has one drive circuit 13 and one voltage monitoring circuit 14 respectively, the same effect can be achieved.

[0101] In addition, according to an embodiment, the boost circuit 12 outputs the voltage VCP to the drive circuit 13-2 together with the drive circuit 13-1. The drive circuit 13-2 transmits the voltage VCP to the gate of the external switching element NTOUT2 via the terminal POUT2. Thereby, the drive circuit 13-2 charges the gate of the switching element NTOUT2 and drives the switching element NTOUT2. That is, the semiconductor device 1 drives the two switching elements NTOUT1 and NTOUT2 in the external switch 2 in parallel. Thus, for example, when a short circuit occurs in the gate of the switching element NTOUT1, by stopping the transmission of the voltage VCP to the gate of the switching element NTOUT1, a significant decrease in the voltage VCP of the boost circuit 12 can be suppressed, and a significant decrease in the voltage VG2 of the gate of the non-shorted switching element NTOUT2 can also be suppressed. Therefore, the semiconductor device 1 can stop driving the switching element NTOUT1 while maintaining the driving of the switching element NTOUT2. Thus, it is possible to suppress the switching element NTOUT that has not short-circuited in the switch 2 from becoming an off state due to a short circuit of the switching element NTOUT in the switch 2.

[0102] 2. Variation

[0103] In addition, the above-described embodiments can be variously modified.

[0104] Hereinafter, a semiconductor device according to a variation will be described. Hereinafter, regarding the configuration and operation of the semiconductor device 1 according to the variation, the description will focus on the differences from the semiconductor device of the embodiment. The semiconductor device according to the variation can also achieve the same effects as the embodiment.

[0105] 2.1 First Variation

[0106] In the above-described embodiment, an example is shown in which the voltage VG of the gate of the switching element NTOUT is directly input to the gate of the switching element NT1 of the voltage monitoring circuit 14, but it is not limited thereto. For example, a voltage obtained by reducing the voltage VG of the gate of the switching element NTOUT may be input to the gate of the switching element NT1 of the voltage monitoring circuit 14.

[0107] Use Figure 5 The semiconductor device 1 according to the first variation will be described. Figure 5 FIG. is a circuit diagram showing an example of the configuration of the voltage monitoring circuit 14-1 of the semiconductor device 1 according to the first variation. In addition, in Figure 5 FIG., the configuration of the voltage monitoring circuit 14-1 is shown as an example. In the following description, the configuration of the voltage monitoring circuit 14-1 will be mainly described. Regarding the configuration of the voltage monitoring circuit 14-2, the description of the same configuration as that of the voltage monitoring circuit 14-1 will be omitted, and mainly the configuration different from that of the voltage monitoring circuit 14-1 will be described.

[0108] In addition, the configuration of the semiconductor device 1 according to the first variation other than the voltage monitoring circuit 14 is the same as that of the embodiment, and thus the description thereof is omitted.

[0109] The voltage monitoring circuit 14 according to the first variation includes a level shifter circuit 140.

[0110] The level shifter circuit 140 is a circuit for reducing the voltage VG of the gate of the switching element NTOUT.

[0111] The level shifter circuit 140 includes a switching element NT9 and a resistor R4. The switching element NT9 is an N-channel MOSFET having a high breakdown voltage such that the potential difference between the first end and the second end of the switching element NT9 can be equal to or higher than the voltage V1 of the boost circuit 12.

[0112] The first terminal of the switching element NT9 is connected to the output terminal of the output circuit 133 of the drive circuit 13-1. Additionally, although not shown, in the voltage monitoring circuit 14-2, the first terminal of the switching element NT9 is connected to the output terminal of the output circuit 133 of the drive circuit 13-2. The second terminal of the switching element NT9 is connected to the gate of the switching element NT1. A reference voltage VREF1 is input to the gate of the switching element NT9. The reference voltage VREF1 is a voltage such that the differential voltage (VREF1 - VNT9) between the reference voltage VREF1 and the threshold voltage VNT9 of the switching element NT9 is equal to or greater than the threshold voltage VNT1 of the switching element NT1 and less than the voltage V1 of the boost circuit 12. For example, the reference voltage VREF1 is supplied from a voltage source inside the semiconductor device 1 different from the voltage VBIAS. However, it is not limited thereto, and the reference voltage VREF1 may be supplied from a voltage source inside the semiconductor device 1 that is the same as the voltage VBIAS, or may be a voltage VIN supplied from outside the semiconductor device 1.

[0113] The first terminal of the resistor R4 is connected to the gate of the switching element NT1 and the second terminal of the switching element NT9. The second terminal of the resistor R4 is grounded.

[0114] The configuration of the voltage monitoring circuit 14 of the first modification example, except for the level shifter circuit 140, is the same as the configuration of the voltage monitoring circuit 14 of the embodiment.

[0115] The operation of the semiconductor device 1 of the first modification example will be described. The operation of the first modification example is substantially the same as that of the embodiment, except for the voltage input to the gate of the switching element NT1. Hereinafter, mainly the voltage input to the gate of the switching element NT1 will be described, and the description of the rest will be omitted.

[0116] At time T2, the switching element NT9 becomes in the on state, and the voltage at the second terminal of the switching element NT9 is input to the gate of the switching element NT1. The voltage at the second terminal of the switching element NT9 is the above differential voltage (VREF1 - VNT9). As a result, the switching element NT1 becomes in the on state, and the signal S3 changes from the "L" level to the "H" level.

[0117] In addition, at time T6, the voltage VG1 at the gate of the switching element NTOUT1 decreases, and the switching element NT9 becomes in the off state. As a result, the switching element NT1 becomes in the off state, and the signal S3 changes from the "H" level to the "L" level.

[0118] According to the first modification example, a voltage equal to or lower than the differential voltage (VREF1 - VNT9) is input to the gate of the switching element NT1. Thereby, even when the voltage VG at the gate of the switched element NTOUT after charging is higher than the voltage that can be input to the gate of the switching element NT1, degradation and breakdown of the switching element NT1 caused by directly inputting the voltage VG to the gate of the switching element NT1 can be suppressed.

[0119] 2.2 Second modification example

[0120] In the above-described embodiment, an example is shown in which when a short circuit occurs at the gate of the switching element NTOUT, the voltage transmission to the gate of the short-circuited switching element NTOUT is stopped, but it is not limited thereto. For example, the voltage monitoring circuit 14 may be configured such that after stopping the voltage transmission to the gate of the short-circuited switching element NTOUT, when the short circuit at the gate of the switching element NTOUT is eliminated, the voltage transmission VCP to the gate of this switching element is restarted by the automatic recovery circuit.

[0121] Use Figure 6 The configuration of the semiconductor device 1 according to the second modification example will be described. Figure 6 FIG. is a circuit diagram showing an example of the configuration of the voltage monitoring circuit 14-1 of the semiconductor device 1 for explaining the second modification example. In the following description, the configuration of the voltage monitoring circuit 14-1 will be mainly described. For the configuration of the voltage monitoring circuit 14-2, the description of the same configuration as that of the voltage monitoring circuit 14-1 will be omitted, and mainly the configuration different from that of the voltage monitoring circuit 14-1 will be described. In addition, the configuration of the semiconductor device 1 according to the second modification example other than the voltage monitoring circuit 14 is the same as that of the embodiment, and thus the description thereof is omitted.

[0122] The voltage monitoring circuit 14 according to the second modification example includes an automatic recovery circuit 141.

[0123] The automatic recovery circuit 141 is a circuit for automatically making the gate voltage of the switching element NTOUT that has become the ground voltage VSS a voltage equal to or higher than the threshold voltage of the switching element NT1 when the short circuit is eliminated.

[0124] The automatic recovery circuit 141 includes a switching element NT10, a diode D, and a resistor R5. The switching element NT10 is an N-channel MOSFET.

[0125] A voltage VBIAS is input to the first terminal of the switching element NT10. A signal S1 of the control circuit 10 is input to the gate of the switching element NT10. The second terminal of the switching element NT10 is connected to the gate of the switching element NT1 and the output terminal of the output circuit 133 of the drive circuit 13-1 via a serially connected diode D and resistor R5. The diode D is forward-connected between the switching element NT10 and the resistor R5. That is, the anode of the diode D is connected to the second terminal of the switching element NT10, and the cathode of the diode D is connected to the first terminal of the resistor R5. The second terminal of the resistor R5 is connected to the gate of the switching element NT1 and the output terminal of the output circuit 133 of the drive circuit 13-1. In addition, with respect to the resistance value Rv2 of the resistor R2 and the resistance value Rv5 of the resistor R5 of the output circuit 133, the on-resistance value of the switching element NT10 is small enough to be negligible. Further, in the second modification, the voltage VBIAS, the forward voltage Vf of the diode D, and the resistors R2 and R5 are configured such that a voltage VRT1 described later satisfies a first condition described later.

[0126] Although not shown, in the voltage monitoring circuit 14-2, the second terminal of the resistor R5 is connected to the gate of the switching element NT1 and the output terminal of the output circuit 133 of the drive circuit 13-2.

[0127] The configuration of the voltage monitoring circuit 14 of the second modification except for the automatic recovery circuit 141 is the same as the configuration of the voltage monitoring circuit 14 of the embodiment.

[0128] Use Figure 7 The operation of the semiconductor device 1 of the second modification will be described. Figure 7 It is a timing chart showing an example of the driving operation of the semiconductor device 1 of the second modification.

[0129] In the following description, the operation after the voltage VG1 is reduced to the ground voltage VSS at a time between the time T6 and the time T7 in the embodiment will be described. The operation until the voltage VG1 is reduced to the ground voltage VSS is substantially the same as that in the embodiment, and thus the description thereof is omitted.

[0130] At time T21, the gate short circuit of the switching element NTOUT1 is eliminated ( Figure 7In this case, a short circuit is eliminated). At this time, the gate of the switching element NTOUT1 is grounded via the resistor R2 of the transmission control circuit SWTC included in the output circuit 133 of the drive circuit 13-1, and is supplied with the voltage VBIAS via the diode D and the resistor R5 of the automatic recovery circuit 141. Thus, the voltage VG1 of the gate of the switching element NTOUT1 becomes the voltage VRT1 represented by the following formula (1). In addition, the voltage VRT1 is a voltage equal to or higher than the threshold voltage VNT1 of the switching element NT1 (first condition). Thus, the switching element NTOUT1 becomes an on state.

[0131] VRT1 = Rv2×(VBIAS - Vf) / (Rv2 + Rv5)) (1)

[0132] In addition, based on the voltage VRT1 input to the gate of the switching element NT1, the signal S3_1 changes from the "L" level to the "H" level through the voltage monitoring circuit 14-1. Based on the signal S2 of the "L" level and the signal S3_1 of the "H" level, the signal S4_1 changes from the "L" level to the "H" level through the OR circuit 131. Based on the signal S1 of the "H" level and the signal S4_1 of the "H" level, the signal S5_1 changes from the "L" level to the "H" level through the AND circuit 132.

[0133] In addition, based on the signal S5 of the "H" level, the charging of the gate of the switching element NTOUT1 is started through the output circuit 133 of the drive circuit 13-1. Through the charging of the gate of the switching element NTOUT1, the voltage VCP and VG2 of the boost circuit 12 become smaller than the voltage V1. Thus, the gate of the switching element NTOUT2 is also charged. However, the voltage VG2 is maintained at a voltage higher than the threshold voltage VNT1 of the switching element NTOUT. That is, the switching element NTOUT2 is maintained in an on state. In addition, during the charging of the gates of the switching elements NTOUT1 and NTOUT2, currents IG1 and IG2 flow through the gates of the switching elements NTOUT1 and NTOUT2, respectively. The current IG1 is a current greater than the current IG2.

[0134] At time T22, the charging of the gates of the switching element NTOUT1 and the switching element NTOUT2 ends, and the voltages VG1, VG2, and VCP become the voltage V1.

[0135] At time T23, through the same operation as the operation at time T7 of the embodiment, the signals S1, S3, S4, and S5 change from the "H" level to the "L" level, and the boosting of the voltage VIN by the boost circuit 12 stops. In addition, the voltages VG1, VG2, and VCP become the ground voltage VSS, and the switching element NTOUT becomes an off state. Thus, the driving operation of the semiconductor device 1 ends (Figure 7 in which the driving operation ends).

[0136] According to the above configuration, when the gate short circuit of the switching element NTOUT that has occurred and is in the off state is eliminated, in order to make the switching element NTOUT conductive again, it is not necessary to stop the operation of the semiconductor device 1 and drive it again. Thus, an increase in current caused by recharging the gates of all the switching elements NTOUT can be suppressed.

[0137] In addition, in Figure 6 the example shown, as an example, the case where the voltage monitoring circuit 14 does not include the level shifter circuit 140 is shown, but it is not limited thereto. The voltage monitoring circuit 14 may also include the level shifter circuit 140. In this case, the second end of the resistor R5 of the automatic recovery circuit 141 is connected to the first end of the switching element NT9 in the first modification and the output end of the output circuit 133 of the drive circuit 13. According to such a configuration, the same effect as that of the first modification can be achieved.

[0138] 2.3 Third Modification

[0139] In the above second modification, the case where the automatic recovery circuit 141 includes an N-channel MOSFET is shown, but it is not limited thereto. The automatic recovery circuit 141 may include a P-channel MOSFET and an inverter circuit instead of the N-channel MOSFET.

[0140] Use Figure 8 to describe the semiconductor device 1 of the third modification. Figure 8 is a circuit diagram showing an example of the configuration of the voltage monitoring circuit 14-1 of the semiconductor device 1 for explaining the third modification.

[0141] In addition, the configuration of the semiconductor device 1 of the third modification other than the automatic recovery circuit 141 is the same as that of the second modification, so its description is omitted. Furthermore, the operation of the semiconductor device 1 of the third modification is substantially the same as that of the second modification, so its description is omitted.

[0142] The automatic recovery circuit 141 of the third modification includes an inverter circuit INVC2, a switching element PT5, a diode D, and a resistor R5. The switching element PT5 is a P-channel MOSFET.

[0143] The inverter circuit INVC2 includes an input terminal and an output terminal. A signal S1 of the control circuit 10 is input to the input terminal of the inverter circuit INVC2. The inverter circuit INVC2 generates a signal / S1 that inverts the voltage level (“H” level or “L” level) of the signal S1. More specifically, the inverter circuit INVC2 sets the signal S1 to the “L” level when the signal S1 is at the “H” level, and sets the signal S1 to the “H” level when the signal S1 is at the “L” level. The generated signal / S1 is output from the output terminal of the inverter circuit INVC2.

[0144] A voltage VBIAS is input to the first terminal of the switching element PT5. The gate of the switching element PT5 is connected to the output terminal of the inverter circuit INVC2. Similar to the second terminal of the switching element NT10 in the second modification example, the second terminal of the switching element PT5 is connected to the gate of the switching element NT1.

[0145] With such a configuration, the same effect as that of the second modification example can also be achieved.

[0146] In addition, in Figure 8 the example shown, it is shown as an example that the voltage monitoring circuit 14 does not include the level shift circuit 140, but it is not limited thereto. The voltage monitoring circuit 14 of the third modification example may also include the level shift circuit 140. In this case, the second terminal of the resistor R5 of the automatic recovery circuit 141 is connected to the first terminal of the switching element NT9 in the first modification example and the output terminal of the output circuit 133 of the driving circuit 13. With such a configuration, the same effect as that of the first modification example can be achieved.

[0147] 2.4 Fourth Modification Example

[0148] In the above second and third modification examples, it is shown as an example that when the short - circuit elimination of the gate of the switching element NTOUT is achieved, the gate voltage of the switching element NTOUT becomes a voltage VRT1 represented by the resistance values Rv2 and Rv5, the voltage VBIAS, and the forward voltage Vf of the diode D, but it is not limited thereto. It may also be that when the short - circuit elimination of the gate of the switching element NTOUT is achieved, the gate voltage of the switching element NTOUT becomes a voltage represented by the voltage VBIAS and the forward voltage Vf.

[0149] Use Figure 9 to describe the semiconductor device 1 of the fourth modification example. Figure 9 It is a circuit diagram showing an example of the configuration of the output circuit 133 of the semiconductor device 1 for explaining the fourth modification example. In addition, the configurations of the semiconductor device 1 of the fourth modification example other than the output circuit 133 can be the same as those of the second and third modification examples, so the description thereof is omitted.

[0150] In the fourth modification example, the signal S1 of the control circuit 10 is input to the input terminal of the inverter circuit INVC1 included in the transmission control circuit SWTC.

[0151] The other components included in the output circuit 133 are the same as those in the embodiment, the first modification example, the second modification example, and the third modification example.

[0152] In addition, in the fourth modification example, the voltage VBIAS and the forward voltage Vf of the diode D are configured such that the voltage VRT2 described later satisfies the second condition described later.

[0153] The operation of the fourth modification example will be described. In addition, the operation of the fourth modification example is substantially the same as that of the second modification example and the third modification example except for the value of the voltage VG at the time T21 of the second modification example. Hereinafter, the voltage VG at the time T21 will be mainly described, and other descriptions will be omitted.

[0154] At time T21, when the gate short - circuit of the switching element NTOUT1 is eliminated, in the automatic recovery circuit 141 of the voltage monitoring circuit 14 - 1, the voltage VBIAS is supplied to the gate of the switching element NTOUT1 via the diode D. As a result, the voltage VG1 at the gate of the switching element NTOUT1 becomes the voltage VRT2 represented by the following formula (2). In addition, the voltage VRT2 is a voltage equal to or higher than the threshold voltage VNT1 of the switching element NT1 (second condition). As a result, the switching element NTOUT1 becomes an on - state.

[0155] VRT2 = VBIAS - Vf (2)

[0156] In addition, similar to the second modification example and the third modification example, the voltage VG2 is maintained, for example, at a voltage higher than the threshold voltage of the switching element NTOUT2, and the switching element NTOUT2 is maintained in an on - state.

[0157] With such a configuration, the same effects as those of the second modification example and the third modification example can also be achieved.

[0158] 2.5 The Fifth Modification Example

[0159] In the above - described embodiment, an example of the voltage monitoring circuit 14 that monitors the voltage VG and outputs the signal S3 based on the monitored voltage VG is shown, but the configuration of the voltage monitoring circuit 14 is not limited thereto. The voltage monitoring circuit 14 may include the following configuration.

[0160] Use Figure 10 The semiconductor device 1 of the fifth modification example will be described. Figure 10 It is a circuit diagram showing an example of the configuration of the voltage monitoring circuit 14 of the semiconductor device 1 for explaining the fifth modification example. In addition, inFigure 10 The configuration of the voltage monitoring circuit 14-1 is shown. In the following description, the configuration of the voltage monitoring circuit 14-1 will be described. Regarding the configuration of the voltage monitoring circuit 14-2, the description of the same configuration as that of the voltage monitoring circuit 14-1 will be omitted, and mainly the configuration different from that of the voltage monitoring circuit 14-1 will be described.

[0161] The voltage monitoring circuit 14 of the fifth modification includes a comparison circuit CMPC and a non-inverting circuit NINVC.

[0162] The comparison circuit CMPC generates a signal based on the comparison result between the voltage VG of the gate of the switching element NTOUT and a reference voltage described later. The non-inverting circuit NINVC generates a non-inverted signal of the signal generated by the comparison circuit CMPC, and outputs the generated non-inverted signal to the second input terminal of the OR circuit 131 of the drive circuit 13.

[0163] The comparison circuit CMPC includes a constant current source I2, a current mirror CM3, and a current mirror CM4.

[0164] The constant current source I2 is connected to the node N5. For example, the voltage VBIAS is input to the constant current source I2. The constant current source I2 outputs a current based on the input voltage VBIAS to the node N5.

[0165] The current mirror CM3 includes switching elements NT11, NT12, and NT13. The switching elements NT11, NT12, and NT13 are N-channel MOSFETs. The ratio W / L of the channel width W to the channel length L of each of the switching elements NT11, NT12, and NT13 is, for example, the same.

[0166] The first terminal of the switching element NT11 is connected to the node N5 together with the gate of the switching element NT11. The second terminal of the switching element NT11 is grounded.

[0167] The first terminal of the switching element NT12 is connected to the node N6. The second terminal of the switching element NT12 is grounded. The gate of the switching element NT12 is connected to the node N5 together with the first terminal of the switching element NT11 and the gate of the switching element NT11.

[0168] The first terminal of the switching element NT13 is connected to the node N7. The second terminal of the switching element NT13 is grounded. The gate of the switching element NT13 is connected to the node N5 together with the first terminal of the switching element NT11, the gate of the switching element NT11, and the gate of the switching element NT12.

[0169] With the configuration of the current mirror CM3 as described above, based on the current of the constant current source I2 flowing through the switching element NT11, currents flowing through the switching elements NT12 and NT13 are generated. As described above, the aspect ratios W / L of the switching elements NT11, NT12, and NT13 are the same, so the currents flowing through the switching elements NT11, NT12, and NT13 are the same respectively.

[0170] The current mirror CM4 includes switching elements PT6 and PT7. The switching elements PT6 and PT7 are P-channel MOSFETs. The ratio of the channel width W to the channel length L (W / L) of the switching elements PT6 and PT7 is the same, for example.

[0171] The first terminal of the switching element PT6 is connected to the gate of the switching element NTOUT1. Additionally, although not shown, in the voltage monitoring circuit 14-2, the first terminal of the switching element PT6 is connected to the gate of the switching element NTOUT2. The second terminal of the switching element PT6 is connected to the node N6. The gate of the switching element PT6 is connected to the node N7.

[0172] The reference voltage VREF2 is input to the first terminal of the switching element PT7. The reference voltage VREF2 is a voltage lower than the voltage V1 of the boost circuit 12. For example, the reference voltage VREF2 is supplied from a voltage source inside the semiconductor device 1 different from the voltage VBIAS and the reference voltage VREF1. However, it is not limited thereto, and the reference voltage VREF2 can be supplied from the same voltage source as the voltage VBIAS, or can be supplied from the same voltage source as the reference voltage VREF1. In addition, the reference voltage VREF2 can also be the voltage VIN. The second terminal of the switching element PT7 and the gate of the switching element PT7 are both connected to the node N7.

[0173] With the configuration of the current mirror CM4 as described above, based on the current flowing through the switching element PT7, a current flowing through the switching element PT6 is generated. As described above, the aspect ratios W / L of the switching elements PT6 and PT7 are the same, so when the voltage VG at the gate of the switching element NTOUT is higher than the reference voltage VREF2, the magnitude of the current flowing through the switching element PT6 becomes greater than the magnitude of the current flowing through the switching element PT7. When the voltage VG is equal to or lower than the reference voltage VREF2, the magnitude of the current flowing through the switching element PT6 becomes equal to or less than the magnitude of the current flowing through the switching element PT7.

[0174] With the configuration of the comparison circuit CMPC as described above, when the voltage VG is higher than the reference voltage VREF2, the voltage of node N6 (hereinafter also referred to as the signal of the comparison circuit CMPC) becomes the "H" level. When the voltage VG is less than the reference voltage VREF2, the signal of the comparison circuit CMPC becomes the "L" level (the voltage of node N6 becomes the ground voltage VSS).

[0175] The non-inverting circuit NINVC includes switching elements NT14, NT15, PT8, and PT9. The switching elements NT14 and NT15 are N-channel MOSFETs. The switching elements PT8 and PT9 are P-channel MOSFETs.

[0176] The reference voltage VREF2 is input to the first terminal of the switching element PT8. The second terminal of the switching element PT8 is connected to node N8. The gate of the switching element PT8 is connected to node N6.

[0177] The first terminal of the switching element NT14 is connected to node N8. The second terminal of the switching element NT14 is grounded. The gate of the switching element NT14 is connected to node N6.

[0178] The reference voltage VREF2 is input to the first terminal of the switching element PT9. The second terminal of the switching element PT9 is connected to the second input terminal of the OR circuit 131 of the drive circuit 13-1 and outputs the signal S3. The gate of the switching element PT9 is connected to node N8.

[0179] The first terminal of the switching element NT15 is connected to the second input terminal of the OR circuit 131 of the drive circuit 13-1. The second terminal of the switching element NT15 is grounded. The gate of the switching element NT15 is connected to node N8.

[0180] With the configuration as described above, when the voltage VG of the switching element NTOUT is equal to or higher than the reference voltage VREF2, based on the signal of the comparison circuit CMPC which is at the "H" level, the signal S3 becomes the "H" level. When the voltage VG of the switching element NTOUT is less than the reference voltage VREF2, based on the signal of the comparison circuit CMPC which is at the "L" level, the signal S3 becomes the "L" level.

[0181] The operation of the fifth modification will be described. In addition, except for the values of the voltage VG at times T2 and T6 in the embodiment, the operation of the fifth modification is the same as that of the embodiment. Therefore, the values of the voltage VG at times T2 and T6 will be mainly described below, and other descriptions will be omitted.

[0182] At time T2, the voltage VG becomes equal to or higher than the reference voltage VREF2, and the signal S3 changes from the "L" level to the "H" level through the voltage monitoring circuit 14.

[0183] In addition, at time T6, the voltage VG1 becomes smaller than the reference voltage VREF2, and the signal S3 changes from the "H" level to the "L" level through the voltage monitoring circuit 14.

[0184] Other operations are the same as those in the embodiment, and thus the description thereof is omitted.

[0185] According to such a configuration, the same effects as those in the embodiment can also be achieved.

[0186] In addition, the voltage monitoring circuit 14 of the fifth modification example may include the automatic recovery circuit 141 of the second modification example or the automatic recovery circuit 141 of the third modification example. In this case, the second terminal of the resistor R5 of the automatic recovery circuit 141 is connected to the output terminal of the output circuit 133 of the drive circuit 13 and the first terminal of the switching element PT6. In addition, the voltage VRT1 is set to a voltage higher than the reference voltage VREF2.

[0187] In addition, the semiconductor device 1 of the fifth modification example may include the automatic recovery circuit 141 of the second modification example or the automatic recovery circuit 141 of the third modification example, and the output circuit 133 of the semiconductor device 1 of the fifth modification example has the same configuration as the output circuit 133 of the fourth modification example. In addition, in this case, the voltage VRT2 is set to a voltage higher than the reference voltage VREF2.

[0188] In addition, in the fifth modification example, an example of the voltage monitoring circuit 14 having the comparison circuit CMPC is shown, but the configuration of the voltage monitoring circuit 14 is not limited thereto. The voltage monitoring circuit 14 may include, for example, a known comparison circuit. In this case, the comparison circuit compares the voltage based on the output terminal voltage of the output circuit 133 with a reference voltage, and the voltage monitoring circuit 14 generates the signal S3 based on the comparison result. More specifically, in Figure 10 the voltage monitoring circuit 14-1, a known comparison circuit may be included instead of the comparison circuit CMPC, and the signal based on the comparison result of the comparison circuit is input to the gate of the switching element PT8 and the gate of the switching element NT14.

[0189] 3. Others

[0190] Several embodiments of the present invention have been described, but these embodiments are presented as examples and are not intended to limit the scope of the invention. These embodiments can be implemented in various other ways, and various omissions, substitutions, and changes can be made without departing from the gist of the invention. These embodiments and their modifications are included in the scope and gist of the invention, and are included in the invention described in the claims and the equivalent scope thereof.

Claims

1. A semiconductor device, comprising: A first circuit configured to generate a first voltage; A second circuit configured to transmit the generated first voltage to a first terminal; and A third circuit configured to generate a first signal, which becomes a first level when the voltage of the first terminal is equal to or higher than a threshold voltage, and becomes a second level when the voltage of the first terminal is less than the threshold voltage. The second circuit is configured to stop the transmission of the first voltage based on the first signal at the second level. The third circuit comprises: A first switching element including a first terminal to which a second voltage is input, a second terminal grounded, and a gate to which a voltage based on the voltage of the first terminal is input; A second switching element including a first terminal connected to the first terminal of the first switching element, a second terminal connected to the second circuit, and a gate connected to the first terminal of the first switching element; A third switching element including a first terminal connected to the second terminal of the second switching element, a second terminal grounded, and a gate connected to the first terminal of the first switching element; A fourth switching element including a first terminal connected to the first terminal, a second terminal connected to the gate of the first switching element, and a gate; and A first resistor including a first terminal connected to the gate of the first switching element and the second terminal of the fourth switching element, and a second terminal grounded. The third circuit outputs the first signal to the second circuit based on the voltages of the second terminal of the second switching element and the first terminal of the third switching element.

2. The semiconductor device according to claim 1, further comprising: A fourth circuit configured to transmit the generated first voltage to a second terminal; and A fifth circuit configured to generate a second signal, which becomes a third level when the voltage of the second terminal is equal to or higher than a threshold voltage, and becomes a fourth level when the voltage of the second terminal is less than the threshold voltage. The fourth circuit is configured to stop the transmission of the first voltage based on the second signal at the fourth level.

3. A semiconductor device, comprising: A first circuit configured to generate a first voltage; A second circuit configured to transmit the generated first voltage to a first terminal; and A third circuit configured to generate a first signal, which becomes a first level when the voltage of the first terminal is equal to or higher than a threshold voltage, and becomes a second level when the voltage of the first terminal is less than the threshold voltage. The second circuit is configured to stop the transmission of the first voltage based on the first signal at the second level. The third circuit comprises: A first switching element including a first terminal connected to a first current source, a second terminal grounded, and a gate connected to the first current source together with the first terminal; A second switching element including a first terminal connected to a first node, a second terminal grounded, and a gate connected to the first current source; A third switching element including a first terminal connected to a second node, a second terminal grounded, and a gate connected to the first current source; The fourth switching element includes a first terminal to which a voltage based on the voltage of the first terminal is input, a second terminal connected to the first node, and a gate connected to the second node; The fifth switching element includes a first terminal to which a second voltage is input, a second terminal connected to the second node, and a gate connected to the second node together with the second terminal; The sixth switching element includes a first terminal connected to the first terminal of the fifth switching element, a second terminal connected to the third node, and a gate connected to the first node; The seventh switching element includes a first terminal connected to the second terminal of the sixth switching element, a second terminal grounded, and a gate connected to the first node; The eighth switching element includes a first terminal connected to the first terminal of the fifth switching element and the first terminal of the sixth switching element, a second terminal connected to the second circuit, and a gate connected to the third node; and The ninth switching element includes a first terminal connected to the second terminal of the eighth switching element, a second terminal grounded, and a gate connected to the third node, The third circuit outputs the first signal to the second circuit based on the voltages of the second terminal of the eighth switching element and the first terminal of the ninth switching element.

4. A semiconductor device comprising: A first circuit configured to generate a first voltage; A second circuit configured to transmit the generated first voltage to a first terminal; and A third circuit configured to generate a first signal that becomes a first level when the voltage of the first terminal is equal to or higher than a threshold voltage and becomes a second level when the voltage of the first terminal is less than the threshold voltage, The second circuit is configured to stop the transmission of the first voltage based on the first signal at the second level. The third circuit includes: A first voltage source configured to be able to output a third voltage; and A second resistor connecting the first voltage source and the first terminal in series, A third signal that becomes a fifth level and a sixth level different from the fifth level is input to the first voltage source, The first voltage source outputs the third voltage to the second resistor based on the third signal at the fifth level.

5. The semiconductor device according to claim 4, wherein The first voltage source includes: A first element; and A fifth switching element including a first terminal to which the third voltage is input, a second terminal connected to the first element, and a gate to which the third signal is input, The first element connects the second resistor and the fifth switching element in series.

6. The semiconductor device according to claim 4, wherein The first voltage source includes: A first element; A sixth circuit including a first terminal to which the third signal is input and a second terminal that outputs a fourth signal based on the third signal; and A fifth switching element including a first terminal to which the third voltage is input, a second terminal connected to the first element, and a gate to which the fourth signal is input, The first element connects the second resistor and the fifth switching element in series.

7. The semiconductor device according to claim 4, wherein The second circuit is configured to ground the first terminal based on the third signal of the sixth level described above.

8. The semiconductor device according to claim 4, wherein the third circuit further includes an eleventh circuit configured to output the third signal according to a command transmitted from the outside.

9. A semiconductor device includes: a first circuit configured to generate a first voltage; a second circuit configured to transmit the generated first voltage to a first terminal; and a third circuit configured to generate a first signal that becomes a first level when the voltage of the first terminal is equal to or higher than a threshold voltage and becomes a second level when the voltage of the first terminal is less than the threshold voltage, the second circuit is configured to stop the transmission of the first voltage based on the first signal of the second level, the second circuit includes: a seventh circuit configured to generate a fifth signal based on the first signal; and an eighth circuit configured to stop transmitting the generated first voltage to the first terminal based on the fifth signal generated according to the first signal of the second level.

10. The semiconductor device according to claim 9, wherein the eighth circuit is configured to ground the first terminal based on the fifth signal generated according to the first signal of the second level.

11. The semiconductor device according to claim 9, wherein the eighth circuit includes: a ninth circuit configured to supply a first current to the first terminal; and a tenth circuit configured to supply a second current to the first terminal, the ninth circuit and the tenth circuit are each configured to stop supplying the first current and the second current based on the fifth signal generated according to the first signal of the second level.

12. The semiconductor device according to claim 11, wherein the ninth circuit includes a tenth switching element having an input terminal to which the first voltage is applied and an output terminal connected to the first terminal and outputting the first current, the tenth circuit includes an eleventh switching element having an input terminal to which the first voltage is applied and an output terminal connected to the first terminal and outputting the second current, the resistance value of the tenth switching element in the on state is greater than the resistance value of the eleventh switching element in the on state.

Images