Semiconductor device, solid-state imaging device, and electronic equipment

Abstract

The present invention provides a semiconductor device capable of suppressing degradation of capacitor performance caused by a bonding process. The semiconductor device includes a first substrate and a second substrate bonded to each other. A first electrode is provided in the first substrate, and one surface of the first electrode is located on the same plane as the bonding surface between the first and second substrates. A second electrode is provided in the second substrate, one surface of the second electrode is located on the same plane as the bonding surface, and the one surface of the second electrode is bonded to the one surface of the first electrode. The semiconductor device also includes at least one of a first capacitor and a second capacitor, the first capacitor being provided in the first substrate, and one electrode of the first capacitor being electrically connected to the non-exposed surface of the first electrode, and the second capacitor being provided in the second substrate, and one electrode of the second capacitor being electrically connected to the non-exposed surface of the second electrode.

Description

Technical Field

[0001] The present technology relates to a semiconductor device, a solid-state imaging device, and an electronic device. Background Art

[0002] Conventionally, a semiconductor device has been proposed that includes a first substrate and a second substrate bonded to the first substrate. In this semiconductor device, a first connection electrode formed on the first substrate and a second connection electrode formed on the second substrate are electrically connected at a bonding surface between the first and second substrates (see, for example, Patent Document 1). In the semiconductor device described in Patent Document 1, an insulating film is provided between the second connection electrode and a metal wiring provided within the second substrate, thereby forming a capacitor.

[0003] [Citation List]

[0004] [Patent Document]

[0005] [Patent Document 1]: Japanese Patent Application Laid-Open No. 2011-166171 Summary of the Invention

[0006] [Technical problems to be solved]

[0007] Incidentally, generally speaking, when the first and second substrates are bonded, warpage correction is performed on them, but this warpage correction applies stress to the capacitor. Furthermore, due to the difference in thermal expansion coefficients between the second connecting electrode and the insulating film, stress is also applied to the capacitor. In the semiconductor device described in Patent Document 1, because the capacitor is located close to the bonding surface and the contact area between the insulating film and the metal wiring forming the capacitor is large, the stress generated by the bonding process is directly applied to the capacitor. Consequently, cracks in the insulating film or changes in the polarization state of the insulating film may occur, and the performance of the capacitor may deteriorate.

[0008] An object of the present invention is to provide a semiconductor device, a solid-state imaging device, and an electronic device capable of suppressing degradation of capacitor performance due to a bonding process.

[0009] [Technical solutions to technical problems]

[0010] The semiconductor device of the present invention includes: (a) a first substrate; (b) a second substrate bonded to the first substrate; (c) a first electrode disposed in the first substrate, with one surface of the first electrode being on the same plane as the bonding surface between the first substrate and the second substrate; (d) a second electrode disposed in the second substrate, with one surface of the second electrode being on the same plane as the bonding surface, and the one surface of the second electrode being bonded to the one surface of the first electrode; and (e) at least one of a first capacitor and a second capacitor, the first capacitor being disposed in the first substrate, with one electrode of the first capacitor being electrically connected to the other surface of the first electrode, and the second capacitor being disposed in the second substrate, with one electrode of the second capacitor being electrically connected to the other surface of the second electrode.

[0011] The solid-state imaging device of the present invention includes: a sensor substrate in which a plurality of photoelectric conversion parts are arranged; a logic substrate bonded to the sensor substrate in which a circuit for processing electrical signals from the photoelectric conversion parts is integrated; a first electrode arranged in the sensor substrate, and one surface of the first electrode is located on the same surface as the bonding surface between the sensor substrate and the logic substrate; a second electrode arranged in the logic substrate, one surface of the second electrode is located on the same surface as the bonding surface, and the one surface of the second electrode is bonded to the one surface of the first electrode; and at least one of a first capacitor and a second capacitor, the first capacitor being arranged in the sensor substrate, and one electrode of the first capacitor being electrically connected to the other surface of the first electrode, and the second capacitor being arranged in the logic substrate, and one electrode of the second capacitor being electrically connected to the other surface of the second electrode.

[0012] An electronic device according to the present invention includes a solid-state imaging device, an optical lens, and a signal processing circuit. The solid-state imaging device includes: a sensor substrate having a plurality of photoelectric conversion units arranged therein; a logic substrate bonded to the sensor substrate, in which a circuit for processing electrical signals from the photoelectric conversion units is integrated; a first electrode provided within the sensor substrate, one surface of the first electrode being coplanar with the bonding surface between the sensor substrate and the logic substrate; a second electrode provided within the logic substrate, one surface of the second electrode being coplanar with the bonding surface and bonded to the one surface of the first electrode; and at least one of a first capacitor provided within the sensor substrate, one electrode of the first capacitor being electrically connected to the other surface of the first electrode, and a second capacitor provided within the logic substrate, one electrode of the second capacitor being electrically connected to the other surface of the second electrode. The optical lens forms an image of image light from a subject on an imaging surface of the solid-state imaging device. The signal processing circuit performs signal processing on a signal output from the solid-state imaging device. BRIEF DESCRIPTION OF THE DRAWINGS

[0013] Figure 1 is a cross-sectional view showing the overall structure of the semiconductor device according to the first embodiment.

[0014] Figure 2 is a cross-sectional view showing an enlarged first electrode.

[0015] Figure 3 is a cross-sectional view showing an enlarged first electrode.

[0016] Figure 4 is a cross-sectional view showing an enlarged second electrode.

[0017] Figure 5 is a cross-sectional view showing an enlarged second electrode.

[0018] Figure 6 is a cross-sectional view showing a first electrode and a second electrode bonded to each other.

[0019] Figure 7 is a cross-sectional view showing a first electrode and a second electrode bonded to each other.

[0020] Figure 8 is a cross-sectional view showing a first electrode and a second electrode bonded to each other.

[0021] Figure 9 is a cross-sectional view showing a first electrode and a second electrode bonded to each other.

[0022] Figure 10A is a cross-sectional view showing the first substrate before the substrate connection region is formed.

[0023] Figure 10B is a cross-sectional view showing the second substrate before the substrate connection region is formed.

[0024] Figure 11A is a cross-sectional view showing the first substrate after the substrate connection region is formed.

[0025] Figure 11B is a cross-sectional view showing the second substrate after the substrate connection region is formed.

[0026] Figure 12 is a cross-sectional view showing the first substrate and the second substrate after bonding.

[0027] Figure 13 is a cross-sectional view showing the first substrate and the second substrate after thinning.

[0028] Figure 14 is a plan view showing the overall structure of the sensor substrate.

[0029] Figure 15 is a cross-sectional view showing a second electrode according to a modification example.

[0030] Figure 16 is a cross-sectional view showing a second capacitor according to a modification example.

[0031] Figure 17 : is a cross-sectional view showing a substrate connection region according to a modification.

[0032] Figure 18A is a cross-sectional view showing a second capacitor according to a modification example.

[0033] Figure 18B When viewed from the joint surface side Figure 18A A plan view of the second substrate.

[0034] Figure 19 is a cross-sectional view showing a second capacitor according to a modification example.

[0035] Figure 20 is a block diagram showing one example of a schematic configuration of a solid-state imaging device.

[0036] Figure 21 is a cross-sectional view showing a cross section for one pixel of the solid-state imaging device.

[0037] Figure 22 is a block diagram showing one example of a schematic configuration of a solid-state imaging device.

[0038] Figure 23A is a cross-sectional view showing an enlarged first substrate.

[0039] Figure 23B is a cross-sectional view showing an enlarged second substrate.

[0040] Figure 24 is a circuit diagram showing a circuit configuration for one pixel of a solid-state imaging device.

[0041] Figure 25 : is a circuit diagram showing a circuit configuration for four pixels in two rows and two columns of a solid-state imaging device.

[0042] Figure 26 is a timing chart showing a driving method of the solid-state imaging device.

[0043] Figure 27 is a diagram showing one example of a schematic configuration of an electronic device.

[0044] Figure 28 is a block diagram showing one example of a schematic configuration of a vehicle control system.

[0045] Figure 29 1 is an explanatory diagram showing an example of the installation positions of the vehicle exterior information detection unit and the imaging unit.

[0046] Figure 30 is a diagram showing one example of a schematic configuration of an endoscopic surgery system.

[0047] Figure 31 : is a block diagram showing one example of the functional configuration of a camera head and a CCU (Camera Control Unit). DETAILED DESCRIPTION

[0048] In the following, reference will be made to Figures 1 to 31 Hereinafter, an example of a semiconductor device according to an embodiment of the present invention will be described. The embodiments of the present invention will be described in the following order. The present invention is not limited to the following examples. The effects described in this specification are exemplary and non-restrictive, and other effects may be provided.

[0049] 1. First embodiment: semiconductor device

[0050] 1-1 Structure of Semiconductor Devices

[0051] 1-2 Method for Manufacturing a Semiconductor Device

[0052] 1-3 Variations

[0053] 2. Application Examples of Solid-State Imaging Devices

[0054] 2-1 Structure of Solid-State Imaging Device

[0055] 2-2 Sensor substrate structure

[0056] 2-3 Variations

[0057] 3. Application examples in electronic devices

[0058] 4. Application examples for mobile objects

[0059] 5. Application examples of endoscopic surgery systems

[0060] <1. First Implementation Method>

[0061] [1-1 Structure of Semiconductor Device]

[0062] like Figure 1 As shown, the semiconductor device 1 according to the first embodiment includes a first substrate 2 and a second substrate 3 bonded to the first substrate 2. As the first substrate 2, for example, a sensor substrate having a plurality of photoelectric conversion units arranged therein can be used. Furthermore, as the second substrate 3, for example, a logic substrate having integrated therein a circuit for processing electrical signals from the photoelectric conversion units can be used. Furthermore, as a method for bonding the first substrate 2 and the second substrate 3, for example, plasma bonding can be used.

[0063] The interlayer insulating film 4 is provided on the second substrate 3 side of the first substrate 2 ( Figure 1 A plurality of wiring layers are provided in the interlayer insulating film 4. Figure 1 An example is shown in which four layers are included as a plurality of wiring layers, namely, a first wiring layer 5a, a second wiring layer 5b, a third wiring layer 5c, and a fourth wiring layer 5d. Figure 1 In the embodiment, the interlayer insulating film 4 and the first wiring layer 5a, the second wiring layer 5b, the third wiring layer 5c and the fourth wiring layer 5d form a multilayer wiring layer. Figure 1 The number of wiring layers shown is an example, and the number of wiring layers included in the interlayer insulating film 4 may be other than four layers.

[0064] Although detailed illustration is omitted, each of the first wiring layer 5 a , the second wiring layer 5 b , the third wiring layer 5 c , and the fourth wiring layer 5 d is electrically connected to elements and the like provided in the first substrate 2 .

[0065] In addition, the interlayer insulating film 6 is provided on the second substrate 3 side of the interlayer insulating film 4 ( Figure 1 On the surface of the lower side of the Figure 2 and Figure 3As shown, a plurality of first electrodes 7 are provided in the interlayer insulating film 6. Each first electrode 7 is provided within the interlayer insulating film 6, and one surface of each first electrode 7 (hereinafter referred to as "exposed surface S1") is coplanar with the bonding surface S2 between the first substrate 2 and the second substrate 3. In other words, the exposed surface S1 of the first electrode 7 is exposed from the surface of the interlayer insulating film 6 on the second substrate 3 side (bonding surface S2). As the first electrode 7, for example, a copper electrode made of pure copper or a copper alloy can be used.

[0066] like Figure 1 、 Figure 2 and Figure 3 As shown, the first electrode 7 includes a flat plate-shaped first electrode pad 8 and a columnar first vertical interconnection path (first VIA) 9. One surface of the first electrode pad 8 ( Figures 1 to 3 The lower surface) is located on the same surface as the bonding surface S2, and the first vertical interconnection path 9 is connected from the other surface of the first electrode pad 8 (on the Figures 1 to 3 The upper surface) is along the thickness direction of the first substrate 2 ( Figure 1 and Figure 2 in the upward direction).

[0067] In addition, if Figure 2 As shown, the wiring of the fourth wiring layer 5d, that is, the wiring closest to the second substrate 3 side ( Figure 2 The wiring of the wiring layer (in the middle, lower side) is electrically connected to the other surface (hereinafter referred to as "non-exposed surface S3") of a portion of the first electrodes 7 (hereinafter referred to as "first electrodes 7a") among the plurality of first electrodes 7. Figure 3 As shown, the wiring of the fourth wiring layer 5d is electrically connected to another surface (non-exposed surface S3) of a portion of the first electrodes 7 among the multiple first electrodes 7 (a portion or all of the other first electrodes 7 other than the above-mentioned first electrode 7a; hereinafter referred to as "first electrode 7b") via the first capacitor 10 arranged in the interlayer insulating film 6.

[0068] The first capacitor 10 includes: two flat-plate electrodes 11 and 12 facing each other; and an insulating film 13 provided between the two electrodes 11 and 12. The electrode 11 is provided on the second substrate 3 side ( Figure 3 The first electrode 7b is electrically connected to the electrode 11. In addition, the electrode 12 is provided on the side opposite to the second substrate 3 side ( Figure 3In the embodiment of the present invention, the first embodiment of the present invention relates to a first wiring layer 5d, wherein the first wiring layer 5d is provided with a first electrode 12 and a second wiring layer 5d is provided with a first wiring layer 5d. The first wiring layer 5d is provided with a first wiring layer 5d and a second wiring layer 5d is provided with a first wiring layer 5d. The first wiring layer 5d is provided with a first wiring layer 5d and a second wiring layer 5d. The first wiring layer 5d is provided with a first wiring layer 5d and a second wiring layer 5d. The first wiring layer 5d is provided with a first wiring layer 5d and a second wiring layer 5d. The first wiring layer 5d is provided with a first wiring layer 5d and a second wiring layer 5d. The first wiring layer 5d is provided with a first wiring layer 5d and a second wiring layer 5d. The first wiring layer 5d is provided with a first wiring layer 5d and a second wiring layer 5d. The first wiring layer 5d is provided with a first wiring layer 5d and a second wiring layer 5d. The first wiring layer 5d is provided with a first wiring layer 5d and a second wiring layer 5d. The first wiring layer 5d is provided with a first wiring layer 5d and a second wiring layer 5d. The first wiring layer 5d is provided with a first wiring layer 5d and a second wiring layer 5d. The first wiring layer 5d is provided with a first wiring layer 5d and a second wiring layer 5d.

[0069] Refer again Figure 1 , the interlayer insulating film 14 is provided on the first substrate 2 side of the second substrate 3 ( Figure 1 The interlayer insulating film 14 includes a plurality of wiring layers. Figure 1 An example is shown in which a first wiring layer 15a, a second wiring layer 15b, a third wiring layer 15c, a fourth wiring layer 15d, a fifth wiring layer 15e, and a sixth wiring layer 15f are included as a plurality of wiring layers. Figure 1 In the embodiment, the interlayer insulating film 14 and the first to sixth wiring layers 15a to 15f form a multilayer wiring layer. Figure 1 The number of wiring layers shown is an example, and the number of wiring layers included in the interlayer insulating film 14 may be other than 6. Although detailed illustration is omitted, each of the first to sixth wiring layers 15a to 15f is electrically connected to the elements and the like provided in the second substrate 3.

[0070] In addition, the interlayer insulating film 16 is provided on the first substrate 2 side of the interlayer insulating film 14 ( Figure 1 On the surface of the upper side of the Figure 4 and Figure 5 As shown, a plurality of second electrodes 17 are provided in the interlayer insulating film 16. Each second electrode 17 is provided within the interlayer insulating film 16, and one surface of each second electrode 17 (hereinafter referred to as "exposed surface S4") is flush with the bonding surface S2. In other words, the exposed surface S4 of the second electrode 17 is exposed from the surface of the interlayer insulating film 16 on the first substrate 2 side (bonding surface S2). For example, a copper electrode made of pure copper or a copper alloy can be used as the second electrode 17.

[0071] like Figure 1 、 Figure 4 and Figure 5As shown, the second electrode 17 includes a flat plate-shaped second electrode pad 18 and a columnar second vertical interconnection path (second VIA) 19. One surface of the second electrode pad 18 (at Figure 1 、 Figure 4 and Figure 5 The upper surface) is located on the same surface as the bonding surface S2, and the second vertical interconnection path 19 is connected from the other surface of the second electrode pad 18 (on the Figure 1 、 Figure 4 and Figure 5 The lower surface) along the thickness direction of the second substrate 3 ( Figure 1 、 Figure 4 and Figure 5 The second electrode pad 18 is arranged to face the first electrode pad 8 with the bonding surface S2 interposed therebetween. That is, at the bonding surface S2, the first electrode pad 8 and the second electrode pad 18 are bonded to each other, and the interlayer insulating film 6 and the interlayer insulating film 16 are bonded to each other.

[0072] In addition, if Figure 4 As shown, the wiring of the sixth wiring layer 15f, that is, the wiring closest to the first substrate 2 side ( Figure 4 The wiring of the wiring layer (on the upper side) is electrically connected to the other surface (hereinafter referred to as "non-exposed surface S5") of a portion of the second electrodes 17 (hereinafter referred to as "second electrodes 17a") among the plurality of second electrodes 17. The second electrodes 17a are connected to the first electrodes 7a connected to the wiring of the fourth wiring layer 5d or to the first electrodes 7b connected to the wiring of the fourth wiring layer 5d via the first capacitor 10. Figure 6 As shown, at the connection portion between the second electrode 17a and the first electrode 7a, the wiring of the fourth wiring layer 5d of the first substrate 2 and the wiring of the sixth wiring layer 15f of the second substrate 3 are electrically connected to each other via the first electrode 7a and the second electrode 17a. Therefore, a DC signal can be transmitted or DC power can be supplied between the wiring of the fourth wiring layer 5d of the first substrate 2 and the wiring of the sixth wiring layer 15f of the second substrate 3.

[0073] On the other hand, Figure 7 As shown, at the connection portion between the second electrode 17a and the first electrode 7b, the wiring of the fourth wiring layer 5d of the first substrate 2 and the wiring of the sixth wiring layer 15f of the second substrate 3 are electrically connected to each other via the first capacitor 10 in addition to the first electrode 7b and the second electrode 17a. Therefore, the charge in these wirings can be accumulated in the first capacitor 10. When the Figure 7 In the configuration of the connection portion shown, for example, the wiring of the fourth wiring layer 5d or the wiring of the sixth wiring layer 15f electrically connected to the first capacitor 10 can be used as the ground wiring.

[0074] In addition, if Figure 5 As shown, the wiring of the sixth wiring layer 15f is electrically connected to the other surface (non-exposed surface S5) of a portion of the second electrodes 17 (a portion or all of the second electrodes 17 other than the above-mentioned second electrode 17a; hereinafter, referred to as "second electrodes 17b") among the plurality of second electrodes 17 via the second capacitor 20 provided in the interlayer insulating film 16. Like the second electrode 17a, the second electrode 17b is connected to the first electrode 7a connected to the wiring of the fourth wiring layer 5d or to the first electrode 7b connected to the wiring of the fourth wiring layer 5d via the first capacitor 10. Figure 8 As shown, at the connection portion between the second electrode 17b and the first electrode 7a, the wiring of the fourth wiring layer 5d of the first substrate 2 and the wiring of the sixth wiring layer 15f of the second substrate 3 are electrically connected to each other via the first electrode 7a, the second electrode 17b, and the second capacitor 20. Therefore, the charge in these wirings can be accumulated in the second capacitor 20.

[0075] On the other hand, Figure 9 As shown, at the connection portion between the second electrode 17b and the first electrode 7b, the wiring of the fourth wiring layer 5d of the first substrate 2 and the wiring of the sixth wiring layer 15f of the second substrate 3 are electrically connected to each other via the first capacitor 10 in addition to the first electrode 7b, the second electrode 17b and the second capacitor 20. Therefore, the charge in these wirings can be accumulated in the first capacitor 10 and the second capacitor 20. Here, when the Figure 8 and Figure 9 With the configuration of the connection portion shown, for example, the wiring of the fourth wiring layer 5d electrically connected to the first capacitor 10 or the wiring of the sixth wiring layer 15f electrically connected to the second capacitor 20 can be used as the ground wiring.

[0076] The second capacitor 20 includes: two flat-plate electrodes 21 and 22 facing each other; and an insulating film 23 provided between the two electrodes 21 and 22. The electrode 21 is provided on the first substrate 2 side ( Figure 5 The second electrode 17b is electrically connected to the electrode 21. In addition, the electrode 22 is provided on the side opposite to the first substrate 2 ( Figure 5 The wiring of the sixth wiring layer 15f is electrically connected to the electrode 22. In addition, as the material of the electrodes 21 and 22 and the insulating film 23, for example, the same material as the electrodes 11 and 12 and the insulating film 13 of the first substrate 2 can be used.

[0077] Here, the area between the fourth wiring layer 5d of the first substrate 2 and the sixth wiring layer 15f of the second substrate 3 is defined as the substrate connection area 24. That is, the substrate connection area 24 is the area in which the interlayer insulating film 6 of the first substrate 2 and the interlayer insulating film 16 of the second substrate 3 are provided. Each of the first capacitor 10 and the second capacitor 20 is provided at the outermost layer of the substrate connection area 24.

[0078] Using this construction, Figure 6 As shown, in the substrate connection area 24, the wiring of the fourth wiring layer 5d and the wiring of the sixth wiring layer 15f are electrically connected to each other via the first electrode 7a and the second electrode 17a, thereby transmitting signals and supplying power between the first substrate 2 and the second substrate 3. Figure 7 、 Figure 8 and Figure 9 As shown, when the wiring of the fourth wiring layer 5d and the wiring of the sixth wiring layer 15f are electrically connected to each other via the first capacitor 10 and / or the second capacitor 20 in addition to the first electrode 7b and the second electrode 17a, the capacitor function for accumulating the charge of the wiring of the fourth wiring layer 5d and the charge of the wiring of the sixth wiring layer 15f is realized.

[0079] [1-2 Method for Manufacturing Semiconductor Device]

[0080] Next, a method for manufacturing the semiconductor device 1 of the first embodiment will be described. Figure 10A 、 Figure 10B 、 Figure 11A 、 Figure 11B 、 Figure 12 、 Figure 13 1 is a diagram showing a manufacturing process of the semiconductor device 1 according to the first embodiment.

[0081] First, if Figure 10A and Figure 10B As shown, the first substrate 2 (e.g., sensor substrate) is prepared before forming the substrate connection area 24, color filter 36, and microlens 37, and the second substrate 3 (e.g., logic substrate) is prepared before forming the substrate connection area 24.

[0082] Then, if Figure 11A As shown in FIG. 1 , the first capacitor 10, the interlayer insulating film 6, the first vertical interconnection path 9 and the first electrode pad 8 are sequentially formed on the prepared first substrate 2. Thus, a substrate connection area 24 is formed on the first substrate 2. Figure 11B As shown, the second capacitor 20, the interlayer insulating film 16, the second vertical interconnection via 19, and the second electrode pad 18 are sequentially formed on the prepared second substrate 3. Thus, a substrate connection region 24 is formed on the second substrate 3.

[0083] Then, if Figure 12 As shown, the first substrate 2 and the second substrate 3 are bonded so that the substrate connection region 24 of the first substrate 2 and the substrate connection region 24 of the second substrate 3 overlap each other. As a method for bonding the first substrate 2 and the second substrate 3, for example, plasma bonding can be used.

[0084] Then, if Figure 13 As shown, the first substrate 2 is thinned.

[0085] Then, if Figure 1 As shown, a color filter 36, a microlens 37, and the like are formed on the light incident side of the first substrate 2. Thus, the semiconductor device 1 of the first embodiment is formed.

[0086] As described above, the semiconductor device 1 of the first embodiment can be Figures 1 to 5 As shown, the present invention includes at least one of a first capacitor 10 and a second capacitor 20, wherein the first capacitor 10 is provided in the first substrate 2 and one electrode 11 of the first capacitor 10 is electrically connected to the non-exposed surface S3 of the first electrode 7 (7b), and the second capacitor 20 is provided in the second substrate 3 and one electrode 21 of the second capacitor 20 is electrically connected to the non-exposed surface S5 of the second electrode 17 (17b). Therefore, compared with a method in which, for example, the first electrode 7 (7b) is used as the electrode 11 of the first capacitor 10 and the second electrode 17 (17b) is used as the electrode 21 of the second capacitor 20, in the present invention, since the positions of the first capacitor 10 and the second capacitor 20 are away from the junction surface S2, stress generated by the junction process is not directly applied to the first capacitor 10 and the second capacitor 20. Thus, a semiconductor device 1 is provided that can suppress performance degradation of the first capacitor 10 and the second capacitor 20 (capacitors) due to the junction process.

[0087] In addition, since the first electrode 7 (7b) and the second electrode 17 (17b) are not in contact with the insulating film 13 of the first capacitor 10 and the insulating film 23 of the second capacitor 20, even if the first electrode 7 (7b) and the second electrode 17 (17b) are copper electrodes made of pure copper or a copper alloy, for example, the copper contained in the first electrode 7 (7b) and the second electrode 17 (17b) can be prevented from diffusing into the insulating films 13 and 23.

[0088] In addition, for example, compared to a method in which the first electrode 7 and the second electrode 17 are used as the electrode 11 of the first capacitor 10 and the electrode 21 of the second capacitor 20, the present invention can increase the freedom of the materials used for the electrodes 11 and 21 and can improve the characteristics of the first capacitor 10 and the second capacitor 20.

[0089] Furthermore, unlike, for example, a method in which the first capacitor 10 and the second capacitor 20 are provided in the fourth wiring layer 5d of the first substrate 2 and the sixth wiring layer 15f of the second substrate 3, the present invention can prevent the first capacitor 10 from using the area within the fourth wiring layer 5d and the second capacitor 20 from using the area within the sixth wiring layer 15f, thereby suppressing an increase in the size of the fourth wiring layer 5d and the sixth wiring layer 15f, and also suppressing an increase in the size of the semiconductor device 1. Furthermore, the present invention can prevent an increase in the wiring density of the fourth wiring layer 5d and the sixth wiring layer 15f, and can improve the yield rate.

[0090] Specifically, in the semiconductor device 1 of the first embodiment, the substrate connection region 24 between the first substrate 2 and the second substrate 3 is designed to have a lower metal density in the substrate connection region than in the first to fourth wiring layers 5a to 5d of the first substrate 2 and the first to sixth wiring layers 15a to 15f of the second substrate 3. According to the semiconductor device 1 of the first embodiment, since the first capacitor 10 and the second capacitor 20 are provided in the substrate connection region 24, the substrate connection region 24 can be effectively utilized.

[0091] Furthermore, in the semiconductor device 1 of the first embodiment, the use of the first capacitor 10 and the second capacitor 20 enables a cutoff function for noise generated in the power supply or analog circuit, as well as a storage function for temporarily retaining charge. For example, if the power supply contains noise, the semiconductor device 1 may not operate properly because it is operating under the power supply containing noise. In contrast, when the noise cutoff function is implemented, the semiconductor device 1 can operate properly because the power supply supplied to the semiconductor device 1 has been noise-eliminated. In particular, by mounting capacitors (the first capacitor 10 and the second capacitor 20) on each of the first substrate 2 and the second substrate 3, the noise elimination performance can be improved by more than 2 times.

[0092] Here, a case where a sensor substrate is used as the first substrate 2, a logic substrate is used as the second substrate 3, and a solid-state imaging device is configured as the semiconductor device 1 can be considered. In such a solid-state imaging device (semiconductor device 1), as Figure 14 As shown, a pixel region 25 provided with a photoelectric conversion portion and the like is provided at the chip center of the sensor substrate (first substrate 2), an I / O (input / output) portion 26 provided with an I / O (input / output) pad and the like is provided at the chip periphery of the sensor substrate, and a driver 27 serving as a transmission path for a signal after photoelectric conversion is provided between the pixel region 25 and the I / O portion 26. The driver 27 is provided by connecting the second electrode 17a (refer to FIG. 1 ) to the first electrode 17a. Figure 4) bonded first electrode 7a (refer to Figure 2 ) are arranged in an array. Therefore, the solid-state imaging device (semiconductor device 1) transmits the signal obtained by photoelectric conversion in the pixel area 25 of the image sensor (first substrate 2) to the logic substrate (second substrate 3) via the driver 27, performs calculations in the logic substrate (second substrate 3) based on the transmitted signal, and outputs the calculation results to an external display or the like via the I / O unit 26.

[0093] exist Figure 14 In the solid-state imaging device (semiconductor device 1) shown, generally speaking, in the area other than the area occupied by the driver 27, that is, in most areas of the sensor substrate (first substrate 2), a dummy electrode is laid out for firmly joining the first substrate 2 and the second substrate 3. The dummy electrode is an electrode that includes an electrode pad and a vertical interconnection path, etc. like the first electrode 7 and the second electrode 17, but is not electrically connected to the first substrate 2 or the second substrate 3. Therefore, since the area where the dummy electrode is laid out does not have the function of electrically connecting the first substrate 2 and the second substrate 3, the area can be used for the layout of the first electrode 7a and the second electrode 17a in the first embodiment, that is, the area can be used for the layout of the electrodes electrically connected to the first capacitor 10 and the second capacitor 20. Thus, in forming Figure 14 In the case of the solid-state imaging device (semiconductor device 1) shown, a wide area can be prepared as an area in which the first capacitor 10 and the second capacitor 20 can be laid out, thereby increasing the layout freedom of the first capacitor 10 and the second capacitor 20 and reducing the difficulty of designing the solid-state imaging device (semiconductor device 1).

[0094] In addition, Figure 14 In the solid-state imaging device (semiconductor device 1) shown, if noise is included in the power supply, then since the solid-state imaging device (semiconductor device 1) operates under the power supply containing noise, the image created by the solid-state imaging device (semiconductor device 1) is sensitive to the noise, and in severe cases, stripes may appear in the image. Here, the power supply is generated by the AC-DC (alternating current-direct current) conversion unit inside various systems such as smartphones, cameras, and surveillance devices equipped with the solid-state imaging device (semiconductor device 1), and is supplied from a plurality of terminals provided in the I / O unit 26. In contrast, in forming Figure 14In the case of the solid-state imaging device (semiconductor device 1) shown, there is a wide area around the I / O section 26 that can be used as an area for arranging the first capacitor 10 and the second capacitor 20. Therefore, by arranging the first capacitor 10 and the second capacitor 20 near the I / O section 26, a noise cutoff function can be achieved, power from which noise has been eliminated can be supplied to the solid-state imaging device (semiconductor device 1), and a clearer image can be created by the solid-state imaging device (semiconductor device 1).

[0095] In addition, when the first capacitor 10 and the second capacitor 20 are arranged near the I / O portion 26 and thereby implement a noise cutoff function, for example, noise can be eliminated from the signal output to the display via the I / O portion 26, the electrical load of the display can be reduced, and an image with less noise can be projected onto the display.

[0096] Heretofore, the case where the noise cutoff function is realized on a macroscopic level has been described, but the same effect can be obtained also for the case where the noise cutoff function is realized on a microscopic level. Figure 14 In the solid-state imaging device (semiconductor device 1) shown, if noise is superimposed on the signal from the photoelectric conversion unit in the analog circuit such as the pixel transistor, it is difficult to prevent signal quality degradation even if the signal is digitized on a pixel or block basis by the AD converter. In contrast, if a noise cut function can be implemented on a pixel or block basis by using the first capacitor 10 and the second capacitor 20, signal quality degradation can be prevented, and a clearer image can be created by the solid-state imaging device (semiconductor device 1).

[0097] Furthermore, when the first and second capacitors 10 and 20 are arranged to realize a storage function, this storage function can also be used to accumulate charge during global shutter operation. By using this for charge accumulation, it is possible to capture distortion-free images of high-speed moving subjects.

[0098] Furthermore, in the semiconductor device 1 of the first embodiment, the first electrode 7 includes a first electrode pad 8, one surface of which is flush with the joint surface S2, and a first vertical interconnection via 9, which extends from the other surface of the first electrode pad 8. Furthermore, the second electrode 17 includes a second electrode pad 18, one surface of which is flush with the joint surface S2, and a second vertical interconnection via 19, which extends from the other surface of the second electrode pad 18. Therefore, the amount of copper used in the first electrode 7 and the second electrode 17 can be reduced, manufacturing costs can be reduced, and the size of the joint surface S2 between the first electrode 7 and the second electrode 17 can be increased.

[0099] In addition, in the semiconductor device 1 of the first embodiment, at least one of the first capacitor 10 and the second capacitor 20 includes two electrodes 11 and 12 facing each other and an insulating film 13 provided between the two electrodes 11 and 12. Therefore, each of the first capacitor 10 and the second capacitor 20 can have an MIM (metal-insulator-metal) structure, and each of the first capacitor 10 and the second capacitor 20 can have a high capacitance density.

[0100] [1-3 Modification Example]

[0101] (1) Here, in the first embodiment, an example is shown in which the second electrode 17 is composed of the second electrode pad 18 and the second vertical interconnection path 19, but other configurations may be adopted. For example, Figure 15 As shown, the second vertical interconnection via 19 may be omitted, whereby the second electrode 17 may be constituted only by the second electrode pad 18. Likewise, the first electrode 7 may be constituted only by the first electrode pad 8.

[0102] (2) In addition, in the first embodiment, an example is shown in which the electrode 22 of the second capacitor 20 is connected to the wiring of the sixth wiring layer 15f, but other configurations may be adopted. For example, Figure 16 As shown, the electrical connection of the second electrode 17 may be formed differently from the second electrode 17 connected to the electrode 21. Figure 16 In order to prevent the electrical connection between the electrode 22 and the wiring of the sixth wiring layer 15f, an insulating film 28 is provided between them. In addition, the periphery of the second vertical interconnection path 19 of the second electrode 17 connected to the electrode 22 is covered with the insulating film 29 so that the second vertical interconnection path 19 is not electrically connected to the electrode 21. Similarly, the electrode 12 of the first capacitor 10 can be electrically connected to the first electrode 7 different from the first electrode 7 connected to the electrode 11.

[0103] (3) Here, generally, the capacitance C of a capacitor is defined by the following formula (1), in which the relative dielectric constant ε is used. r , vacuum dielectric constant ε0, electrode area S, and the distance d between electrodes.

[0104] C=ε r ·ε0·S / d (1)

[0105] According to formula (1), the distance d between electrodes can be reduced, the electrode area S can be increased, and the relative dielectric constant ε can be increased. rAny of these three methods can increase the capacitance C of the capacitor. However, in order to reduce the distance d between the electrodes, the insulating film provided between the electrodes must be thinned, so there is a high possibility of short circuits between the electrodes. In particular, when forming a capacitor by stacking using planar technology, from the perspective of flattening, in order to make the area where the capacitor is formed not higher than other areas, a material with a large relative dielectric constant ε is generally used. r The insulating film is made of a thin film of a material. Therefore, there is a higher probability of a short circuit between the electrodes. In addition, the probability of a short circuit between the electrodes is greatly affected by defects in the insulating film caused by dust, etc., and is determined by the defect density of the insulating film. The defect density of the insulating film can be reduced to a certain extent by designing the equipment and processes used to manufacture the semiconductor device 1, but it cannot be reduced to zero.

[0106] In contrast, a configuration may be used in which at least one of the first capacitor 10 and the second capacitor 20 is divided and laid out using a high degree of freedom in the layout of the first capacitor 10 and the second capacitor 20. In this case, as shown in FIG. Figure 17 As shown, a configuration is used in which two or more of the plurality of first capacitors 10 or two or more of the plurality of second capacitors 20 are connected to the same wiring. Figure 17 A configuration is shown in which two or more second capacitors 20 are connected to the same wiring (wiring of the fourth wiring layer 5d) in the first substrate 2. Figure 17 The structure shown can connect two or more second capacitors 20 in parallel and achieve the same capacitance as a large capacitor having an area equal to the total area of the second capacitors 20 connected in parallel. That is, since a large capacitance can be achieved using a small capacitor (second capacitor 20), the yield of the semiconductor device 1 can be improved. In addition, by redundantly laying out the divided capacitors (second capacitors 20), the yield of the semiconductor device 1 can be further improved. Here, an example has been described in which two or more of the plurality of second capacitors 20 are connected to the same wiring, but the same effect can be achieved when two or more of the plurality of first capacitors 10 are connected to the same wiring.

[0107] (4) In addition, in the first embodiment, an example is shown in which the first capacitor 10 has a configuration in which the insulating film 13 is provided between the two electrodes 11 and 12, and the second capacitor 20 has a configuration in which the insulating film 23 is provided between the two electrodes 21 and 22, but other configurations may be adopted. For example, Figure 18A and Figure 18BAs shown, at least one of the first capacitor 10 and the second capacitor 20 may have a multilayer structure in which electrodes 30 and insulating films 31 are alternately and repeatedly arranged.

[0108] Figure 18A and Figure 18B 2 shows a configuration in which the second capacitor 20 has a multilayer structure. Figure 18A and Figure 18B , the electrode 30 closest to the sixth wiring layer 15f side among those electrodes 30 used to form the multilayer structure (hereinafter, referred to as "electrode 30a") is electrically connected to the sixth wiring layer 15f, and the other electrodes 30 (hereinafter, referred to as "electrode 30b", "electrode 30c", "electrode 30d" or "electrode 30e") are electrically connected to different second electrodes 17. That is, each of the electrodes 30b to 30e corresponds to "one electrode 21" in the first embodiment. The periphery of the second vertical interconnection path 19 of the second electrode 17 is covered with an insulating film 32 to prevent the second vertical interconnection path from being electrically connected to an electrode 30 that is not a connection object. Figure 18A and Figure 18B In the second capacitor 20 shown, a capacitor is formed by electrodes 30a and 30b and an insulating film 31, a capacitor is formed by electrodes 30b and 30c and an insulating film 31, a capacitor is formed by electrodes 30c and 30d and an insulating film 31, and a capacitor is formed by electrodes 30d and 30e and an insulating film 31, thereby forming a total of four capacitors.

[0109] For example, using Figure 18A and Figure 18B In the illustrated configuration, for example, when a capacitor (second capacitor 20) is provided corresponding to each pixel, the capacitor can be appropriately arranged even if the area available for arrangement of the capacitor is limited. Here, an example has been described in which the second capacitor 20 has a multilayer structure, but the same effect can be achieved even when the first capacitor 10 has a multilayer structure.

[0110] (5) In addition, in the first embodiment, an example is shown in which the first capacitor 10 and the second capacitor 20 are flat plate-shaped, but other configurations may be adopted. For example, Figure 19 As shown, in order to increase the area of the electrodes 11 , 12 , 21 , and 22 of the first capacitor 10 and the second capacitor 20 , the first capacitor 10 and the second capacitor 20 may have a 3D (three-dimensional) shape.

[0111] Figure 19 FIG shows a configuration in which the second capacitor 20 has a 3D shape. Figure 19In the embodiment, the second capacitor 20 has a bottom portion 33 and sidewall portions 34 and 35 extending from the edge of the bottom portion 33 in a direction intersecting the bottom portion 33. In addition, the second capacitor 20 is provided in the sixth wiring layer 15f, and the end surfaces of the sidewall portions 34 and 35 on the first substrate 2 side are located on the same plane as the bonding surface S2. Figure 19 The structure shown can increase the area of the electrodes 21 and 22 of the second capacitor 20, thereby increasing the capacitance of the second capacitor 20. In addition, when the second capacitors 20 having large capacitance are connected in parallel, the same capacitance as that of a capacitor having an area equal to the total area of the second capacitors 20 connected in parallel can be achieved. In this case, when aluminum (Al) is used for the wiring of the sixth wiring layer 15f provided with the second capacitors 20, processing can be facilitated and processing costs can be reduced.

[0112] Here, an example has been described in which the second capacitor 20 is composed of the bottom 33 and the side wall portions 34 and 35 , but the same effect can be obtained also in the case where the first capacitor 10 is composed of the bottom and the side wall portions.

[0113] <2. Application Examples of Solid-State Imaging Devices>

[0114] [2-1 Structure of Solid-State Imaging Device]

[0115] The technology according to the present invention (the present technology) can be applied to various products. For example, the technology according to the present invention can be applied to a solid-state imaging device.

[0116] Figure 20 : is a diagram showing one example of a schematic configuration of a solid-state image pickup device to which the technology according to the present invention (present technology) is applicable.

[0117] like Figure 20 As shown, the solid-state imaging device 101 has a structure including a pixel portion 103, a vertical driving circuit 104, a column signal processing circuit 105, a horizontal driving circuit 106, an output circuit 107 and a control circuit 108, wherein the pixel portion 103 includes a plurality of pixels 102 arranged on a substrate 111 made of silicon.

[0118] Multiple pixels 102 are regularly arranged in a 2D (two-dimensional) array on a substrate 111. Each pixel 102 includes a photoelectric conversion unit consisting of a photodiode; a charge accumulation capacitor; and multiple MOS transistors. The MOS transistors used to form a pixel 102 can be four MOS transistors consisting of a transfer transistor, a reset transistor, a select transistor, and an amplifier transistor, or can be three MOS transistors excluding the select transistor.

[0119] The pixel section 103 includes a plurality of pixels 102 regularly arranged in a 2D array. The pixel section 103 comprises an effective pixel region, where light is actually received and the signal charge generated by photoelectric conversion is amplified and read out to the column signal processing circuit 105; and a black reference pixel region (not shown) for outputting optical black, which serves as a reference for the black level. The black reference pixel region is typically formed on the periphery of the effective pixel region.

[0120] The control circuit 108 generates a clock signal or a control signal based on the vertical synchronization signal, the horizontal synchronization signal, and the main clock, which serves as an operation reference for the vertical drive circuit 104, the column signal processing circuit 105, the horizontal drive circuit 106, and the like. The clock signal and the control signal generated by the control circuit 108 are then input to the vertical drive circuit 104, the column signal processing circuit 105, the horizontal drive circuit 106, and the like.

[0121] The vertical drive circuit 104 is configured, for example, by a shift register, and sequentially selects and scans each pixel 102 of the pixel portion 103 in the vertical direction on a row-by-row basis. Consequently, a pixel signal based on a signal charge generated in the photodiode of each pixel 102 in accordance with the amount of light received is supplied to the column signal processing circuit 105 via a vertical signal line 109.

[0122] For example, the column signal processing circuit 105 is provided for each column of pixels 102, and performs signal processing such as noise cancellation and signal amplification on each pixel column of the signals output from the pixels 102 in one row using signals from a black reference pixel region (not shown, but formed around the effective pixel region). A horizontal selection switch (not shown) is provided between the output stage of the column signal processing circuit 105 and the horizontal signal line 110.

[0123] For example, the horizontal drive circuit 106 is configured by a shift register, sequentially selects each of the column signal processing circuits 105 by sequentially outputting horizontal scanning pulses, and outputs pixel signals from each of the column signal processing circuits 105 to the horizontal signal line 110 .

[0124] The output circuit 107 performs signal processing on the signals sequentially supplied from each of the column signal processing circuits 105 via the horizontal signal line 110 and then outputs them.

[0125] [2-2 Sensor substrate structure]

[0126] Next, a schematic configuration of a sensor substrate constituting the solid-state imaging device 101 will be described. Figure 21 2 is a cross-sectional view showing a cross section of the sensor substrate 2000 for one pixel.

[0127] like Figure 21 As shown, in the sensor substrate 2000, a photodiode (PD: photodiode) 20019 receives light from the back surface ( Figure 21 A planarization film 20013, a color filter (CF) 20012, and a microlens 20011 are provided above the PD 20019, and the incident light 20001 incident through each component in sequence is received by the light receiving surface 20017 and photoelectric conversion is performed.

[0128] For example, in PD 20019, n-type semiconductor region 20020 is formed as a charge accumulation region for accumulating charge (electrons). In PD 20019, n-type semiconductor region 20020 is provided within p-type semiconductor regions 20016 and 20041 of semiconductor substrate 20018. P-type semiconductor region 20041, which has a higher impurity concentration than the back (upper) side, is provided on the front (lower) side of semiconductor substrate 20018 within n-type semiconductor region 20020. In other words, PD 20019 has a hole-accumulation diode (HAD) structure, with p-type semiconductor regions 20016 and 20041 formed at the interfaces on the upper and lower sides of n-type semiconductor region 20020, respectively, thereby suppressing the generation of dark current.

[0129] A pixel separator 20030 for achieving electrical isolation between the plurality of pixels 20010 is provided inside the semiconductor substrate 20018, and PDs 20019 are provided in the regions partitioned by the pixel separator 20030. In this figure, when the solid-state imaging device is viewed from above, for example, the pixel separator 20030 is formed so as to be interposed between the plurality of pixels 20010 in a lattice shape, and the PDs 20019 are formed in the regions partitioned by the pixel separator 20030.

[0130] In each PD 20019, the anode is grounded, and in the solid-state imaging device, the signal charge (e.g., electrons) accumulated in the PD 20019 is read out via a transfer Tr (MOS FET: metal oxide semiconductor field effect transistor) (not shown) or the like, and is output as an electrical signal to a vertical signal line (VSL: vertical signal line) (not shown).

[0131] The wiring layer 20050 is provided on the front surface (lower surface) of the semiconductor substrate 20018 which is on the opposite side to the back surface (upper surface) of the semiconductor substrate 20018 on which various components such as the light shielding film 20014 , the CF 20012 , and the microlens 20011 are provided.

[0132] The wiring layer 20050 includes wiring 20051 and an insulating layer 20052, and is formed so that the wiring 20051 is electrically connected to each element in the insulating layer 20052. The wiring layer 20050 is a so-called multilayer wiring layer, formed by alternately stacking the interlayer insulating film constituting the insulating layer 20052 and the wiring 20051 multiple times. Here, as the wiring 20051, wiring for Tr such as the transfer Tr for reading charge from the PD 20019 and various wirings such as the VSL are stacked with the insulating layer 20052 interposed therebetween.

[0133] The substrate connection region 20061 is provided on the surface of the wiring layer 20050 on the side opposite to the side provided with the PD 20019. The substrate connection region 20061 includes a capacitor 20062, an electrode 20063, and an interlayer insulating film 20064. One electrode of the capacitor 20062 is electrically connected to the wiring 20051 of the wiring layer 20050 in the interlayer insulating film 20064. The other electrode of the capacitor 20062 is electrically connected to the electrode 20063, and the electrode 20063 is exposed from the back surface (the bottom surface in the figure) of the substrate connection region 20061. Figure 21 The electrode 20063 is shown as an example, which includes: a flat electrode pad 20065 located on the same surface as the back surface of the substrate connection area 20061; and a columnar vertical interconnection via 20066 extending from the back surface (the top surface in the figure) of the electrode pad 20065 along the thickness direction of the sensor substrate 2000 ( Figure 21 The substrate connection region 20061 is bonded to the substrate connection region (not shown) of the logic substrate so that the electrodes (not shown) of the logic chip and the electrodes 20063 overlap with each other.

[0134] The light-shielding film 20014 is provided on the back surface (upper surface in the figure) side of the semiconductor substrate 20018 .

[0135] The light shielding film 20014 is configured to shield a portion of the incident light 20001 from above the semiconductor substrate 20018 toward the back surface of the semiconductor substrate 20018 .

[0136] A light shielding film 20014 is provided above the pixel separator 20030 provided within the semiconductor substrate 20018. The light shielding film 20014 is provided on the back surface (upper surface) of the semiconductor substrate 20018 via an insulating film 20015 such as a silicon oxide film, and projects convexly. On the other hand, the light shielding film 20014 is not provided above the PD 20019 provided within the semiconductor substrate 20018. The light shielding film 20014 is opened to allow the incident light 20001 to enter the PD 20019.

[0137] That is, in this figure, when the solid-state imaging device is viewed from above, the planar shape of the light shielding film 20014 is a lattice pattern, and openings are formed therein, through which incident light 20001 passes to reach the light receiving surface 20017 .

[0138] The light shielding film 20014 is formed of a light shielding material capable of shielding light. For example, the light shielding film 20014 can be formed by sequentially stacking a titanium (Ti) film and a tungsten (W) film. Alternatively, for example, the light shielding film 20014 can be formed by sequentially stacking a titanium nitride (TiN) film and a tungsten (W) film.

[0139] The light shielding film 20014 is covered with a planarizing film 20013. The planarizing film 20013 is formed using an insulating material that can transmit light.

[0140] The pixel separation portion 20030 includes a groove portion 20031 , a fixed charge film 20032 , and an insulating film 20033 .

[0141] The fixed charge film 20032 is formed on the back surface (upper surface) side of the semiconductor substrate 20018 and covers the groove portion 20031 for partitioning between the plurality of pixels 20010 .

[0142] Specifically, the fixed charge film 20032 is provided with a certain thickness to cover the inner surface of the groove portion 20031 formed on the back surface (upper surface) side of the semiconductor substrate 20018. Therefore, the insulating film 20033 is provided (filled) so as to be buried in the groove portion 20031 covered by the fixed charge film 20032.

[0143] Here, the fixed charge film 20032 is formed using a high dielectric material having a negative fixed charge, thereby forming a positive charge (hole) accumulation region at the interface portion with the semiconductor substrate 20018, thereby suppressing the generation of dark current. When the fixed charge film 20032 is formed to have a negative fixed charge, an electric field is applied to the interface with the semiconductor substrate 20018 due to the negative fixed charge, and a positive charge (hole) accumulation region is formed.

[0144] For example, the fixed charge film 20032 may be formed as a hafnium oxide film (HfO2 film). Alternatively, the fixed charge film 20032 may be formed as at least one of other oxides containing hafnium, zirconium, aluminum, tantalum, titanium, magnesium, yttrium, or lanthanide elements.

[0145] An example of a solid-state imaging device to which the technology according to the present invention is applicable has been described above. The technology according to the present invention can be applied to the sensor substrate 2000 in the configuration described above. Specifically, Figure 1 The first capacitor 10 can be applied to Figure 21 The capacitor 20062, and Figure 1 The first electrode 7 can be applied to Figure 21 When the technology according to the present invention is applied to the sensor substrate 2000, since the degradation of the capacitor performance due to the bonding process can be suppressed, a better captured image can be obtained.

[0146] [2-3 Modification Example]

[0147] In addition, the present technology can be applied to a solid-state imaging device having a global shutter function. Figure 20 The same, therefore, the illustration is omitted. Figure 22 1 is a cross-sectional view of one pixel of the solid-state imaging device 101 according to this modification.

[0148] like Figure 22 As shown, the solid-state imaging device 101 includes a first substrate 180 on which the photoelectric converter PD is formed, and a second substrate 181 on which the charge storage capacitor 153 and a plurality of MOS transistors are formed. Thus, the first substrate 180 and the second substrate 181 are stacked and bonded together. The side of the first substrate 180 on which the photoelectric converter PD is formed constitutes the light incident surface on which light L is incident, and the color filter 159 and the on-chip lens 160 are formed on the light incident surface of the first substrate 180.

[0149] Will refer to Figure 23A and Figure 23B The structures of the first substrate 180 and the second substrate 181 will be described in detail.

[0150] First, the first substrate 180 will be described.

[0151] like Figure 23A As shown, the first substrate 180 includes: a photoelectric conversion unit PD; a semiconductor substrate 112 having an impurity region 116 formed thereon, the impurity region 116 serving as a drain of the first transfer transistor Tr1; a multilayer wiring layer 117 formed above the semiconductor substrate 112; and a substrate connection region 190 formed above the multilayer wiring layer 117.

[0152] The semiconductor substrate 112 is formed of an N-type silicon substrate, and a P-type well layer 113 is formed on the semiconductor substrate 112. The P-type well layer 113 may be formed by implanting P-type impurity ions into the semiconductor substrate 112.

[0153] The photoelectric converter PD is composed of an N-type well layer 114 formed in a P-type well layer 113, and a P+-type impurity region 115. The P+-type impurity region 115 is a region in contact with the N-type well layer 114 and formed on the surface side of the P-type well layer 113. The N-type well layer 114 is formed by implanting N-type impurity ions into a desired region of the P-type well layer 113. Separately, the P+-type impurity region 115 is formed by implanting P-type impurity ions at a high concentration into a desired region of the P-type well layer 113. In the photoelectric converter PD, a hole accumulation diode (HAD: registered trademark) structure is formed due to the pn junction between the P+-type impurity region 115 and the N-type well layer 114, and the pn junction between the N-type well layer 114 and the P-type well layer 113.

[0154] In the photoelectric converter PD having such a configuration, signal charges corresponding to the light amount of incident light L are generated, and the photoelectrically converted signal charges are accumulated in a depletion layer formed between the P + -type impurity region 115 and the N-type well layer 114 .

[0155] Impurity region 116 is formed in a region located on the surface side of P-type well layer 113 and separated from photoelectric converter PD by a predetermined distance. Impurity region 116 temporarily accumulates signal charge transferred from photoelectric converter PD. Impurity region 116 is formed by implanting high-concentration N-type impurity ions into a desired region of P-type well layer 113.

[0156] In this modification, a region between the photoelectric conversion portion PD and the impurity region 116 is defined as a channel portion of the first transfer transistor Tr1 .

[0157] A multilayer wiring layer 117 is formed on the semiconductor substrate 112 above the P-type well layer 113 in which the photoelectric conversion unit PD and the impurity region 116 are already formed. In the multilayer wiring layer 117, a gate electrode 119 constituting the first transfer transistor Tr1 and a first wiring layer M1 formed above the gate electrode 119 are stacked with an interlayer insulating film 118 interposed therebetween.

[0158] The gate electrode 119 is formed above a channel portion formed in the P-type well layer 113 between the photoelectric conversion portion PD and the impurity region 116 via a gate insulating film (not shown).

[0159] In the first wiring layer M1, a first connecting wiring 123 and a second connecting wiring 122 are formed. The first connecting wiring 123 is connected to the impurity region 116 via a contact portion 121 formed in the interlayer insulating film 118. In addition, the second connecting wiring 122 is connected to the gate electrode 119 via a contact portion 120 formed in the interlayer insulating film 118.

[0160] The substrate connection region 190 is formed above the first wiring layer M1 in the multilayer wiring layer 117. In the substrate connection region 190, the second wiring layer M2 is stacked above the first wiring layer M1 with an interlayer insulating film 191 interposed therebetween.

[0161] The second wiring layer M2 includes a first connection electrode 127 and a second connection electrode 126, each of which is exposed from the surface of the interlayer insulating film 191. The first connection electrode 127 is connected to the first connection wiring 123 formed in the first wiring layer M1 via a contact portion 124 formed in the interlayer insulating film 191. The second connection electrode 126 is connected to the second connection wiring 122 formed in the first wiring layer M1 via a contact portion 125 formed in the interlayer insulating film 191.

[0162] In the first substrate 180 having the above-described configuration, the side opposite to the side of the semiconductor substrate 112 on which the first connection electrode 127 and the second connection electrode 126 are formed is a light incident side.

[0163] Next, the second substrate 181 will be described.

[0164] like Figure 23B As shown, second substrate 181 includes: a semiconductor substrate 128 having impurity regions 130, 131, 132, 134, and 135 formed therein, which serve as sources and drains for a plurality of MOS transistors; a multilayer wiring layer 136 formed above semiconductor substrate 128; and a substrate connection region 195 formed above multilayer wiring layer 136. Therefore, charge storage capacitor 153 is formed in substrate connection region 195. In this modified example, the plurality of MOS transistors formed in second substrate 181 are a second transfer transistor Tr2, a reset transistor Tr3, an amplification transistor Tr4, and a selection transistor Tr5.

[0165] The semiconductor substrate 128 is formed of an N-type silicon substrate, and a P-type well layer 129 is formed on the semiconductor substrate 128. The P-type well layer 129 may be formed by implanting P-type impurity ions into the semiconductor substrate 128.

[0166] Impurity regions 130, 131, 132, 134, and 135 for constituting the second transfer transistor Tr2, the reset transistor Tr3, the amplifying transistor Tr4, and the selecting transistor Tr5 are formed in desired regions on the surface side of the P-type well layer 129. These impurity regions 130, 131, 132, 134, and 135 are formed by implanting N-type impurity ions at a high concentration into desired regions of the P-type well layer 129.

[0167] Impurity region 130 serves as the source of the second transfer transistor Tr2. Furthermore, impurity region 131 is shared by the drain of the second transfer transistor Tr2 and the source of the reset transistor Tr3 and serves as a floating diffusion region from which signal charge is read. Furthermore, impurity region 132 is shared by the drain of the reset transistor Tr3 and the source of the amplifier transistor Tr4. Furthermore, impurity region 134 is shared by the drain of the amplifier transistor Tr4 and the source of the select transistor Tr5. Furthermore, impurity region 135 serves as the drain of the select transistor Tr5. Therefore, the region of the P-type well layer 129 between impurity regions 130, 131, 132, 134, and 135 serves as the channel portion constituting each MOS transistor.

[0168] A multilayer wiring layer 136 is formed on a semiconductor substrate 128 above a P-type well layer 129 having impurity regions 130, 131, 132, 134, and 135. In the multilayer wiring layer 136, gate electrodes 138, 139, 140, and 141, which constitute each MOS transistor, a first wiring layer M1′, and a second wiring layer M2′ are stacked with an interlayer insulating film 137 interposed therebetween.

[0169] Gate electrodes 138, 139, 140, and 141 are formed on the channel portions of the respective MOS transistors, with a gate insulating film (not shown) interposed therebetween. Gate electrode 138, formed above P-type well layer 129 between impurity regions 130 and 131, serves as gate electrode 138 for second transfer transistor Tr2. Furthermore, gate electrode 139, formed above P-type well layer 129 between impurity regions 131 and 132, serves as the gate electrode for reset transistor Tr3. Furthermore, gate electrode 140, formed above P-type well layer 129 between impurity regions 132 and 134, serves as the gate electrode for amplifier transistor Tr4. Furthermore, gate electrode 141, formed above P-type well layer 129 between impurity regions 134 and 135, serves as the gate electrode for select transistor Tr5.

[0170] The first wiring layer M1′ is formed above the gate electrodes 138, 139, 140, and 141 via the interlayer insulating film 137. In addition, the first connection wiring 150, the second connection wiring 149, the selection wiring 148, and the vertical signal line 109 are formed in the first wiring layer M1′ (see FIG. Figure 20 ). The first connecting wiring 150 is connected to the impurity region 130 serving as the source of the second transfer transistor Tr2 via a contact portion 142 formed in the interlayer insulating film 137. The second connecting wiring 149 is connected to the impurity region 131 and the gate electrode 140 of the amplifier transistor Tr4 via contacts 143 and 144 formed in the interlayer insulating film 137. That is, the impurity region 131 serving as a floating diffusion region and the gate electrode 140 of the amplifier transistor Tr4 are electrically connected via the second connecting wiring 149. In addition, the selection wiring 148 is connected to the gate electrode 141 of the selection transistor Tr5 via a contact portion 145 formed in the interlayer insulating film 137. Therefore, a selection pulse is supplied from the selection wiring 148 to the gate electrode 141 of the selection transistor Tr5. In addition, the vertical signal line 109 (refer to Figure 20 ) is connected to the impurity region 135 serving as the drain of the selection transistor Tr5 via a contact portion 146 formed in the interlayer insulating film 137.

[0171] In the second wiring layer M2′, a third connecting wiring 152 and a fourth connecting wiring 151 are formed. The third connecting wiring 152 is connected to the first connecting wiring 150 via a contact portion 147 formed in the interlayer insulating film 137. Furthermore, the fourth connecting wiring 151 is formed to extend to a predetermined area. Furthermore, a first transmission wiring (not shown) formed in the multilayer wiring layer 136 of the second substrate 181 is connected to the fourth connecting wiring 151, and a first transmission pulse is supplied from the first transmission wiring to the fourth connecting wiring 151.

[0172] The substrate connection region 195 is formed above the third connection wiring 152 and the fourth connection wiring 151 in the multilayer wiring layer 136. In the substrate connection region 195, the charge accumulation capacitor section 153 is formed above the fourth connection wiring 151 of the second wiring layer M2′, and the third wiring layer M3′ is formed above the second wiring layer M2′ with the charge accumulation capacitor section 153 interposed therebetween. In other words, the charge accumulation capacitor section 153 is inserted between the second wiring layer M2′ and the third wiring layer M3′. As the charge accumulation capacitor section 153, a capacitor having an MIM structure can be used.

[0173] The third wiring layer M3′ includes a first connection electrode 156 and a second connection electrode 157, each of which is exposed from the front surface of the substrate connection region 195. The first connection electrode 156 is connected to the third connection wiring 152 formed on the second wiring layer M2′ via a contact portion 155 formed in the interlayer insulating film 196. The first connection electrode 156 is also formed so as to extend above the fourth connection wiring 151 formed on the second wiring layer M2′ via the charge storage capacitor 153. Furthermore, the second connection electrode 157 is connected to the fourth connection wiring 151 formed on the second wiring layer M2′ via a contact portion 154 formed in the interlayer insulating film 196.

[0174] Here, although Figure 23B Although not shown in the figure, the second transfer wiring for supplying the second transfer pulse is connected to the gate electrode 138 of the second transfer transistor Tr2. Similarly, the reset wiring for supplying the reset pulse is connected to the gate electrode 139 of the reset transistor Tr3. Therefore, the second transfer wiring and the reset wiring are formed by the desired wiring layer formed in the multilayer wiring layer 136.

[0175] Therefore, the solid-state imaging device 101 of this modified example connects the first connection electrode 127 and the second connection electrode 126 of the first substrate 180 to the first connection electrode 156 and the second connection electrode 157 of the second substrate 181 by laminating the first substrate 180 onto the second substrate 181. Therefore, when the first substrate 180 and the second substrate 181 are bonded together, the impurity region 116 and the charge storage capacitor 153 that constitute the first transfer transistor Tr1, and the impurity region 130 that constitutes the second transfer transistor Tr2 are electrically connected. Furthermore, in the solid-state imaging device 101 of this modified example, when the first substrate 180 and the second substrate 181 are laminated and bonded together, the photoelectric conversion portion PD and the charge storage capacitor 153 are three-dimensionally stacked.

[0176] Furthermore, in the solid-state imaging device 101 of this modified example, the first connection electrode 156 functions as a light-shielding film, and the impurity region 130, which serves as the source of the second transfer transistor Tr2, is shielded from light by the first connection electrode 156. Consequently, the amount of light incident on the impurity region 130 is reduced, and the generation of unnecessary signal charge is suppressed, thereby reducing color mixing. Therefore, in this case, all regions except the opening of the photoelectric converter PD are preferably shielded from light.

[0177] Next, we will refer to Figure 24 A method of driving the solid-state imaging device 101 according to this modification will be described. Figure 24 is a circuit configuration for one pixel of the solid-state imaging device 101 of this modification, and Figure 25 This is a circuit structure for four pixels arranged in two rows and two columns adjacent to each other.

[0178] Figure 24 The line a in φ represents an electrode connection surface between the first connection electrode 127 and the second connection electrode 126 formed in the first substrate 180 and the first connection electrode 156 and the second connection electrode 157 formed in the second substrate 181 .

[0179] The anode side of the photodiode as the photoelectric conversion unit PD is grounded, and the cathode side is connected to the source of the first transfer transistor Tr1. Figure 22 Not shown in the figure, but Figure 24 and Figure 25 As shown, a reset transistor Tr6 for the photoelectric converter is formed in the first substrate 180, and the drain of the reset transistor Tr6 for the photoelectric converter is connected to the cathode side of the photoelectric converter PD. A power supply voltage wiring 185 for applying a power supply voltage VDD is connected to the source of the reset transistor Tr6 for the photoelectric converter. Furthermore, a reset wiring 175 for supplying a reset pulse φPDRST is connected to the gate electrode 162 of the reset transistor Tr6 for the photoelectric converter.

[0180] The drain of the first transfer transistor Tr1 is connected to the source of the second transfer transistor Tr2 via a first connection electrode 156 connected to one electrode of the charge storage capacitor 153. A first transfer wiring 184 for supplying a first transfer pulse φTRG1 is connected to the gate electrode 119 of the first transfer transistor Tr1. Furthermore, the first transfer wiring 184 is connected to a fourth connection wiring 151 connected to the other electrode of the charge storage capacitor 153.

[0181] The drain of the second transfer transistor Tr2 is connected to the source of the reset transistor Tr3 and also to the gate electrode 140 of the amplification transistor Tr4. A second transfer wiring 163 for supplying a second transfer pulse φTRG2 is connected to the gate electrode 138 of the second transfer transistor Tr2.

[0182] A power supply voltage wiring 188 for applying a power supply voltage VDD is connected to the drain of the reset transistor Tr3 , and a reset wiring 164 for supplying a reset pulse φRST is connected to the gate electrode 139 of the reset transistor Tr3 .

[0183] A power supply voltage wiring 188 for applying a power supply voltage VDD is connected to the source of the amplification transistor Tr4 , and the drain of the amplification transistor Tr4 is connected to the source of the selection transistor Tr5 .

[0184] The selection wiring 148 for supplying the selection pulse φSEL is connected to the gate electrode 141 of the selection transistor Tr5, and the drain of the selection transistor Tr5 is connected to the vertical signal line 109 (see Figure 20 ).

[0185] Therefore, if Figure 25 As shown, in the solid-state imaging device 101 in which pixels 102 are arranged in a 2D matrix, the second transfer wiring 163, reset wiring 164, and selection wiring 148, which are common to each row, are connected to the gate electrodes 138, 139, and 141, respectively. Therefore, the second transfer pulse φTRG2, reset pulse φRST, and selection pulse φSEL input to the gate electrodes 138, 139, and 141 are supplied from the vertical drive circuit 104. Although not shown, the reset pulse φPDRST supplied to the gate electrode 162 of the reset transistor Tr6 for the photoelectric conversion portion and the first transfer pulse φTRG1 supplied to the gate electrode 119 of the first transfer transistor Tr1 are also supplied from the vertical drive circuit 104.

[0186] In addition, the vertical signal line 109 (see Figure 20 ) is connected to the drain of the selection transistor Tr5.

[0187] The column signal processing circuit 105 provided for each column is connected to the subsequent stage of the vertical signal line 109. Therefore, the horizontal transistor Tr7 is connected to the subsequent stage of the column signal processing circuit 105, and a horizontal selection pulse is input from the horizontal drive circuit 106 to the horizontal transistor Tr7.

[0188] Next, we will use Figure 26 The timing diagram shown and Figure 25 A driving method of the solid-state imaging device 101 having the above-described circuit configuration will be described with reference to the circuit configuration of FIG.

[0189] First, the reset pulse φPDRST is set to a high level. This turns on the reset transistors Tr6 for the photoelectric converters of all pixels simultaneously, resetting the potential of the photoelectric converters PD of all pixels to the same potential as the power supply voltage VDD. Specifically, this operation discharges unnecessary charge accumulated in the photoelectric converters PD of all pixels, resetting the potential of the photoelectric converters PD to a specific value (VDD).

[0190] Next, the reset pulse φPDRST is set to a low level, turning off the reset transistors Tr6 for the photoelectric converters of all pixels simultaneously. Signal charge generation and accumulation begins in the photoelectric converters PD of all pixels. Signal charge is generated in accordance with the amount of light incident on the photoelectric converters PD, and the generated signal charge is accumulated in a potential well created by the pn junction effect in the photoelectric converters PD. In this case, it is assumed that the signal charge stored in the charge accumulation capacitors 153 was read out sequentially during the previous readout period, and the charge accumulation capacitors 153 are now empty. However, the timing for resetting the charge accumulation capacitors 153 can also be individually set.

[0191] Next, after the reset pulse φPDRST is set to low and before a predetermined accumulation time has elapsed, the first transfer pulse φTRG1 is set to high. This causes the first transfer transistors Tr1 of all pixels to be simultaneously turned on, and the signal charge stored in the photoelectric conversion portion PD is transferred to the impurity region 116. Then, since the impurity region 116, the impurity region 130, and the charge accumulation capacitor portion 153 formed in the first substrate 180 are electrically connected, the above-mentioned signal charge is temporarily accumulated in the impurity region 116, the impurity region 130, and the charge accumulation capacitor portion 153. In this manner, when the first transfer pulse φTRG1 is set to high, the signal charge is mainly accumulated in the charge accumulation capacitor portion 153.

[0192] Then, the first transfer pulse φTRG1 is set to low and thereby the first transfer transistors Tr1 of all pixels are turned off, thereby transferring the signal charges mainly accumulated in the charge accumulation capacitor 153 to the depletion layers of the impurity region 116 and the impurity region 130. Figure 26 As shown, the time from when the reset pulse φPDRST is set to low until the first transfer pulse φTRG1 is set to low again is the cumulative exposure time (electronic shutter time). Here, when the first transfer pulse φTRG1 is set to high and the signal charge is transferred from the photoelectric converter PD to the charge accumulation capacitor 153, the potential of the first transfer pulse φTRG1 is set to a potential that enables the signal charge from the photoelectric converter PD to be completely transferred.

[0193] Next, the reset pulse φPDRST is set high, turning on the reset transistor Tr6 for the photoelectric converter in all pixels and resetting the photoelectric converter PD. This prevents the amount of signal charge accumulated in the photoelectric converter PD, which exceeds the maximum charge capacity of the photoelectric converter PD, from overflowing into the charge accumulation capacitor 153 while the signal charge stored in the charge accumulation capacitor 153 is read out. Alternatively, the photoelectric converter PD is reset to the same potential as the power supply voltage VDD to prepare for the next accumulation of signal charge. While signal charge is accumulating in the charge accumulation capacitor 153 and the impurity regions 116 and 130, a potential capable of forming an inversion layer on the surface of the charge accumulation capacitor 153 can be applied as the potential of the first transfer pulse φTRG1. This suppresses the generation of dark current during the accumulation of signal charge.

[0194] Then, the selection pulse φSEL(1) is set high, the selection transistor Tr5 in the first row is turned on, and thereby the pixel 102 in the first row is selected. When the selection pulse φSEL(1) in the first row is set high, the reset pulse φRST(1) is set high, and thereby the reset transistor Tr3 in the first row is turned on. Thereby, the potential of the impurity region 131 as the floating diffusion region connected to the gate electrode 140 of the amplifier transistor Tr4 is reset to the same potential as the power supply voltage VDD. In this case, the output of the amplifier transistor Tr4 when reset is transmitted via the vertical signal line 109 (refer to Figure 20 ) and is stored in the column signal processing circuit 105.

[0195] Next, the second transfer pulse φTRG2(1) is set to high, thereby turning on the second transfer transistor Tr2 of the pixel 102 in the first row, and transferring the signal charge in the impurity region 130 and the impurity region 116 of the pixel 102 in the first row to the impurity region 131 as the floating diffusion region. In this case, the potential of the second transfer pulse φTRG2(1) is set to a potential that enables the signal charge to be completely transferred from the impurity region 130 and the impurity region 116 to the impurity region 131. When the signal charge is read out to the impurity region 131, the potential of the impurity region 131 as the floating diffusion region changes, and a signal voltage corresponding to the potential change is applied to the gate electrode 140 of the amplifier transistor Tr4. Therefore, the signal voltage amplified by the amplifier transistor Tr4 is output to the vertical signal line 109 (refer to Figure 20 ).

[0196] Therefore, the signal output to the vertical signal line 109 (see Figure 20) is sent to the column signal processing circuit 105. In the column signal processing circuit 105, the difference between the output during the reset period previously stored and the amplified signal voltage is output as the pixel signal of the pixel 102 in the first row. Therefore, when the horizontal transistors Tr7 are sequentially turned on by the horizontal driving circuit 106, the pixel signal of the pixel 102 in the first row is output via the output circuit 107 (refer to Figure 20 ) are serially output from the output terminal Vout.

[0197] Then, after the selection pulse φSEL(1) is set to low, the selection pulse φSEL(2) is set to high, thereby turning on the selection transistor Tr5 in the second row and selecting the pixel 102 in the second row. When the selection pulse φSEL(2) of the selection transistor Tr5 in the second row is set to high, the states of the second transfer pulse φTRG2(2) and the reset pulse φRST(2) are driven in the same manner as the second transfer pulse φTRG2(1) and the reset pulse φRST(1) in the first row. Thus, the same readout operation as the readout operation in the first row described above is performed for the pixel 102 in the second row.

[0198] As can be understood from the above description, in the solid-state imaging device 101 of this modified example, the cumulative exposure time for generating and accumulating signal charges in the photoelectric conversion unit PD is performed simultaneously for all pixels. That is, since each pixel 102 has a charge accumulation capacitor 153, an electronic shutter operation (global shutter operation) can be performed simultaneously for all pixels. Therefore, the signal charges accumulated simultaneously for all pixels are accumulated and maintained in each charge accumulation capacitor 153, and are read out in the impurity region 131 in a line-sequential manner, and the signal voltage amplified based on the potential of the signal charge is transmitted via the vertical signal line 109 (refer to Figure 20 ) output.

[0199] An example of a solid-state imaging device to which the technology according to the present invention can be applied has been described above. The technology according to the present invention can be applied to the first substrate 180, the second substrate 181, the first connection electrode 127, the first connection electrode 156, and the charge accumulation capacitor 153 in the configuration described above. Specifically, Figure 1 The first substrate 2 can be applied to Figure 22 The first substrate 180, Figure 1 The second substrate 3 can be applied to Figure 22 The second substrate 181, Figure 1 The first electrode pad 8 in the embodiment can be applied to Figure 22 The first connection electrode 127, Figure 1 The second electrode 17 can be applied to Figure 22 The first connection electrode 156 in the embodiment of the present invention is Figure 1 The second capacitor 20 can be applied to Figure 22 The charge accumulation capacitor 153 in FIG. Figure 1 The second capacitor 20 in the embodiment can form a charge accumulation capacitor 153 for accumulating signal charges generated in the photoelectric conversion portion PD when a global shutter operation is performed. When the technology according to the present invention is applied to the first substrate 180, the second substrate 181, the first connection electrode 127, the first connection electrode 156, and the charge accumulation capacitor 153, since the performance degradation of the capacitor (charge accumulation capacitor 153) caused by the bonding process can be suppressed, a better captured image can be obtained.

[0200] Here, in this modification, an example is shown in which the charge accumulation capacitor section 153 is formed in the substrate connection area 195 of the second substrate 181, but other configurations may be adopted. For example, the charge accumulation capacitor section 153 may be formed in the substrate connection area 190 of the first substrate 180. When the charge accumulation capacitor section 153 is formed in the substrate connection area 190, Figure 1 The first capacitor 10 can be applied to the charge accumulation capacitor 153. Figure 1 The first capacitor 10 in FIG. 1 can form a charge accumulation capacitance portion 153 for accumulating signal charges generated in the photoelectric conversion portion PD when the global shutter operation is performed.

[0201] <3. Application Examples of Electronic Devices>

[0202] The technology according to the present invention (the present technology) can be applied to various electronic devices such as imaging devices such as digital cameras and digital video cameras, mobile phones with an imaging function, or other devices with an imaging function.

[0203] Figure 27 1 is a diagram showing one example of a schematic configuration of an imaging device as an electronic device to which the technology of the present invention (present technology) is applicable.

[0204] like Figure 27 As shown, the imaging device 201 includes an optical system 202, a shutter device 203, a solid-state imaging element 204, a control circuit 205, a signal processing circuit 206, a monitor 207, and a memory 208, and can capture still images and moving images.

[0205] The optical system 202 includes one or more lenses, and guides light (incident light) from a subject to the solid-state imaging element 204 , thereby forming an image on a light-receiving surface of the solid-state imaging element 204 .

[0206] The shutter device 203 is provided between the optical system 202 and the solid-state imaging element 204 , and controls a light irradiation period and a light shielding period for the solid-state imaging element 204 according to control of the control circuit 205 .

[0207] The solid-state imaging element 204 is formed from a package containing the solid-state imaging element 204. The solid-state imaging element 204 accumulates signal charge for a predetermined period of time in response to light formed on a light-receiving surface via the optical system 202 and the shutter device 203. The signal charge accumulated in the solid-state imaging element 204 is transferred based on a drive signal (timing signal) supplied from the control circuit 205.

[0208] The control circuit 205 outputs a drive signal for controlling a transfer operation of the solid-state imaging element 204 and a shutter operation of the shutter device 203 , and thereby drives the solid-state imaging element 204 and the shutter device 203 .

[0209] The signal processing circuit 206 performs various signal processing on the signal charge output from the solid-state imaging element 204. The image (image data) obtained by the signal processing performed by the signal processing circuit 206 is supplied to the monitor 207 to be displayed on the monitor 207, and is supplied to the memory 208 to be stored (recorded) in the memory 208.

[0210] An example of an electronic device (imaging device) to which the technology of the present invention is applicable has been described above. The technology according to the present invention can be applied to the solid-state imaging element 204 in the configuration described above. Specifically, Figure 21 and Figure 22 The solid-state imaging device in can be applied to the solid-state imaging element 204. When the technology according to the present invention is applied to the solid-state imaging element 204, since the performance degradation of the capacitor due to the bonding process can be suppressed, a better captured image can be obtained.

[0211] <4. Application Examples of Mobile Objects>

[0212] The technology according to the present invention (this technology) can be applied to devices installed on any type of mobile body such as automobiles, electric vehicles, hybrid vehicles, two-wheeled vehicles, bicycles, personal mobility vehicles, airplanes, unmanned aerial vehicles, ships, robots, etc.

[0213] Figure 28 is a block diagram of a schematic configuration example of a vehicle control system as one example of a mobile body control system to which the technology according to the present invention is applicable.

[0214] The vehicle control system 12000 includes a plurality of electronic control units interconnected via a communication network 12001. Figure 28In the illustrated example, vehicle control system 12000 includes a drive system control unit 12010, a body system control unit 12020, an exterior information detection unit 12030, an interior information detection unit 12040, and an integrated control unit 12050. Furthermore, the functional configuration of integrated control unit 12050 includes a microcomputer 12051, an audio and video output unit 12052, and an in-vehicle network interface (I / F) 12053.

[0215] Drive system control unit 12010 controls the operation of devices related to the vehicle's drive system according to various programs. For example, drive system control unit 12010 functions as a control device for various devices such as a drive force generating device such as an internal combustion engine or a drive motor for generating vehicle drive force; a drive force transmission mechanism for transmitting drive force to wheels; a steering mechanism for adjusting the vehicle's steering angle; and a braking device for generating vehicle braking force.

[0216] The body system control unit 12020 controls the operation of various devices installed in the vehicle body according to various programs. For example, the body system control unit 12020 functions as a controller for various devices such as the keyless entry system, the smart key system, the power windows, or various lights such as the headlights, backup lights, brake lights, turn signals, and fog lights. In this case, radio waves emitted from a portable device that replaces a key or signals from various switches can be input to the body system control unit 12020. The body system control unit 12020 receives these radio waves or signals and controls the vehicle's door locks, power windows, and lights.

[0217] The vehicle exterior information detection unit 12030 detects information outside the vehicle in which the vehicle control system 12000 is installed. For example, the vehicle exterior information detection unit 12030 is connected to the camera unit 12031. The vehicle exterior information detection unit 12030 causes the camera unit 12031 to capture an image of the vehicle exterior and receives the captured image. Based on the received image, the vehicle exterior information detection unit 12030 can perform object detection processing or distance detection processing for objects such as people, vehicles, obstacles, signs, and text on the road surface.

[0218] The imaging unit 12031 is an optical sensor that receives light and outputs an electrical signal corresponding to the amount of light received. The imaging unit 12031 can output the electrical signal as an image or as distance measurement information. The light received by the imaging unit 12031 can be visible light or non-visible light such as infrared light.

[0219] The in-vehicle information detection unit 12040 detects information about the interior of the vehicle. For example, the in-vehicle information detection unit 12040 is connected to a driver state detection unit 12041 for detecting the driver's condition. For example, the driver state detection unit 12041 includes a camera that captures the driver's image. Based on the detection information input from the driver state detection unit 12041, the in-vehicle information detection unit 12040 can calculate the driver's level of fatigue or concentration, and can also determine whether the driver is dozing off.

[0220] Based on the information inside or outside the vehicle acquired by the vehicle exterior information detection unit 12030 or the vehicle interior information detection unit 12040, the microcomputer 12051 can calculate a control target value for a driving force generating device, a steering mechanism, or a braking device, and output a control instruction to the drive system control unit 12010. For example, the microcomputer 12051 can perform coordinated control for implementing functions of an advanced driver assistance system (ADAS), including functions such as vehicle collision avoidance, vehicle impact mitigation, following driving based on vehicle-to-vehicle distance, vehicle constant speed driving, vehicle collision warning, and vehicle lane departure warning.

[0221] In addition, based on the information around the vehicle obtained by the external information detection unit 12030 or the internal information detection unit 12040, the microcomputer 12051 can perform coordinated control for achieving automatic driving, etc., so that the vehicle can drive autonomously without the driver's operation, by controlling the driving force generating device, steering mechanism or braking device, etc.

[0222] Furthermore, based on the information outside the vehicle obtained by the vehicle exterior information detection unit 12030, the microcomputer 12051 can output a control command to the body system control unit 12020. For example, based on the position of the preceding vehicle or oncoming vehicle detected by the vehicle exterior information detection unit 12030, the microcomputer 12051 can perform coordinated control such as switching the headlights from high beam to low beam to achieve anti-glare.

[0223] The audio and video output unit 12052 transmits an output signal of at least one of audio and video to an output device capable of visually or auditorily notifying the vehicle passengers or the outside of the vehicle of information. Figure 28 In the illustrated example, as output devices, an audio speaker 12061, a display portion 12062, and an instrument panel 12063 are illustrated. For example, the display portion 12062 may include at least one of an onboard display and a head-up display.

[0224] Figure 29 This is a diagram showing an example of the installation position of the camera unit 12031.

[0225] exist Figure 29 , the vehicle 12100 includes imaging units 12101 , 12102 , 12103 , 12104 , and 12105 as the imaging unit 12031 .

[0226] Camera units 12101, 12102, 12103, 12104, and 12105 are located at various locations on vehicle 12100, such as the front nose, sideview mirrors, rear bumper, trunk lid, and the upper portion of the windshield inside the vehicle. Camera unit 12101 located at the front nose and camera unit 12105 located at the upper portion of the windshield inside the vehicle primarily capture images in front of vehicle 12100. Camera units 12102 and 12103 located at the sideview mirrors primarily capture images from the sides of vehicle 12100. Camera unit 12104 located at the rear bumper or trunk lid primarily captures images from the rear of vehicle 12100. The forward images captured by cameras 12101 and 12105 are primarily used to detect vehicles ahead, pedestrians, obstacles, traffic lights, traffic signs, lanes, and the like.

[0227] here, Figure 29 An example of the imaging ranges of the imaging units 12101 to 12104 is shown. Imaging range 12111 represents the imaging range of the imaging unit 12101 located at the front nose, imaging ranges 12112 and 12113 represent the imaging ranges of the imaging units 12102 and 12103 located at the side mirrors, respectively, and imaging range 12114 represents the imaging range of the imaging unit 12104 located at the rear bumper or trunk door. For example, by superimposing the image data captured by the imaging units 12101 to 12104, a bird's-eye view image of the vehicle 12100 can be obtained.

[0228] At least one of the imaging units 12101 to 12104 may have a function of acquiring distance information. For example, at least one of the imaging units 12101 to 12104 may be a stereo camera including a plurality of imaging devices, or an imaging device having pixels for phase difference detection.

[0229] For example, based on the distance information obtained from imaging units 12101 to 12104, microcomputer 12051 can determine the distance to each 3D object within imaging ranges 12111 to 12114 and the change in this distance over time (relative speed to vehicle 12100). Furthermore, microcomputer 12051 can identify as a preceding vehicle a 3D object that is the closest 3D object on the path of vehicle 12100 and is traveling in the same direction as vehicle 12100 at a predetermined speed (e.g., 0 km / h or higher). Furthermore, microcomputer 12051 can set a predetermined distance to be maintained in front of the preceding vehicle and execute automatic braking control (including follow-up stop control) and automatic acceleration control (including follow-up start control). In this way, coordinated control can be implemented to achieve autonomous driving, such as enabling the vehicle to travel autonomously without driver input.

[0230] For example, based on the distance information obtained from the imaging units 12101 to 12104, the microcomputer 12051 can classify 3D object data related to 3D objects into data for two-wheeled vehicles, ordinary cars, large vehicles, pedestrians, utility poles, or other 3D objects. It then extracts this data and uses the extracted data to automatically avoid obstacles. For example, the microcomputer 12051 classifies obstacles around the vehicle 12100 into those that the driver of the vehicle 12100 can visually identify and those that are difficult for the driver to visually identify. In this way, the microcomputer 12051 determines a collision risk, which indicates the degree of risk of collision with each obstacle. If the collision risk is equal to or greater than a set value, indicating a potential collision, the microcomputer 12051 issues a warning to the driver via the audio speaker 12061 or display unit 12062, or initiates forced deceleration or evasive steering via the drive system control unit 12010, thereby providing driving assistance that can avoid collisions.

[0231] At least one of the imaging units 12101 to 12104 may be an infrared camera that detects infrared rays. For example, the microcomputer 12051 may identify pedestrians by determining whether a pedestrian exists in images captured by the imaging units 12101 to 12104. This pedestrian identification is performed, for example, by extracting feature points from the images captured by the imaging units 12101 to 12104, which are infrared cameras; and performing pattern matching on a series of feature points representing the outline of an object to determine whether the object is a pedestrian. If the microcomputer 12051 determines that a pedestrian exists in the images captured by the imaging units 12101 to 12104 and identifies the pedestrian, the audio and video output unit 12052 controls the display unit 12062 to display a square outline superimposed on the identified pedestrian for emphasis. Alternatively, the audio and video output unit 12052 may control the display unit 12062 to display an icon representing the pedestrian at a desired location.

[0232] An example of a vehicle control system to which the technology of the present invention is applicable has been described above. The technology of the present invention can be applied to the camera unit 12031 in the above-described configuration. Specifically, Figure 21 and Figure 22 The solid-state imaging device in can be applied to the imaging section 12031. When the technology according to the present invention is applied to the imaging section 12031, since degradation of capacitor performance due to the bonding process can be suppressed, a better captured image can be obtained and driver fatigue can be reduced.

[0233] <5. Application Examples of Endoscopic Surgery Systems>

[0234] The technology according to the present invention (the present technology) can be applied to, for example, an endoscopic surgical system.

[0235] Figure 30 : is a diagram showing one example of a schematic configuration of an endoscopic surgery system to which the technology according to the present invention (the present technology) can be applied.

[0236] Figure 30 The figure shows a state in which a surgeon (doctor) 11131 performs surgery on a patient 11132 on a bed 11133 using an endoscopic surgery system 11000. As shown in the figure, the endoscopic surgery system 11000 includes an endoscope 11100, other surgical instruments 11110 such as a pneumoperitoneum tube 11111 and an energy treatment instrument 11112, a support arm device 11120 for supporting the endoscope 11100, and a cart 11200 equipped with various instruments used for endoscopic surgery.

[0237] The endoscope 11100 includes a lens barrel 11101, a region of a predetermined length from the front end of which is inserted into a body cavity of a patient 11132, and a camera head 11102 connected to the base end of the lens barrel 11101. In the example shown in the figure, the endoscope 11100 is configured as a so-called hard scope having a rigid lens barrel 11101, but the endoscope 11100 may be configured as a so-called soft scope having a flexible lens barrel.

[0238] An opening is provided at the front end of the lens barrel 11101, into which the objective lens is embedded. A light source device 11203 is connected to the endoscope 11100. Light generated by the light source device 11203 is guided to the front end of the lens barrel via a light guide extending within the lens barrel 11101. This light is then directed toward an object to be observed within the body cavity of the patient 11132 via the objective lens. The endoscope 11100 may be a straight-view mirror, an oblique-view mirror, or a side-view mirror.

[0239] The camera head 11102 includes an optical system and an imaging element. Light reflected from an observation object (observation light) is focused onto the imaging element through the optical system. The imaging element performs photoelectric conversion on the observation light and generates an electrical signal corresponding to the observation light, i.e., an image signal corresponding to the observed image. This image signal is transmitted as RAW data to the camera control unit (CCU) 11201.

[0240] The CCU 11201 is composed of a central processing unit (CPU) or a graphics processing unit (GPU), and comprehensively controls the operations of the endoscope 11100 and the display device 11202. In addition, the CCU 11201 receives image signals from the camera head 11102 and performs various image processing such as development processing (demosaicing) on the image signals to display an image based on the image signals.

[0241] Under the control of the CCU 11201 , the display device 11202 displays an image based on an image signal on which image processing has been performed by the CCU 11201 .

[0242] The light source device 11203 is constituted by a light source such as a light emitting diode (LED), for example, and supplies irradiation light to the endoscope 11100 when imaging a surgical site or the like.

[0243] The input device 11204 is an input interface for the endoscopic surgery system 11000. The user can input various information and commands to the endoscopic surgery system 11000 via the input device 11204. For example, the user can input commands for changing the imaging conditions (such as the type of irradiation light, magnification, and focal length) of the endoscope 11100.

[0244] The treatment device control unit 11205 controls the driving of the energy treatment device 11112 used for cauterization and incision of tissue, or sealing of blood vessels. The pneumoperitoneum device 11206 injects gas into the body cavity of the patient 11132 via the pneumoperitoneum tube 11111 to inflate the cavity, thereby ensuring the field of view of the endoscope 11100 and the operating space for the surgeon. The recorder 11207 is a device capable of recording various information related to the surgery. The printer 11208 is a device capable of printing various information related to the surgery in various formats, such as text, images, or graphics.

[0245] Here, the light source device 11203 used to supply irradiation light to the endoscope 11100 when imaging the surgical site can include, for example, an LED, a laser light source, or a white light source composed of a combination of laser light sources. When the white light source is composed of a combination of RGB laser light sources, since the output intensity and output timing of each color (various wavelengths) can be controlled with high precision, the light source device 11203 can adjust the white balance of the captured image. In this case, by irradiating the observation object with laser light from each of the RGB laser light sources in a time-division manner and controlling the drive of the imaging element of the camera head 11102 in synchronization with the irradiation timing, images corresponding to each of the RGB light sources can be captured in a time-division manner. According to this method, a color image can be obtained without providing a color filter in the imaging element.

[0246] Furthermore, the light source device 11203 can be controlled so that the intensity of the light output changes at predetermined intervals. By controlling the driving of the imaging element of the camera head 11102 in synchronization with the timing of the light intensity changes, images can be acquired in a time-division manner and synthesized to generate a so-called high dynamic range image without underexposure or overexposure.

[0247] In addition, the light source device 11203 can be configured to provide light in a predetermined wavelength band corresponding to special light observation. In special light observation, for example, so-called narrowband light observation (i.e., narrowband imaging) can be performed, whereby light having a narrower bandwidth than that used for conventional observation (i.e., white light) is emitted by utilizing the wavelength dependence of light absorption in body tissue, allowing high-contrast imaging of predetermined tissue, such as blood vessels in the surface layer of a mucosa. Alternatively, in special light observation, fluorescence observation can be performed, where images are obtained using fluorescence generated by irradiating excitation light. This fluorescence observation can be performed, for example, by irradiating body tissue with excitation light to observe fluorescence from the body tissue (autofluorescence observation), or by locally injecting an agent, such as indocyanine green (ICG), into the body tissue and irradiating the body tissue with excitation light corresponding to the fluorescence wavelength of the agent to obtain a fluorescence image. The light source device 11203 can be configured to provide narrowband light and / or excitation light corresponding to such special light observation.

[0248] Figure 31 It shows Figure 30 A block diagram showing an example of the functional configuration of the camera head 11102 and the CCU 11201 is shown.

[0249] The camera head 11102 includes a lens unit 11401, an imaging unit 11402, a driving unit 11403, a communication unit 11404, and a camera head control unit 11405. The CCU 11201 includes a communication unit 11411, an image processing unit 11412, and a control unit 11413. The camera head 11102 and the CCU 11201 are connected to each other via a transmission cable 11400 so as to be communicable with each other.

[0250] The lens unit 11401 is an optical system provided at the connection portion with the lens barrel 11101. Observation light taken in from the front end of the lens barrel 11101 is guided to the camera head 11102 and incident on the lens unit 11401. The lens unit 11401 is composed of a combination of multiple lenses including a zoom lens and a focus lens.

[0251] The imaging unit 11402 includes an imaging element. The imaging element used to constitute the imaging unit 11402 can be one element (so-called single-board type) or multiple elements (so-called multi-board type). In the case where the imaging unit 11402 is constructed as a multi-board type, for example, each imaging element can be used to generate an image signal corresponding to each of RGB, and these image signals can be synthesized to obtain a color image. Alternatively, the imaging unit 11402 may include a pair of imaging elements, which are respectively used to obtain an image signal for the right eye and an image signal for the left eye corresponding to a 3D (three-dimensional) display. By performing a 3D display, the surgeon 11131 can more accurately grasp the depth of the biological tissue in the surgical site. Note that in the case where the imaging unit 11402 is constructed as a multi-board type, a plurality of lens units 11401 can be provided corresponding to the plurality of imaging elements.

[0252] Furthermore, the imaging unit 11402 does not necessarily need to be provided in the camera head 11102. For example, the imaging unit 11402 may be provided inside the lens barrel 11101 and immediately behind the objective lens.

[0253] The driving section 11403 includes an actuator and moves the zoom lens and focus lens of the lens unit 11401 by a predetermined distance along the optical axis under the control of the camera head control section 11405. Thus, the magnification and focus of the image captured by the imaging section 11402 can be appropriately adjusted.

[0254] The communication unit 11404 includes a communication device for transmitting and receiving various information to and from the CCU 11201. The communication unit 11404 transmits the image signal acquired from the imaging unit 11402 to the CCU 11201 via the transmission cable 11400 as RAW data.

[0255] Furthermore, the communication unit 11404 receives a control signal for controlling the driving of the camera head 11102 from the CCU 11201, and supplies the control signal to the camera head control unit 11405. For example, the control signal includes information related to imaging conditions such as information for specifying the frame rate of the captured image, information for specifying the exposure value during imaging, and / or information for specifying the magnification and focus of the captured image.

[0256] Here, the above-mentioned imaging conditions such as the frame rate, exposure value, magnification, and focus can be appropriately specified by the user, or can be automatically set based on the acquired image signal by the control unit 11413 of the CCU 11201. In the latter case, the endoscope 11100 is equipped with a so-called automatic exposure (AE) function, an automatic focus (AF) function, and an automatic white balance (AWB) function.

[0257] The camera head control section 11405 controls the driving of the camera head 11102 based on a control signal received from the CCU 11201 via the communication section 11404 .

[0258] The communication unit 11411 includes a communication device for transmitting and receiving various information to and from the camera head 11102. The communication unit 11411 receives an image signal transmitted from the camera head 11102 via the transmission cable 11400.

[0259] Furthermore, the communication unit 11411 transmits a control signal for controlling the driving of the camera head 11102 to the camera head 11102. The image signal and the control signal can be transmitted by electrical communication, optical communication, or the like.

[0260] The image processing unit 11412 performs various image processing on the image signal transmitted as RAW data from the camera head 11102 .

[0261] The control unit 11413 performs various controls related to imaging of the surgical site, etc. using the endoscope 11100 and displaying images obtained by imaging the surgical site, etc. For example, the control unit 11413 generates a control signal for controlling the driving of the camera head 11102 .

[0262] Furthermore, the control unit 11413 causes the display device 11202 to display a captured image reflecting the surgical site, etc., based on the image signal processed by the image processing unit 11412. In this case, the control unit 11413 can use various image recognition technologies to identify various objects within the captured image. For example, the control unit 11413 can detect the edge shape and color of objects contained in the captured image to identify surgical instruments such as forceps, specific biological sites, bleeding, and mist generated when the energy treatment device 11112 is used. When the control unit 11413 causes the display device 11202 to display the captured image, it can use the recognition results to cause various surgical support information to be superimposed on the image of the surgical site. When this superimposed display of surgical support information is presented to the surgeon 11131, the burden on the surgeon 11131 can be reduced, allowing the surgeon 11131 to perform the surgery reliably.

[0263] The transmission cable 11400 connecting the camera head 11102 and the CCU 11201 is an electrical signal cable capable of supporting electrical signal communication, an optical fiber capable of supporting optical communication, or a composite cable thereof.

[0264] Here, in the illustrated example, communication is performed in a wired manner by using the transmission cable 11400 , but communication between the camera head 11102 and the CCU 11201 can also be performed in a wireless manner.

[0265] An example of an endoscopic surgery system to which the technology of the present invention is applicable has been described above. The technology of the present invention can be applied to the imaging unit 11402 in the structure described above. Specifically, Figure 21 and Figure 22 The solid-state imaging device in can be applied to the imaging unit 11402. When the technology according to the present invention is applied to the imaging unit 11402, since the performance degradation of the capacitor due to the bonding process can be suppressed, a clearer surgical site image can be obtained, and the surgeon can reliably confirm the surgical site.

[0266] Although an endoscopic surgical system has been described as an example here, the technology according to the present invention can be applied to other systems, such as a microscope surgical system, etc.

[0267] In addition, the present technology may have the following technical solutions.

[0268] (1) A semiconductor device comprising:

[0269] a first substrate;

[0270] a second substrate bonded to the first substrate;

[0271] a first electrode disposed in the first substrate, wherein one surface of the first electrode is coplanar with a bonding surface between the first substrate and the second substrate;

[0272] a second electrode disposed in the second substrate, wherein one surface of the second electrode and the bonding surface are coplanar with each other, and the one surface of the second electrode is bonded to the one surface of the first electrode; and

[0273] At least one of a first capacitor and a second capacitor, wherein the first capacitor is disposed in the first substrate, and one electrode of the first capacitor is electrically connected to the other surface of the first electrode, and the second capacitor is disposed in the second substrate, and one electrode of the second capacitor is electrically connected to the other surface of the second electrode.

[0274] (2) The semiconductor device according to (1), wherein

[0275] The first electrode and the second electrode are copper electrodes made of pure copper or a copper alloy.

[0276] (3) The semiconductor device according to (1) or (2), wherein

[0277] The first electrode includes a first electrode pad and a first vertical interconnection path, one surface of the first electrode pad is located on the same plane as the bonding surface, and the first vertical interconnection path extends from the other surface of the first electrode pad, and

[0278] The second electrode includes a second electrode pad, one surface of the second electrode pad is coplanar with the bonding surface, and a second vertical interconnection path extends from the other surface of the second electrode pad.

[0279] (4) The semiconductor device according to any one of (1) to (3), wherein

[0280] The first electrode and the second electrode are each provided in plural numbers,

[0281] At least one of the first capacitor and the second capacitor is provided in plural, and

[0282] Two or more of the plurality of first capacitors or two or more of the plurality of second capacitors are electrically connected to the same wiring.

[0283] (5) The semiconductor device according to any one of (1) to (4), wherein

[0284] At least one of the first capacitor and the second capacitor includes: two electrodes facing each other; and an insulating film arranged between the two electrodes.

[0285] (6) The semiconductor device according to any one of (1) to (4), wherein

[0286] At least one of the first capacitor and the second capacitor forms a multilayer structure in which electrodes and insulating films are alternately and repeatedly arranged.

[0287] (7) The semiconductor device according to any one of (1) to (4), wherein

[0288] At least one of the first capacitor and the second capacitor includes a bottom portion and a side wall portion extending from an edge portion of the bottom portion in a direction intersecting the bottom portion.

[0289] (8) The semiconductor device according to any one of (1) to (7), wherein

[0290] The electrode material of the first capacitor and the second capacitor is tantalum, tantalum nitride, titanium, titanium nitride, tungsten nitride, zirconium nitride, or cobalt.

[0291] (9) The semiconductor device according to any one of (1) to (8), wherein

[0292] The insulating films of the first capacitor and the second capacitor are single-layer films made of any one of tantalum oxide, hafnium oxide, aluminum oxide, silicon nitride, and zirconium oxide, or multilayer films formed of a combination thereof.

[0293] (10) A solid-state imaging device comprising:

[0294] a sensor substrate in which a plurality of photoelectric conversion portions are arranged;

[0295] a logic substrate bonded to the sensor substrate, wherein a circuit for processing an electrical signal from the photoelectric conversion portion is integrated into the logic substrate;

[0296] a first electrode disposed in the sensor substrate, wherein one surface of the first electrode is coplanar with a bonding surface between the sensor substrate and the logic substrate;

[0297] a second electrode disposed in the logic substrate, wherein one surface of the second electrode is coplanar with the bonding surface and the one surface of the second electrode is bonded to the one surface of the first electrode; and

[0298] At least one of a first capacitor and a second capacitor, wherein the first capacitor is arranged in the sensor substrate, and one electrode of the first capacitor is electrically connected to the other surface of the first electrode, and the second capacitor is arranged in the logic substrate, and one electrode of the second capacitor is electrically connected to the other surface of the second electrode.

[0299] (11) The solid-state imaging device according to (10), wherein

[0300] At least one of the first capacitor and the second capacitor constitutes a charge accumulation capacitance portion for accumulating signal charges generated by the photoelectric conversion portion when a global shutter operation is performed.

[0301] (12) An electronic device comprising:

[0302] A solid-state imaging device comprising:

[0303] a sensor substrate in which a plurality of photoelectric conversion portions are arranged;

[0304] a logic substrate bonded to the sensor substrate, wherein a circuit for processing an electrical signal from the photoelectric conversion portion is integrated into the logic substrate;

[0305] a first electrode disposed in the sensor substrate, wherein one surface of the first electrode is coplanar with a bonding surface between the sensor substrate and the logic substrate;

[0306] a second electrode disposed in the logic substrate, wherein one surface of the second electrode is coplanar with the bonding surface and the one surface of the second electrode is bonded to the one surface of the first electrode; and

[0307] at least one of a first capacitor and a second capacitor, wherein the first capacitor is disposed in the sensor substrate and one electrode of the first capacitor is electrically connected to the other surface of the first electrode, and the second capacitor is disposed in the logic substrate and one electrode of the second capacitor is electrically connected to the other surface of the second electrode;

[0308] an optical lens for forming an image of image light from a subject on an imaging surface of the solid-state imaging device; and

[0309] A signal processing circuit performs signal processing on a signal output from the solid-state imaging device.

[0310] [Reference Signs List]

[0311] 1: Semiconductor devices

[0312] 2: First substrate

[0313] 3: Second substrate

[0314] 4: Interlayer insulation film

[0315] 5a: First wiring layer

[0316] 5b: Second wiring layer

[0317] 5c: The third wiring layer

[0318] 5d: Fourth wiring layer

[0319] 6: Interlayer insulation film

[0320] 7, 7a, 7b: First electrode

[0321] 8: First electrode pad

[0322] 9: First vertical interconnection path

[0323] 10: First capacitor

[0324] 11: Electrode

[0325] 12: Electrode

[0326] 13: Insulation film

[0327] 14: Interlayer insulation film

[0328] 15a: First wiring layer

[0329] 15b: Second wiring layer

[0330] 15c: The third wiring layer

[0331] 15d: Fourth wiring layer

[0332] 15e: Fifth wiring layer

[0333] 15f: Sixth wiring layer

[0334] 16: Interlayer insulation film

[0335] 17, 17a, 17b: second electrode

[0336] 18: Second electrode pad

[0337] 19: Second vertical interconnection path

[0338] 20: Second capacitor

[0339] 21: Electrode

[0340] 22: Electrode

[0341] 23: Insulation film

[0342] 24: Substrate connection area

[0343] 25: Pixel area

[0344] 26: I / O department (input / output unit)

[0345] 27: Drive

[0346] 28, 29: Insulating film

[0347] 30, 30a to 30e: Electrodes

[0348] 31, 32: Insulating film

[0349] 33: Bottom

[0350] 34, 35: Side wall

[0351] 36: Color filter

[0352] 37: Micro lens

Claims

1. A semiconductor device comprising: a first substrate; a second substrate bonded to the first substrate; a first electrode disposed in the first substrate, wherein one surface of the first electrode is coplanar with a bonding surface between the first substrate and the second substrate; a second electrode disposed in the second substrate, wherein one surface of the second electrode and the bonding surface are coplanar, and the one surface of the second electrode is bonded to the one surface of the first electrode; and At least one of a first capacitor and a second capacitor, wherein the first capacitor is disposed in the first substrate, and one electrode of the first capacitor is electrically connected to the other surface of the first electrode, and the second capacitor is disposed in the second substrate, and one electrode of the second capacitor is electrically connected to the other surface of the second electrode.

2. The semiconductor device according to claim 1, wherein The first electrode and the second electrode are copper electrodes made of pure copper or a copper alloy.

3. The semiconductor device according to claim 1, wherein The first electrode includes a first electrode pad and a first vertical interconnection path, one surface of the first electrode pad is coplanar with the bonding surface, and the first vertical interconnection path extends from the other surface of the first electrode pad, and The second electrode includes a second electrode pad, one surface of the second electrode pad is coplanar with the bonding surface, and a second vertical interconnection path extends from the other surface of the second electrode pad.

4. The semiconductor device according to claim 1, wherein The first electrode and the second electrode are each provided in plural numbers, At least one of the first capacitor and the second capacitor is provided in plural, and Two or more of the plurality of first capacitors or two or more of the plurality of second capacitors are electrically connected to the same wiring.

5. The semiconductor device according to claim 1, wherein At least one of the first capacitor and the second capacitor includes: two electrodes facing each other; and an insulating film arranged between the two electrodes. The semiconductor device according to claim 1 , wherein: At least one of the first capacitor and the second capacitor forms a multilayer structure in which electrodes and insulating films are alternately and repeatedly arranged.

7. The semiconductor device according to claim 1, wherein At least one of the first capacitor and the second capacitor includes a bottom portion and a side wall portion extending from an edge portion of the bottom portion in a direction intersecting the bottom portion.

8. The semiconductor device according to any one of claims 1 to 7, wherein The electrode material of the first capacitor and the second capacitor is tantalum, tantalum nitride, titanium, titanium nitride, tungsten nitride, zirconium nitride, or cobalt.

9. The semiconductor device according to any one of claims 1 to 7, wherein The insulating films of the first capacitor and the second capacitor are single-layer films made of any one of tantalum oxide, hafnium oxide, aluminum oxide, silicon nitride, and zirconium oxide, or multilayer films formed of a combination thereof.

10. A solid-state imaging device comprising: a sensor substrate in which a plurality of photoelectric conversion portions are arranged; a logic substrate bonded to the sensor substrate, wherein a circuit for processing an electrical signal from the photoelectric conversion portion is integrated into the logic substrate; a first electrode disposed in the sensor substrate, wherein one surface of the first electrode is coplanar with a bonding surface between the sensor substrate and the logic substrate; a second electrode disposed in the logic substrate, wherein one surface of the second electrode and the bonding surface are coplanar, and the one surface of the second electrode is bonded to the one surface of the first electrode; and At least one of a first capacitor and a second capacitor, wherein the first capacitor is arranged in the sensor substrate, and one electrode of the first capacitor is electrically connected to the other surface of the first electrode, and the second capacitor is arranged in the logic substrate, and one electrode of the second capacitor is electrically connected to the other surface of the second electrode.

11. The solid-state imaging device according to claim 10, wherein At least one of the first capacitor and the second capacitor constitutes a charge accumulation capacitance portion for accumulating signal charges generated by the photoelectric conversion portion when a global shutter operation is performed.

12. An electronic device comprising: The solid-state imaging device according to claim 10 or 11; an optical lens for forming an image of image light from a subject on an imaging surface of the solid-state imaging device; and A signal processing circuit performs signal processing on a signal output from the solid-state imaging device.

Images