Method for forming a processing substrate of a composite structure for RF applications and processing substrate

Abstract

The present invention relates to a processing substrate (100) for a composite structure, the processing substrate (100) comprising: a base substrate (12), the base substrate (12) consisting of a silicon epitaxial layer (2) on a single-crystal silicon wafer (1) obtained by Czochralski pulling, the single-crystal silicon wafer (1) having a resistivity between 10 and 500 ohm.cm, the silicon epitaxial layer (2) having a resistivity greater than 2000 ohm.cm and a thickness between 2 and 100 micrometers; a passivation layer (3), the passivation layer (3) being on the silicon epitaxial layer (2) and in contact with the silicon epitaxial layer (2), the passivation layer (3) being amorphous or polycrystalline; and a charge trapping layer (4), the charge trapping layer (4) being on the passivation layer (3) and in contact with the passivation layer (3). The present invention also relates to a method for forming such a substrate.

Description

Technical Field

[0001] The present invention relates to a handle substrate for a composite substrate compatible with high performance RF applications. The present invention also relates to a method of forming such a handle substrate. Background Art

[0002] High-resistivity (HR) silicon substrates are the most commonly used process substrates for fabricating RF devices. HR silicon substrates typically exhibit a resistivity greater than 1000 ohm.cm, and more typically greater than 5000 ohm.cm.

[0003] Composite structures such as SOI (Silicon-On-Insulator) with a HR silicon handle substrate (with or without a charge-trapping layer between the handle substrate and the buried oxide) are well known in the radio frequency (RF) field. In particular, composite structures with charge-trapping layers ensure high performance quality of RF devices produced on the structures, provided that the charge-trapping layer is not damaged when the structure is exposed to high temperatures (e.g., during its fabrication or during the fabrication of the RF device). For example, if a charge-trapping layer made of polycrystalline silicon recrystallizes, even partially, the RF performance quality of the composite structure and the integrated devices formed thereon may be affected, which is clearly undesirable.

[0004] Another issue comes from the supply of HR substrates, which is becoming increasingly limited as RF device manufacturing increases. As a result, this material is becoming increasingly expensive.

[0005] Subject matter of the invention

[0006] The present invention proposes an alternative solution for providing a handle substrate suitable for composite structures on which high performance RF devices can be produced and which facilitates the supply and manufacturing process. Summary of the Invention

[0007] To achieve this object, the subject of the present invention proposes a handling substrate for a composite structure, the handling substrate comprising:

[0008] - a base substrate formed by a silicon epitaxial layer on a Cz-type (ie obtained by Czochralski pulling) single-crystalline silicon wafer having a resistivity between 10 and 500 ohm.cm, said silicon epitaxial layer exhibiting a resistivity greater than 2000 ohm.cm and a thickness ranging from 2 to 100 micrometers,

[0009] a passivation layer on and in contact with the silicon epitaxial layer, the passivation layer being amorphous or polycrystalline,

[0010] - a charge-trapping layer on and in contact with the passivation layer.

[0011] According to other advantageous and non-limiting features of the invention, alone or in any technically realizable combination:

[0012] The passivation layer is a silicon carbide layer formed by carbonizing the surface of the silicon epitaxial layer;

[0013] The passivation layer is a silicon nitride layer formed by nitriding the surface of the silicon epitaxial layer.

[0014] The present invention also relates to a composite structure for radio frequency applications, comprising:

[0015] - a processed substrate as described above,

[0016] - a dielectric layer on and in contact with the passivation layer,

[0017] - a thin film on the dielectric layer, the thin film being suitable for a radio frequency device.

[0018] The present invention finally relates to a method for forming a handle substrate for a composite structure, said method comprising the following steps:

[0019] a) providing a single crystal silicon wafer obtained by Czochralski pulling having a resistivity between 10 and 500 ohm.cm;

[0020] b) growing a silicon epitaxial layer on said single crystal silicon wafer obtained by Czochralski pulling to form a base substrate, said silicon epitaxial layer exhibiting a resistivity greater than 2000 ohm.cm and a thickness ranging from 2 to 100 micrometers;

[0021] c) forming a passivation layer on the silicon epitaxial layer, wherein the passivation layer is amorphous or polycrystalline;

[0022] d) growing a polycrystalline charge-trapping layer on the passivation layer.

[0023] According to other advantageous and non-limiting features of the invention, alone or in any technically realizable combination:

[0024] Step c) comprises carbonizing the surface of the silicon epitaxial layer to form a passivation layer made of polycrystalline silicon carbide;

[0025] The carbonization of step c) comprises exposing the base substrate to a single carbon precursor at a pressure below atmospheric pressure so as to form a passivation layer made of polycrystalline silicon carbide with a thickness of at least 5 nm on the surface of the silicon epitaxial layer;

[0026] The single carbon precursor exhibits a temperature between 700°C and 1200°C;

[0027] Step c) comprises nitriding the surface of the silicon epitaxial layer to form a passivation layer made of amorphous silicon nitride;

[0028] The passivation layer exhibits a thickness of at least 10 nm;

[0029] The charge-trapping layer has a thickness greater than 5 or 10 microns;

[0030] The charge trapping layer is made of polysilicon;

[0031] Step b), step c) and step d) are all carried out continuously in situ in the epitaxial device;

[0032] • Step b) is performed in a first reactor, and steps c) and d) are performed in a second reactor, and wherein the base substrate is transferred from the first reactor to the second reactor without breaking vacuum. BRIEF DESCRIPTION OF THE DRAWINGS

[0033] Other features and advantages of the present invention will become apparent from the following detailed description of the present invention with reference to the accompanying drawings, in which:

[0034] Figure 1 represents a processed substrate according to the present invention;

[0035] Figure 2 represents a composite structure according to the present invention. DETAILED DESCRIPTION

[0036] In the description, the same reference numerals may be used in the figures to represent the same type of elements. These figures are diagrammatic representations and, for the sake of readability, are not to scale. In particular, the thickness of a layer along the z-axis is not proportional to the lateral dimensions along the x- and y-axes; and the thickness of layers relative to each other need not be considered in the figures.

[0037] Figure 1 A handle substrate 100 for a composite substrate according to the present invention is schematically shown. The handle substrate 100 can be provided in the form of a circular slice having standardized dimensions, for example, a diameter of 200 mm, 300 mm, or even 450 mm. However, the present invention is by no means limited to these dimensions or this shape.

[0038] The handle substrate 100 comprises a base substrate 12 formed of a silicon epitaxial layer 2 located on a silicon wafer 1. The silicon wafer 1 typically has a thickness of several hundred micrometers and exhibits a standard resistivity ranging from 10 to 500 ohm.cm. Single-crystal silicon obtained by Czochralski pulling, a widely available material, may be preferred.

[0039] The silicon epitaxial layer 2 exhibits a resistivity greater than 2000 ohm.cm, preferably between 2000 ohm.cm and 20000 ohm.cm. Thus, the density of charges, holes or electrons that can easily move in the silicon epitaxial layer is limited. The epitaxial layer 2 has a thickness ranging from 2 to 100 micrometers.

[0040] The handle substrate 100 further comprises a charge-trapping layer 4 on the base substrate 12. The function of the charge-trapping layer 4 is to trap any charge carriers that may be present in the handle substrate 100 and to restrict their migration.

[0041] For reasons of availability and cost, the charge-trapping layer 4 is preferably made of polycrystalline silicon. However, the charge-trapping layer 4 may be formed of another semiconductor and a polycrystalline material, or the charge-trapping layer 4 may include portions made of another semiconductor and a polycrystalline material. For example, the charge-trapping layer 4 may include germanium, silicon-germanium, or the like.

[0042] In all cases, the polycrystalline charge trapping layer 4 exhibits a high resistivity, typically greater than 3000 ohm.cm. For this purpose, this layer is not intentionally doped, that is, the polycrystalline charge trapping layer 4 exhibits a resistivity less than 10 14 atoms / cm 3 It can be enriched with nitrogen or carbon to improve its resistivity characteristics.

[0043] The thickness of the polycrystalline charge trapping layer 4 can be greater than 0.5 micron, or greater than 5 micron, or even greater than 10 micron. Regardless of whether its thickness is greater than or less than these limits, the charge trapping layer 4 can be composed of grains with a size between 10 nm and 1000 nm.

[0044] The handle substrate 100 further comprises an amorphous or polycrystalline passivation layer 3 interposed between the base substrate 12 and the polycrystalline charge-trapping layer 4. The passivation layer 3 is formed directly on the silicon epitaxial layer 2 and allows the polycrystalline charge-trapping layer 4 to be grown on this passivation layer 3. This layer is necessary to prevent the charge-trapping layer 4 from recrystallizing during high-temperature processing.

[0045] Thus, the passivation layer 3 can remain in an amorphous or polycrystalline form during the implementation of the high temperature processes necessary to manufacture the handle substrate 100 and subsequently the composite structure 110 and the RF devices. Typically, the handle substrate 100 is subjected to a thermal budget of the order of several hours to 10 hours at temperatures ranging from 950° C. to 1200° C.

[0046] The passivation layer 3 may be of different natures. Advantageously, the passivation layer 3 consists of a polycrystalline silicon carbide layer formed by carbonization of the free surface of the silicon epitaxial layer 2. Alternatively, the passivation layer 3 may consist of a silicon nitride layer formed by nitridation of the surface of the silicon epitaxial layer.

[0047] Of course, the passivation layer 3 may be made of other materials with different properties, as long as it meets the requirements of microelectronics and maintains its amorphous or polycrystalline structure after overall thermal equilibrium until the RF device is completed.

[0048] Typically, the passivation layer 3 may have a thickness of at least 2 nm, preferably at least 10 nm.

[0049] Thus, the handle substrate 100 is composed of a base substrate 12 formed of a silicon epitaxial layer 2 located on a single-crystal silicon wafer 1, a passivation layer 3 in direct contact with the silicon epitaxial layer 2, and a polycrystalline charge-trapping layer 4 on the passivation layer 3 and in direct contact with the passivation layer 3. It is not intended to include other layers, in particular electrically insulating layers, since this could alter the properties of the proposed handle substrate 100.

[0050] The handle substrate 100 may optionally include a dielectric layer 5 directly on the charge trapping layer 4. The dielectric layer 5 (which is optional) may facilitate assembly of the handle substrate 100 with another substrate. The dielectric layer 5 may be made of silicon oxide or silicon nitride, for example.

[0051] Figure 2 FIG. 1 shows a composite structure 110 according to the present invention, which includes the handle substrate 100 described above. As can be clearly seen from the figure, the composite structure includes a dielectric layer 5 on the handle substrate 100 and a thin film 6, preferably made of a single-crystalline material, on the dielectric layer 5. For example, but not limited to, the thin film 6 can be made of a semiconductor material such as silicon or a piezoelectric material such as lithium tantalate (LiTaO3), lithium niobate (LiNbO3), lithium aluminate (LiAlO3), barium titanate (BaTiO3), lead zirconate titanate (PbZrTiO3), potassium niobate (KNbO3), barium zirconate (BaZrO3), calcium titanate (CaTiO3), lead titanate (PbTiO3), potassium tantalate (KTaO3), etc.

[0052] Figure 2The composite structure 110 can be formed from the handle substrate 100 in various ways, but advantageously, this formation includes a step of transferring the thin film 6 onto the handle substrate 100. As is known, this transfer is usually performed by assembling the face of a donor substrate onto the handle substrate 100. This can be done with or without the presence of the dielectric layer 5.

[0053] When the film 6 is made of a piezoelectric material, its crystal orientation is selected according to the intended application. For surface acoustic wave filters made of lithium tantalate LiTaO3, an orientation between 30° and 60°XY or between 40° and 50°XY is usually selected. For lithium niobate LiNbO3, an orientation of around 128°XY is usually selected. However, the present invention is in no way limited to a specific crystal orientation of the piezoelectric film. The donor substrate can be taken out of an ingot made of a ferroelectric material so that the donor substrate exhibits a selected crystal orientation. Alternatively, the donor substrate can include a thick layer made of a ferroelectric material assembled with a supporting substrate.

[0054] After this assembly step, the thickness of the donor substrate is reduced in order to form the thin film 6. This reduction step can be performed by mechanical or chemical thinning. It can also be performed by, for example, according to Smart Cut TM The principle of the technology is to perform this reduction step by fracturing at fragile areas previously introduced into the donor substrate.

[0055] The steps of finishing the thin film 6 (for example a polishing step, a heat treatment under a reducing or neutral atmosphere or a sacrificial oxidation) can be connected after the thickness reduction step.

[0056] When the donor substrate is a bulk substrate (i.e., does not include an integrated device), a composite structure 110 of the "semiconductor on insulator" type is formed, comprising the handle substrate 100 according to the present invention, wherein the thin film 6 is the original semiconductor layer. The composite structure 110 can then be used to form an integrated device.

[0057] When the donor substrate has been pre-processed to form integrated devices on its surface, the thin film 6 including the devices can be transferred to the handle substrate 100 to form a composite structure 110 having an integrated device layer on the handle substrate 100 according to the present invention.

[0058] The fabrication of the handle substrate 100 according to the present description can be achieved by providing standard materials and by using conventional epitaxial / deposition equipment in the industry.

[0059] Firstly, the method comprises a step a) comprising providing a single-crystal silicon wafer 1 obtained by Czochralski pulling and having a resistivity ranging from 10 to 500 ohm.cm.

[0060] The next step b) consists in growing a silicon epitaxial layer 2 on the silicon wafer 1 so as to form a base substrate 12. To this end, the silicon wafer 1 is placed in a reactor (or chamber) of an epitaxial device. The silicon wafer 1 can be prepared before epitaxial growth in order to clean its surface (i.e., to remove organic or metallic dopants or particulate contaminants) and to remove the native oxide layer from its surface. Cleaning is usually carried out using conventional wet cleaning processes. Deoxidation can be carried out by wet or dry chemical etching before the silicon wafer 1 is placed in the reactor; deoxidation can also be carried out by exposing the silicon wafer 1 in the reactor to a reducing atmosphere at a temperature of at least 900°C.

[0061] The goal of step b) is to grow an intrinsic silicon epitaxial layer 2. The intrinsic silicon epitaxial layer 2 has a resistivity greater than 2000 ohm.cm and a thickness ranging from 2 to 100 micrometers.

[0062] Advantageously, the epitaxial growth of the silicon layer is performed at high temperatures ranging from 1000° C. to 1200° C., at atmospheric pressure or under reduced pressure using conventional gaseous silicon sources such as trichlorosilane (TCS), dichlorosilane (DCS) or silane (SiH 4 ).

[0063] The method according to the invention then comprises a step c) consisting in forming an amorphous or polycrystalline passivation layer 3 on the silicon epitaxial layer 2 .

[0064] According to the first option, the passivation layer 3 is formed in the same reactor used for epitaxial growth. This is advantageous because the base substrate 12 remains in place under a controlled atmosphere. On the one hand, this avoids breaking the vacuum, thereby improving the roughing time and overall efficiency of the method. On the other hand, it prevents the base substrate 12 from capturing contaminants from the ambient atmosphere, such as boron particles or residues that may be present in the cleanroom. Consequently, the interface between the silicon epitaxial layer 2 and the passivation layer 3 is protected and maintained at a high resistivity.

[0065] According to the second option, the formation of the passivation layer 3 is carried out in a second reactor that shares the same transfer module with the first reactor for the silicon epitaxial layer, under a vacuum or argon or nitrogen atmosphere. Again, the vacuum is not broken and the base substrate 12 remains in place under a controlled atmosphere, preventing non-in-situ contamination and ensuring that the interface between the silicon epitaxial layer 2 and the passivation layer 3 exhibits high resistivity. In addition, the second option facilitates the cleaning of the reactor. This is because if carbonization or nitridation has not been performed, the epitaxial silicon material (from a few microns to tens of microns) deposited on the inner wall of the first reactor during epitaxial growth can be more easily removed. The passivation layer 3 formed by carbonization or nitridation in the second reactor is only formed on the silicon material, that is, only formed on the silicon epitaxial layer. Therefore, this has no effect on the part located inside the second reactor, because carbonization and nitridation are reactions that occur between the source gas and the silicon surface. The fact that steps b) and c) are carried out in the separated first and second reactors makes it possible to better manage the cleanliness and performance quality of the chamber.

[0066] Of course, according to a third option, the base substrate 12 can be removed from the first reactor in order to return it to the atmosphere of the clean room. In this case, the base substrate 12 can be prepared before forming the passivation layer in order to clean the surface of the silicon epitaxial layer (i.e., to remove organic or metallic dopants or particulate contaminants) and to remove the native oxide layer from the surface. Cleaning can be carried out using conventional wet cleaning processes. Deoxidation can be carried out by wet or dry chemical etching. Alternatively, deoxidation can be carried out after the base substrate 12 is loaded into the reactor by exposing it to a reducing atmosphere at a temperature of at least 800°C. However, this step is not mandatory and the native oxide can be retained. This is because, without generating an insulating effect (conduction through the layer due to the tunneling effect), a thickness of 1 nm to 2 nm is already thin enough, as long as future heat treatments do not cause it to completely disappear by decomposition.

[0067] According to any of the above options, after having been placed in the reactor, the base substrate 12 undergoes the formation of the passivation layer 3 .

[0068] According to a first embodiment, step c) consists in carbonizing the free surface of the silicon epitaxial layer 2 in order to form a passivation layer 3 made of polycrystalline silicon carbide.

[0069] To this end, the base substrate 12 (more specifically, the free surface of the silicon epitaxial layer 2) is exposed to a single carbon precursor gas at a pressure below atmospheric pressure (e.g., between 0.01 Torr and 760 Torr). The carbon precursor gas can be composed of methane (CH4), ethane (C2H6), propane (C3H8), acetylene (C2H2), ethylene (C2H4), etc. The precursor gas can be introduced into the reactor at a temperature between 700°C and 1200°C (or heated inside the reactor) so that the carbon-based entities are nucleated on the surface of the silicon epitaxial layer 2. A carrier gas flow (e.g., H2) can also be introduced into the chamber at the same time, but no other precursor gas flows through the base substrate 12 besides the carbon precursor gas. By preventing the carbon-based entities from reacting with other entities of the second precursor, the deposition of carbon-based compounds on the reactor walls is limited and the generation of particles is avoided.

[0070] Surprisingly, it was observed that when the carbonization step is carried out at a reduced carbon partial pressure below 760 Torr, nucleation of carbon-based entities occurs in isolated islets on the surface. Silicon atoms from the base wafer then diffuse into the carbon islands, forming stoichiometric or near-stoichiometric 3C / 6H and 4H silicon carbide islands. These islands merge to form a relatively thick polycrystalline silicon carbide layer. When the carbon precursor gas flow is maintained for several minutes, the thickness of the polycrystalline layer increases to several nanometers.

[0071] In a specific example, a carbon precursor gas made of a mixture of C3H8 and H2 at a ratio of 180 sccm / 5 slm was introduced into the chamber and circulated at a pressure of 10 Torr for 5 minutes and heated to 1000° C. A polycrystalline passivation layer 3 made of silicon carbide having a thickness of 10 nm was then observed on the surface of the silicon epitaxial layer 2.

[0072] When the carbonization step is performed at a higher carbon partial pressure, greater than 760 Torr, a completely different phenomenon occurs on the surface of the base substrate 12. Carbon-based entities nucleate at a high density on the surface and prevent silicon atoms from diffusing from the surface. A crystalline or partially crystalline carbon layer then slowly grows on the surface in a 3C structure aligned with the silicon lattice. Such a layer typically exhibits a thickness of 2 nm after 10 minutes of deposition.

[0073] Thus, circulating a single carbon precursor gas at a reduced carbon partial pressure on the base substrate 12 appears to be a very effective means for forming a relatively thick (greater than 5 nm or 10 nm) polycrystalline silicon carbide layer. Such a passivation layer 3 is advantageous because, by virtue of its polycrystalline nature, it thus makes it possible to prepare and maintain the polycrystalline nature of the charge-trapping layer 4 grown thereon. Furthermore, the relatively large thickness of the passivation layer forms quite quickly and constitutes an effective diffusion barrier to prevent migration of dopant entities from the base substrate 12 to the charge-trapping layer 4.

[0074] Furthermore, it has been observed that, at a reduced carbon partial pressure, such a carbonization step incorporates very little dopant (e.g., boron) in the passivation layer 3 made of silicon carbide. Measurements have shown that the boron concentration in such a layer is less than 10 14 atoms / cm 3 It is believed that dopant entities (which may be present at the surface of base substrate 12 or incorporated into base substrate 12) diffuse out of the silicon carbide layer during its formation and are exhausted from the deposition chamber (or reactor) along with the precursor and carrier gases.

[0075] According to a second embodiment, step c) consists in nitriding the free surface of the silicon epitaxial layer 2 in order to form a passivation layer 3 made of silicon nitride.

[0076] To this end, the base substrate 12 (more specifically, the free surface of the silicon epitaxial layer 2) is exposed to a nitrogen precursor gas at a pressure between 0.1 Torr and 760 Torr, for example. The precursor gas may be composed of ammonia (NH3). The precursor gas may be introduced into the chamber (or heated within the chamber) at a temperature between 800°C and 1300°C, causing nitrogen-based entities to nucleate on the surface of the silicon epitaxial layer 2.

[0077] After step c), a passivation layer made of silicon nitride is obtained. This passivation layer generally exhibits a thickness of less than 10 nm after nitridation for 10 seconds to 60 minutes.

[0078] Such a passivation layer 3 is advantageous because, by virtue of its non-epitaxial nature on silicon, it makes it possible to produce and maintain the polycrystalline nature of the charge-trapping layer 4 grown thereon. The passivation layer 3 forms relatively quickly only on silicon and constitutes an effective diffusion barrier preventing the migration of dopant species from the base substrate 12 into the charge-trapping layer.

[0079] After the growth of the passivation layer 3 on the base substrate 12 according to either of the first and second embodiments, another stream of precursor gas is passed through the reactor at a temperature of around 1000° C. in order to form the polycrystalline charge-trapping layer 4 in a conventional manner: this is step d of the method according to the invention. The duration of the precursor gas circulation determines the thickness of the polycrystalline layer 4 and can be selected so as to allow the growth of a layer of 5 micrometers, 10 micrometers or more.

[0080] Advantageously, the passivation layer 3 and the polycrystalline charge trapping layer 4 are formed in situ in the same reactor or chamber. This avoids contamination of the stack by dopants or contaminants from the ambient atmosphere and preserves the high resistivity characteristics of the processed substrate 100.

[0081] For the sake of completeness, the handle substrate 100 may be provided with a dielectric layer 5, for example silicon oxide or silicon nitride, deposited in a conventional manner. The dielectric layer 5 and / or the polycrystalline charge trapping layer 4 may also be polished to provide an upper surface of the handle substrate 100 that is compatible with conventional steps for transferring the thin film 6 onto the handle substrate 100.

[0082] Of course, the invention is not limited to the embodiments described and alternative embodiments may be fostered without departing from the scope of the invention as defined by the claims.

Claims

1. A processing substrate (100) for a composite structure, the processing substrate (100) comprising: - a base substrate (12) formed by a silicon epitaxial layer (2) on a single-crystal silicon wafer (1) obtained by Czochralski pulling, said single-crystal silicon wafer (1) having a resistivity between 10 and 500 ohm.cm, said silicon epitaxial layer (2) exhibiting a resistivity greater than 2000 ohm.cm and a thickness ranging from 2 to 100 micrometers, - a passivation layer (3), said passivation layer (3) being on said silicon epitaxial layer (2) and in contact with said silicon epitaxial layer (2), said passivation layer (3) being amorphous or polycrystalline, - a charge-trapping layer (4), said charge-trapping layer (4) being on and in contact with said passivation layer (3), The processing substrate (100) is characterized in that: - the passivation layer (3) is a silicon carbide layer formed by carbonizing the surface of the silicon epitaxial layer (2), the carbonization being performed by exposing the free surface of the silicon epitaxial layer (2) to a single carbon precursor gas at a pressure below atmospheric pressure, or The passivation layer (3) is a silicon nitride layer formed by nitriding the surface of the silicon epitaxial layer (2), the nitridation being performed by exposing the free surface of the silicon epitaxial layer (2) to a nitrogen precursor gas at a pressure between 0.1 Torr and 760 Torr.

2. A composite structure (110) for radio frequency applications, the composite structure (110) comprising: - The handle substrate (100) according to claim 1, a dielectric layer (5) on the charge-trapping layer (4) and in contact with the charge-trapping layer (4), - a thin film (6), said thin film (6) being on said dielectric layer (5), said thin film (6) being suitable for use in radio frequency devices.

3. A method of forming a handle substrate (100) for a composite structure, the method comprising the steps of: a) providing a single crystal silicon wafer (1) obtained by Czochralski pulling and having a resistivity between 10 and 500 ohm.cm; b) growing a silicon epitaxial layer (2) on said single crystal silicon wafer (1) obtained by Czochralski pulling to form a base substrate (12), said silicon epitaxial layer (2) exhibiting a resistivity greater than 2000 ohm.cm and a thickness ranging from 2 to 100 micrometers; c) forming a passivation layer (3) on the silicon epitaxial layer (2), wherein the passivation layer (3) is amorphous or polycrystalline; d) growing a polycrystalline charge trapping layer (4) on the passivation layer (3); The method is characterized in that step c) comprises: - carbonizing the surface of the silicon epitaxial layer (2) so as to form a passivation layer (3) made of polycrystalline silicon carbide, said carbonization being performed by exposing the free surface of the silicon epitaxial layer (2) to a single carbon precursor gas at a pressure below atmospheric pressure, or - Nitriding the surface of the silicon epitaxial layer (2) to form a passivation layer (3) made of silicon nitride, the nitridation being performed by exposing the free surface of the silicon epitaxial layer (2) to a nitrogen precursor gas at a pressure between 0.1 Torr and 760 Torr.

4. The method according to claim 3, wherein: The carbonization of step c) comprises exposing the base substrate (12) to the single carbon precursor gas at a pressure below atmospheric pressure to form a passivation layer (3) of polycrystalline silicon carbide of at least 5 nm on the surface of the silicon epitaxial layer (2).

5. The method according to claim 4, wherein The single carbon precursor gas exhibits a temperature between 700°C and 1200°C.

6. The method according to claim 3, wherein: The passivation layer (3) exhibits a thickness of at least 10 nm.

7. The method according to claim 3, wherein: The charge-trapping layer (4) has a thickness greater than 5 or 10 microns.

8. The method according to claim 3, wherein: The charge trapping layer (4) is made of polycrystalline silicon.

9. The method according to claim 3, wherein: Step b), step c) and step d) are all carried out continuously in situ in the epitaxial device.

10. The method according to claim 9, wherein: Step b) is performed in a first reactor, and steps c) and d) are performed in a second reactor, and wherein the base substrate (12) is transferred from the first reactor to the second reactor without breaking the vacuum.

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